MLK-17363-1 imx8: pm-domain: fix clock parent restore issue after suspend/resume

Currently the clock parent actually is failed to be restored in power
domain driver due to the set_parent will bail out early as the clk core
already cached the same old parent.

Implement a CLK_SET_PARENT_NOCACHE flag in clk core and register all
SC mux clocks with this flag to make sure the clk core won't bypass
the SC clock parent setting.

[ Aisheng: "Add commit message" ]

Reviewed-by: Anson Huang <anson.huang@nxp.com>
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
Signed-off-by: Ranjani Vaidyanathan <Ranjani.Vaidyanathan@nxp.com>
(cherry picked from commit 459b9d4dfb)

drivers/clk/clk.c

@@ -1797,7 +1797,8 @@ static int clk_core_set_parent(struct clk_core *core, struct clk_core *parent)
 	/* prevent racing with updates to the clock topology */
 	clk_prepare_lock();
 
-	if (core->parent == parent)
+	if ((core->parent == parent) &&
+		!(core->flags & CLK_SET_PARENT_NOCACHE))
 		goto out;
 
 	/* verify ops for for multi-parent clks */

drivers/clk/imx/clk-mux-scu.c

@@ -354,7 +354,7 @@ struct clk *clk_register_mux_gpr_scu(struct device *dev, const char *name,
 	init.ops = &clk_mux_gpr_scu_ops;
 	init.parent_names = parents;
 	init.num_parents = num_parents;
-	init.flags = 0;
+	init.flags |= CLK_SET_PARENT_NOCACHE;
 
 	gpr_scu_mux->hw.init = &init;
 	gpr_scu_mux->rsrc_id = rsrc_id;
@@ -431,7 +431,7 @@ struct clk *clk_register_mux2_scu(struct device *dev, const char *name,
 	init.ops = &clk_mux2_scu_ops;
 	init.parent_names = parents;
 	init.num_parents = num_parents;
-	init.flags = flags;
+	init.flags = flags |= CLK_SET_PARENT_NOCACHE;
 
 	mux->hw.init = &init;
 	mux->rsrc_id = rsrc_id;

drivers/soc/imx/pm-domains.c

@@ -54,6 +54,7 @@ enum imx_pd_state {
 
 struct clk_stat {
 	struct clk *clk;
+	struct clk *parent;
 	unsigned long rate;
 };
 
@@ -146,11 +147,15 @@ static int imx8_pd_power_on(struct generic_pm_domain *domain)
 
 			list_for_each_entry(imx8_rsrc_clk, &pd->clks, node) {
 				clk_stats[i].clk = imx8_rsrc_clk->clk;
+				clk_stats[i].parent = imx8_rsrc_clk->parent;
 				clk_stats[i].rate = clk_hw_get_rate(__clk_get_hw(imx8_rsrc_clk->clk));
 				i++;
 			}
 
 			for (i = 0; i <= count; i++) {
+				/* restore parent first */
+				clk_set_parent(clk_stats[i].clk, clk_stats[i].parent);
+
 				/* invalid cached rate first by get rate once */
 				clk_get_rate(clk_stats[i].clk);
 				/* restore the lost rate */

include/linux/clk-provider.h

@@ -35,6 +35,7 @@
 #define CLK_IS_CRITICAL		BIT(11) /* do not gate, ever */
 /* parents need enable during gate/ungate, set rate and re-parent */
 #define CLK_OPS_PARENT_ENABLE	BIT(12)
+#define CLK_SET_PARENT_NOCACHE	BIT(13) /* do not use the cached clk parent */
 
 struct clk;
 struct clk_hw;