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MLK-18003 ARM64: dts: imx8qxp: change back usdhc clock parent to PLL0

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8QXP B0 chip already fix the PLL0 unstable issue, so change back
the usdhc clock parent to PLL0.

To track the history, refer to commit 7834eee6df ("MLK-17188-2
ARM64: dts: imx8qxp: assign usdhc clock parent").

Signed-off-by: Haibo Chen <haibo.chen@nxp.com>
This commit is contained in:
Haibo Chen
2018-04-12 10:20:17 +08:00
parent 50af8be483
commit 0611d9138e
1 changed files with 3 additions and 3 deletions
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6
arch/arm64/boot/dts/freescale/fsl-imx8qxp.dtsi
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@ -2499,7 +2499,7 @@
<&clk IMX8QXP_CLK_DUMMY>;
clock-names = "ipg", "per", "ahb";
assigned-clocks = <&clk IMX8QXP_SDHC0_SEL>, <&clk IMX8QXP_SDHC0_DIV>;
assigned-clock-parents = <&clk IMX8QXP_CONN_PLL1_CLK>;
assigned-clock-parents = <&clk IMX8QXP_CONN_PLL0_CLK>;
assigned-clock-rates = <0>, <400000000>;
power-domains = <&pd_conn_sdch0>;
fsl,tuning-start-tap = <20>;
@ -2517,7 +2517,7 @@
<&clk IMX8QXP_CLK_DUMMY>;
clock-names = "ipg", "per", "ahb";
assigned-clocks = <&clk IMX8QXP_SDHC1_SEL>, <&clk IMX8QXP_SDHC1_DIV>;
assigned-clock-parents = <&clk IMX8QXP_CONN_PLL1_CLK>;
assigned-clock-parents = <&clk IMX8QXP_CONN_PLL0_CLK>;
assigned-clock-rates = <0>, <200000000>;
power-domains = <&pd_conn_sdch1>;
fsl,tuning-start-tap = <20>;
@ -2535,7 +2535,7 @@
<&clk IMX8QXP_CLK_DUMMY>;
clock-names = "ipg", "per", "ahb";
assigned-clocks = <&clk IMX8QXP_SDHC2_SEL>, <&clk IMX8QXP_SDHC2_DIV>;
assigned-clock-parents = <&clk IMX8QXP_CONN_PLL1_CLK>;
assigned-clock-parents = <&clk IMX8QXP_CONN_PLL0_CLK>;
assigned-clock-rates = <0>, <200000000>;
power-domains = <&pd_conn_sdch2>;
status = "disabled";