MLK-15004-4: ASoC: fsl_esai: esai workaround for imx8qxp Rev1
In imx8qxp rev1, there is hardware issue (TKT331800). ESAI dma request signal connection issue in SS_ADMA top level integration, The ESAI dma request signal are active_low, the EDMA input is high active, but there is no polarity convert logic between them. This patch is to add a workaround for this issue. It use the GPT to convert dma request signal to EDMA, and use anther GPT to clear the dma request. Signed-off-by: Shengjiu Wang <shengjiu.wang@freescale.com>
This commit is contained in:
Shengjiu Wang
committed by
Leonard Crestez
Leonard Crestez
parent
f519337c4f
commit
175fcc2bd4
@ -12,12 +12,17 @@
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#include <linux/clk.h>
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#include <linux/dmaengine.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/of_irq.h>
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#include <linux/of_platform.h>
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#include <linux/dma-mapping.h>
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#include <linux/dmapool.h>
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#include <sound/dmaengine_pcm.h>
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#include <sound/pcm_params.h>
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#include "fsl_esai.h"
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#include "fsl_acm.h"
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#include "imx-pcm.h"
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#define FSL_ESAI_RATES SNDRV_PCM_RATE_8000_192000
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@ -26,6 +31,57 @@
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SNDRV_PCM_FMTBIT_S20_3LE | \
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SNDRV_PCM_FMTBIT_S24_LE)
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#define EDMA_CH_CSR 0x00
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#define EDMA_CH_ES 0x04
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#define EDMA_CH_INT 0x08
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#define EDMA_CH_SBR 0x0C
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#define EDMA_CH_PRI 0x10
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#define EDMA_TCD_SADDR 0x20
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#define EDMA_TCD_SOFF 0x24
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#define EDMA_TCD_ATTR 0x26
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#define EDMA_TCD_NBYTES 0x28
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#define EDMA_TCD_SLAST 0x2C
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#define EDMA_TCD_DADDR 0x30
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#define EDMA_TCD_DOFF 0x34
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#define EDMA_TCD_CITER_ELINK 0x36
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#define EDMA_TCD_CITER 0x36
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#define EDMA_TCD_DLAST_SGA 0x38
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#define EDMA_TCD_CSR 0x3C
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#define EDMA_TCD_BITER_ELINK 0x3E
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#define EDMA_TCD_BITER 0x3E
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#define GPT_CR 0x00
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#define GPT_PR 0x04
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#define GPT_SR 0x08
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#define GPT_IR 0x0C
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#define GPT5_ADDR 0x590b0000
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#define GPT6_ADDR 0x590c0000
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#define GPT7_ADDR 0x590d0000
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#define GPT8_ADDR 0x590e0000
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#define EDMA_GPT6_ADDR 0x59360000
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#define EDMA_GPT8_ADDR 0x59380000
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struct fsl_edma3_hw_tcd {
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__le32 saddr;
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__le16 soff;
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__le16 attr;
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__le32 nbytes;
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__le32 slast;
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__le32 daddr;
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__le16 doff;
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__le16 citer;
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__le32 dlast_sga;
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__le16 csr;
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__le16 biter;
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};
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struct fsl_edma3_sw_tcd {
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dma_addr_t ptcd;
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struct fsl_edma3_hw_tcd *vtcd;
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};
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/**
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* fsl_esai: ESAI private data
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*
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@ -58,6 +114,16 @@ struct fsl_esai {
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struct clk *extalclk;
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struct clk *fsysclk;
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struct clk *spbaclk;
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struct fsl_edma3_sw_tcd tcd_sw[4];
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struct dma_pool *tcd_pool;
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struct snd_dma_buffer buf;
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void __iomem *base_gpt0;
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void __iomem *base_gpt1;
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void __iomem *base_gpt2;
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void __iomem *base_gpt3;
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void __iomem *base_edma_gpt1;
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void __iomem *base_edma_gpt3;
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void __iomem *base_acm;
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u32 fifo_depth;
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u32 slot_width;
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u32 slots;
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@ -69,6 +135,7 @@ struct fsl_esai {
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bool sck_div[2];
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bool slave_mode;
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bool synchronous;
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bool dma_workaround;
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char name[32];
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};
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@ -529,6 +596,142 @@ err_spbaclk:
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return ret;
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}
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static int configure_gpt_dma(struct snd_pcm_substream *substream,
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struct snd_soc_dai *dai)
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{
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bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
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struct fsl_esai *esai_priv = snd_soc_dai_get_drvdata(dai);
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if (tx) {
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writel_relaxed(ESAI0_IPD_ESAI_TX_B,
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esai_priv->base_acm + GPT0_CAPIN1_SEL_OFF);
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writel_relaxed(ESAI0_IPD_ESAI_TX_B,
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esai_priv->base_acm + GPT1_CAPIN1_SEL_OFF);
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writel(le32_to_cpu(esai_priv->tcd_sw[0].vtcd->saddr),
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esai_priv->base_edma_gpt1 + EDMA_TCD_SADDR);
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writel(le32_to_cpu(esai_priv->tcd_sw[0].vtcd->daddr),
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esai_priv->base_edma_gpt1 + EDMA_TCD_DADDR);
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writew(le16_to_cpu(esai_priv->tcd_sw[0].vtcd->attr),
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esai_priv->base_edma_gpt1 + EDMA_TCD_ATTR);
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writew(le16_to_cpu(esai_priv->tcd_sw[0].vtcd->soff),
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esai_priv->base_edma_gpt1 + EDMA_TCD_SOFF);
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writel(le32_to_cpu(esai_priv->tcd_sw[0].vtcd->nbytes),
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esai_priv->base_edma_gpt1 + EDMA_TCD_NBYTES);
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writel(le32_to_cpu(esai_priv->tcd_sw[0].vtcd->slast),
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esai_priv->base_edma_gpt1 + EDMA_TCD_SLAST);
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writew(le16_to_cpu(esai_priv->tcd_sw[0].vtcd->citer),
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esai_priv->base_edma_gpt1 + EDMA_TCD_CITER);
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writew(le16_to_cpu(esai_priv->tcd_sw[0].vtcd->biter),
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esai_priv->base_edma_gpt1 + EDMA_TCD_BITER);
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writew(le16_to_cpu(esai_priv->tcd_sw[0].vtcd->doff),
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esai_priv->base_edma_gpt1 + EDMA_TCD_DOFF);
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writel(le32_to_cpu(esai_priv->tcd_sw[0].vtcd->dlast_sga),
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esai_priv->base_edma_gpt1 + EDMA_TCD_DLAST_SGA);
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writew(le16_to_cpu(esai_priv->tcd_sw[0].vtcd->csr),
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esai_priv->base_edma_gpt1 + EDMA_TCD_CSR);
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writel(0x0, esai_priv->base_edma_gpt1 + EDMA_CH_SBR);
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writel(0x1, esai_priv->base_edma_gpt1 + EDMA_CH_CSR);
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/* configure this gpt for dma tx*/
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writel_relaxed(0x8, esai_priv->base_gpt0 + GPT_IR);
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writel_relaxed(0x7<<12, esai_priv->base_gpt0 + GPT_PR);
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writel_relaxed(0x20441, esai_priv->base_gpt0 + GPT_CR);
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/* configure this gpt for dma tx request clearn*/
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writel_relaxed(0x8, esai_priv->base_gpt1 + GPT_IR);
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writel_relaxed(0x7<<12, esai_priv->base_gpt1 + GPT_PR);
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writel_relaxed(0x10441, esai_priv->base_gpt1 + GPT_CR);
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} else {
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writel_relaxed(ESAI0_IPD_ESAI_RX_B,
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esai_priv->base_acm + GPT2_CAPIN1_SEL_OFF);
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writel_relaxed(ESAI0_IPD_ESAI_RX_B,
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esai_priv->base_acm + GPT3_CAPIN1_SEL_OFF);
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writel(le32_to_cpu(esai_priv->tcd_sw[2].vtcd->saddr),
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esai_priv->base_edma_gpt3 + EDMA_TCD_SADDR);
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writel(le32_to_cpu(esai_priv->tcd_sw[2].vtcd->daddr),
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esai_priv->base_edma_gpt3 + EDMA_TCD_DADDR);
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writew(le16_to_cpu(esai_priv->tcd_sw[2].vtcd->attr),
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esai_priv->base_edma_gpt3 + EDMA_TCD_ATTR);
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writew(le16_to_cpu(esai_priv->tcd_sw[2].vtcd->soff),
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esai_priv->base_edma_gpt3 + EDMA_TCD_SOFF);
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writel(le32_to_cpu(esai_priv->tcd_sw[2].vtcd->nbytes),
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esai_priv->base_edma_gpt3 + EDMA_TCD_NBYTES);
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writel(le32_to_cpu(esai_priv->tcd_sw[2].vtcd->slast),
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esai_priv->base_edma_gpt3 + EDMA_TCD_SLAST);
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writew(le16_to_cpu(esai_priv->tcd_sw[2].vtcd->citer),
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esai_priv->base_edma_gpt3 + EDMA_TCD_CITER);
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writew(le16_to_cpu(esai_priv->tcd_sw[2].vtcd->biter),
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esai_priv->base_edma_gpt3 + EDMA_TCD_BITER);
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writew(le16_to_cpu(esai_priv->tcd_sw[2].vtcd->doff),
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esai_priv->base_edma_gpt3 + EDMA_TCD_DOFF);
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writel(le32_to_cpu(esai_priv->tcd_sw[2].vtcd->dlast_sga),
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esai_priv->base_edma_gpt3 + EDMA_TCD_DLAST_SGA);
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writew(le16_to_cpu(esai_priv->tcd_sw[2].vtcd->csr),
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esai_priv->base_edma_gpt3 + EDMA_TCD_CSR);
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writel(0x0, esai_priv->base_edma_gpt3 + EDMA_CH_SBR);
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writel(0x1, esai_priv->base_edma_gpt3 + EDMA_CH_CSR);
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/* configure this gpt for dma tx*/
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writel_relaxed(0x8, esai_priv->base_gpt2 + GPT_IR);
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writel_relaxed(0x7<<12, esai_priv->base_gpt2 + GPT_PR);
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writel_relaxed(0x20441, esai_priv->base_gpt2 + GPT_CR);
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/* configure this gpt for dma tx request clearn*/
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writel_relaxed(0x8, esai_priv->base_gpt3 + GPT_IR);
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writel_relaxed(0x7<<12, esai_priv->base_gpt3 + GPT_PR);
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writel_relaxed(0x10441, esai_priv->base_gpt3 + GPT_CR);
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}
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return 0;
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}
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static int clear_gpt_dma(struct snd_pcm_substream *substream,
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struct snd_soc_dai *dai)
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{
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bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
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struct fsl_esai *esai_priv = snd_soc_dai_get_drvdata(dai);
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u32 val;
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if (tx) {
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val = readl(esai_priv->base_edma_gpt1 + EDMA_CH_CSR);
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val &= ~0x1;
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writel(val, esai_priv->base_edma_gpt1 + EDMA_CH_CSR);
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/* disable gpt */
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writel_relaxed(0, esai_priv->base_gpt0 + GPT_IR);
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writel_relaxed(0, esai_priv->base_gpt0 + GPT_PR);
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writel_relaxed(0, esai_priv->base_gpt0 + GPT_CR);
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writel_relaxed(0, esai_priv->base_gpt1 + GPT_IR);
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writel_relaxed(0, esai_priv->base_gpt1 + GPT_PR);
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writel_relaxed(0, esai_priv->base_gpt1 + GPT_CR);
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} else {
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val = readl(esai_priv->base_edma_gpt3 + EDMA_CH_CSR);
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val &= ~0x1;
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writel(val, esai_priv->base_edma_gpt3 + EDMA_CH_CSR);
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/* disable gpt */
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writel_relaxed(0, esai_priv->base_gpt2 + GPT_IR);
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writel_relaxed(0, esai_priv->base_gpt2 + GPT_PR);
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writel_relaxed(0, esai_priv->base_gpt2 + GPT_CR);
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writel_relaxed(0, esai_priv->base_gpt3 + GPT_IR);
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writel_relaxed(0, esai_priv->base_gpt3 + GPT_PR);
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writel_relaxed(0, esai_priv->base_gpt3 + GPT_CR);
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}
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return 0;
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}
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static int fsl_esai_hw_params(struct snd_pcm_substream *substream,
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struct snd_pcm_hw_params *params,
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struct snd_soc_dai *dai)
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@ -542,6 +745,9 @@ static int fsl_esai_hw_params(struct snd_pcm_substream *substream,
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u32 bclk, mask, val;
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int ret;
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if (esai_priv->dma_workaround)
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configure_gpt_dma(substream, dai);
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/* Override slot_width if being specifically set */
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if (esai_priv->slot_width)
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slot_width = esai_priv->slot_width;
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@ -661,11 +867,23 @@ static int fsl_esai_trigger(struct snd_pcm_substream *substream, int cmd,
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return 0;
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}
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static int fsl_esai_hw_free(struct snd_pcm_substream *substream,
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struct snd_soc_dai *cpu_dai)
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{
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struct fsl_esai *esai_priv = snd_soc_dai_get_drvdata(cpu_dai);
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if (esai_priv->dma_workaround)
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clear_gpt_dma(substream, cpu_dai);
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return 0;
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}
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static struct snd_soc_dai_ops fsl_esai_dai_ops = {
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.startup = fsl_esai_startup,
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.shutdown = fsl_esai_shutdown,
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.trigger = fsl_esai_trigger,
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.hw_params = fsl_esai_hw_params,
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.hw_free = fsl_esai_hw_free,
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.set_sysclk = fsl_esai_set_dai_sysclk,
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.set_fmt = fsl_esai_set_dai_fmt,
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.set_tdm_slot = fsl_esai_set_dai_tdm_slot,
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@ -911,6 +1129,8 @@ static int fsl_esai_probe(struct platform_device *pdev)
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int irq, ret;
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u32 buffer_size;
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unsigned long irqflag = 0;
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int *buffer;
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int i;
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esai_priv = devm_kzalloc(&pdev->dev, sizeof(*esai_priv), GFP_KERNEL);
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if (!esai_priv)
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@ -995,13 +1215,22 @@ static int fsl_esai_probe(struct platform_device *pdev)
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/* From imx6ull, the channel swap issue in underrun/overrun is
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* fixed in hardware. So remove the workaround.
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*/
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if (!of_device_is_compatible(pdev->dev.of_node, "fsl,imx6ull-esai")) {
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if (of_device_is_compatible(pdev->dev.of_node, "fsl,imx35-esai") ||
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of_device_is_compatible(pdev->dev.of_node, "fsl,vf610-esai")) {
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esai_priv->dma_params_tx.check_xrun = fsl_esai_check_xrun;
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esai_priv->dma_params_rx.check_xrun = fsl_esai_check_xrun;
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esai_priv->dma_params_tx.device_reset = fsl_esai_reset;
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esai_priv->dma_params_rx.device_reset = fsl_esai_reset;
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}
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/* In imx8qxp rev1, the dma request signal is not revert. For esai
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* dma request is low valid, but edma assert it as high level valid.
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* so we need to use GPT to transfer the dma request signal.
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*
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*/
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if (of_device_is_compatible(pdev->dev.of_node, "fsl,imx8qxp-v1-esai"))
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esai_priv->dma_workaround = true;
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esai_priv->synchronous =
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of_property_read_bool(np, "fsl,esai-synchronous");
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@ -1047,6 +1276,67 @@ static int fsl_esai_probe(struct platform_device *pdev)
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if (of_property_read_u32(np, "fsl,dma-buffer-size", &buffer_size))
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buffer_size = IMX_ESAI_DMABUF_SIZE;
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/*workaround for esai issue in imx8qxp*/
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if (esai_priv->dma_workaround) {
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esai_priv->tcd_pool = dma_pool_create("tcd_pool_esai",
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&esai_priv->pdev->dev,
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sizeof(struct fsl_edma3_hw_tcd), 32, 0);
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esai_priv->buf.area = dma_alloc_writecombine(
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&esai_priv->pdev->dev,
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0x1000,
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&esai_priv->buf.addr, GFP_KERNEL);
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buffer = (int *)esai_priv->buf.area;
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buffer[0] = 0x8;
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esai_priv->tcd_sw[0].vtcd = dma_pool_alloc(esai_priv->tcd_pool,
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GFP_ATOMIC, &esai_priv->tcd_sw[0].ptcd);
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esai_priv->tcd_sw[1].vtcd = dma_pool_alloc(esai_priv->tcd_pool,
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GFP_ATOMIC, &esai_priv->tcd_sw[1].ptcd);
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esai_priv->tcd_sw[2].vtcd = dma_pool_alloc(esai_priv->tcd_pool,
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GFP_ATOMIC, &esai_priv->tcd_sw[2].ptcd);
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esai_priv->tcd_sw[3].vtcd = dma_pool_alloc(esai_priv->tcd_pool,
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GFP_ATOMIC, &esai_priv->tcd_sw[3].ptcd);
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for (i = 0; i < 4; i++) {
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esai_priv->tcd_sw[i].vtcd->saddr = esai_priv->buf.addr;
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esai_priv->tcd_sw[i].vtcd->attr = 0x0202;
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esai_priv->tcd_sw[i].vtcd->soff = 0x0;
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esai_priv->tcd_sw[i].vtcd->nbytes = 0x4;
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esai_priv->tcd_sw[i].vtcd->slast = 0x0;
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esai_priv->tcd_sw[i].vtcd->citer = 0x1;
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esai_priv->tcd_sw[i].vtcd->biter = 0x1;
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esai_priv->tcd_sw[i].vtcd->doff = 0x0;
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esai_priv->tcd_sw[i].vtcd->csr = 0x10;
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}
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|
||||
esai_priv->tcd_sw[0].vtcd->daddr = GPT5_ADDR + GPT_SR;
|
||||
esai_priv->tcd_sw[1].vtcd->daddr = GPT6_ADDR + GPT_SR;
|
||||
esai_priv->tcd_sw[2].vtcd->daddr = GPT7_ADDR + GPT_SR;
|
||||
esai_priv->tcd_sw[3].vtcd->daddr = GPT8_ADDR + GPT_SR;
|
||||
|
||||
esai_priv->tcd_sw[0].vtcd->dlast_sga =
|
||||
esai_priv->tcd_sw[1].ptcd;
|
||||
esai_priv->tcd_sw[1].vtcd->dlast_sga =
|
||||
esai_priv->tcd_sw[0].ptcd;
|
||||
esai_priv->tcd_sw[2].vtcd->dlast_sga =
|
||||
esai_priv->tcd_sw[3].ptcd;
|
||||
esai_priv->tcd_sw[3].vtcd->dlast_sga =
|
||||
esai_priv->tcd_sw[2].ptcd;
|
||||
|
||||
esai_priv->base_gpt0 = ioremap(GPT5_ADDR, SZ_64K);
|
||||
esai_priv->base_gpt1 = ioremap(GPT6_ADDR, SZ_64K);
|
||||
esai_priv->base_gpt2 = ioremap(GPT7_ADDR, SZ_64K);
|
||||
esai_priv->base_gpt3 = ioremap(GPT8_ADDR, SZ_64K);
|
||||
|
||||
esai_priv->base_edma_gpt1 = ioremap(EDMA_GPT6_ADDR, SZ_64K);
|
||||
esai_priv->base_edma_gpt3 = ioremap(EDMA_GPT8_ADDR, SZ_64K);
|
||||
|
||||
esai_priv->base_acm = of_iomap(of_find_compatible_node(
|
||||
NULL, NULL, "nxp,imx8qm-acm"), 0);
|
||||
}
|
||||
|
||||
ret = imx_pcm_platform_register(&pdev->dev);
|
||||
if (ret)
|
||||
dev_err(&pdev->dev, "failed to init imx pcm dma: %d\n", ret);
|
||||
@ -1054,7 +1344,37 @@ static int fsl_esai_probe(struct platform_device *pdev)
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int fsl_esai_remove(struct platform_device *pdev)
|
||||
{
|
||||
struct fsl_esai *esai_priv = dev_get_drvdata(&pdev->dev);
|
||||
|
||||
if (esai_priv->dma_workaround) {
|
||||
dma_free_writecombine(&esai_priv->pdev->dev,
|
||||
0x1000,
|
||||
esai_priv->buf.area,
|
||||
esai_priv->buf.addr);
|
||||
|
||||
dma_pool_free(esai_priv->tcd_pool,
|
||||
esai_priv->tcd_sw[0].vtcd,
|
||||
esai_priv->tcd_sw[0].ptcd);
|
||||
dma_pool_free(esai_priv->tcd_pool,
|
||||
esai_priv->tcd_sw[1].vtcd,
|
||||
esai_priv->tcd_sw[1].ptcd);
|
||||
dma_pool_free(esai_priv->tcd_pool,
|
||||
esai_priv->tcd_sw[2].vtcd,
|
||||
esai_priv->tcd_sw[2].ptcd);
|
||||
dma_pool_free(esai_priv->tcd_pool,
|
||||
esai_priv->tcd_sw[3].vtcd,
|
||||
esai_priv->tcd_sw[3].ptcd);
|
||||
|
||||
dma_pool_destroy(esai_priv->tcd_pool);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct of_device_id fsl_esai_dt_ids[] = {
|
||||
{ .compatible = "fsl,imx8qxp-v1-esai", },
|
||||
{ .compatible = "fsl,imx6ull-esai", },
|
||||
{ .compatible = "fsl,imx35-esai", },
|
||||
{ .compatible = "fsl,vf610-esai", },
|
||||
@ -1104,6 +1424,7 @@ static const struct dev_pm_ops fsl_esai_pm_ops = {
|
||||
|
||||
static struct platform_driver fsl_esai_driver = {
|
||||
.probe = fsl_esai_probe,
|
||||
.remove = fsl_esai_remove,
|
||||
.driver = {
|
||||
.name = "fsl-esai-dai",
|
||||
.pm = &fsl_esai_pm_ops,
|
||||
|
||||
Reference in New Issue
Block a user