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MLK-15473-1: crypto: caam: Add CAAM driver support for iMX8 soc family

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Enable CAAM driver for i.MX8 family:
	- Use a Job ring for RNG instantiation rather than DECO, even
     for i.MX6/7 families.
	- Use of aliased CAAM registers instead of original registers in page 0
     since page 0 is no more accessible in i.MX8 family except mScale.

Signed-off-by: Aymen Sghaier <aymen.sghaier@nxp.com>
(Vipul: Fixed merge conflicts)
Signed-off-by: Vipul Kumar <vipul_kumar@mentor.com>
This commit is contained in:
Franck LENORMAND
2018-07-03 13:27:23 +02:00
committed by Leonard Crestez
parent bcdbdc15c7
commit 41cf3d4c58
10 changed files with 628 additions and 465 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
Documentation/devicetree/bindings/crypto/fsl-sec4.txt
View File

@ -54,7 +54,7 @@ PROPERTIES
- compatible
Usage: required
Value type: <string>
Definition: Must include "fsl,sec-v4.0"
Definition: Must include "fsl,sec-v4.0" or "fsl,sec4.0"
- fsl,sec-era
Usage: optional

10
drivers/crypto/caam/caamalg.c
View File

@ -3598,8 +3598,14 @@ static int __init caam_algapi_init(void)
* Register crypto algorithms the device supports.
* First, detect presence and attributes of DES, AES, and MD blocks.
*/
cha_vid = rd_reg32(&priv->ctrl->perfmon.cha_id_ls);
cha_inst = rd_reg32(&priv->ctrl->perfmon.cha_num_ls);
if (priv->has_seco) {
i = priv->first_jr_index;
cha_vid = rd_reg32(&priv->jr[i]->perfmon.cha_id_ls);
cha_inst = rd_reg32(&priv->jr[i]->perfmon.cha_num_ls);
} else {
cha_vid = rd_reg32(&priv->ctrl->perfmon.cha_id_ls);
cha_inst = rd_reg32(&priv->ctrl->perfmon.cha_num_ls);
}
des_inst = (cha_inst & CHA_ID_LS_DES_MASK) >> CHA_ID_LS_DES_SHIFT;
aes_inst = (cha_inst & CHA_ID_LS_AES_MASK) >> CHA_ID_LS_AES_SHIFT;
md_inst = (cha_inst & CHA_ID_LS_MD_MASK) >> CHA_ID_LS_MD_SHIFT;

12
drivers/crypto/caam/caamhash.c
View File

@ -1,7 +1,7 @@
/*
* caam - Freescale FSL CAAM support for ahash functions of crypto API
*
* Copyright 2011 Freescale Semiconductor, Inc.
* Copyright (C) 2017 Freescale Semiconductor, Inc.
*
* Based on caamalg.c crypto API driver.
*
@ -2129,8 +2129,14 @@ static int __init caam_algapi_hash_init(void)
* Register crypto algorithms the device supports. First, identify
* presence and attributes of MD block.
*/
cha_vid = rd_reg32(&priv->ctrl->perfmon.cha_id_ls);
cha_inst = rd_reg32(&priv->ctrl->perfmon.cha_num_ls);
if (priv->has_seco) {
i = priv->first_jr_index;
cha_vid = rd_reg32(&priv->jr[i]->perfmon.cha_id_ls);
cha_inst = rd_reg32(&priv->jr[i]->perfmon.cha_num_ls);
} else {
cha_vid = rd_reg32(&priv->ctrl->perfmon.cha_id_ls);
cha_inst = rd_reg32(&priv->ctrl->perfmon.cha_num_ls);
}
/*
* Skip registration of any hashing algorithms if MD block

10
drivers/crypto/caam/caampkc.c
View File

@ -1,7 +1,7 @@
/*
* caam - Freescale FSL CAAM support for Public Key Cryptography
*
* Copyright 2016 Freescale Semiconductor, Inc.
* Copyright (C) 2017 Freescale Semiconductor, Inc.
*
* There is no Shared Descriptor for PKC so that the Job Descriptor must carry
* all the desired key parameters, input and output pointers.
@ -1044,7 +1044,13 @@ static int __init caam_pkc_init(void)
return -ENODEV;
/* Determine public key hardware accelerator presence. */
cha_inst = rd_reg32(&priv->ctrl->perfmon.cha_num_ls);
if (priv->has_seco) {
int i = priv->first_jr_index;
cha_inst = rd_reg32(&priv->jr[i]->perfmon.cha_num_ls);
} else {
cha_inst = rd_reg32(&priv->ctrl->perfmon.cha_num_ls);
}
pk_inst = (cha_inst & CHA_ID_LS_PK_MASK) >> CHA_ID_LS_PK_SHIFT;
/* Do not register algorithms if PKHA is not present. */

10
drivers/crypto/caam/caamrng.c
View File

@ -352,6 +352,7 @@ static int __init caam_rng_init(void)
struct device *ctrldev;
struct caam_drv_private *priv;
int err;
u32 cha_inst;
dev_node = of_find_compatible_node(NULL, NULL, "fsl,sec-v4.0");
if (!dev_node) {
@ -378,7 +379,14 @@ static int __init caam_rng_init(void)
return -ENODEV;
/* Check for an instantiated RNG before registration */
if (!(rd_reg32(&priv->ctrl->perfmon.cha_num_ls) & CHA_ID_LS_RNG_MASK))
if (priv->has_seco) {
int i = priv->first_jr_index;
cha_inst = rd_reg32(&priv->jr[i]->perfmon.cha_num_ls);
} else {
cha_inst = rd_reg32(&priv->ctrl->perfmon.cha_num_ls);
}
if (!(cha_inst & CHA_ID_LS_RNG_MASK))
return -ENODEV;
dev = caam_jr_alloc();

984
drivers/crypto/caam/ctrl.c
View File

File diff suppressed because it is too large Load Diff

30
drivers/crypto/caam/desc_constr.h
View File

@ -2,7 +2,7 @@
/*
* caam descriptor construction helper functions
*
* Copyright 2008-2012 Freescale Semiconductor, Inc.
* Copyright 2008-2017 Freescale Semiconductor, Inc.
*/
#ifndef DESC_CONSTR_H
@ -13,7 +13,8 @@
#define IMMEDIATE (1 << 23)
#define CAAM_CMD_SZ sizeof(u32)
#define CAAM_PTR_SZ sizeof(dma_addr_t)
/* CAAM Pointer Size in MCFGR[PS] is 0 by default (32bits) */
#define CAAM_PTR_SZ sizeof(u32)
#define CAAM_DESC_BYTES_MAX (CAAM_CMD_SZ * MAX_CAAM_DESCSIZE)
#define DESC_JOB_IO_LEN (CAAM_CMD_SZ * 5 + CAAM_PTR_SZ * 3)
@ -90,9 +91,10 @@ static inline void init_job_desc_pdb(u32 * const desc, u32 options,
init_job_desc(desc, (((pdb_len + 1) << HDR_START_IDX_SHIFT)) | options);
}
static inline void append_ptr(u32 * const desc, dma_addr_t ptr)
static inline void append_ptr(u32 * const desc, u32 ptr)
{
dma_addr_t *offset = (dma_addr_t *)desc_end(desc);
u32 *offset = (u32 *)desc_end(desc);
*offset = cpu_to_caam_dma(ptr);
@ -100,7 +102,7 @@ static inline void append_ptr(u32 * const desc, dma_addr_t ptr)
CAAM_PTR_SZ / CAAM_CMD_SZ);
}
static inline void init_job_desc_shared(u32 * const desc, dma_addr_t ptr,
static inline void init_job_desc_shared(u32 * const desc, u32 ptr,
int len, u32 options)
{
PRINT_POS;
@ -155,7 +157,7 @@ static inline u32 *write_cmd(u32 * const desc, u32 command)
return desc + 1;
}
static inline void append_cmd_ptr(u32 * const desc, dma_addr_t ptr, int len,
static inline void append_cmd_ptr(u32 * const desc, u32 ptr, int len,
u32 command)
{
append_cmd(desc, command | len);
@ -163,7 +165,7 @@ static inline void append_cmd_ptr(u32 * const desc, dma_addr_t ptr, int len,
}
/* Write length after pointer, rather than inside command */
static inline void append_cmd_ptr_extlen(u32 * const desc, dma_addr_t ptr,
static inline void append_cmd_ptr_extlen(u32 * const desc, u32 ptr,
unsigned int len, u32 command)
{
append_cmd(desc, command);
@ -227,7 +229,7 @@ APPEND_CMD_LEN(seq_fifo_load, SEQ_FIFO_LOAD)
APPEND_CMD_LEN(seq_fifo_store, SEQ_FIFO_STORE)
#define APPEND_CMD_PTR(cmd, op) \
static inline void append_##cmd(u32 * const desc, dma_addr_t ptr, \
static inline void append_##cmd(u32 * const desc, u32 ptr, \
unsigned int len, u32 options) \
{ \
PRINT_POS; \
@ -238,7 +240,7 @@ APPEND_CMD_PTR(load, LOAD)
APPEND_CMD_PTR(fifo_load, FIFO_LOAD)
APPEND_CMD_PTR(fifo_store, FIFO_STORE)
static inline void append_store(u32 * const desc, dma_addr_t ptr,
static inline void append_store(u32 * const desc, u32 ptr,
unsigned int len, u32 options)
{
u32 cmd_src;
@ -257,7 +259,7 @@ static inline void append_store(u32 * const desc, dma_addr_t ptr,
#define APPEND_SEQ_PTR_INTLEN(cmd, op) \
static inline void append_seq_##cmd##_ptr_intlen(u32 * const desc, \
dma_addr_t ptr, \
u32 ptr, \
unsigned int len, \
u32 options) \
{ \
@ -281,7 +283,7 @@ APPEND_CMD_PTR_TO_IMM(load, LOAD);
APPEND_CMD_PTR_TO_IMM(fifo_load, FIFO_LOAD);
#define APPEND_CMD_PTR_EXTLEN(cmd, op) \
static inline void append_##cmd##_extlen(u32 * const desc, dma_addr_t ptr, \
static inline void append_##cmd##_extlen(u32 * const desc, u32 ptr, \
unsigned int len, u32 options) \
{ \
PRINT_POS; \
@ -295,7 +297,7 @@ APPEND_CMD_PTR_EXTLEN(seq_out_ptr, SEQ_OUT_PTR)
* the size of its type
*/
#define APPEND_CMD_PTR_LEN(cmd, op, type) \
static inline void append_##cmd(u32 * const desc, dma_addr_t ptr, \
static inline void append_##cmd(u32 * const desc, u32 ptr, \
type len, u32 options) \
{ \
PRINT_POS; \
@ -451,8 +453,8 @@ struct alginfo {
unsigned int keylen;
unsigned int keylen_pad;
union {
dma_addr_t key_dma;
const void *key_virt;
caam_dma_addr_t key_dma;
void *key_virt;
};
bool key_inline;
};

24
drivers/crypto/caam/intern.h
View File

@ -3,7 +3,7 @@
* CAAM/SEC 4.x driver backend
* Private/internal definitions between modules
*
* Copyright 2008-2011 Freescale Semiconductor, Inc.
* Copyright 2008-2017 Freescale Semiconductor, Inc.
*
*/
@ -13,6 +13,9 @@
/* Currently comes from Kconfig param as a ^2 (driver-required) */
#define JOBR_DEPTH (1 << CONFIG_CRYPTO_DEV_FSL_CAAM_RINGSIZE)
/* Job ring count */
#define JOBR_MAX_COUNT 4
/* Kconfig params for interrupt coalescing if selected (else zero) */
#ifdef CONFIG_CRYPTO_DEV_FSL_CAAM_INTC
#define JOBR_INTC JRCFG_ICEN
@ -32,7 +35,8 @@ struct caam_jrentry_info {
void (*callbk)(struct device *dev, u32 *desc, u32 status, void *arg);
void *cbkarg; /* Argument per ring entry */
u32 *desc_addr_virt; /* Stored virt addr for postprocessing */
dma_addr_t desc_addr_dma; /* Stored bus addr for done matching */
/* CAAM Pointer Size in MCFGR[PS] is 0 by default (32bits) */
u32 desc_addr_dma; /* Stored bus addr for done matching */
u32 desc_size; /* Stored size for postprocessing, header derived */
};
@ -54,7 +58,8 @@ struct caam_drv_private_jr {
spinlock_t inplock ____cacheline_aligned; /* Input ring index lock */
int inp_ring_write_index; /* Input index "tail" */
int head; /* entinfo (s/w ring) head index */
dma_addr_t *inpring; /* Base of input ring, alloc DMA-safe */
/* CAAM Pointer Size in MCFGR[PS] is 0 by default (32bits) */
u32 *inpring; /* Base of input ring, alloc DMA-safe */
spinlock_t outlock ____cacheline_aligned; /* Output ring index lock */
int out_ring_read_index; /* Output index "tail" */
int tail; /* entinfo (s/w ring) tail index */
@ -68,7 +73,8 @@ struct caam_drv_private {
#ifdef CONFIG_CAAM_QI
struct device *qidev;
#endif
struct device *dev;
struct platform_device *pdev;
struct device *smdev;
/*
@ -83,7 +89,8 @@ struct caam_drv_private {
struct caam_deco __iomem *deco; /* DECO/CCB views */
struct caam_assurance __iomem *assure;
struct caam_queue_if __iomem *qi; /* QI control region */
struct caam_job_ring __iomem *jr[4]; /* JobR's register space */
/* JobR's register space */
struct caam_job_ring __iomem *jr[JOBR_MAX_COUNT];
dma_addr_t __iomem *sm_base; /* Secure memory storage base */
u32 sm_size;
@ -108,6 +115,8 @@ struct caam_drv_private {
struct clk *caam_aclk;
struct clk *caam_emi_slow;
bool has_seco;
u32 first_jr_index;
/*
* debugfs entries for developer view into driver/device
* variables at runtime.
@ -115,6 +124,11 @@ struct caam_drv_private {
#ifdef CONFIG_DEBUG_FS
struct dentry *dfs_root;
struct dentry *ctl; /* controller dir */
struct dentry *ctl_rq_dequeued, *ctl_ob_enc_req, *ctl_ib_dec_req;
struct dentry *ctl_ob_enc_bytes, *ctl_ob_prot_bytes;
struct dentry *ctl_ib_dec_bytes, *ctl_ib_valid_bytes;
struct dentry *ctl_faultaddr, *ctl_faultdetail, *ctl_faultstatus;
struct debugfs_blob_wrapper ctl_kek_wrap, ctl_tkek_wrap, ctl_tdsk_wrap;
struct dentry *ctl_kek, *ctl_tkek, *ctl_tdsk;
#endif

2
drivers/crypto/caam/jr.c
View File

@ -2,7 +2,7 @@
* CAAM/SEC 4.x transport/backend driver
* JobR backend functionality
*
* Copyright 2008-2015 Freescale Semiconductor, Inc.
* Copyright 2008-2017 Freescale Semiconductor, Inc.
*/
#include <linux/of_irq.h>

9
drivers/crypto/caam/regs.h
View File

@ -2,7 +2,7 @@
/*
* CAAM hardware register-level view
*
* Copyright 2008-2011 Freescale Semiconductor, Inc.
* Copyright 2008-2017 Freescale Semiconductor, Inc.
*/
#ifndef REGS_H
@ -136,7 +136,7 @@ static inline void clrsetbits_32(void __iomem *reg, u32 clear, u32 set)
* base + 0x0000 : least-significant 32 bits
* base + 0x0004 : most-significant 32 bits
*/
#ifdef CONFIG_64BIT
#if defined(CONFIG_64BIT) && !(defined(CONFIG_HAVE_IMX8_SOC))
static inline void wr_reg64(void __iomem *reg, u64 data)
{
if (caam_little_end)
@ -194,7 +194,7 @@ static inline u64 caam_dma64_to_cpu(u64 value)
return caam64_to_cpu(value);
}
#ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
#if defined(CONFIG_ARCH_DMA_ADDR_T_64BIT) && !defined(CONFIG_HAVE_IMX8_SOC)
#define cpu_to_caam_dma(value) cpu_to_caam_dma64(value)
#define caam_dma_to_cpu(value) caam_dma64_to_cpu(value)
#else
@ -207,7 +207,8 @@ static inline u64 caam_dma64_to_cpu(u64 value)
* Represents each entry in a JobR output ring
*/
struct jr_outentry {
dma_addr_t desc;/* Pointer to completed descriptor */
/* CAAM Pointer Size in MCFGR[PS] is 0 by default (32bits) */
u32 desc;/* Pointer to completed descriptor */
u32 jrstatus; /* Status for completed descriptor */
} __packed;