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MLK-17317 arm: imx: add no_console_suspend support for i.mx7ulp vlls mode

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LPUART driver currently turns off clocks during device
suspend phase, but in i.MX7ULP platform low level suspend
routine, lpuart will be saved/restored during suspend/resume,
to avoid system hang caused by accessing lpuart registers
without clocks enable, add console_suspend_enabled check for
lpuart register save/restore.

SCG1 SOSCDIV register needs to be saved/restored anyway,
move it to asm code, all SCG1 registers will be restored
there.

Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Acked-by: Fugang Duan <fugang.duan@nxp.com>
Rviewed-by: Bai Ping <ping.bai@nxp.com>
This commit is contained in:
Anson Huang
2017-12-28 00:54:19 +08:00
parent 624786953e
commit 468f38d857
2 changed files with 24 additions and 16 deletions
Download Patch File Download Diff File Expand all files Collapse all files

15
arch/arm/mach-imx/pm-imx7ulp.c
View File

@ -11,6 +11,7 @@
*/
#include <linux/delay.h>
#include <linux/console.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/interrupt.h>
@ -155,11 +156,12 @@ static u32 pcc3_regs[16][2] = {
{0xc0, 0}, {0xc4, 0}, {0x140, 0}, {0x144, 0},
};
static u32 scg1_offset[16] = {
static u32 scg1_offset[17] = {
0x14, 0x30, 0x40, 0x304,
0x500, 0x504, 0x508, 0x50c,
0x510, 0x514, 0x600, 0x604,
0x608, 0x60c, 0x610, 0x614,
0x104,
};
extern unsigned long iram_tlb_base_addr;
@ -251,7 +253,7 @@ struct imx7ulp_cpu_pm_info {
void __iomem *mmdc_base;
void __iomem *mmdc_io_base;
void __iomem *smc1_base;
u32 scg1[16];
u32 scg1[17];
u32 ttbr1; /* Store TTBR1 */
u32 gpio[4][2];
u32 iomux_num; /* Number of IOs which need saved/restored. */
@ -290,7 +292,7 @@ static void imx7ulp_scg1_save(void)
{
int i;
for (i = 0; i < 16; i++)
for (i = 0; i < 17; i++)
pm_info->scg1[i] = readl_relaxed(scg1_base + scg1_offset[i]);
}
@ -353,7 +355,6 @@ static void imx7ulp_lpuart_save(void)
static void imx7ulp_lpuart_restore(void)
{
writel_relaxed(0x10101, scg1_base + 0x104);
writel_relaxed(LPUART4_MUX_VALUE,
iomuxc1_base + PTC2_LPUART4_TX_OFFSET);
writel_relaxed(LPUART4_MUX_VALUE,
@ -491,7 +492,8 @@ static int imx7ulp_pm_enter(suspend_state_t state)
imx7ulp_pcc2_save();
imx7ulp_pcc3_save();
imx7ulp_tpm_save();
imx7ulp_lpuart_save();
if (!console_suspend_enabled)
imx7ulp_lpuart_save();
imx7ulp_iomuxc_save();
imx7ulp_set_lpm(VLLS);
@ -500,7 +502,8 @@ static int imx7ulp_pm_enter(suspend_state_t state)
imx7ulp_pcc2_restore();
imx7ulp_pcc3_restore();
imx7ulp_lpuart_restore();
if (!console_suspend_enabled)
imx7ulp_lpuart_restore();
imx7ulp_set_dgo(0);
imx7ulp_tpm_restore();
imx7ulp_set_lpm(RUN);

25
arch/arm/mach-imx/suspend-imx7ulp.S
View File

@ -50,17 +50,17 @@
#define PM_INFO_PM_INFO_MMDC_IO_VBASE_OFFSET 0x24
#define PM_INFO_PM_INFO_SMC1_VBASE_OFFSET 0x28
#define PM_INFO_PM_INFO_SCG1_VAL_OFFSET 0x2c
#define PM_INFO_MX7ULP_TTBR1_V_OFFSET 0x6c
#define PM_INFO_MX7ULP_GPIO_REG_OFFSET 0x70
#define PM_INFO_IOMUX_NUM_OFFSET 0x90
#define PM_INFO_IOMUX_VAL_OFFSET 0x94
#define PM_INFO_SELECT_INPUT_NUM_OFFSET 0x264
#define PM_INFO_SELECT_INPUT_VAL_OFFSET 0x268
#define PM_INFO_MMDC_IO_NUM_OFFSET 0x3a0
#define PM_INFO_MMDC_IO_VAL_OFFSET 0x3a4
#define PM_INFO_MX7ULP_TTBR1_V_OFFSET 0x70
#define PM_INFO_MX7ULP_GPIO_REG_OFFSET 0x74
#define PM_INFO_IOMUX_NUM_OFFSET 0x94
#define PM_INFO_IOMUX_VAL_OFFSET 0x98
#define PM_INFO_SELECT_INPUT_NUM_OFFSET 0x268
#define PM_INFO_SELECT_INPUT_VAL_OFFSET 0x26c
#define PM_INFO_MMDC_IO_NUM_OFFSET 0x3a4
#define PM_INFO_MMDC_IO_VAL_OFFSET 0x3a8
/* below offsets depends on MX7ULP_MAX_MMDC_IO_NUM(36) definition */
#define PM_INFO_MMDC_NUM_OFFSET 0x4c4
#define PM_INFO_MMDC_VAL_OFFSET 0x4c8
#define PM_INFO_MMDC_NUM_OFFSET 0x4c8
#define PM_INFO_MMDC_VAL_OFFSET 0x4cc
#define DGO_CTRL0 0x50
#define DGO_GPR3 0x60
@ -527,6 +527,11 @@ resume:
ldr r7, [r0, r6]
str r7, [r11, #SCG_FIRCDIV]
/* restore system OSC div */
add r6, r5, #64
ldr r7, [r0, r6]
str r7, [r11, #SCG_SOSCDIV]
/* enable mmdc clock in pcc3 */
ldr r11, =MX7ULP_PCC3_BASE_ADDR
ldr r7, [r11, #0xac]