MLK-20252 ARM64: dts: correct imx8mm root memory
Correct the memory for root linux. Because rpmsg reserved memory, we could not support 2nd Linux now with the new memory. So remove the support for 2nd linux. Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Flynn xu <flynn.xu@nxp.com>
This commit is contained in:
Peng Fan
@ -1,224 +0,0 @@
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/*
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* Copyright 2018 NXP
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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/dts-v1/;
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#include "fsl-imx8mm.dtsi"
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/ {
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model = "Freescale i.MX8MM EVK";
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compatible = "fsl,imx8mm-evk", "fsl,imx8mm";
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interrupt-parent = <&gic>;
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timer {
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compatible = "arm,armv8-timer";
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interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, /* Physical Secure */
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<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, /* Physical Non-Secure */
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<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, /* Virtual */
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<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>; /* Hypervisor */
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clock-frequency = <8333333>;
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};
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clocks {
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clk_dummy: clock@7 {
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compatible = "fixed-clock";
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reg = <7>;
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#clock-cells = <0>;
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clock-frequency = <0>;
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clock-output-names = "clk_dummy";
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};
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/* The clocks are configured by 1st OS */
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clk_200m: clock@8 {
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compatible = "fixed-clock";
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reg = <8>;
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#clock-cells = <0>;
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clock-frequency = <200000000>;
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clock-output-names = "200m";
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};
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clk_266m: clock@9 {
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compatible = "fixed-clock";
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reg = <9>;
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#clock-cells = <0>;
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clock-frequency = <266000000>;
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clock-output-names = "266m";
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};
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clk_80m: clock@10 {
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compatible = "fixed-clock";
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reg = <10>;
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#clock-cells = <0>;
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clock-frequency = <80000000>;
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clock-output-names = "80m";
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};
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};
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display-subsystem {
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/delete-property/ compatible;
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};
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pci@bfb00000 {
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compatible = "pci-host-ecam-generic";
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device_type = "pci";
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bus-range = <0 0>;
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#address-cells = <3>;
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#size-cells = <2>;
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 0 7>;
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interrupt-map = <0 0 0 1 &gic GIC_SPI 76 IRQ_TYPE_EDGE_RISING>;
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reg = <0x0 0x7fb00000 0x0 0x100000>;
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ranges = <0x02000000 0x00 0x10000000 0x0 0x10000000 0x00 0x10000>;
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};
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};
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/delete-node/ &{/memory@40000000};
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/delete-node/ &{/reserved-memory};
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/delete-node/ &{/busfreq};
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/delete-node/ &ddr_pmu0;
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&hsio_pd {
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status = "disabled";
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};
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&pcie0_pd {
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status = "disabled";
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};
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&usb_otg1_pd {
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status = "disabled";
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};
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&usb_otg2_pd {
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status = "disabled";
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};
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&gpumix_pd {
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status = "disabled";
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};
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&vpumix_pd {
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status = "disabled";
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};
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&vpu_g1_pd {
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status = "disabled";
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};
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&vpu_g2_pd {
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status = "disabled";
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};
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&vpu_h1_pd {
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status = "disabled";
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};
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&dispmix_pd {
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status = "disabled";
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};
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&mipi_pd {
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status = "disabled";
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};
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&gpio1 {
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status = "disabled";
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};
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&gpio2 {
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status = "disabled";
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};
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&gpio3 {
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status = "disabled";
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};
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&gpio4 {
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status = "disabled";
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};
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&gpio5 {
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status = "disabled";
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};
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/delete-node/ &tmu;
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/delete-node/ &{/thermal-zones};
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/delete-node/ &iomuxc;
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&gpr {
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/delete-property/ compatible;
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};
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/delete-node/ &anatop;
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/delete-node/ &snvs;
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&clk {
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/delete-property/ compatible;
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};
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&src {
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/delete-property/ compatible;
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};
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/delete-node/ &system_counter;
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/delete-node/ &imx_rpmsg;
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/delete-node/ &ocotp;
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&dispmix_gpr {
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/delete-property/ compatible;
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};
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&sdma1 {
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status = "disabled";
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};
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&sdma2 {
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status = "disabled";
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};
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&sdma3 {
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status = "disabled";
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};
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/delete-node/ &{/imx_ion};
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/delete-node/ &pcie0;
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/delete-node/ &crypto;
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/delete-node/ &caam_sm;
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/delete-node/ &caam_snvs;
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/delete-node/ &irq_sec_vio;
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/delete-node/ &{/cpus/cpu@0};
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/delete-node/ &{/cpus/cpu@1};
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/delete-node/ &{/pmu};
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&gic {
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reg = <0x0 0x38800000 0 0x10000>, /* GIC Dist */
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<0x0 0x38880000 0 0xC0000>; /* GICR (RD_base + SGI_base) */
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};
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&uart4 {
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clocks = <&osc_24m>,
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<&osc_24m>;
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clock-names = "ipg", "per";
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/delete-property/ dmas;
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/delete-property/ dmas-names;
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status = "okay";
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};
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&usdhc3 {
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clocks = <&clk_dummy>,
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<&clk_266m>,
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<&clk_200m>;
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/delete-property/assigned-clocks;
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/delete-property/assigned-clock-rates;
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clock-names = "ipg", "ahb", "per";
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bus-width = <8>;
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non-removable;
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status = "okay";
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};
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@ -26,33 +26,6 @@
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/*arm,psci-suspend-param = <0x0>;*/
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};
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&clk {
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init-on-array = <IMX8MM_CLK_AHB_CG IMX8MM_CLK_DRAM_CORE
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IMX8MM_CLK_NOC_CG IMX8MM_CLK_NOC_APB_CG
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IMX8MM_CLK_USB_BUS_CG
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IMX8MM_CLK_MAIN_AXI_CG IMX8MM_CLK_AUDIO_AHB_CG
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IMX8MM_CLK_DRAM_APB_DIV IMX8MM_CLK_A53_DIV
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IMX8MM_ARM_PLL_OUT IMX8MM_CLK_DISP_AXI_CG
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IMX8MM_CLK_DISP_APB_CG
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IMX8MM_CLK_NAND_USDHC_BUS_CG>;
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};
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&iomuxc {
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imx8mq-evk {
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/*
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* Used for the 2nd Linux.
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* TODO: M4 may use these pins.
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*/
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pinctrl_uart4: uart4grp {
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fsl,pins = <
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MX8MM_IOMUXC_UART4_RXD_UART4_DCE_RX 0x140
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MX8MM_IOMUXC_UART4_TXD_UART4_DCE_TX 0x140
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>;
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};
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};
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};
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&{/busfreq} {
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/* Disable busfreq, to avoid 1st Linux busfreq crash other inmates */
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status = "disabled";
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@ -64,46 +37,28 @@
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reg = <0 0xbfc00000 0x0 0x400000>;
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};
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inmate_reserved: inmate@0x80000000 {
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inmate_reserved: inmate@0xbbc00000 {
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no-map;
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reg = <0 0x80000000 0x0 0x3fc00000>;
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reg = <0 0xbbc00000 0x0 0x4000000>;
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};
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loader_reserved: loader@0x7ff00000 {
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ivshmem_reserved: ivshmem@0xbbb00000 {
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no-map;
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reg = <0 0x7ff00000 0x0 0x00100000>;
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reg = <0 0xbbb00000 0x0 0x00100000>;
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};
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ivshmem_reserved: ivshmem@0x7fe00000 {
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ivshmem2_reserved: ivshmem2@0xbba00000 {
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no-map;
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reg = <0 0x7fe00000 0x0 0x00100000>;
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reg = <0 0xbba00000 0x0 0x00100000>;
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};
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ivshmem2_reserved: ivshmem2@0x7fd00000 {
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pci_reserved: pci@0xbb800000 {
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no-map;
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reg = <0 0x7fd00000 0x0 0x00100000>;
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reg = <0 0xbb800000 0x0 0x00200000>;
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};
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pci_reserved: pci@0x7fb00000 {
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loader_reserved: loader@0xbb700000 {
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no-map;
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reg = <0 0x7fb00000 0x0 0x00200000>;
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reg = <0 0xbb700000 0x0 0x00100000>;
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};
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};
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&uart2 {
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/* uart2 is used by the 2nd OS, so configure pin and clk */
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pinctrl-0 = <&pinctrl_uart2>, <&pinctrl_uart4>;
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assigned-clocks = <&clk IMX8MM_CLK_UART4_SRC>;
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assigned-clock-parents = <&clk IMX8MM_CLK_24M>;
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};
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&usdhc3 {
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status = "disabled";
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};
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&usdhc2 {
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/* sdhc3 is used by 2nd linux, configure the pin */
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pinctrl-0 = <&pinctrl_usdhc3>, <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
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pinctrl-1 = <&pinctrl_usdhc3>, <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
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pinctrl-2 = <&pinctrl_usdhc3>, <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
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};
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