MLK-13911-10 clk: imx: imx8qm: add clk driver
Add i.MX8QM clock driver support. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Signed-off-by: Ranjani Vaidyanathan <Ranjani.Vaidyanathan@nxp.com> Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com> Signed-off-by: Adrian Alonso <adrian.alonso@nxp.com> Signed-off-by: Shengjiu Wang <shengjiu.wang@freescale.com>
This commit is contained in:
Anson Huang
@ -64,6 +64,7 @@ obj-$(CONFIG_H8300) += h8300/
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obj-$(CONFIG_ARCH_HISI) += hisilicon/
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obj-y += imgtec/
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obj-$(CONFIG_ARCH_MXC) += imx/
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obj-$(CONFIG_ARCH_FSL_IMX8QM) += imx/
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obj-$(CONFIG_MACH_INGENIC) += ingenic/
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obj-$(CONFIG_ARCH_KEYSTONE) += keystone/
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obj-$(CONFIG_MACH_LOONGSON32) += loongson1/
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@ -1,6 +1,6 @@
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# SPDX-License-Identifier: GPL-2.0
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obj-y += \
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obj-$(CONFIG_ARM) += \
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clk.o \
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clk-busy.o \
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clk-cpu.o \
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@ -34,3 +34,7 @@ obj-$(CONFIG_SOC_IMX6UL) += clk-imx6ul.o
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obj-$(CONFIG_SOC_IMX7D) += clk-imx7d.o
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obj-$(CONFIG_SOC_IMX7ULP) += clk-imx7ulp.o
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obj-$(CONFIG_SOC_VF610) += clk-vf610.o
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#
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# IMX Clock specific Makefile
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#
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obj-$(CONFIG_ARCH_FSL_IMX8QM) += clk-imx8qm.o clk-imx8.o clk-divider-scu.o clk-gate-scu.o clk-mux-scu.o
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235
drivers/clk/imx/clk-divider-scu.c
Normal file
235
drivers/clk/imx/clk-divider-scu.c
Normal file
@ -0,0 +1,235 @@
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/*
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* Copyright (C) 2016 Freescale Semiconductor, Inc.
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* Copyright 2017 NXP
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <linux/clk.h>
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#include <linux/clk-provider.h>
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#include <linux/err.h>
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#include <linux/io.h>
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#include <linux/jiffies.h>
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#include <linux/slab.h>
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#include <soc/imx8/sc/sci.h>
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#include "clk-imx8.h"
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struct clk_divider_scu {
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struct clk_divider div;
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sc_rsrc_t rsrc_id;
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sc_pm_clk_t clk_type;
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};
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struct clk_divider3_scu {
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struct clk_divider div;
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sc_rsrc_t rsrc_id;
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sc_ctrl_t gpr_id;
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};
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static inline struct clk_divider3_scu *to_clk_divider3_scu(struct clk_hw *hw)
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{
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struct clk_divider *div = container_of(hw, struct clk_divider, hw);
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return container_of(div, struct clk_divider3_scu, div);
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}
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static inline struct clk_divider_scu *to_clk_divider_scu(struct clk_hw *hw)
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{
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struct clk_divider *div = container_of(hw, struct clk_divider, hw);
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return container_of(div, struct clk_divider_scu, div);
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}
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static unsigned long clk_divider_scu_recalc_rate(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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struct clk_divider_scu *clk = to_clk_divider_scu(hw);
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sc_err_t sci_err;
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sc_pm_clock_rate_t rate = 0;
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if (!ccm_ipc_handle)
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return 0;
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sci_err = sc_pm_get_clock_rate(ccm_ipc_handle, clk->rsrc_id,
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clk->clk_type, &rate);
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return sci_err ? 0 : rate;
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}
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static long clk_divider_scu_round_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long *prate)
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{
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/* TODO */
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*prate = rate;
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return rate;
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}
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static int clk_divider_scu_set_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long parent_rate)
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{
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struct clk_divider_scu *clk = to_clk_divider_scu(hw);
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sc_err_t sci_err;
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if (!ccm_ipc_handle) {
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return -EAGAIN;
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}
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sci_err = sc_pm_set_clock_rate(ccm_ipc_handle, clk->rsrc_id,
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clk->clk_type, (sc_pm_clock_rate_t *)&rate);
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return sci_err ? -EINVAL : 0;
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}
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static struct clk_ops clk_divider_scu_ops = {
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.recalc_rate = clk_divider_scu_recalc_rate,
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.round_rate = clk_divider_scu_round_rate,
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.set_rate = clk_divider_scu_set_rate,
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};
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struct clk *imx_clk_divider_scu(const char *name,
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sc_rsrc_t rsrc_id, sc_pm_clk_t clk_type)
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{
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struct clk_divider_scu *div_clk;
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struct clk *clk;
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struct clk_init_data init;
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div_clk = kzalloc(sizeof(*div_clk), GFP_KERNEL);
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if (!div_clk)
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return ERR_PTR(-ENOMEM);
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div_clk->rsrc_id = rsrc_id;
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div_clk->clk_type = clk_type;
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init.name = name;
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init.ops = &clk_divider_scu_ops;
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init.flags = CLK_GET_RATE_NOCACHE;
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init.num_parents = 0;
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div_clk->div.hw.init = &init;
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clk = clk_register(NULL, &div_clk->div.hw);
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if (IS_ERR(clk))
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kfree(div_clk);
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return clk;
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}
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struct clk *imx_clk_divider2_scu(const char *name, const char *parent_name,
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sc_rsrc_t rsrc_id, sc_pm_clk_t clk_type)
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{
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struct clk_divider_scu *div_clk;
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struct clk *clk;
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struct clk_init_data init;
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div_clk = kzalloc(sizeof(*div_clk), GFP_KERNEL);
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if (!div_clk)
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return ERR_PTR(-ENOMEM);
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div_clk->rsrc_id = rsrc_id;
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div_clk->clk_type = clk_type;
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init.name = name;
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init.ops = &clk_divider_scu_ops;
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init.flags = CLK_GET_RATE_NOCACHE;
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init.parent_names = parent_name ? &parent_name : NULL;
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init.num_parents = parent_name ? 1 : 0;
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div_clk->div.hw.init = &init;
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clk = clk_register(NULL, &div_clk->div.hw);
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if (IS_ERR(clk))
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kfree(div_clk);
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return clk;
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}
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static unsigned long clk_divider3_scu_recalc_rate(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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struct clk_divider3_scu *clk = to_clk_divider3_scu(hw);
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uint32_t val;
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sc_err_t sci_err;
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sc_pm_clock_rate_t rate = 0;
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if (!ccm_ipc_handle)
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return 0;
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sci_err = sc_misc_get_control(ccm_ipc_handle, clk->rsrc_id,
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clk->gpr_id, &val);
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rate = (val) ? parent_rate / 2 : parent_rate;
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return sci_err ? 0 : rate;
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}
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static long clk_divider3_scu_round_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long *prate)
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{
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if (rate < *prate)
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rate = *prate / 2;
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else
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rate = *prate;
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return rate;
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}
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static int clk_divider3_scu_set_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long parent_rate)
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{
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struct clk_divider3_scu *clk = to_clk_divider3_scu(hw);
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uint32_t val;
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sc_err_t sci_err;
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if (!ccm_ipc_handle) {
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return -EAGAIN;
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}
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val = (rate < parent_rate) ? 1 : 0;
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sci_err = sc_misc_set_control(ccm_ipc_handle, clk->rsrc_id,
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clk->gpr_id, val);
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return sci_err ? -EINVAL : 0;
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}
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static struct clk_ops clk_divider3_scu_ops = {
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.recalc_rate = clk_divider3_scu_recalc_rate,
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.round_rate = clk_divider3_scu_round_rate,
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.set_rate = clk_divider3_scu_set_rate,
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};
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struct clk *imx_clk_divider3_scu(const char *name, const char *parent_name,
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sc_rsrc_t rsrc_id, sc_ctrl_t gpr_id)
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{
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struct clk_divider3_scu *div;
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struct clk *clk;
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struct clk_init_data init;
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div = kzalloc(sizeof(struct clk_divider3_scu), GFP_KERNEL);
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if (!div)
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return ERR_PTR(-ENOMEM);
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div->rsrc_id = rsrc_id;
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div->gpr_id = gpr_id;
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init.name = name;
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init.ops = &clk_divider3_scu_ops;
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init.flags = 0;
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init.parent_names = parent_name ? &parent_name : NULL;
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init.num_parents = parent_name ? 1 : 0;
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div->div.hw.init = &init;
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clk = clk_register(NULL, &div->div.hw);
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if (IS_ERR(clk))
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kfree(div);
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return clk;
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}
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395
drivers/clk/imx/clk-gate-scu.c
Normal file
395
drivers/clk/imx/clk-gate-scu.c
Normal file
@ -0,0 +1,395 @@
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/*
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* Copyright (C) 2016 Freescale Semiconductor, Inc.
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* Copyright 2017 NXP
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <linux/clk-provider.h>
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#include <linux/err.h>
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#include <linux/io.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/pm_domain.h>
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#include <linux/slab.h>
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#include <linux/string.h>
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#include <soc/imx8/sc/sci.h>
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#include "clk-imx8.h"
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/*
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* DOC: basic gatable clock which can gate and ungate it's ouput
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*
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* Traits of this clock:
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* prepare - clk_(un)prepare only ensures parent is (un)prepared
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* enable - clk_enable and clk_disable are functional & control gating
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* rate - inherits rate from parent. No clk_set_rate support
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* parent - fixed parent. No clk_set_parent support
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*/
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struct clk_gate_scu {
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struct clk_hw hw;
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void __iomem *reg;
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u8 bit_idx;
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bool hw_gate;
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u8 flags;
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spinlock_t *lock;
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sc_rsrc_t rsrc_id;
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sc_pm_clk_t clk_type;
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};
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struct clk_gate2_scu {
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struct clk_hw hw;
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void __iomem *reg;
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u8 bit_idx;
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u8 flags;
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spinlock_t *lock;
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char *pd_name;
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struct generic_pm_domain *pd;
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};
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struct clk_gate3_scu {
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struct clk_hw hw;
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spinlock_t *lock;
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sc_rsrc_t rsrc_id;
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sc_ctrl_t gpr_id;
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bool invert;
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};
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#define to_clk_gate_scu(_hw) container_of(_hw, struct clk_gate_scu, hw)
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#define to_clk_gate2_scu(_hw) container_of(_hw, struct clk_gate2_scu, hw)
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#define to_clk_gate3_scu(_hw) container_of(_hw, struct clk_gate3_scu, hw)
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/* Write to the LPCG bits. */
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static int clk_gate_scu_enable(struct clk_hw *hw)
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{
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struct clk_gate_scu *gate = to_clk_gate_scu(hw);
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u32 reg;
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if (!ccm_ipc_handle)
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return -1;
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if (gate->reg) {
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reg = readl(gate->reg);
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if (gate->hw_gate)
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reg |= (0x3 << gate->bit_idx);
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else
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reg |= (0x2 << gate->bit_idx);
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writel(reg, gate->reg);
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}
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return 0;
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}
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/* Write to the LPCG bits. */
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static void clk_gate_scu_disable(struct clk_hw *hw)
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{
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struct clk_gate_scu *gate = to_clk_gate_scu(hw);
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u32 reg;
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if (!ccm_ipc_handle)
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return;
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if (gate->reg) {
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reg = readl(gate->reg);
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if (gate->hw_gate)
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reg &= ~(0x3 << gate->bit_idx);
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else
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reg &= ~(0x2 << gate->bit_idx);
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writel(reg, gate->reg);
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}
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}
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static int clk_gate_scu_prepare(struct clk_hw *hw)
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{
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struct clk_gate_scu *gate = to_clk_gate_scu(hw);
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sc_err_t sci_err = SC_ERR_NONE;
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if (!ccm_ipc_handle)
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return -1;
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/* Enable the clock at the DSC slice level */
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sci_err = sc_pm_clock_enable(ccm_ipc_handle, gate->rsrc_id,
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gate->clk_type, true, gate->hw_gate);
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return sci_err;
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}
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static void clk_gate_scu_unprepare(struct clk_hw *hw)
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{
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struct clk_gate_scu *gate = to_clk_gate_scu(hw);
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sc_err_t sci_err;
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if (!ccm_ipc_handle)
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return;
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sci_err = sc_pm_clock_enable(ccm_ipc_handle, gate->rsrc_id,
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gate->clk_type, false, false);
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if (sci_err)
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pr_err("clk gate scu unprepare clk fail!\n");
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}
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static struct clk_ops clk_gate_scu_ops = {
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.prepare = clk_gate_scu_prepare,
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.unprepare = clk_gate_scu_unprepare,
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.enable = clk_gate_scu_enable,
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.disable = clk_gate_scu_disable,
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};
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struct clk *clk_register_gate_scu(struct device *dev, const char *name,
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const char *parent_name, unsigned long flags,
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u8 clk_gate_scu_flags, spinlock_t *lock,
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sc_rsrc_t rsrc_id, sc_pm_clk_t clk_type,
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void __iomem *reg, u8 bit_idx, bool hw_gate)
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{
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struct clk_gate_scu *gate;
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struct clk *clk;
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struct clk_init_data init;
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gate = kzalloc(sizeof(struct clk_gate_scu), GFP_KERNEL);
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if (!gate)
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return ERR_PTR(-ENOMEM);
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/* struct clk_gate_scu assignments */
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gate->flags = clk_gate_scu_flags;
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gate->lock = lock;
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gate->rsrc_id = rsrc_id;
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gate->clk_type = clk_type;
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if (reg != NULL)
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gate->reg = ioremap((phys_addr_t)reg, SZ_64K);
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else
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gate->reg = NULL;
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gate->bit_idx = bit_idx;
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gate->hw_gate = hw_gate;
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init.name = name;
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init.ops = &clk_gate_scu_ops;
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init.flags = flags;
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init.parent_names = parent_name ? &parent_name : NULL;
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init.num_parents = parent_name ? 1 : 0;
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gate->hw.init = &init;
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clk = clk_register(dev, &gate->hw);
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if (IS_ERR(clk)) {
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iounmap(gate->reg);
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kfree(gate);
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}
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return clk;
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}
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/* Get the power domain associated with the clock from the device tree. */
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static void populate_gate_pd(struct clk_gate2_scu *clk)
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{
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struct device_node *np;
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struct of_phandle_args pd_args;
|
||||
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np = of_find_node_by_name(NULL, clk->pd_name);
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if (np) {
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pd_args.np = np;
|
||||
pd_args.args_count = 0;
|
||||
of_genpd_add_provider_simple(np, clk->pd);
|
||||
}
|
||||
return;
|
||||
}
|
||||
|
||||
/* Write to the LPCG bits. */
|
||||
static int clk_gate2_scu_enable(struct clk_hw *hw)
|
||||
{
|
||||
struct clk_gate2_scu *gate = to_clk_gate2_scu(hw);
|
||||
u32 reg;
|
||||
|
||||
if (!ccm_ipc_handle)
|
||||
return -1;
|
||||
|
||||
if (gate->pd == NULL && gate->pd_name)
|
||||
populate_gate_pd(gate);
|
||||
|
||||
if (!gate->pd)
|
||||
return -1;
|
||||
|
||||
if (gate->pd->status != GPD_STATE_ACTIVE)
|
||||
return -1;
|
||||
|
||||
if (gate->reg) {
|
||||
reg = readl(gate->reg);
|
||||
reg |= (0x2 << gate->bit_idx);
|
||||
writel(reg, gate->reg);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* Write to the LPCG bits. */
|
||||
static void clk_gate2_scu_disable(struct clk_hw *hw)
|
||||
{
|
||||
struct clk_gate2_scu *gate = to_clk_gate2_scu(hw);
|
||||
u32 reg;
|
||||
|
||||
if (!ccm_ipc_handle)
|
||||
return;
|
||||
|
||||
if (gate->pd == NULL && gate->pd_name)
|
||||
populate_gate_pd(gate);
|
||||
|
||||
if (!gate->pd)
|
||||
return;
|
||||
|
||||
if (gate->pd->status != GPD_STATE_ACTIVE)
|
||||
return;
|
||||
|
||||
if (gate->reg) {
|
||||
reg = readl(gate->reg);
|
||||
reg &= ~(0x2 << gate->bit_idx);
|
||||
writel(reg, gate->reg);
|
||||
}
|
||||
}
|
||||
|
||||
static int clk_gate2_scu_is_enabled(struct clk_hw *hw)
|
||||
{
|
||||
struct clk_gate2_scu *gate = to_clk_gate2_scu(hw);
|
||||
u32 val;
|
||||
|
||||
if (gate->pd == NULL && gate->pd_name)
|
||||
populate_gate_pd(gate);
|
||||
|
||||
if (!gate->pd)
|
||||
return 0;
|
||||
|
||||
if (gate->pd->status != GPD_STATE_ACTIVE)
|
||||
return 0;
|
||||
|
||||
val = readl(gate->reg);
|
||||
|
||||
if (((val >> gate->bit_idx) & 2) == 2)
|
||||
return 1;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
static struct clk_ops clk_gate2_scu_ops = {
|
||||
.enable = clk_gate2_scu_enable,
|
||||
.disable = clk_gate2_scu_disable,
|
||||
.is_enabled = clk_gate2_scu_is_enabled,
|
||||
};
|
||||
|
||||
struct clk *clk_register_gate2_scu(struct device *dev, const char *name,
|
||||
const char *parent_name, unsigned long flags,
|
||||
void __iomem *reg, u8 bit_idx,
|
||||
u8 clk_gate_flags, spinlock_t *lock, const char *pd_name)
|
||||
{
|
||||
struct clk_gate2_scu *gate;
|
||||
struct clk *clk;
|
||||
struct clk_init_data init;
|
||||
|
||||
gate = kzalloc(sizeof(struct clk_gate2_scu), GFP_KERNEL);
|
||||
if (!gate)
|
||||
return ERR_PTR(-ENOMEM);
|
||||
|
||||
/* struct clk_gate_scu assignments */
|
||||
gate->flags = clk_gate_flags;
|
||||
gate->lock = lock;
|
||||
if (reg != NULL)
|
||||
gate->reg = ioremap((phys_addr_t)reg, SZ_64K);
|
||||
else
|
||||
gate->reg = NULL;
|
||||
gate->bit_idx = bit_idx;
|
||||
gate->pd = NULL;
|
||||
gate->pd_name = NULL;
|
||||
if (pd_name) {
|
||||
gate->pd_name = kzalloc(strlen(pd_name) + 1, GFP_KERNEL);
|
||||
strcpy(gate->pd_name, pd_name);
|
||||
}
|
||||
|
||||
init.name = name;
|
||||
init.ops = &clk_gate2_scu_ops;
|
||||
init.flags = flags;
|
||||
init.parent_names = parent_name ? &parent_name : NULL;
|
||||
init.num_parents = parent_name ? 1 : 0;
|
||||
|
||||
gate->hw.init = &init;
|
||||
|
||||
clk = clk_register(dev, &gate->hw);
|
||||
if (IS_ERR(clk)) {
|
||||
iounmap(gate->reg);
|
||||
kfree(gate->pd_name);
|
||||
kfree(gate);
|
||||
}
|
||||
|
||||
return clk;
|
||||
}
|
||||
|
||||
static int clk_gate3_scu_enable(struct clk_hw *hw)
|
||||
{
|
||||
struct clk_gate3_scu *gate = to_clk_gate3_scu(hw);
|
||||
uint32_t val;
|
||||
|
||||
if (!ccm_ipc_handle)
|
||||
return -1;
|
||||
|
||||
val = (gate->invert) ? 0 : 1;
|
||||
|
||||
return sc_misc_set_control(ccm_ipc_handle,
|
||||
gate->rsrc_id, gate->gpr_id, val);
|
||||
}
|
||||
|
||||
/* Write to the LPCG bits. */
|
||||
static void clk_gate3_scu_disable(struct clk_hw *hw)
|
||||
{
|
||||
struct clk_gate3_scu *gate = to_clk_gate3_scu(hw);
|
||||
uint32_t val;
|
||||
|
||||
if (!ccm_ipc_handle)
|
||||
return;
|
||||
|
||||
val = (gate->invert) ? 1 : 0;
|
||||
sc_misc_set_control(ccm_ipc_handle, gate->rsrc_id, gate->gpr_id, val);
|
||||
}
|
||||
|
||||
static struct clk_ops clk_gate3_scu_ops = {
|
||||
.enable = clk_gate3_scu_enable,
|
||||
.disable = clk_gate3_scu_disable,
|
||||
};
|
||||
|
||||
struct clk *clk_register_gate3_scu(struct device *dev, const char *name,
|
||||
const char *parent_name, spinlock_t *lock,
|
||||
sc_rsrc_t rsrc_id, sc_ctrl_t gpr_id, bool invert_flag)
|
||||
{
|
||||
struct clk_gate3_scu *gate;
|
||||
struct clk *clk;
|
||||
struct clk_init_data init;
|
||||
|
||||
gate = kzalloc(sizeof(struct clk_gate_scu), GFP_KERNEL);
|
||||
if (!gate)
|
||||
return ERR_PTR(-ENOMEM);
|
||||
|
||||
/* struct clk_gate_scu assignments */
|
||||
gate->lock = lock;
|
||||
gate->rsrc_id = rsrc_id;
|
||||
gate->gpr_id = gpr_id;
|
||||
gate->invert = invert_flag;
|
||||
|
||||
init.name = name;
|
||||
init.ops = &clk_gate3_scu_ops;
|
||||
init.flags = 0;
|
||||
init.parent_names = parent_name ? &parent_name : NULL;
|
||||
init.num_parents = parent_name ? 1 : 0;
|
||||
|
||||
gate->hw.init = &init;
|
||||
|
||||
clk = clk_register(dev, &gate->hw);
|
||||
if (IS_ERR(clk))
|
||||
kfree(gate);
|
||||
|
||||
return clk;
|
||||
}
|
||||
45
drivers/clk/imx/clk-imx8.c
Normal file
45
drivers/clk/imx/clk-imx8.c
Normal file
@ -0,0 +1,45 @@
|
||||
/*
|
||||
* Copyright (C) 2016 Freescale Semiconductor, Inc.
|
||||
* Copyright 2017 NXP
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License
|
||||
* as published by the Free Software Foundation; either version 2
|
||||
* of the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <soc/imx8/sc/sci.h>
|
||||
|
||||
#include "clk-imx8.h"
|
||||
|
||||
spinlock_t imx_ccm_lock;
|
||||
sc_ipc_t ccm_ipc_handle;
|
||||
|
||||
static int __init notify_imx8_clk(void)
|
||||
{
|
||||
uint32_t mu_id;
|
||||
sc_err_t sciErr;
|
||||
|
||||
printk("MU and Power domains initialized\n");
|
||||
|
||||
sciErr = sc_ipc_getMuID(&mu_id);
|
||||
if (sciErr != SC_ERR_NONE) {
|
||||
pr_info("Cannot obtain MU ID\n");
|
||||
return sciErr;
|
||||
}
|
||||
|
||||
sciErr = sc_ipc_open(&ccm_ipc_handle, mu_id);
|
||||
|
||||
if (sciErr != SC_ERR_NONE) {
|
||||
pr_info("Cannot open MU channel to SCU\n");
|
||||
return sciErr;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
core_initcall(notify_imx8_clk);
|
||||
116
drivers/clk/imx/clk-imx8.h
Normal file
116
drivers/clk/imx/clk-imx8.h
Normal file
@ -0,0 +1,116 @@
|
||||
#ifndef __IMX8_CLK_H
|
||||
#define __IMX8_CLK_H
|
||||
|
||||
#include <linux/spinlock.h>
|
||||
#include <linux/clk.h>
|
||||
#include <linux/clk-provider.h>
|
||||
#include <soc/imx8/sc/sci.h>
|
||||
|
||||
extern spinlock_t imx_ccm_lock;
|
||||
extern sc_ipc_t ccm_ipc_handle;
|
||||
|
||||
struct clk *imx_clk_divider_scu(const char *name,
|
||||
sc_rsrc_t rsrc_id, sc_pm_clk_t clk_type);
|
||||
|
||||
struct clk *imx_clk_divider2_scu(const char *name, const char *parent_name,
|
||||
sc_rsrc_t rsrc_id, sc_pm_clk_t clk_type);
|
||||
|
||||
struct clk *imx_clk_divider3_scu(const char *name, const char *parent_name,
|
||||
sc_rsrc_t rsrc_id, sc_ctrl_t gpr_id);
|
||||
|
||||
struct clk *imx_clk_divider2_scu(const char *name, const char *parent_name,
|
||||
sc_rsrc_t rsrc_id, sc_pm_clk_t clk_type);
|
||||
|
||||
struct clk *clk_register_gate_scu(struct device *dev, const char *name,
|
||||
const char *parent_name, unsigned long flags,
|
||||
u8 clk_gate_scu_flags, spinlock_t *lock,
|
||||
sc_rsrc_t rsrc_id, sc_pm_clk_t clk_type,
|
||||
void __iomem *reg, u8 bit_idx, bool hw_gate);
|
||||
|
||||
struct clk *clk_register_gate2_scu(struct device *dev, const char *name,
|
||||
const char *parent_name, unsigned long flags,
|
||||
void __iomem *reg, u8 bit_idx,
|
||||
u8 clk_gate_flags, spinlock_t *lock, const char *pd_name);
|
||||
|
||||
struct clk *clk_register_mux_scu(struct device *dev, const char *name,
|
||||
const char **parent_names, u8 num_parents, unsigned long flags,
|
||||
void __iomem *reg, u8 shift, u8 width,
|
||||
u8 clk_mux_flags, spinlock_t *lock,
|
||||
const char *pd_name);
|
||||
|
||||
struct clk *clk_register_gate3_scu(struct device *dev, const char *name,
|
||||
const char *parent_name, spinlock_t *lock,
|
||||
sc_rsrc_t rsrc_id, sc_ctrl_t gpr_id, bool invert_flag);
|
||||
|
||||
struct clk *clk_register_mux_gpr_scu(struct device *dev, const char *name,
|
||||
const char **parents, int num_parents, spinlock_t *lock,
|
||||
sc_rsrc_t rsrc_id, sc_ctrl_t gpr_id);
|
||||
|
||||
static inline struct clk *imx_clk_fixed(const char *name, int rate)
|
||||
{
|
||||
return clk_register_fixed_rate(NULL, name, NULL, 0, rate);
|
||||
}
|
||||
|
||||
static inline struct clk *imx_clk_gate_scu(const char *name, const char *parent,
|
||||
sc_rsrc_t rsrc_id, sc_pm_clk_t clk_type,
|
||||
void __iomem *reg, u8 bit_idx, bool hw_gate)
|
||||
{
|
||||
return clk_register_gate_scu(NULL, name, parent,
|
||||
CLK_SET_RATE_PARENT, 0, &imx_ccm_lock, rsrc_id, clk_type,
|
||||
reg, bit_idx, hw_gate);
|
||||
}
|
||||
|
||||
static inline struct clk *imx_clk_gate2_scu(const char *name, const char *parent,
|
||||
void __iomem *reg, u8 bit_idx, const char *pd_name)
|
||||
{
|
||||
return clk_register_gate2_scu(NULL, name, parent, 0, reg,
|
||||
bit_idx, 0, &imx_ccm_lock, pd_name);
|
||||
}
|
||||
|
||||
static inline struct clk *imx_clk_gate3_scu(const char *name, const char *parent,
|
||||
sc_rsrc_t rsrc_id, sc_ctrl_t gpr_id, bool invert_flag)
|
||||
{
|
||||
return clk_register_gate3_scu(NULL, name, parent,
|
||||
&imx_ccm_lock, rsrc_id, gpr_id, invert_flag);
|
||||
}
|
||||
|
||||
static inline struct clk *imx_clk_mux_gpr_scu(const char *name, const char **parents,
|
||||
int num_parents, sc_rsrc_t rsrc_id, sc_ctrl_t gpr_id)
|
||||
{
|
||||
return clk_register_mux_gpr_scu(NULL, name, parents, num_parents,
|
||||
&imx_ccm_lock, rsrc_id, gpr_id);
|
||||
}
|
||||
|
||||
static inline void imx_clk_set_rate(struct clk *clk, unsigned long rate)
|
||||
{
|
||||
int ret = clk_set_rate(clk, rate);
|
||||
|
||||
if (ret)
|
||||
pr_err("failed to set rate of clk %s to %ld: %d\n",
|
||||
__clk_get_name(clk), rate, ret);
|
||||
}
|
||||
|
||||
static inline struct clk *imx_clk_gate(const char *name, const char *parent,
|
||||
void __iomem *reg, u8 shift)
|
||||
{
|
||||
return clk_register_gate(NULL, name, parent, CLK_SET_RATE_PARENT, reg,
|
||||
shift, 0, &imx_ccm_lock);
|
||||
}
|
||||
|
||||
static inline struct clk *imx_clk_fixed_factor(const char *name,
|
||||
const char *parent, unsigned int mult, unsigned int div)
|
||||
{
|
||||
return clk_register_fixed_factor(NULL, name, parent,
|
||||
CLK_SET_RATE_PARENT, mult, div);
|
||||
}
|
||||
|
||||
static inline struct clk *imx_clk_mux_scu(const char *name, void __iomem *reg,
|
||||
u8 shift, u8 width, const char **parents, int num_parents, const char *pd_name)
|
||||
{
|
||||
return clk_register_mux_scu(NULL, name, parents, num_parents,
|
||||
CLK_SET_RATE_NO_REPARENT, reg, shift,
|
||||
width, 0, &imx_ccm_lock, pd_name);
|
||||
}
|
||||
|
||||
|
||||
#endif
|
||||
874
drivers/clk/imx/clk-imx8qm.c
Normal file
874
drivers/clk/imx/clk-imx8qm.c
Normal file
@ -0,0 +1,874 @@
|
||||
/*
|
||||
* Copyright (C) 2016 Freescale Semiconductor, Inc.
|
||||
* Copyright 2017 NXP
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License
|
||||
* as published by the Free Software Foundation; either version 2
|
||||
* of the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <dt-bindings/clock/imx8qm-clock.h>
|
||||
#include <dt-bindings/soc/imx8_pd.h>
|
||||
#include <linux/clk.h>
|
||||
#include <linux/clkdev.h>
|
||||
#include <linux/clk-provider.h>
|
||||
#include <linux/err.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/of.h>
|
||||
#include <linux/of_address.h>
|
||||
#include <linux/of_irq.h>
|
||||
#include <linux/pm_domain.h>
|
||||
#include <linux/types.h>
|
||||
|
||||
#include <soc/imx8/imx8qm/lpcg.h>
|
||||
#include <soc/imx8/sc/sci.h>
|
||||
|
||||
#include "clk-imx8.h"
|
||||
|
||||
#define STR_VALUE(arg) #arg
|
||||
#define FUNCTION_NAME(name) STR_VALUE(name)
|
||||
|
||||
static const char *aud_clk_sels[] = {
|
||||
"aud_acm_aud_rec_clk0_clk",
|
||||
"aud_acm_aud_rec_clk1_clk",
|
||||
"mlb_clk",
|
||||
"hdmi_rx_mclk",
|
||||
"ext_aud_mclk0",
|
||||
"ext_aud_mclk1",
|
||||
"esai0_rx_clk",
|
||||
"esai0_rx_hf_clk",
|
||||
"esai0_tx_clk",
|
||||
"esai0_tx_hf_clk",
|
||||
"esai1_rx_clk",
|
||||
"esai1_rx_hf_clk",
|
||||
"esai1_tx_clk",
|
||||
"esai1_tx_hf_clk",
|
||||
"spdif0_rx",
|
||||
"spdif1_rx",
|
||||
"sai0_rx_bclk",
|
||||
"sai0_tx_bclk",
|
||||
"sai1_rx_bclk",
|
||||
"sai1_tx_bclk",
|
||||
"sai2_rx_bclk",
|
||||
"sai3_rx_bclk",
|
||||
"hdmi_rx_sai0_rx_bclk",
|
||||
};
|
||||
|
||||
static const char *mclk_out_sels[] = {
|
||||
"aud_acm_aud_rec_clk0_clk",
|
||||
"aud_acm_aud_rec_clk1_clk",
|
||||
"mlb_clk",
|
||||
"hdmi_rx_mclk",
|
||||
"spdif0_rx",
|
||||
"spdif1_rx",
|
||||
"hdmi_rx_sai0_rx_bclk",
|
||||
"sai6_rx_bclk",
|
||||
};
|
||||
|
||||
static const char *sai_mclk_sels[] = {
|
||||
"aud_acm_aud_pll_clk0_clk",
|
||||
"aud_acm_aud_pll_clk1_clk",
|
||||
"acm_aud_clk0_clk",
|
||||
"acm_aud_clk1_clk",
|
||||
};
|
||||
|
||||
static const char *asrc_mux_clk_sels[] = {
|
||||
"hdmi_rx_sai0_rx_bclk",
|
||||
"hdmi_tx_sai0_tx_bclk",
|
||||
"dummy",
|
||||
"mlb_clk",
|
||||
};
|
||||
|
||||
static const char *esai_mclk_sels[] = {
|
||||
"aud_acm_aud_pll_clk0_clk",
|
||||
"aud_acm_aud_pll_clk1_clk",
|
||||
"acm_aud_clk0_clk",
|
||||
"acm_aud_clk1_clk",
|
||||
};
|
||||
|
||||
static const char *spdif_mclk_sels[] = {
|
||||
"aud_acm_aud_pll_clk0_clk",
|
||||
"aud_acm_aud_pll_clk1_clk",
|
||||
"acm_aud_clk0_clk",
|
||||
"acm_aud_clk1_clk",
|
||||
};
|
||||
|
||||
static const char *mqs_mclk_sels[] = {
|
||||
"aud_acm_aud_pll_clk0_clk",
|
||||
"aud_acm_aud_pll_clk1_clk",
|
||||
"acm_aud_clk0_clk",
|
||||
"acm_aud_clk1_clk",
|
||||
};
|
||||
|
||||
static struct clk *clks[IMX8QM_CLK_END];
|
||||
static struct clk_onecell_data clk_data;
|
||||
|
||||
static const char *enet_sels[] = {"enet_25MHz", "enet_125MHz",};
|
||||
static const char *enet0_rmii_tx_sels[] = {"enet0_root_div", "dummy",};
|
||||
static const char *enet1_rmii_tx_sels[] = {"enet1_root_div", "dummy",};
|
||||
|
||||
static void __init imx8qm_clocks_init(struct device_node *ccm_node)
|
||||
{
|
||||
int i;
|
||||
struct device_node *np_acm;
|
||||
void __iomem *base_acm;
|
||||
|
||||
pr_info("***** imx8qm_clocks_init *****\n");
|
||||
|
||||
clks[IMX8QM_CLK_DUMMY] = imx_clk_fixed("dummy", 0);
|
||||
|
||||
/* ARM core */
|
||||
clks[IMX8QM_A53_DIV] = imx_clk_divider_scu("a53_div", SC_R_A53, SC_PM_CLK_CPU);
|
||||
clks[IMX8QM_A72_DIV] = imx_clk_divider_scu("a72_div", SC_R_A72, SC_PM_CLK_CPU);
|
||||
|
||||
/* User Defined PLLs dividers */
|
||||
clks[IMX8QM_AUD_PLL0_DIV] = imx_clk_divider_scu("audio_pll0_div", SC_R_AUDIO_PLL_0, SC_PM_CLK_PLL);
|
||||
clks[IMX8QM_AUD_PLL1_DIV] = imx_clk_divider_scu("audio_pll1_div", SC_R_AUDIO_PLL_1, SC_PM_CLK_PLL);
|
||||
clks[IMX8QM_DC0_PLL0_DIV] = imx_clk_divider_scu("dc0_pll0_div", SC_R_DC_0_PLL_0, SC_PM_CLK_PLL);
|
||||
clks[IMX8QM_DC0_PLL1_DIV] = imx_clk_divider_scu("dc0_pll1_div", SC_R_DC_0_PLL_1, SC_PM_CLK_PLL);
|
||||
clks[IMX8QM_DC1_PLL1_DIV] = imx_clk_divider_scu("dc1_pll0_div", SC_R_DC_1_PLL_0, SC_PM_CLK_PLL);
|
||||
clks[IMX8QM_DC1_PLL1_DIV] = imx_clk_divider_scu("dc1_pll1_div", SC_R_DC_1_PLL_1, SC_PM_CLK_PLL);
|
||||
clks[IMX8QM_HDMI_AUD_PLL_2_DIV] = imx_clk_divider_scu("hdmi_aud_pll_div", SC_R_HDMI_PLL_1, SC_PM_CLK_PLL);
|
||||
|
||||
/* User Defined PLLs clocks*/
|
||||
clks[IMX8QM_AUD_PLL0] = imx_clk_gate_scu("audio_pll0_clk", "audio_pll0_div", SC_R_AUDIO_PLL_0, SC_PM_CLK_PLL, NULL, 0, 0);
|
||||
clks[IMX8QM_AUD_PLL1] = imx_clk_gate_scu("audio_pll1_clk", "audio_pll1_div", SC_R_AUDIO_PLL_1, SC_PM_CLK_PLL, NULL, 0, 0);
|
||||
clks[IMX8QM_DC0_PLL0_CLK] = imx_clk_gate_scu("dc0_pll0_clk", "dc0_pll0_div", SC_R_DC_0_PLL_0, SC_PM_CLK_PLL, NULL, 0, 0);
|
||||
clks[IMX8QM_DC0_PLL1_CLK] = imx_clk_gate_scu("dc0_pll1_clk", "dc0_pll1_div", SC_R_DC_0_PLL_1, SC_PM_CLK_PLL, NULL, 0, 0);
|
||||
clks[IMX8QM_DC1_PLL0_CLK] = imx_clk_gate_scu("dc1_pll0_clk", "dc1_pll0_div", SC_R_DC_1_PLL_0, SC_PM_CLK_PLL, NULL, 0, 0);
|
||||
clks[IMX8QM_DC1_PLL1_CLK] = imx_clk_gate_scu("dc1_pll1_clk", "dc1_pll1_div", SC_R_DC_1_PLL_1, SC_PM_CLK_PLL, NULL, 0, 0);
|
||||
clks[IMX8QM_HDMI_AUD_PLL_2_CLK] = imx_clk_gate_scu("hdmi_aud_pll_clk", "hdmi_aud_pll_div", SC_R_HDMI_PLL_1, SC_PM_CLK_PLL, NULL, 0, 0);
|
||||
|
||||
/* DMA SS */
|
||||
clks[IMX8QM_UART0_DIV] = imx_clk_divider_scu("uart0_div", SC_R_UART_0, SC_PM_CLK_PER);
|
||||
clks[IMX8QM_UART1_DIV] = imx_clk_divider_scu("uart1_div", SC_R_UART_1, SC_PM_CLK_PER);
|
||||
clks[IMX8QM_UART2_DIV] = imx_clk_divider_scu("uart2_div", SC_R_UART_2, SC_PM_CLK_PER);
|
||||
clks[IMX8QM_UART3_DIV] = imx_clk_divider_scu("uart3_div", SC_R_UART_3, SC_PM_CLK_PER);
|
||||
clks[IMX8QM_UART4_DIV] = imx_clk_divider_scu("uart4_div", SC_R_UART_4, SC_PM_CLK_PER);
|
||||
clks[IMX8QM_SPI0_DIV] = imx_clk_divider_scu("spi0_div", SC_R_SPI_0, SC_PM_CLK_PER);
|
||||
clks[IMX8QM_SPI1_DIV] = imx_clk_divider_scu("spi1_div", SC_R_SPI_1, SC_PM_CLK_PER);
|
||||
clks[IMX8QM_SPI2_DIV] = imx_clk_divider_scu("spi2_div", SC_R_SPI_2, SC_PM_CLK_PER);
|
||||
clks[IMX8QM_SPI3_DIV] = imx_clk_divider_scu("spi3_div", SC_R_SPI_3, SC_PM_CLK_PER);
|
||||
clks[IMX8QM_EMVSIM0_DIV] = imx_clk_divider_scu("emvsim0_div", SC_R_EMVSIM_0, SC_PM_CLK_PER);
|
||||
clks[IMX8QM_EMVSIM1_DIV] = imx_clk_divider_scu("emvsim1_div", SC_R_EMVSIM_1, SC_PM_CLK_PER);
|
||||
clks[IMX8QM_CAN0_DIV] = imx_clk_divider_scu("can0_div", SC_R_CAN_0, SC_PM_CLK_PER);
|
||||
clks[IMX8QM_CAN1_DIV] = imx_clk_divider_scu("can1_div", SC_R_CAN_1, SC_PM_CLK_PER);
|
||||
clks[IMX8QM_CAN2_DIV] = imx_clk_divider_scu("can2_div", SC_R_CAN_2, SC_PM_CLK_PER);
|
||||
clks[IMX8QM_I2C0_DIV] = imx_clk_divider_scu("i2c0_div", SC_R_I2C_0, SC_PM_CLK_PER);
|
||||
clks[IMX8QM_I2C1_DIV] = imx_clk_divider_scu("i2c1_div", SC_R_I2C_1, SC_PM_CLK_PER);
|
||||
clks[IMX8QM_I2C2_DIV] = imx_clk_divider_scu("i2c2_div", SC_R_I2C_2, SC_PM_CLK_PER);
|
||||
clks[IMX8QM_I2C3_DIV] = imx_clk_divider_scu("i2c3_div", SC_R_I2C_3, SC_PM_CLK_PER);
|
||||
clks[IMX8QM_I2C4_DIV] = imx_clk_divider_scu("i2c4_div", SC_R_I2C_4, SC_PM_CLK_PER);
|
||||
clks[IMX8QM_FTM0_DIV] = imx_clk_divider_scu("ftm0_div", SC_R_FTM_0, SC_PM_CLK_PER);
|
||||
clks[IMX8QM_FTM1_DIV] = imx_clk_divider_scu("ftm1_div", SC_R_FTM_1, SC_PM_CLK_PER);
|
||||
clks[IMX8QM_ADC0_DIV] = imx_clk_divider_scu("adc0_div", SC_R_ADC_0, SC_PM_CLK_PER);
|
||||
clks[IMX8QM_ADC1_DIV] = imx_clk_divider_scu("adc1_div", SC_R_ADC_1, SC_PM_CLK_PER);
|
||||
|
||||
/* LSIO SS */
|
||||
clks[IMX8QM_PWM0_DIV] = imx_clk_divider_scu("pwm_0_div", SC_R_PWM_0, SC_PM_CLK_PER);
|
||||
clks[IMX8QM_PWM1_DIV] = imx_clk_divider_scu("pwm_1_div", SC_R_PWM_1, SC_PM_CLK_PER);
|
||||
clks[IMX8QM_PWM2_DIV] = imx_clk_divider_scu("pwm_2_div", SC_R_PWM_2, SC_PM_CLK_PER);
|
||||
clks[IMX8QM_PWM3_DIV] = imx_clk_divider_scu("pwm_3_div", SC_R_PWM_3, SC_PM_CLK_PER);
|
||||
clks[IMX8QM_PWM4_DIV] = imx_clk_divider_scu("pwm_4_div", SC_R_PWM_4, SC_PM_CLK_PER);
|
||||
clks[IMX8QM_PWM5_DIV] = imx_clk_divider_scu("pwm_5_div", SC_R_PWM_5, SC_PM_CLK_PER);
|
||||
clks[IMX8QM_PWM6_DIV] = imx_clk_divider_scu("pwm_6_div", SC_R_PWM_6, SC_PM_CLK_PER);
|
||||
clks[IMX8QM_PWM7_DIV] = imx_clk_divider_scu("pwm_7_div", SC_R_PWM_7, SC_PM_CLK_PER);
|
||||
clks[IMX8QM_FSPI0_DIV] = imx_clk_divider_scu("fspi_0_div", SC_R_FSPI_0, SC_PM_CLK_PER);
|
||||
clks[IMX8QM_FSPI1_DIV] = imx_clk_divider_scu("fspi_1_div", SC_R_FSPI_1, SC_PM_CLK_PER);
|
||||
clks[IMX8QM_GPT0_DIV] = imx_clk_divider_scu("gpt_0_div", SC_R_GPT_0, SC_PM_CLK_PER);
|
||||
clks[IMX8QM_GPT1_DIV] = imx_clk_divider_scu("gpt_1_div", SC_R_GPT_1, SC_PM_CLK_PER);
|
||||
clks[IMX8QM_GPT2_DIV] = imx_clk_divider_scu("gpt_2_div", SC_R_GPT_2, SC_PM_CLK_PER);
|
||||
clks[IMX8QM_GPT3_DIV] = imx_clk_divider_scu("gpt_3_div", SC_R_GPT_3, SC_PM_CLK_PER);
|
||||
clks[IMX8QM_GPT4_DIV] = imx_clk_divider_scu("gpt_4_div", SC_R_GPT_4, SC_PM_CLK_PER);
|
||||
|
||||
/* lvds subsystem */
|
||||
clks[IMX8QM_LVDS0_BYPASS_CLK] = imx_clk_divider_scu("lvds0_bypass_clk", SC_R_LVDS_0, SC_PM_CLK_BYPASS);
|
||||
clks[IMX8QM_LVDS0_PIXEL_DIV] = imx_clk_divider_scu("lvds0_pixel_div", SC_R_LVDS_0, SC_PM_CLK_PER);
|
||||
clks[IMX8QM_LVDS0_I2C0_DIV] = imx_clk_divider_scu("lvds0_i2c0_div", SC_R_LVDS_0_I2C_0, SC_PM_CLK_PER);
|
||||
clks[IMX8QM_LVDS0_I2C1_DIV] = imx_clk_divider_scu("lvds0_i2c1_div", SC_R_LVDS_0_I2C_1, SC_PM_CLK_PER);
|
||||
clks[IMX8QM_LVDS0_PWM0_DIV] = imx_clk_divider_scu("lvds0_pwm0_div", SC_R_LVDS_0_PWM_0, SC_PM_CLK_PER);
|
||||
clks[IMX8QM_LVDS0_PHY_DIV] = imx_clk_divider_scu("lvds0_phy_div", SC_R_LVDS_0, SC_PM_CLK_PHY);
|
||||
clks[IMX8QM_LVDS1_BYPASS_CLK] = imx_clk_divider_scu("lvds1_bypass_clk", SC_R_LVDS_1, SC_PM_CLK_BYPASS);
|
||||
clks[IMX8QM_LVDS1_PIXEL_DIV] = imx_clk_divider_scu("lvds1_pixel_div", SC_R_LVDS_1, SC_PM_CLK_PER);
|
||||
clks[IMX8QM_LVDS1_I2C0_DIV] = imx_clk_divider_scu("lvds1_i2c0_div", SC_R_LVDS_1_I2C_0, SC_PM_CLK_PER);
|
||||
clks[IMX8QM_LVDS1_I2C1_DIV] = imx_clk_divider_scu("lvds1_i2c1_div", SC_R_LVDS_1_I2C_1, SC_PM_CLK_PER);
|
||||
clks[IMX8QM_LVDS1_PWM0_DIV] = imx_clk_divider_scu("lvds1_pwm0_div", SC_R_LVDS_1_PWM_0, SC_PM_CLK_PER);
|
||||
clks[IMX8QM_LVDS1_PHY_DIV] = imx_clk_divider_scu("lvds1_phy_div", SC_R_LVDS_1, SC_PM_CLK_PHY);
|
||||
|
||||
/* vpu/zpu subsystem */
|
||||
clks[IMX8QM_VPU_DDR_DIV] = imx_clk_divider_scu("vpu_ddr_div", SC_R_VPU_PID0, SC_PM_CLK_SLV_BUS);
|
||||
clks[IMX8QM_VPU_SYS_DIV] = imx_clk_divider_scu("vpu_sys_div", SC_R_VPU_PID0, SC_PM_CLK_MST_BUS);
|
||||
clks[IMX8QM_VPU_XUVI_DIV] = imx_clk_divider_scu("vpu_xuvi_div", SC_R_VPU_PID0, SC_PM_CLK_PER);
|
||||
clks[IMX8QM_VPU_UART_DIV] = imx_clk_divider_scu("vpu_uart_div", SC_R_VPU_UART, SC_PM_CLK_PER);
|
||||
clks[IMX8QM_VPU_CORE_DIV] = imx_clk_divider_scu("vpu_core_div", SC_R_VPUCORE, SC_PM_CLK_PER);
|
||||
|
||||
/* gpu */
|
||||
clks[IMX8QM_GPU0_CORE_DIV] = imx_clk_divider_scu("gpu_core0_div", SC_R_GPU_0_PID0, SC_PM_CLK_PER);
|
||||
clks[IMX8QM_GPU0_SHADER_DIV] = imx_clk_divider_scu("gpu_shader0_div", SC_R_GPU_0_PID0, SC_PM_CLK_MISC);
|
||||
clks[IMX8QM_GPU1_CORE_DIV] = imx_clk_divider_scu("gpu_core1_div", SC_R_GPU_1_PID0, SC_PM_CLK_PER);
|
||||
clks[IMX8QM_GPU1_SHADER_DIV] = imx_clk_divider_scu("gpu_shader1_div", SC_R_GPU_1_PID0, SC_PM_CLK_MISC);
|
||||
|
||||
/* Connectivity */
|
||||
clks[IMX8QM_SDHC0_DIV] = imx_clk_divider_scu("sdhc0_div", SC_R_SDHC_0, SC_PM_CLK_PER);
|
||||
clks[IMX8QM_SDHC1_DIV] = imx_clk_divider_scu("sdhc1_div", SC_R_SDHC_1, SC_PM_CLK_PER);
|
||||
clks[IMX8QM_SDHC2_DIV] = imx_clk_divider_scu("sdhc2_div", SC_R_SDHC_2, SC_PM_CLK_PER);
|
||||
clks[IMX8QM_ENET0_ROOT_DIV] = imx_clk_divider_scu("enet0_root_div", SC_R_ENET_0, SC_PM_CLK_PER);
|
||||
clks[IMX8QM_ENET0_REF_DIV] = imx_clk_divider3_scu("enet0_ref_div", "enet0_root_clk", SC_R_ENET_0, SC_C_CLKDIV);
|
||||
clks[IMX8QM_ENET1_REF_DIV] = imx_clk_divider3_scu("enet1_ref_div", "enet1_root_clk", SC_R_ENET_1, SC_C_CLKDIV);
|
||||
clks[IMX8QM_ENET0_BYPASS_DIV] = imx_clk_divider_scu("enet0_bypass_div", SC_R_ENET_0, SC_PM_CLK_BYPASS);
|
||||
clks[IMX8QM_ENET0_RGMII_DIV] = imx_clk_divider_scu("enet0_rgmii_div", SC_R_ENET_0, SC_PM_CLK_MISC0);
|
||||
clks[IMX8QM_ENET1_ROOT_DIV] = imx_clk_divider_scu("enet1_root_div", SC_R_ENET_0, SC_PM_CLK_PER);
|
||||
clks[IMX8QM_ENET1_BYPASS_DIV] = imx_clk_divider_scu("enet1_bypass_div", SC_R_ENET_1, SC_PM_CLK_BYPASS);
|
||||
clks[IMX8QM_ENET1_RGMII_DIV] = imx_clk_divider_scu("enet1_rgmii_div", SC_R_ENET_1, SC_PM_CLK_MISC0);
|
||||
clks[IMX8QM_GPMI_BCH_IO_DIV] = imx_clk_divider_scu("gpmi_io_div", SC_R_NAND, SC_PM_CLK_MST_BUS);
|
||||
clks[IMX8QM_GPMI_BCH_DIV] = imx_clk_divider_scu("gpmi_bch_div", SC_R_NAND, SC_PM_CLK_PER);
|
||||
clks[IMX8QM_GPT0_DIV] = imx_clk_divider_scu("gpt0_div", SC_R_GPT_0, SC_PM_CLK_PER);
|
||||
clks[IMX8QM_GPT1_DIV] = imx_clk_divider_scu("gpt1_div", SC_R_GPT_1, SC_PM_CLK_PER);
|
||||
clks[IMX8QM_GPT2_DIV] = imx_clk_divider_scu("gpt2_div", SC_R_GPT_2, SC_PM_CLK_PER);
|
||||
clks[IMX8QM_GPT3_DIV] = imx_clk_divider_scu("gpt3_div", SC_R_GPT_3, SC_PM_CLK_PER);
|
||||
clks[IMX8QM_GPT4_DIV] = imx_clk_divider_scu("gpt4_div", SC_R_GPT_4, SC_PM_CLK_PER);
|
||||
clks[IMX8QM_USB3_ACLK_DIV] = imx_clk_divider_scu("usb3_aclk_div", SC_R_USB_2, SC_PM_CLK_PER);
|
||||
clks[IMX8QM_USB3_BUS_DIV] = imx_clk_divider_scu("usb3_bus_div", SC_R_USB_2, SC_PM_CLK_MST_BUS);
|
||||
clks[IMX8QM_USB3_LPM_DIV] = imx_clk_divider_scu("usb3_lpm_div", SC_R_USB_2, SC_PM_CLK_MISC);
|
||||
|
||||
/* Audio */
|
||||
clks[IMX8QM_AUD_ACM_AUD_PLL_CLK0_DIV] = imx_clk_divider2_scu("aud_acm_aud_pll_clk0_div", "audio_pll0_clk", SC_R_AUDIO_PLL_0, SC_PM_CLK_MISC0);
|
||||
clks[IMX8QM_AUD_ACM_AUD_PLL_CLK1_DIV] = imx_clk_divider2_scu("aud_acm_aud_pll_clk1_div", "audio_pll1_clk", SC_R_AUDIO_PLL_1, SC_PM_CLK_MISC0);
|
||||
clks[IMX8QM_AUD_ACM_AUD_REC_CLK0_DIV] = imx_clk_divider2_scu("aud_acm_aud_rec_clk0_div", "audio_pll0_clk", SC_R_AUDIO_PLL_0, SC_PM_CLK_MISC1);
|
||||
clks[IMX8QM_AUD_ACM_AUD_REC_CLK1_DIV] = imx_clk_divider2_scu("aud_acm_aud_rec_clk1_div", "audio_pll1_clk", SC_R_AUDIO_PLL_1, SC_PM_CLK_MISC1);
|
||||
|
||||
/* MIPI CSI */
|
||||
clks[IMX8QM_CSI0_I2C0_DIV] = imx_clk_divider_scu("mipi_csi0_i2c0_div", SC_R_CSI_0_I2C_0, SC_PM_CLK_PER);
|
||||
clks[IMX8QM_CSI0_PWM0_DIV] = imx_clk_divider_scu("mipi_csi0_pwm0_div", SC_R_CSI_0_PWM_0, SC_PM_CLK_PER);
|
||||
clks[IMX8QM_CSI0_CORE_DIV] = imx_clk_divider_scu("mipi_csi0_core_div", SC_R_CSI_0, SC_PM_CLK_PER);
|
||||
clks[IMX8QM_CSI0_ESC_DIV] = imx_clk_divider_scu("mipi_csi0_esc_div", SC_R_CSI_0, SC_PM_CLK_MISC);
|
||||
clks[IMX8QM_CSI1_I2C0_DIV] = imx_clk_divider_scu("mipi_csi1_i2c0_div", SC_R_CSI_1_I2C_0, SC_PM_CLK_PER);
|
||||
clks[IMX8QM_CSI1_PWM0_DIV] = imx_clk_divider_scu("mipi_csi1_pwm0_div", SC_R_CSI_1_PWM_0, SC_PM_CLK_PER);
|
||||
clks[IMX8QM_CSI1_CORE_DIV] = imx_clk_divider_scu("mipi_csi1_core_div", SC_R_CSI_1, SC_PM_CLK_PER);
|
||||
clks[IMX8QM_CSI1_ESC_DIV] = imx_clk_divider_scu("mipi_csi1_esc_div", SC_R_CSI_1, SC_PM_CLK_MISC);
|
||||
|
||||
/* RX-HDMI */
|
||||
clks[IMX8QM_HDMI_RX_I2S_BYPASS_CLK] = imx_clk_divider_scu("hdmi_rx_i2s_bypass_clk", SC_R_HDMI_RX_BYPASS, SC_PM_CLK_MISC0);
|
||||
clks[IMX8QM_HDMI_RX_BYPASS_CLK] = imx_clk_divider_scu("hdmi_rx_bypass_clk", SC_R_HDMI_RX_BYPASS, SC_PM_CLK_MISC1);
|
||||
clks[IMX8QM_HDMI_RX_SPDIF_BYPASS_CLK] = imx_clk_divider_scu("hdmi_rx_spdif_bypass_clk", SC_R_HDMI_RX_BYPASS, SC_PM_CLK_MISC2);
|
||||
clks[IMX8QM_HDMI_RX_I2C0_DIV] = imx_clk_divider_scu("hdmi_rx_i2c0_div", SC_R_HDMI_RX_I2C_0, SC_PM_CLK_MISC2);
|
||||
clks[IMX8QM_HDMI_RX_SPDIF_DIV] = imx_clk_divider_scu("hdmi_rx_spdif_div", SC_R_HDMI_RX, SC_PM_CLK_MISC0);
|
||||
clks[IMX8QM_HDMI_RX_HD_REF_DIV] = imx_clk_divider_scu("hdmi_rx_hd_ref_div", SC_R_HDMI_RX, SC_PM_CLK_MISC1);
|
||||
clks[IMX8QM_HDMI_RX_HD_CORE_DIV] = imx_clk_divider_scu("hdmi_rx_hd_core_div", SC_R_HDMI_RX, SC_PM_CLK_MISC2);
|
||||
clks[IMX8QM_HDMI_RX_PXL_DIV] = imx_clk_divider_scu("hdmi_rx_pxl_div", SC_R_HDMI_RX, SC_PM_CLK_MISC3);
|
||||
clks[IMX8QM_HDMI_RX_I2S_DIV] = imx_clk_divider_scu("hdmi_rx_i2s_div", SC_R_HDMI_RX, SC_PM_CLK_MISC4);
|
||||
clks[IMX8QM_HDMI_RX_PWM_DIV] = imx_clk_divider_scu("hdmi_rx_pwm_div", SC_R_HDMI_RX_PWM_0, SC_PM_CLK_MISC2);
|
||||
|
||||
/* DC SS */
|
||||
clks[IMX8QM_DC0_DISP0_DIV] = imx_clk_divider_scu("dc0_disp0_div", SC_R_DC_0, SC_PM_CLK_MISC0);
|
||||
clks[IMX8QM_DC0_DISP1_DIV] = imx_clk_divider_scu("dc0_disp1_div", SC_R_DC_0, SC_PM_CLK_MISC1);
|
||||
clks[IMX8QM_DC0_BYPASS_0_DIV] = imx_clk_divider_scu("dc0_bypass0_div", SC_R_DC_0_VIDEO0, SC_PM_CLK_MISC);
|
||||
clks[IMX8QM_DC0_BYPASS_1_DIV] = imx_clk_divider_scu("dc0_bypass1_div", SC_R_DC_0_VIDEO1, SC_PM_CLK_MISC);
|
||||
clks[IMX8QM_DC1_DISP0_DIV] = imx_clk_divider_scu("dc1_disp0_div", SC_R_DC_1, SC_PM_CLK_MISC0);
|
||||
clks[IMX8QM_DC1_DISP1_DIV] = imx_clk_divider_scu("dc1_disp1_div", SC_R_DC_1, SC_PM_CLK_MISC1);
|
||||
clks[IMX8QM_DC1_BYPASS_0_DIV] = imx_clk_divider_scu("dc1_bypass0_div", SC_R_DC_1_VIDEO0, SC_PM_CLK_BYPASS);
|
||||
clks[IMX8QM_DC1_BYPASS_1_DIV] = imx_clk_divider_scu("dc1_bypass1_div", SC_R_DC_1_VIDEO1, SC_PM_CLK_BYPASS);
|
||||
|
||||
/* HDMI SS */
|
||||
clks[IMX8QM_HDMI_I2S_BYPASS_CLK] = imx_clk_divider_scu("hdmi_i2s_bypass_clk", SC_R_HDMI_I2S, SC_PM_CLK_MISC0);
|
||||
clks[IMX8QM_HDMI_I2C0_DIV] = imx_clk_divider_scu("hdmi_i2c0_div", SC_R_HDMI_I2C_0, SC_PM_CLK_MISC2);
|
||||
clks[IMX8QM_HDMI_PXL_DIV] = imx_clk_divider_scu("hdmi_pxl_div", SC_R_HDMI, SC_PM_CLK_MISC3);
|
||||
clks[IMX8QM_HDMI_PXL_LINK_DIV] = imx_clk_divider_scu("hdmi_pxl_link_div", SC_R_HDMI, SC_PM_CLK_MISC1);
|
||||
clks[IMX8QM_HDMI_PXL_MUX_DIV] = imx_clk_divider_scu("hdmi_pxl_mux_div", SC_R_HDMI, SC_PM_CLK_MISC0);
|
||||
clks[IMX8QM_HDMI_I2S_DIV] = imx_clk_divider_scu("hdmi_i2s_div", SC_R_HDMI, SC_PM_CLK_MISC4);
|
||||
clks[IMX8QM_HDMI_HDP_CORE_DIV] = imx_clk_divider_scu("hdmi_core_div", SC_R_HDMI, SC_PM_CLK_MISC2);
|
||||
|
||||
/* MIPI -DI SS */
|
||||
clks[IMX8QM_MIPI0_BYPASS_CLK] = imx_clk_divider_scu("mipi0_bypass_clk", SC_R_MIPI_0, SC_PM_CLK_BYPASS);
|
||||
clks[IMX8QM_MIPI0_I2C0_DIV] = imx_clk_divider_scu("mipi0_i2c0_div", SC_R_MIPI_0_I2C_0, SC_PM_CLK_PER);
|
||||
clks[IMX8QM_MIPI0_I2C1_DIV] = imx_clk_divider_scu("mipi0_i2c1_div", SC_R_MIPI_0_I2C_1, SC_PM_CLK_PER);
|
||||
clks[IMX8QM_MIPI0_PWM0_DIV] = imx_clk_divider_scu("mipi0_pwm0_div", SC_R_MIPI_0_PWM_0, SC_PM_CLK_PER);
|
||||
clks[IMX8QM_MIPI0_DSI_TX_ESC_DIV] = imx_clk_divider_scu("mipi0_dsi_tx_esc_div", SC_R_MIPI_0, SC_PM_CLK_MST_BUS);
|
||||
clks[IMX8QM_MIPI0_DSI_RX_ESC_DIV] = imx_clk_divider_scu("mipi0_dsi_rx_esc_div", SC_R_MIPI_0, SC_PM_CLK_SLV_BUS);
|
||||
clks[IMX8QM_MIPI0_PXL_DIV] = imx_clk_divider_scu("mipi0_pxl_div", SC_R_MIPI_0, SC_PM_CLK_PER);
|
||||
clks[IMX8QM_MIPI1_BYPASS_CLK] = imx_clk_divider_scu("mipi1_bypass_clk", SC_R_MIPI_1, SC_PM_CLK_BYPASS);
|
||||
clks[IMX8QM_MIPI1_I2C0_DIV] = imx_clk_divider_scu("mipi1_i2c0_div", SC_R_MIPI_1_I2C_0, SC_PM_CLK_PER);
|
||||
clks[IMX8QM_MIPI1_I2C1_DIV] = imx_clk_divider_scu("mipi1_i2c1_div", SC_R_MIPI_1_I2C_1, SC_PM_CLK_PER);
|
||||
clks[IMX8QM_MIPI1_PWM0_DIV] = imx_clk_divider_scu("mipi1_pwm0_div", SC_R_MIPI_1_PWM_0, SC_PM_CLK_PER);
|
||||
clks[IMX8QM_MIPI1_DSI_TX_ESC_DIV] = imx_clk_divider_scu("mipi1_dsi_tx_esc_div", SC_R_MIPI_1, SC_PM_CLK_MST_BUS);
|
||||
clks[IMX8QM_MIPI1_DSI_RX_ESC_DIV] = imx_clk_divider_scu("mipi1_dsi_rx_esc_div", SC_R_MIPI_1, SC_PM_CLK_SLV_BUS);
|
||||
clks[IMX8QM_MIPI1_PXL_DIV] = imx_clk_divider_scu("mipi1_pxl_div", SC_R_MIPI_1, SC_PM_CLK_PER);
|
||||
|
||||
/* Fixed clocks. */
|
||||
clks[IMX8QM_IPG_DMA_CLK_ROOT] = imx_clk_fixed("ipg_dma_clk_root", SC_120MHZ);
|
||||
clks[IMX8QM_IPG_AUD_CLK_ROOT] = imx_clk_fixed("ipg_aud_clk_root", SC_175MHZ);
|
||||
clks[IMX8QM_AXI_CONN_CLK_ROOT] = imx_clk_fixed("axi_conn_clk_root", SC_333MHZ);
|
||||
clks[IMX8QM_AHB_CONN_CLK_ROOT] = imx_clk_fixed("ahb_conn_clk_root", SC_166MHZ);
|
||||
clks[IMX8QM_IPG_CONN_CLK_ROOT] = imx_clk_fixed("ipg_conn_clk_root", SC_83MHZ);
|
||||
clks[IMX8QM_IPG_MIPI_CSI_CLK_ROOT] = imx_clk_fixed("ipg_mipi_csi_clk_root", SC_120MHZ);
|
||||
clks[IMX8QM_DC_AXI_EXT_CLK] = imx_clk_fixed("axi_ext_dc_clk_root", SC_800MHZ);
|
||||
clks[IMX8QM_DC_AXI_INT_CLK] = imx_clk_fixed("axi_int_dc_clk_root", SC_400MHZ);
|
||||
clks[IMX8QM_DC_CFG_CLK] = imx_clk_fixed("cfg_dc_clk_root", SC_100MHZ);
|
||||
clks[IMX8QM_HDMI_IPG_CLK] = imx_clk_fixed("ipg_hdmi_clk_root", SC_62MHZ);
|
||||
clks[IMX8QM_LVDS_IPG_CLK] = imx_clk_fixed("ipg_lvds_clk_root", SC_24MHZ);
|
||||
clks[IMX8QM_IMG_AXI_CLK] = imx_clk_fixed("axi_img_clk_root", SC_400MHZ);
|
||||
clks[IMX8QM_IMG_IPG_CLK] = imx_clk_fixed("ipg_img_clk_root", SC_200MHZ);
|
||||
clks[IMX8QM_IMG_PXL_CLK] = imx_clk_fixed("pxl_img_clk_root", SC_600MHZ);
|
||||
clks[IMX8QM_HSIO_AXI_CLK] = imx_clk_fixed("axi_hsio_clk_root", SC_400MHZ);
|
||||
clks[IMX8QM_HSIO_PER_CLK] = imx_clk_fixed("per_hsio_clk_root", SC_133MHZ);
|
||||
clks[IMX8QM_HDMI_RX_IPG_CLK] = imx_clk_fixed("ipg_hdmi_rx_clk_root", SC_400MHZ);
|
||||
clks[IMX8QM_ENET_25MHZ_CLK] = imx_clk_fixed("enet_25MHz", SC_25MHZ);
|
||||
clks[IMX8QM_ENET_125MHZ_CLK] = imx_clk_fixed("enet_125MHz", SC_125MHZ);
|
||||
clks[IMX8QM_LSIO_BUS_CLK] = imx_clk_fixed("lsio_bus_clk_root", SC_100MHZ);
|
||||
clks[IMX8QM_LSIO_MEM_CLK] = imx_clk_fixed("lsio_mem_clk_root", SC_200MHZ);
|
||||
clks[IMX8QM_24MHZ] = imx_clk_fixed("xtal_24MHz", 24000000);
|
||||
clks[IMX8QM_GPT_3M] = imx_clk_fixed("gpt_3m", 3000000);
|
||||
clks[IMX8QM_32KHZ] = imx_clk_fixed("xtal_32KHz", 32768);
|
||||
|
||||
/* Conectivity */
|
||||
clks[IMX8QM_SDHC0_IPG_CLK] = imx_clk_gate2_scu("sdhc0_ipg_clk", "ipg_conn_clk_root", (void __iomem *)(USDHC_0_LPCG), 16, FUNCTION_NAME(PD_CONN_SDHC_0));
|
||||
clks[IMX8QM_SDHC1_IPG_CLK] = imx_clk_gate2_scu("sdhc1_ipg_clk", "ipg_conn_clk_root", (void __iomem *)(USDHC_1_LPCG), 16, FUNCTION_NAME(PD_CONN_SDHC_1));
|
||||
clks[IMX8QM_SDHC2_IPG_CLK] = imx_clk_gate2_scu("sdhc2_ipg_clk", "ipg_conn_clk_root", (void __iomem *)(USDHC_2_LPCG), 16, FUNCTION_NAME(PD_CONN_SDHC_2));
|
||||
clks[IMX8QM_SDHC0_CLK] = imx_clk_gate_scu("sdhc0_clk", "sdhc0_div", SC_R_SDHC_0, SC_PM_CLK_PER, (void __iomem *)(USDHC_0_LPCG), 0, 0);
|
||||
clks[IMX8QM_SDHC1_CLK] = imx_clk_gate_scu("sdhc1_clk", "sdhc1_div", SC_R_SDHC_1, SC_PM_CLK_PER, (void __iomem *)(USDHC_1_LPCG), 0, 0);
|
||||
clks[IMX8QM_SDHC2_CLK] = imx_clk_gate_scu("sdhc2_clk", "sdhc2_div", SC_R_SDHC_2, SC_PM_CLK_PER, (void __iomem *)(USDHC_2_LPCG), 0, 0);
|
||||
clks[IMX8QM_GPT0_CLK] = imx_clk_gate_scu("gpt0_clk", "gpt0_div", SC_R_GPT_0, SC_PM_CLK_PER, (void __iomem *)(GPT_0_LPCG + 0x4), 0, 0);
|
||||
clks[IMX8QM_GPT1_CLK] = imx_clk_gate_scu("gpt1_clk", "gpt1_div", SC_R_GPT_1, SC_PM_CLK_PER, (void __iomem *)(GPT_1_LPCG + 0x4), 0, 0);
|
||||
clks[IMX8QM_GPT2_CLK] = imx_clk_gate_scu("gpt2_clk", "gpt2_div", SC_R_GPT_2, SC_PM_CLK_PER, (void __iomem *)(GPT_2_LPCG + 0x4), 0, 0);
|
||||
clks[IMX8QM_GPT3_CLK] = imx_clk_gate_scu("gpt3_clk", "gpt3_div", SC_R_GPT_3, SC_PM_CLK_PER, (void __iomem *)(GPT_3_LPCG + 0x4), 0, 0);
|
||||
clks[IMX8QM_GPT4_CLK] = imx_clk_gate_scu("gpt4_clk", "gpt4_div", SC_R_GPT_4, SC_PM_CLK_PER, (void __iomem *)(GPT_4_LPCG + 0x4), 0, 0);
|
||||
clks[IMX8QM_ENET0_AHB_CLK] = imx_clk_gate2_scu("enet0_ahb_clk", "axi_conn_clk_root", (void __iomem *)(ENET_0_LPCG), 8, FUNCTION_NAME(PD_CONN_ENET_0));
|
||||
clks[IMX8QM_ENET0_IPG_S_CLK] = imx_clk_gate2_scu("enet0_ipg_s_clk", "ipg_conn_clk_root", (void __iomem *)(ENET_0_LPCG), 20, FUNCTION_NAME(PD_CONN_ENET_0));
|
||||
clks[IMX8QM_ENET0_IPG_CLK] = imx_clk_gate2_scu("enet0_ipg_clk", "enet0_ipg_s_clk", (void __iomem *)(ENET_0_LPCG), 16, FUNCTION_NAME(PD_CONN_ENET_0));
|
||||
clks[IMX8QM_ENET1_AHB_CLK] = imx_clk_gate2_scu("enet1_ahb_clk", "axi_conn_clk_root", (void __iomem *)(ENET_1_LPCG), 8, FUNCTION_NAME(PD_CONN_ENET_1));
|
||||
clks[IMX8QM_ENET1_IPG_S_CLK] = imx_clk_gate2_scu("enet1_ipg_s_clk", "ipg_conn_clk_root", (void __iomem *)(ENET_1_LPCG), 20, FUNCTION_NAME(PD_CONN_ENET_1));
|
||||
clks[IMX8QM_ENET1_IPG_CLK] = imx_clk_gate2_scu("enet1_ipg_clk", "enet1_ipg_s_clk", (void __iomem *)(ENET_1_LPCG), 16, FUNCTION_NAME(PD_CONN_ENET_1));
|
||||
clks[IMX8QM_ENET0_ROOT_CLK] = imx_clk_gate_scu("enet0_root_clk", "enet0_root_div", SC_R_ENET_0, SC_PM_CLK_PER, NULL, 0, 0);
|
||||
clks[IMX8QM_ENET1_ROOT_CLK] = imx_clk_gate_scu("enet1_root_clk", "enet1_root_div", SC_R_ENET_1, SC_PM_CLK_PER, NULL, 0, 0);
|
||||
clks[IMX8QM_ENET0_TX_CLK] = imx_clk_gate2_scu("enet0_tx_clk", "enet0_ref_div", (void __iomem *)(ENET_0_LPCG), 4, FUNCTION_NAME(PD_CONN_ENET_0));
|
||||
clks[IMX8QM_ENET1_TX_CLK] = imx_clk_gate2_scu("enet1_tx_src_clk", "enet1_ref_div", (void __iomem *)(ENET_1_LPCG), 4, FUNCTION_NAME(PD_CONN_ENET_1));
|
||||
clks[IMX8QM_ENET0_PTP_CLK] = imx_clk_gate2_scu("enet0_ptp_clk", "enet0_ref_div", (void __iomem *)(ENET_0_LPCG), 0, FUNCTION_NAME(PD_CONN_ENET_0));
|
||||
clks[IMX8QM_ENET1_PTP_CLK] = imx_clk_gate2_scu("enet1_ptp_clk", "enet1_ref_div", (void __iomem *)(ENET_1_LPCG), 0, FUNCTION_NAME(PD_CONN_ENET_1));
|
||||
clks[IMX8QM_ENET0_REF_25MHZ_125MHZ_SEL] = imx_clk_mux_gpr_scu("enet0_ref_25_125_sel", enet_sels, ARRAY_SIZE(enet_sels), SC_R_ENET_0, SC_C_SEL_125);
|
||||
clks[IMX8QM_ENET1_REF_25MHZ_125MHZ_SEL] = imx_clk_mux_gpr_scu("enet1_ref_25_125_sel", enet_sels, ARRAY_SIZE(enet_sels), SC_R_ENET_1, SC_C_SEL_125);
|
||||
clks[IMX8QM_ENET0_RMII_TX_SEL] = imx_clk_mux_gpr_scu("enet0_rmii_tx_sel", enet0_rmii_tx_sels, ARRAY_SIZE(enet0_rmii_tx_sels), SC_R_ENET_0, SC_C_TXCLK);
|
||||
clks[IMX8QM_ENET1_RMII_TX_SEL] = imx_clk_mux_gpr_scu("enet1_rmii_tx_sel", enet1_rmii_tx_sels, ARRAY_SIZE(enet1_rmii_tx_sels), SC_R_ENET_1, SC_C_TXCLK);
|
||||
clks[IMX8QM_ENET0_RGMII_TX_CLK] = imx_clk_gate2_scu("enet0_rgmii_tx_clk", "enet0_rmii_tx_sel", (void __iomem *)(ENET_0_LPCG), 12, FUNCTION_NAME(PD_CONN_ENET_0));
|
||||
clks[IMX8QM_ENET1_RGMII_TX_CLK] = imx_clk_gate2_scu("enet1_rgmii_tx_clk", "enet1_rmii_tx_sel", (void __iomem *)(ENET_1_LPCG), 12, FUNCTION_NAME(PD_CONN_ENET_1));
|
||||
clks[IMX8QM_ENET0_RMII_RX_CLK] = imx_clk_gate2_scu("enet0_rgmii_rx_clk", "enet0_rgmii_div", (void __iomem *)(ENET_0_LPCG + 0x4), 0, FUNCTION_NAME(PD_CONN_ENET_0));
|
||||
clks[IMX8QM_ENET1_RMII_RX_CLK] = imx_clk_gate2_scu("enet1_rgmii_rx_clk", "enet1_rgmii_div", (void __iomem *)(ENET_1_LPCG + 0x4), 0, FUNCTION_NAME(PD_CONN_ENET_1));
|
||||
clks[IMX8QM_ENET0_REF_25MHZ_125MHZ_CLK] = imx_clk_gate3_scu("enet0_ref_25_125_clk", "enet0_ref_25_125_sel", SC_R_ENET_0, SC_C_DISABLE_125, true);
|
||||
clks[IMX8QM_ENET1_REF_25MHZ_125MHZ_CLK] = imx_clk_gate3_scu("enet1_ref_25_125_clk", "enet1_ref_25_125_sel", SC_R_ENET_1, SC_C_DISABLE_125, true);
|
||||
clks[IMX8QM_ENET0_REF_50MHZ_CLK] = imx_clk_gate3_scu("enet0_ref_50_clk", NULL, SC_R_ENET_0, SC_C_DISABLE_50, true);
|
||||
clks[IMX8QM_ENET1_REF_50MHZ_CLK] = imx_clk_gate3_scu("enet1_ref_50_clk", NULL, SC_R_ENET_1, SC_C_DISABLE_50, true);
|
||||
clks[IMX8QM_GPMI_APB_CLK] = imx_clk_gate2_scu("gpmi_apb_clk", "axi_conn_clk_root", (void __iomem *)(NAND_LPCG), 16, FUNCTION_NAME(PD_CONN_NAND));
|
||||
clks[IMX8QM_GPMI_APB_BCH_CLK] = imx_clk_gate2_scu("gpmi_apb_bch_clk", "axi_conn_clk_root", (void __iomem *)(NAND_LPCG), 20, FUNCTION_NAME(PD_CONN_NAND));
|
||||
clks[IMX8QM_GPMI_BCH_IO_CLK] = imx_clk_gate_scu("gpmi_io_clk", "gpmi_io_div", SC_R_NAND, SC_PM_CLK_MST_BUS, (void __iomem *)(NAND_LPCG), 4, 0);
|
||||
clks[IMX8QM_GPMI_BCH_CLK] = imx_clk_gate_scu("gpmi_bch_clk", "gpmi_bch_div", SC_R_NAND, SC_PM_CLK_PER, (void __iomem *)(NAND_LPCG), 0, 0);
|
||||
clks[IMX8QM_APBHDMA_CLK] = imx_clk_gate2_scu("gpmi_clk", "axi_conn_clk_root", (void __iomem *)(NAND_LPCG + 0x4), 16, FUNCTION_NAME(PD_CONN_NAND));
|
||||
clks[IMX8QM_USB2_OH_AHB_CLK] = imx_clk_gate2_scu("usboh3", "ahb_conn_clk_root", (void __iomem *)(USB_2_LPCG), 24, FUNCTION_NAME(PD_CONN_USB_0));
|
||||
clks[IMX8QM_USB2_OH_IPG_S_CLK] = imx_clk_gate2_scu("usboh3_ipg_s", "ipg_conn_clk_root", (void __iomem *)(USB_2_LPCG), 16, FUNCTION_NAME(PD_CONN_USB_0));
|
||||
clks[IMX8QM_USB2_OH_IPG_S_PL301_CLK] = imx_clk_gate2_scu("usboh3_ipg_pl301_s", "ipg_conn_clk_root", (void __iomem *)(USB_2_LPCG), 20, FUNCTION_NAME(PD_CONN_USB_0));
|
||||
clks[IMX8QM_USB2_PHY_IPG_CLK] = imx_clk_gate2_scu("usboh3_phy_clk", "ipg_conn_clk_root", (void __iomem *)(USB_2_LPCG), 28, FUNCTION_NAME(PD_CONN_USB_0));
|
||||
clks[IMX8QM_USB3_IPG_CLK] = imx_clk_gate2_scu("usb3_ipg_clk", "ipg_conn_clk_root", (void __iomem *)(USB_3_LPCG), 16, FUNCTION_NAME(PD_CONN_USB_2));
|
||||
clks[IMX8QM_USB3_CORE_PCLK] = imx_clk_gate2_scu("usb3_core_clk", "ipg_conn_clk_root", (void __iomem *)(USB_3_LPCG), 20, FUNCTION_NAME(PD_CONN_USB_2));
|
||||
clks[IMX8QM_USB3_PHY_CLK] = imx_clk_gate2_scu("usb3_phy_clk", "usb3_ipg_clk", (void __iomem *)(USB_3_LPCG), 24, FUNCTION_NAME(PD_CONN_USB_2_PHY));
|
||||
clks[IMX8QM_USB3_ACLK] = imx_clk_gate_scu("usb3_aclk", "usb3_aclk_div", SC_R_USB_2, SC_PM_CLK_PER, (void __iomem *)(USB_3_LPCG), 28, 0);
|
||||
clks[IMX8QM_USB3_BUS_CLK] = imx_clk_gate_scu("usb3_bus_clk", "usb3_bus_div", SC_R_USB_2, SC_PM_CLK_MST_BUS, (void __iomem *)(USB_3_LPCG), 0, 0);
|
||||
clks[IMX8QM_USB3_LPM_CLK] = imx_clk_gate_scu("usb3_lpm_clk", "usb3_lpm_div", SC_R_USB_2, SC_PM_CLK_MISC, (void __iomem *)(USB_3_LPCG), 4, 0);
|
||||
clks[IMX8QM_EDMA_CLK] = imx_clk_gate2_scu("edma_clk", "axi_conn_clk_root", (void __iomem *)(EDMA_LPCG), 0, FUNCTION_NAME(PD_CONN_DMA_4_CH0));
|
||||
clks[IMX8QM_EDMA_IPG_CLK] = imx_clk_gate2_scu("edma_ipg_clk", "ipg_conn_clk_root", (void __iomem *)(EDMA_LPCG), 16, FUNCTION_NAME(PD_CONN_DMA_4_CH0));
|
||||
clks[IMX8QM_MLB_HCLK] = imx_clk_gate2_scu("mlb_hclk", "axi_conn_clk_root", (void __iomem *)(MLB_LPCG), 20, FUNCTION_NAME(PD_CONN_MLB_0));
|
||||
clks[IMX8QM_MLB_CLK] = imx_clk_gate2_scu("mlb_clk", "mlb_hclk", (void __iomem *)(MLB_LPCG), 0, FUNCTION_NAME(PD_CONN_MLB_0));
|
||||
clks[IMX8QM_MLB_IPG_CLK] = imx_clk_gate2_scu("mlb_ipg_clk", "ipg_conn_clk_root", (void __iomem *)(MLB_LPCG), 16, FUNCTION_NAME(PD_CONN_MLB_0));
|
||||
|
||||
/* DMA */
|
||||
clks[IMX8QM_UART0_IPG_CLK] = imx_clk_gate2_scu("uart0_ipg_clk", "ipg_dma_clk_root", (void __iomem *)(LPUART_0_LPCG), 16, FUNCTION_NAME(PD_DMA_UART0));
|
||||
clks[IMX8QM_UART1_IPG_CLK] = imx_clk_gate2_scu("uart1_ipg_clk", "ipg_dma_clk_root", (void __iomem *)(LPUART_1_LPCG), 16, FUNCTION_NAME(PD_DMA_UART1));
|
||||
clks[IMX8QM_UART2_IPG_CLK] = imx_clk_gate2_scu("uart2_ipg_clk", "ipg_dma_clk_root", (void __iomem *)(LPUART_2_LPCG), 16, FUNCTION_NAME(PD_DMA_UART2));
|
||||
clks[IMX8QM_UART3_IPG_CLK] = imx_clk_gate2_scu("uart3_ipg_clk", "ipg_dma_clk_root", (void __iomem *)(LPUART_3_LPCG), 16, FUNCTION_NAME(PD_DMA_UART3));
|
||||
clks[IMX8QM_UART4_IPG_CLK] = imx_clk_gate2_scu("uart4_ipg_clk", "ipg_dma_clk_root", (void __iomem *)(LPUART_4_LPCG), 16, FUNCTION_NAME(PD_DMA_UART4));
|
||||
clks[IMX8QM_UART0_CLK] = imx_clk_gate_scu("uart0_clk", "uart0_div", SC_R_UART_0, SC_PM_CLK_PER, (void __iomem *)(LPUART_0_LPCG), 0, 0);
|
||||
clks[IMX8QM_UART1_CLK] = imx_clk_gate_scu("uart1_clk", "uart1_div", SC_R_UART_1, SC_PM_CLK_PER, (void __iomem *)(LPUART_1_LPCG), 0, 0);
|
||||
clks[IMX8QM_UART2_CLK] = imx_clk_gate_scu("uart2_clk", "uart2_div", SC_R_UART_2, SC_PM_CLK_PER, (void __iomem *)(LPUART_2_LPCG), 0, 0);
|
||||
clks[IMX8QM_UART3_CLK] = imx_clk_gate_scu("uart3_clk", "uart3_div", SC_R_UART_3, SC_PM_CLK_PER, (void __iomem *)(LPUART_3_LPCG), 0, 0);
|
||||
clks[IMX8QM_UART4_CLK] = imx_clk_gate_scu("uart4_clk", "uart4_div", SC_R_UART_4, SC_PM_CLK_PER, (void __iomem *)(LPUART_4_LPCG), 0, 0);
|
||||
clks[IMX8QM_SPI0_IPG_CLK] = imx_clk_gate2_scu("spi0_ipg_clk", "ipg_dma_clk_root", (void __iomem *)(LPSPI_0_LPCG), 16, FUNCTION_NAME(PD_DMA_SPI_0));
|
||||
clks[IMX8QM_SPI1_IPG_CLK] = imx_clk_gate2_scu("spi1_ipg_clk", "ipg_dma_clk_root", (void __iomem *)(LPSPI_1_LPCG), 16, FUNCTION_NAME(PD_DMA_SPI_1));
|
||||
clks[IMX8QM_SPI2_IPG_CLK] = imx_clk_gate2_scu("spi2_ipg_clk", "ipg_dma_clk_root", (void __iomem *)(LPSPI_2_LPCG), 16, FUNCTION_NAME(PD_DMA_SPI_2));
|
||||
clks[IMX8QM_SPI3_IPG_CLK] = imx_clk_gate2_scu("spi3_ipg_clk", "ipg_dma_clk_root", (void __iomem *)(LPSPI_3_LPCG), 16, FUNCTION_NAME(PD_DMA_SPI_3));
|
||||
clks[IMX8QM_SPI0_CLK] = imx_clk_gate_scu("spi0_clk", "spi0_div", SC_R_SPI_0, SC_PM_CLK_PER, (void __iomem *)(LPSPI_0_LPCG), 0, 0);
|
||||
clks[IMX8QM_SPI1_CLK] = imx_clk_gate_scu("spi1_clk", "spi1_div", SC_R_SPI_2, SC_PM_CLK_PER, (void __iomem *)(LPSPI_1_LPCG), 0, 0);
|
||||
clks[IMX8QM_SPI2_CLK] = imx_clk_gate_scu("spi2_clk", "spi2_div", SC_R_SPI_2, SC_PM_CLK_PER, (void __iomem *)(LPSPI_2_LPCG), 0, 0);
|
||||
clks[IMX8QM_SPI3_CLK] = imx_clk_gate_scu("spi3_clk", "spi3_div", SC_R_SPI_3, SC_PM_CLK_PER, (void __iomem *)(LPSPI_3_LPCG), 0, 0);
|
||||
clks[IMX8QM_EMVSIM0_IPG_CLK] = imx_clk_gate2_scu("emvsim0_ipg_clk", "ipg_dma_clk_root", (void __iomem *)(EMVSIM_0_LPCG), 16, FUNCTION_NAME(PD_DMA_EMVSIM_0));
|
||||
clks[IMX8QM_EMVSIM1_IPG_CLK] = imx_clk_gate2_scu("emvsim1_ipg_clk", "ipg_dma_clk_root", (void __iomem *)(EMVSIM_1_LPCG), 16, FUNCTION_NAME(PD_DMA_EMVSIM_1));
|
||||
clks[IMX8QM_EMVSIM0_CLK] = imx_clk_gate_scu("emvsim0_clk", "emvsim0_div", SC_R_EMVSIM_0, SC_PM_CLK_PER, (void __iomem *)(EMVSIM_0_LPCG), 0, 0);
|
||||
clks[IMX8QM_EMVSIM1_CLK] = imx_clk_gate_scu("emvsim1_clk", "emvsim1_div", SC_R_EMVSIM_0, SC_PM_CLK_PER, (void __iomem *)(EMVSIM_1_LPCG), 0, 0);
|
||||
clks[IMX8QM_CAN0_IPG_CHI_CLK] = imx_clk_gate2_scu("can0_ipg_chi_clk", "ipg_dma_clk_root", (void __iomem *)(FLEX_CAN_0_LPCG), 20, FUNCTION_NAME(PD_DMA_CAN_0));
|
||||
clks[IMX8QM_CAN0_IPG_CLK] = imx_clk_gate2_scu("can0_ipg_clk", "can0_ipg_chi_clk", (void __iomem *)(FLEX_CAN_0_LPCG), 16, FUNCTION_NAME(PD_DMA_CAN_0));
|
||||
clks[IMX8QM_CAN1_IPG_CHI_CLK] = imx_clk_gate2_scu("can1_ipg_chi_clk", "ipg_dma_clk_root", (void __iomem *)(FLEX_CAN_1_LPCG), 20, FUNCTION_NAME(PD_DMA_CAN_1));
|
||||
clks[IMX8QM_CAN1_IPG_CLK] = imx_clk_gate2_scu("can1_ipg_clk", "can1_ipg_chi_clk", (void __iomem *)(FLEX_CAN_1_LPCG), 16, FUNCTION_NAME(PD_DMA_CAN_1));
|
||||
clks[IMX8QM_CAN2_IPG_CHI_CLK] = imx_clk_gate2_scu("can2_ipg_chi_clk", "ipg_dma_clk_root", (void __iomem *)(FLEX_CAN_2_LPCG), 20, FUNCTION_NAME(PD_DMA_CAN_2));
|
||||
clks[IMX8QM_CAN2_IPG_CLK] = imx_clk_gate2_scu("can2_ipg_clk", "can2_ipg_chi_clk", (void __iomem *)(FLEX_CAN_2_LPCG), 16, FUNCTION_NAME(PD_DMA_CAN_2));
|
||||
clks[IMX8QM_CAN0_CLK] = imx_clk_gate_scu("can0_clk", "can0_div", SC_R_CAN_0, SC_PM_CLK_PER, (void __iomem *)(FLEX_CAN_0_LPCG), 0, 0);
|
||||
clks[IMX8QM_CAN1_CLK] = imx_clk_gate_scu("can1_clk", "can1_div", SC_R_CAN_1, SC_PM_CLK_PER, (void __iomem *)(FLEX_CAN_1_LPCG), 0, 0);
|
||||
clks[IMX8QM_CAN2_CLK] = imx_clk_gate_scu("can2_clk", "can2_div", SC_R_CAN_2, SC_PM_CLK_PER, (void __iomem *)(FLEX_CAN_2_LPCG), 0, 0);
|
||||
clks[IMX8QM_I2C0_IPG_CLK] = imx_clk_gate2_scu("i2c0_ipg_clk", "ipg_dma_clk_root", (void __iomem *)(LPI2C_0_LPCG), 16, FUNCTION_NAME(PD_DMA_I2C_0));
|
||||
clks[IMX8QM_I2C1_IPG_CLK] = imx_clk_gate2_scu("i2c1_ipg_clk", "ipg_dma_clk_root", (void __iomem *)(LPI2C_1_LPCG), 16, FUNCTION_NAME(PD_DMA_I2C_1));
|
||||
clks[IMX8QM_I2C2_IPG_CLK] = imx_clk_gate2_scu("i2c2_ipg_clk", "ipg_dma_clk_root", (void __iomem *)(LPI2C_2_LPCG), 16, FUNCTION_NAME(PD_DMA_I2C_2));
|
||||
clks[IMX8QM_I2C3_IPG_CLK] = imx_clk_gate2_scu("i2c3_ipg_clk", "ipg_dma_clk_root", (void __iomem *)(LPI2C_3_LPCG), 16, FUNCTION_NAME(PD_DMA_I2C_3));
|
||||
clks[IMX8QM_I2C4_IPG_CLK] = imx_clk_gate2_scu("i2c4_ipg_clk", "ipg_dma_clk_root", (void __iomem *)(LPI2C_4_LPCG), 16, FUNCTION_NAME(PD_DMA_I2C_4));
|
||||
clks[IMX8QM_I2C0_CLK] = imx_clk_gate_scu("i2c0_clk", "i2c0_div", SC_R_I2C_0, SC_PM_CLK_PER, (void __iomem *)(LPI2C_0_LPCG), 0, 0);
|
||||
clks[IMX8QM_I2C1_CLK] = imx_clk_gate_scu("i2c1_clk", "i2c1_div", SC_R_I2C_1, SC_PM_CLK_PER, (void __iomem *)(LPI2C_1_LPCG), 0, 0);
|
||||
clks[IMX8QM_I2C2_CLK] = imx_clk_gate_scu("i2c2_clk", "i2c2_div", SC_R_I2C_2, SC_PM_CLK_PER, (void __iomem *)(LPI2C_2_LPCG), 0, 0);
|
||||
clks[IMX8QM_I2C3_CLK] = imx_clk_gate_scu("i2c3_clk", "i2c3_div", SC_R_I2C_3, SC_PM_CLK_PER, (void __iomem *)(LPI2C_3_LPCG), 0, 0);
|
||||
clks[IMX8QM_I2C4_CLK] = imx_clk_gate_scu("i2c4_clk", "i2c4_div", SC_R_I2C_4, SC_PM_CLK_PER, (void __iomem *)(LPI2C_4_LPCG), 0, 0);
|
||||
clks[IMX8QM_FTM0_IPG_CLK] = imx_clk_gate2_scu("ftm0_ipg_clk", "ipg_dma_clk_root", (void __iomem *)(FTM_0_LPCG), 16, FUNCTION_NAME(PD_DMA_FTM_0));
|
||||
clks[IMX8QM_FTM1_IPG_CLK] = imx_clk_gate2_scu("ftm1_ipg_clk", "ipg_dma_clk_root", (void __iomem *)(FTM_1_LPCG), 16, FUNCTION_NAME(PD_DMA_FTM_1));
|
||||
clks[IMX8QM_FTM0_CLK] = imx_clk_gate_scu("ftm0_clk", "ftm0_div", SC_R_FTM_0, SC_PM_CLK_PER, (void __iomem *)(FTM_0_LPCG), 0, 0);
|
||||
clks[IMX8QM_FTM1_CLK] = imx_clk_gate_scu("ftm1_clk", "ftm1_div", SC_R_FTM_1, SC_PM_CLK_PER, (void __iomem *)(FTM_1_LPCG), 0, 0);
|
||||
clks[IMX8QM_ADC0_IPG_CLK] = imx_clk_gate2_scu("adc0_ipg_clk", "ipg_dma_clk_root", (void __iomem *)(ADC_0_LPCG), 16, FUNCTION_NAME(PD_DMA_ADC_0));
|
||||
clks[IMX8QM_ADC1_IPG_CLK] = imx_clk_gate2_scu("adc1_ipg_clk", "ipg_dma_clk_root", (void __iomem *)(ADC_1_LPCG), 16, FUNCTION_NAME(PD_DMA_ADC_1));
|
||||
clks[IMX8QM_ADC0_CLK] = imx_clk_gate_scu("adc0_clk", "adc0_div", SC_R_ADC_0, SC_PM_CLK_PER, (void __iomem *)(ADC_0_LPCG), 0, 0);
|
||||
clks[IMX8QM_ADC1_CLK] = imx_clk_gate_scu("adc1_clk", "adc1_div", SC_R_ADC_1, SC_PM_CLK_PER, (void __iomem *)(ADC_1_LPCG), 0, 0);
|
||||
|
||||
/* LSIO SS */
|
||||
clks[IMX8QM_PWM0_IPG_S_CLK] = imx_clk_gate_scu("pwm_0_ipg_s_clk", "pwm_0_div", SC_R_PWM_0, SC_PM_CLK_PER, (void __iomem *)(PWM_0_LPCG), 0x10, 0);
|
||||
clks[IMX8QM_PWM0_IPG_SLV_CLK] = imx_clk_gate_scu("pwm_0_ipg_slv_clk", "pwm_0_ipg_s_clk", SC_R_PWM_0, SC_PM_CLK_PER, (void __iomem *)(PWM_0_LPCG), 0x14, 0);
|
||||
clks[IMX8QM_PWM0_IPG_MSTR_CLK] = imx_clk_gate2_scu("pwm_0_ipg_mstr_clk", "lsio_bus_clk_root", (void __iomem *)(PWM_0_LPCG), 0x18, FUNCTION_NAME(PD_LSIO_PWM_0));
|
||||
clks[IMX8QM_PWM0_HF_CLK] = imx_clk_gate_scu("pwm_0_hf_clk", "pwm_0_ipg_slv_clk", SC_R_PWM_0, SC_PM_CLK_PER, (void __iomem *)(PWM_0_LPCG), 4, 0);
|
||||
clks[IMX8QM_PWM0_CLK] = imx_clk_gate_scu("pwm_0_clk", "pwm_0_ipg_slv_clk", SC_R_PWM_0, SC_PM_CLK_PER, (void __iomem *)(PWM_0_LPCG), 0, 0);
|
||||
clks[IMX8QM_PWM1_IPG_S_CLK] = imx_clk_gate_scu("pwm_1_ipg_s_clk", "pwm_1_div", SC_R_PWM_1, SC_PM_CLK_PER, (void __iomem *)(PWM_1_LPCG), 0x10, 0);
|
||||
clks[IMX8QM_PWM1_IPG_SLV_CLK] = imx_clk_gate_scu("pwm_1_ipg_slv_clk", "pwm_1_ipg_s_clk", SC_R_PWM_1, SC_PM_CLK_PER, (void __iomem *)(PWM_1_LPCG), 0x14, 0);
|
||||
clks[IMX8QM_PWM1_IPG_MSTR_CLK] = imx_clk_gate2_scu("pwm_1_ipg_mstr_clk", "lsio_bus_clk_root", (void __iomem *)(PWM_1_LPCG), 0x18, FUNCTION_NAME(PD_LSIO_PWM_1));
|
||||
clks[IMX8QM_PWM1_HF_CLK] = imx_clk_gate_scu("pwm_1_hf_clk", "pwm_1_ipg_slv_clk", SC_R_PWM_1, SC_PM_CLK_PER, (void __iomem *)(PWM_1_LPCG), 4, 0);
|
||||
clks[IMX8QM_PWM1_CLK] = imx_clk_gate_scu("pwm_1_clk", "pwm_1_ipg_slv_clk", SC_R_PWM_1, SC_PM_CLK_PER, (void __iomem *)(PWM_1_LPCG), 0, 0);
|
||||
clks[IMX8QM_PWM2_IPG_S_CLK] = imx_clk_gate_scu("pwm_2_ipg_s_clk", "pwm_2_div", SC_R_PWM_2, SC_PM_CLK_PER, (void __iomem *)(PWM_2_LPCG), 0x10, 0);
|
||||
clks[IMX8QM_PWM2_IPG_SLV_CLK] = imx_clk_gate_scu("pwm_2_ipg_slv_clk", "pwm_2_ipg_s_clk", SC_R_PWM_2, SC_PM_CLK_PER, (void __iomem *)(PWM_2_LPCG), 0x14, 0);
|
||||
clks[IMX8QM_PWM2_IPG_MSTR_CLK] = imx_clk_gate2_scu("pwm_2_ipg_mstr_clk", "lsio_bus_clk_root", (void __iomem *)(PWM_2_LPCG), 0x18, FUNCTION_NAME(PD_LSIO_PWM_2));
|
||||
clks[IMX8QM_PWM2_HF_CLK] = imx_clk_gate_scu("pwm_2_hf_clk", "pwm_2_ipg_slv_clk", SC_R_PWM_2, SC_PM_CLK_PER, (void __iomem *)(PWM_2_LPCG), 4, 0);
|
||||
clks[IMX8QM_PWM2_CLK] = imx_clk_gate_scu("pwm_2_clk", "pwm_2_ipg_slv_clk", SC_R_PWM_2, SC_PM_CLK_PER, (void __iomem *)(PWM_2_LPCG), 0, 0);
|
||||
clks[IMX8QM_PWM3_IPG_S_CLK] = imx_clk_gate_scu("pwm_3_ipg_s_clk", "pwm_3_div", SC_R_PWM_3, SC_PM_CLK_PER, (void __iomem *)(PWM_3_LPCG), 0x10, 0);
|
||||
clks[IMX8QM_PWM3_IPG_SLV_CLK] = imx_clk_gate_scu("pwm_3_ipg_slv_clk", "pwm_3_ipg_s_clk", SC_R_PWM_3, SC_PM_CLK_PER, (void __iomem *)(PWM_3_LPCG), 0x14, 0);
|
||||
clks[IMX8QM_PWM3_IPG_MSTR_CLK] = imx_clk_gate2_scu("pwm_3_ipg_mstr_clk", "lsio_bus_clk_root", (void __iomem *)(PWM_3_LPCG), 0x18, FUNCTION_NAME(PD_LSIO_PWM_3));
|
||||
clks[IMX8QM_PWM3_HF_CLK] = imx_clk_gate_scu("pwm_3_hf_clk", "pwm_3_ipg_slv_clk", SC_R_PWM_3, SC_PM_CLK_PER, (void __iomem *)(PWM_3_LPCG), 4, 0);
|
||||
clks[IMX8QM_PWM3_CLK] = imx_clk_gate_scu("pwm_3_clk", "pwm_3_ipg_slv_clk", SC_R_PWM_3, SC_PM_CLK_PER, (void __iomem *)(PWM_3_LPCG), 0, 0);
|
||||
clks[IMX8QM_PWM4_IPG_S_CLK] = imx_clk_gate_scu("pwm_4_ipg_s_clk", "pwm_4_div", SC_R_PWM_4, SC_PM_CLK_PER, (void __iomem *)(PWM_4_LPCG), 0x10, 0);
|
||||
clks[IMX8QM_PWM4_IPG_SLV_CLK] = imx_clk_gate_scu("pwm_4_ipg_slv_clk", "pwm_4_ipg_s_clk", SC_R_PWM_4, SC_PM_CLK_PER, (void __iomem *)(PWM_4_LPCG), 0x14, 0);
|
||||
clks[IMX8QM_PWM4_IPG_MSTR_CLK] = imx_clk_gate2_scu("pwm_4_ipg_mstr_clk", "lsio_bus_clk_root", (void __iomem *)(PWM_4_LPCG), 0x18, FUNCTION_NAME(PD_LSIO_PWM_4));
|
||||
clks[IMX8QM_PWM4_HF_CLK] = imx_clk_gate_scu("pwm_4_hf_clk", "pwm_4_ipg_slv_clk", SC_R_PWM_4, SC_PM_CLK_PER, (void __iomem *)(PWM_4_LPCG), 4, 0);
|
||||
clks[IMX8QM_PWM4_CLK] = imx_clk_gate_scu("pwm_4_clk", "pwm_4_ipg_slv_clk", SC_R_PWM_4, SC_PM_CLK_PER, (void __iomem *)(PWM_4_LPCG), 0, 0);
|
||||
clks[IMX8QM_PWM5_IPG_S_CLK] = imx_clk_gate_scu("pwm_5_ipg_s_clk", "pwm_5_div", SC_R_PWM_5, SC_PM_CLK_PER, (void __iomem *)(PWM_5_LPCG), 0x10, 0);
|
||||
clks[IMX8QM_PWM5_IPG_SLV_CLK] = imx_clk_gate_scu("pwm_5_ipg_slv_clk", "pwm_5_ipg_s_clk", SC_R_PWM_5, SC_PM_CLK_PER, (void __iomem *)(PWM_5_LPCG), 0x14, 0);
|
||||
clks[IMX8QM_PWM5_IPG_MSTR_CLK] = imx_clk_gate2_scu("pwm_5_ipg_mstr_clk", "lsio_bus_clk_root", (void __iomem *)(PWM_5_LPCG), 0x18, FUNCTION_NAME(PD_LSIO_PWM_5));
|
||||
clks[IMX8QM_PWM5_HF_CLK] = imx_clk_gate_scu("pwm_5_hf_clk", "pwm_5_ipg_slv_clk", SC_R_PWM_5, SC_PM_CLK_PER, (void __iomem *)(PWM_5_LPCG), 4, 0);
|
||||
clks[IMX8QM_PWM5_CLK] = imx_clk_gate_scu("pwm_5_clk", "pwm_5_ipg_slv_clk", SC_R_PWM_5, SC_PM_CLK_PER, (void __iomem *)(PWM_5_LPCG), 0, 0);
|
||||
clks[IMX8QM_PWM6_IPG_S_CLK] = imx_clk_gate_scu("pwm_6_ipg_s_clk", "pwm_6_div", SC_R_PWM_6, SC_PM_CLK_PER, (void __iomem *)(PWM_6_LPCG), 0x10, 0);
|
||||
clks[IMX8QM_PWM6_IPG_SLV_CLK] = imx_clk_gate_scu("pwm_6_ipg_slv_clk", "pwm_6_ipg_s_clk", SC_R_PWM_6, SC_PM_CLK_PER, (void __iomem *)(PWM_6_LPCG), 0x14, 0);
|
||||
clks[IMX8QM_PWM6_IPG_MSTR_CLK] = imx_clk_gate2_scu("pwm_6_ipg_mstr_clk", "lsio_bus_clk_root", (void __iomem *)(PWM_6_LPCG), 0x18, FUNCTION_NAME(PD_LSIO_PWM_6));
|
||||
clks[IMX8QM_PWM6_HF_CLK] = imx_clk_gate_scu("pwm_6_hf_clk", "pwm_6_ipg_slv_clk", SC_R_PWM_6, SC_PM_CLK_PER, (void __iomem *)(PWM_6_LPCG), 4, 0);
|
||||
clks[IMX8QM_PWM6_CLK] = imx_clk_gate_scu("pwm_6_clk", "pwm_6_ipg_slv_clk", SC_R_PWM_6, SC_PM_CLK_PER, (void __iomem *)(PWM_6_LPCG), 0, 0);
|
||||
clks[IMX8QM_PWM7_IPG_S_CLK] = imx_clk_gate_scu("pwm_7_ipg_s_clk", "pwm_7_div", SC_R_PWM_7, SC_PM_CLK_PER, (void __iomem *)(PWM_7_LPCG), 0x10, 0);
|
||||
clks[IMX8QM_PWM7_IPG_SLV_CLK] = imx_clk_gate_scu("pwm_7_ipg_slv_clk", "pwm_7_ipg_s_clk", SC_R_PWM_7, SC_PM_CLK_PER, (void __iomem *)(PWM_7_LPCG), 0x14, 0);
|
||||
clks[IMX8QM_PWM7_IPG_MSTR_CLK] = imx_clk_gate2_scu("pwm_7_ipg_mstr_clk", "lsio_bus_clk_root", (void __iomem *)(PWM_7_LPCG), 0x18, FUNCTION_NAME(PD_LSIO_PWM_7));
|
||||
clks[IMX8QM_PWM7_HF_CLK] = imx_clk_gate_scu("pwm_7_hf_clk", "pwm_7_ipg_slv_clk", SC_R_PWM_7, SC_PM_CLK_PER, (void __iomem *)(PWM_7_LPCG), 4, 0);
|
||||
clks[IMX8QM_PWM7_CLK] = imx_clk_gate_scu("pwm_7_clk", "pwm_7_ipg_slv_clk", SC_R_PWM_7, SC_PM_CLK_PER, (void __iomem *)(PWM_7_LPCG), 0, 0);
|
||||
clks[IMX8QM_GPT0_IPG_S_CLK] = imx_clk_gate_scu("gpt_0_ipg_s_clk", "gpt_0_div", SC_R_GPT_0, SC_PM_CLK_PER, (void __iomem *)(GPT_0_LPCG), 0x10, 0);
|
||||
clks[IMX8QM_GPT0_IPG_SLV_CLK] = imx_clk_gate_scu("gpt_0_ipg_slv_clk", "gpt_0_ipg_s_clk", SC_R_GPT_0, SC_PM_CLK_PER, (void __iomem *)(GPT_0_LPCG), 0x14, 0);
|
||||
clks[IMX8QM_GPT0_CLK] = imx_clk_gate_scu("gpt_0_clk", "gpt_0_ipg_slv_clk", SC_R_GPT_0, SC_PM_CLK_PER, (void __iomem *)(GPT_0_LPCG), 0, 0);
|
||||
clks[IMX8QM_GPT0_IPG_MSTR_CLK] = imx_clk_gate2_scu("gpt_0_ipg_mstr_clk", "lsio_bus_clk_root", (void __iomem *)(GPT_0_LPCG), 0x18, FUNCTION_NAME(PD_LSIO_GPT_0));
|
||||
clks[IMX8QM_GPT0_HF_CLK] = imx_clk_gate_scu("gpt_0_hf_clk", "gpt_0_ipg_slv_clk", SC_R_GPT_0, SC_PM_CLK_PER, (void __iomem *)(GPT_0_LPCG), 4, 0);
|
||||
clks[IMX8QM_GPT1_IPG_S_CLK] = imx_clk_gate_scu("gpt_1_ipg_s_clk", "gpt_1_div", SC_R_GPT_1, SC_PM_CLK_PER, (void __iomem *)(GPT_1_LPCG), 0x10, 0);
|
||||
clks[IMX8QM_GPT1_IPG_SLV_CLK] = imx_clk_gate_scu("gpt_1_ipg_slv_clk", "gpt_1_ipg_s_clk", SC_R_GPT_1, SC_PM_CLK_PER, (void __iomem *)(GPT_1_LPCG), 0x14, 0);
|
||||
clks[IMX8QM_GPT1_CLK] = imx_clk_gate_scu("gpt_1_clk", "gpt_1_ipg_slv_clk", SC_R_GPT_1, SC_PM_CLK_PER, (void __iomem *)(GPT_1_LPCG), 0, 0);
|
||||
clks[IMX8QM_GPT1_HF_CLK] = imx_clk_gate_scu("gpt_1_hf_clk", "gpt_1_ipg_slv_clk", SC_R_GPT_1, SC_PM_CLK_PER, (void __iomem *)(GPT_1_LPCG), 4, 0);
|
||||
clks[IMX8QM_GPT1_IPG_MSTR_CLK] = imx_clk_gate2_scu("gpt_1_ipg_mstr_clk", "lsio_bus_clk_root", (void __iomem *)(GPT_1_LPCG), 0x18, FUNCTION_NAME(PD_LSIO_GPT_1));
|
||||
clks[IMX8QM_GPT2_IPG_S_CLK] = imx_clk_gate_scu("gpt_2_ipg_s_clk", "gpt_2_div", SC_R_GPT_2, SC_PM_CLK_PER, (void __iomem *)(GPT_2_LPCG), 0x10, 0);
|
||||
clks[IMX8QM_GPT2_IPG_SLV_CLK] = imx_clk_gate_scu("gpt_2_ipg_slv_clk", "gpt_2_ipg_s_clk", SC_R_GPT_2, SC_PM_CLK_PER, (void __iomem *)(GPT_2_LPCG), 0x14, 0);
|
||||
clks[IMX8QM_GPT2_CLK] = imx_clk_gate_scu("gpt_2_clk", "gpt_2_ipg_slv_clk", SC_R_GPT_2, SC_PM_CLK_PER, (void __iomem *)(GPT_2_LPCG), 0, 0);
|
||||
clks[IMX8QM_GPT2_HF_CLK] = imx_clk_gate_scu("gpt_2_hf_clk", "gpt_2_div", SC_R_GPT_2, SC_PM_CLK_PER, (void __iomem *)(GPT_2_LPCG), 4, 0);
|
||||
clks[IMX8QM_GPT2_IPG_MSTR_CLK] = imx_clk_gate2_scu("gpt_2_ipg_mstr_clk", "lsio_bus_clk_root", (void __iomem *)(GPT_2_LPCG), 0x18, FUNCTION_NAME(PD_LSIO_GPT_2));
|
||||
clks[IMX8QM_GPT3_IPG_S_CLK] = imx_clk_gate_scu("gpt_3_ipg_s_clk", "gpt_3_div", SC_R_GPT_3, SC_PM_CLK_PER, (void __iomem *)(GPT_3_LPCG), 0x10, 0);
|
||||
clks[IMX8QM_GPT3_IPG_SLV_CLK] = imx_clk_gate_scu("gpt_3_ipg_slv_clk", "gpt_3_ipg_s_clk", SC_R_GPT_3, SC_PM_CLK_PER, (void __iomem *)(GPT_3_LPCG), 0x14, 0);
|
||||
clks[IMX8QM_GPT3_CLK] = imx_clk_gate_scu("gpt_3_clk", "gpt_3_ipg_slv_clk", SC_R_GPT_3, SC_PM_CLK_PER, (void __iomem *)(GPT_3_LPCG), 0, 0);
|
||||
clks[IMX8QM_GPT3_HF_CLK] = imx_clk_gate_scu("gpt_3_hf_clk", "gpt_3_ipg_slv_clk", SC_R_GPT_3, SC_PM_CLK_PER, (void __iomem *)(GPT_3_LPCG), 4, 0);
|
||||
clks[IMX8QM_GPT3_IPG_MSTR_CLK] = imx_clk_gate2_scu("gpt_3_ipg_mstr_clk", "lsio_bus_clk_root", (void __iomem *)(GPT_3_LPCG), 0x18, FUNCTION_NAME(PD_LSIO_GPT_3));
|
||||
clks[IMX8QM_GPT4_IPG_S_CLK] = imx_clk_gate_scu("gpt_4_ipg_s_clk", "gpt_4_div", SC_R_GPT_4, SC_PM_CLK_PER, (void __iomem *)(GPT_4_LPCG), 0x10, 0);
|
||||
clks[IMX8QM_GPT4_IPG_SLV_CLK] = imx_clk_gate_scu("gpt_4_ipg_slv_clk", "gpt_4_ipg_s_clk", SC_R_GPT_4, SC_PM_CLK_PER, (void __iomem *)(GPT_4_LPCG), 0x14, 0);
|
||||
clks[IMX8QM_GPT4_CLK] = imx_clk_gate_scu("gpt_4_clk", "gpt_4_div", SC_R_GPT_4, SC_PM_CLK_PER, (void __iomem *)(GPT_4_LPCG), 0, 0);
|
||||
clks[IMX8QM_GPT4_HF_CLK] = imx_clk_gate_scu("gpt_4_hf_clk", "gpt_4_div", SC_R_GPT_4, SC_PM_CLK_PER, (void __iomem *)(GPT_4_LPCG), 4, 0);
|
||||
clks[IMX8QM_GPT4_IPG_MSTR_CLK] = imx_clk_gate2_scu("gpt_4_ipg_mstr_clk", "lsio_bus_clk_root", (void __iomem *)(GPT_4_LPCG), 0x18, FUNCTION_NAME(PD_LSIO_GPT_4));
|
||||
clks[IMX8QM_FSPI0_HCLK] = imx_clk_gate2_scu("fspi0_hclk_clk", "lsio_mem_clk_root", (void __iomem *)(FSPI_0_LPCG), 0x10, FUNCTION_NAME(PD_LSIO_FSPI_0));
|
||||
clks[IMX8QM_FSPI0_IPG_S_CLK] = imx_clk_gate2_scu("fspi0_ipg_s_clk", "lsio_bus_clk_root", (void __iomem *)(FSPI_0_LPCG), 0x18, FUNCTION_NAME(PD_LSIO_FSPI_0));
|
||||
clks[IMX8QM_FSPI0_IPG_CLK] = imx_clk_gate2_scu("fspi0_ipg_clk", "fspi0_ipg_s_clk", (void __iomem *)(FSPI_0_LPCG), 0x14, FUNCTION_NAME(PD_LSIO_FSPI_0));
|
||||
clks[IMX8QM_FSPI0_CLK] = imx_clk_gate_scu("fspi_0_clk", "fspi_0_div", SC_R_FSPI_0, SC_PM_CLK_PER, (void __iomem *)(FSPI_0_LPCG), 0, 0);
|
||||
clks[IMX8QM_FSPI1_HCLK] = imx_clk_gate2_scu("fspi1_hclk_clk", "lsio_mem_clk_root", (void __iomem *)(FSPI_1_LPCG), 0x10, FUNCTION_NAME(PD_LSIO_FSPI_1));
|
||||
clks[IMX8QM_FSPI1_IPG_S_CLK] = imx_clk_gate2_scu("fspi1_ipg_s_clk", "lsio_bus_clk_root", (void __iomem *)(FSPI_1_LPCG), 0x18, FUNCTION_NAME(PD_LSIO_FSPI_1));
|
||||
clks[IMX8QM_FSPI1_IPG_CLK] = imx_clk_gate2_scu("fspi1_ipg_clk", "fspi1_ipg_s_clk", (void __iomem *)(FSPI_1_LPCG), 0x14, FUNCTION_NAME(PD_LSIO_FSPI_1));
|
||||
clks[IMX8QM_FSPI1_CLK] = imx_clk_gate_scu("fspi_1_clk", "fspi_1_div", SC_R_FSPI_1, SC_PM_CLK_PER, (void __iomem *)(FSPI_1_LPCG), 0, 0);
|
||||
clks[IMX8QM_GPIO0_IPG_S_CLK] = imx_clk_gate2_scu("gpio0_ipg_s_clk", "lsio_bus_clk_root", (void __iomem *)(GPIO_0_LPCG), 0x10, FUNCTION_NAME(PD_LSIO_GPIO_0));
|
||||
clks[IMX8QM_GPIO1_IPG_S_CLK] = imx_clk_gate2_scu("gpio1_ipg_s_clk", "lsio_bus_clk_root", (void __iomem *)(GPIO_1_LPCG), 0x10, FUNCTION_NAME(PD_LSIO_GPIO_1));
|
||||
clks[IMX8QM_GPIO2_IPG_S_CLK] = imx_clk_gate2_scu("gpio2_ipg_s_clk", "lsio_bus_clk_root", (void __iomem *)(GPIO_2_LPCG), 0x10, FUNCTION_NAME(PD_LSIO_GPIO_2));
|
||||
clks[IMX8QM_GPIO3_IPG_S_CLK] = imx_clk_gate2_scu("gpio3_ipg_s_clk", "lsio_bus_clk_root", (void __iomem *)(GPIO_3_LPCG), 0x10, FUNCTION_NAME(PD_LSIO_GPIO_3));
|
||||
clks[IMX8QM_GPIO4_IPG_S_CLK] = imx_clk_gate2_scu("gpio4_ipg_s_clk", "lsio_bus_clk_root", (void __iomem *)(GPIO_4_LPCG), 0x10, FUNCTION_NAME(PD_LSIO_GPIO_4));
|
||||
clks[IMX8QM_GPIO5_IPG_S_CLK] = imx_clk_gate2_scu("gpio5_ipg_s_clk", "lsio_bus_clk_root", (void __iomem *)(GPIO_5_LPCG), 0x10, FUNCTION_NAME(PD_LSIO_GPIO_5));
|
||||
clks[IMX8QM_GPIO6_IPG_S_CLK] = imx_clk_gate2_scu("gpio6_ipg_s_clk", "lsio_bus_clk_root", (void __iomem *)(GPIO_6_LPCG), 0x10, FUNCTION_NAME(PD_LSIO_GPIO_6));
|
||||
clks[IMX8QM_GPIO7_IPG_S_CLK] = imx_clk_gate2_scu("gpio7_ipg_s_clk", "lsio_bus_clk_root", (void __iomem *)(GPIO_7_LPCG), 0x10, FUNCTION_NAME(PD_LSIO_GPIO_7));
|
||||
clks[IMX8QM_ROMCP_REG_CLK] = imx_clk_gate2_scu("romcp_reg_clk", "lsio_bus_clk_root", (void __iomem *)(ROMCP_LPCG), 0x10, FUNCTION_NAME(PD_LSIO));
|
||||
clks[IMX8QM_ROMCP_CLK] = imx_clk_gate2_scu("romcp_clk", "lsio_mem_clk_root", (void __iomem *)(ROMCP_LPCG), 0x0, FUNCTION_NAME(PD_LSIO));
|
||||
clks[IMX8QM_96KROM_CLK] = imx_clk_gate2_scu("96krom_clk", "lsio_mem_clk_root", (void __iomem *)(ROMCP_LPCG), 0x4, FUNCTION_NAME(PD_LSIO));
|
||||
clks[IMX8QM_OCRAM_MEM_CLK] = imx_clk_gate2_scu("ocram_lk", "lsio_mem_clk_root", (void __iomem *)(OCRAM_LPCG), 0x4, FUNCTION_NAME(PD_LSIO));
|
||||
clks[IMX8QM_OCRAM_CTRL_CLK] = imx_clk_gate2_scu("ocram_ctrl_clk", "lsio_mem_clk_root", (void __iomem *)(OCRAM_LPCG), 0x0, FUNCTION_NAME(PD_LSIO));
|
||||
|
||||
/* Audio */
|
||||
clks[IMX8QM_AUD_ACM_AUD_PLL_CLK0_CLK] = imx_clk_gate_scu("aud_acm_aud_pll_clk0_clk", "aud_acm_aud_pll_clk0_div", SC_R_AUDIO_PLL_0, SC_PM_CLK_MISC0, (void __iomem *)(AUD_PLL_CLK0_LPCG), 0, 0);
|
||||
clks[IMX8QM_AUD_ACM_AUD_PLL_CLK1_CLK] = imx_clk_gate_scu("aud_acm_aud_pll_clk1_clk", "aud_acm_aud_pll_clk1_div", SC_R_AUDIO_PLL_1, SC_PM_CLK_MISC0, (void __iomem *)(AUD_PLL_CLK1_LPCG), 0, 0);
|
||||
clks[IMX8QM_AUD_ACM_AUD_REC_CLK0_CLK] = imx_clk_gate_scu("aud_acm_aud_rec_clk0_clk", "aud_acm_aud_rec_clk0_div", SC_R_AUDIO_PLL_0, SC_PM_CLK_MISC1, (void __iomem *)(AUD_REC_CLK0_LPCG), 0, 0);
|
||||
clks[IMX8QM_AUD_ACM_AUD_REC_CLK1_CLK] = imx_clk_gate_scu("aud_acm_aud_rec_clk1_clk", "aud_acm_aud_rec_clk1_div", SC_R_AUDIO_PLL_1, SC_PM_CLK_MISC1, (void __iomem *)(AUD_REC_CLK1_LPCG), 0, 0);
|
||||
|
||||
np_acm = of_find_compatible_node(NULL, NULL, "nxp,imx8qm-acm");
|
||||
base_acm = of_iomap(np_acm, 0);
|
||||
WARN_ON(!base_acm);
|
||||
|
||||
clks[IMX8QM_HDMI_RX_MCLK] = imx_clk_fixed("hdmi_rx_mclk", 0);
|
||||
clks[IMX8QM_EXT_AUD_MCLK0] = imx_clk_fixed("ext_aud_mclk0", 0);
|
||||
clks[IMX8QM_EXT_AUD_MCLK1] = imx_clk_fixed("ext_aud_mclk1", 0);
|
||||
clks[IMX8QM_ESAI0_RX_CLK] = imx_clk_fixed("esai0_rx_clk", 0);
|
||||
clks[IMX8QM_ESAI0_RX_HF_CLK] = imx_clk_fixed("esai0_rx_hf_clk", 0);
|
||||
clks[IMX8QM_ESAI0_TX_CLK] = imx_clk_fixed("esai0_tx_clk", 0);
|
||||
clks[IMX8QM_ESAI0_TX_HF_CLK] = imx_clk_fixed("esai0_tx_hf_clk", 0);
|
||||
clks[IMX8QM_ESAI1_RX_CLK] = imx_clk_fixed("esai1_rx_clk", 0);
|
||||
clks[IMX8QM_ESAI1_RX_HF_CLK] = imx_clk_fixed("esai1_rx_hf_clk", 0);
|
||||
clks[IMX8QM_ESAI1_TX_CLK] = imx_clk_fixed("esai1_tx_clk", 0);
|
||||
clks[IMX8QM_ESAI1_TX_HF_CLK] = imx_clk_fixed("esai1_tx_hf_clk", 0);
|
||||
clks[IMX8QM_SPDIF0_RX] = imx_clk_fixed("spdif0_rx", 0);
|
||||
clks[IMX8QM_SPDIF1_RX] = imx_clk_fixed("spdif1_rx", 0);
|
||||
clks[IMX8QM_SAI0_RX_BCLK] = imx_clk_fixed("sai0_rx_bclk", 0);
|
||||
clks[IMX8QM_SAI0_TX_BCLK] = imx_clk_fixed("sai0_tx_bclk", 0);
|
||||
clks[IMX8QM_SAI1_RX_BCLK] = imx_clk_fixed("sai1_rx_bclk", 0);
|
||||
clks[IMX8QM_SAI1_TX_BCLK] = imx_clk_fixed("sai1_tx_bclk", 0);
|
||||
clks[IMX8QM_SAI2_RX_BCLK] = imx_clk_fixed("sai2_rx_bclk", 0);
|
||||
clks[IMX8QM_SAI3_RX_BCLK] = imx_clk_fixed("sai3_rx_bclk", 0);
|
||||
clks[IMX8QM_HDMI_RX_SAI0_RX_BCLK] = imx_clk_fixed("hdmi_rx_sai0_rx_bclk", 0);
|
||||
clks[IMX8QM_SAI6_RX_BCLK] = imx_clk_fixed("sai6_rx_bclk", 0);
|
||||
clks[IMX8QM_HDMI_TX_SAI0_TX_BCLK] = imx_clk_fixed("hdmi_tx_sai0_tx_bclk", 0);
|
||||
clks[IMX8QM_ACM_AUD_CLK0_SEL] = imx_clk_mux_scu("acm_aud_clk0_sel", base_acm + 0x00000, 0, 5, aud_clk_sels, ARRAY_SIZE(aud_clk_sels), FUNCTION_NAME(PD_AUDIO));
|
||||
clks[IMX8QM_ACM_AUD_CLK0_CLK] = imx_clk_gate_scu("acm_aud_clk0_clk", "acm_aud_clk0_sel", SC_R_AUDIO_CLK_0, SC_PM_CLK_SLV_BUS, NULL, 0, 0);
|
||||
|
||||
clks[IMX8QM_ACM_AUD_CLK1_SEL] = imx_clk_mux_scu("acm_aud_clk1_sel", base_acm + 0x10000, 0, 5, aud_clk_sels, ARRAY_SIZE(aud_clk_sels), FUNCTION_NAME(PD_AUDIO));
|
||||
clks[IMX8QM_ACM_AUD_CLK1_CLK] = imx_clk_gate_scu("acm_aud_clk1_clk", "acm_aud_clk1_sel", SC_R_AUDIO_CLK_1, SC_PM_CLK_SLV_BUS, NULL, 0, 0);
|
||||
clks[IMX8QM_ACM_MCLKOUT0_SEL] = imx_clk_mux_scu("acm_mclkout0_sel", base_acm + 0x20000, 0, 3, mclk_out_sels, ARRAY_SIZE(mclk_out_sels), FUNCTION_NAME(PD_AUDIO));
|
||||
clks[IMX8QM_ACM_MCLKOUT1_SEL] = imx_clk_mux_scu("acm_mclkout1_sel", base_acm + 0x30000, 0, 3, mclk_out_sels, ARRAY_SIZE(mclk_out_sels), FUNCTION_NAME(PD_AUDIO));
|
||||
clks[IMX8QM_ACM_SAI0_MCLK_SEL] = imx_clk_mux_scu("acm_sai0_mclk_sel", base_acm + 0xE0000, 0, 2, sai_mclk_sels, ARRAY_SIZE(sai_mclk_sels), FUNCTION_NAME(PD_AUD_SAI_0));
|
||||
clks[IMX8QM_ACM_SAI1_MCLK_SEL] = imx_clk_mux_scu("acm_sai1_mclk_sel", base_acm + 0xF0000, 0, 2, sai_mclk_sels, ARRAY_SIZE(sai_mclk_sels), FUNCTION_NAME(PD_AUD_SAI_0));
|
||||
clks[IMX8QM_ACM_SAI2_MCLK_SEL] = imx_clk_mux_scu("acm_sai2_mclk_sel", base_acm + 0x100000, 0, 2, sai_mclk_sels, ARRAY_SIZE(sai_mclk_sels), FUNCTION_NAME(PD_AUD_SAI_1));
|
||||
clks[IMX8QM_ACM_SAI3_MCLK_SEL] = imx_clk_mux_scu("acm_sai3_mclk_sel", base_acm + 0x110000, 0, 2, sai_mclk_sels, ARRAY_SIZE(sai_mclk_sels), FUNCTION_NAME(PD_AUD_SAI_3));
|
||||
clks[IMX8QM_ACM_HDMI_RX_SAI0_MCLK_SEL] = imx_clk_mux_scu("acm_hdmi_rx_sai0_mclk_sel", base_acm + 0x120000, 0, 2, sai_mclk_sels, ARRAY_SIZE(sai_mclk_sels), FUNCTION_NAME(PD_AUD_SAI_4));
|
||||
clks[IMX8QM_ACM_HDMI_TX_SAI0_MCLK_SEL] = imx_clk_mux_scu("acm_hdmi_tx_sai0_mclk_sel", base_acm + 0x130000, 0, 2, sai_mclk_sels, ARRAY_SIZE(sai_mclk_sels), FUNCTION_NAME(PD_AUD_SAI_5));
|
||||
clks[IMX8QM_ACM_SAI6_MCLK_SEL] = imx_clk_mux_scu("acm_sai6_mclk_sel", base_acm + 0x140000, 0, 2, sai_mclk_sels, ARRAY_SIZE(sai_mclk_sels), FUNCTION_NAME(PD_AUD_SAI_6));
|
||||
clks[IMX8QM_ACM_SAI7_MCLK_SEL] = imx_clk_mux_scu("acm_sai7_mclk_sel", base_acm + 0x150000, 0, 2, sai_mclk_sels, ARRAY_SIZE(sai_mclk_sels), FUNCTION_NAME(PD_AUD_SAI_7));
|
||||
clks[IMX8QM_ACM_SPDIF0_TX_CLK_SEL] = imx_clk_mux_scu("acm_spdif0_mclk_sel", base_acm + 0x1A0000, 0, 2, spdif_mclk_sels, ARRAY_SIZE(spdif_mclk_sels), FUNCTION_NAME(PD_AUD_SPDIF_0));
|
||||
clks[IMX8QM_ACM_SPDIF1_TX_CLK_SEL] = imx_clk_mux_scu("acm_spdif1_mclk_sel", base_acm + 0x1B0000, 0, 2, spdif_mclk_sels, ARRAY_SIZE(spdif_mclk_sels), FUNCTION_NAME(PD_AUD_SPDIF_1));
|
||||
clks[IMX8QM_ACM_MQS_TX_CLK_SEL] = imx_clk_mux_scu("acm_mqs_mclk_sel", base_acm + 0x1C0000, 0, 2, mqs_mclk_sels, ARRAY_SIZE(mqs_mclk_sels), FUNCTION_NAME(PD_AUD_MQS_0));
|
||||
clks[IMX8QM_ACM_ASRC0_MUX_CLK_SEL] = imx_clk_mux_scu("acm_asrc0_mclk_sel", base_acm + 0x40000, 0, 2, asrc_mux_clk_sels, ARRAY_SIZE(asrc_mux_clk_sels), FUNCTION_NAME(PD_AUD_ASRC_0));
|
||||
clks[IMX8QM_ACM_ASRC1_MUX_CLK_SEL] = imx_clk_mux_scu("acm_asrc1_mclk_sel", base_acm + 0x50000, 0, 2, asrc_mux_clk_sels, ARRAY_SIZE(asrc_mux_clk_sels), FUNCTION_NAME(PD_AUD_ASRC_1));
|
||||
clks[IMX8QM_ACM_ESAI0_MCLK_SEL] = imx_clk_mux_scu("acm_esai0_mclk_sel", base_acm + 0x60000, 0, 2, esai_mclk_sels, ARRAY_SIZE(esai_mclk_sels), FUNCTION_NAME(PD_AUD_ESAI_0));
|
||||
clks[IMX8QM_ACM_ESAI1_MCLK_SEL] = imx_clk_mux_scu("acm_esai1_mclk_sel", base_acm + 0x70000, 0, 2, esai_mclk_sels, ARRAY_SIZE(esai_mclk_sels), FUNCTION_NAME(PD_AUD_ESAI_1));
|
||||
|
||||
clks[IMX8QM_AUD_AMIX_IPG] = imx_clk_gate2_scu("aud_amix_ipg_clk", "ipg_aud_clk_root", (void __iomem *)(AUD_AMIX_LPCG), 0, FUNCTION_NAME(PD_AUD_AMIX));
|
||||
clks[IMX8QM_AUD_ESAI_0_IPG] = imx_clk_gate2_scu("aud_esai0_ipg_clk", "ipg_aud_clk_root", (void __iomem *)(AUD_ESAI_0_LPCG), 0, FUNCTION_NAME(PD_AUD_ESAI_0));
|
||||
clks[IMX8QM_AUD_ESAI_1_IPG] = imx_clk_gate2_scu("aud_esai1_ipg_clk", "ipg_aud_clk_root", (void __iomem *)(AUD_ESAI_1_LPCG), 0, FUNCTION_NAME(PD_AUD_ESAI_1));
|
||||
clks[IMX8QM_AUD_ESAI_0_EXTAL_IPG] = imx_clk_gate2_scu("aud_esai0_extal_ipg_clk", "ipg_aud_clk_root", (void __iomem *)(AUD_ESAI_0_LPCG), 16, FUNCTION_NAME(PD_AUD_ESAI_0));
|
||||
clks[IMX8QM_AUD_ESAI_1_EXTAL_IPG] = imx_clk_gate2_scu("aud_esai1_extal_ipg_clk", "ipg_aud_clk_root", (void __iomem *)(AUD_ESAI_1_LPCG), 16, FUNCTION_NAME(PD_AUD_ESAI_1));
|
||||
clks[IMX8QM_AUD_SAI_0_IPG_S] = imx_clk_gate2_scu("aud_sai0_ipg_s_clk", "ipg_aud_clk_root", (void __iomem *)(AUD_SAI_0_LPCG), 8, FUNCTION_NAME(PD_AUD_SAI_0));
|
||||
clks[IMX8QM_AUD_SAI_0_IPG] = imx_clk_gate2_scu("aud_sai0_ipg_clk", "aud_sai0_ipg_s_clk", (void __iomem *)(AUD_SAI_0_LPCG), 0, FUNCTION_NAME(PD_AUD_SAI_0));
|
||||
clks[IMX8QM_AUD_SAI_0_MCLK] = imx_clk_gate2_scu("aud_sai0_mclk_clk", "acm_sai0_mclk_sel", (void __iomem *)(AUD_SAI_0_LPCG), 16, FUNCTION_NAME(PD_AUD_SAI_0));
|
||||
clks[IMX8QM_AUD_SAI_1_IPG_S] = imx_clk_gate2_scu("aud_sai1_ipg_s_clk", "ipg_aud_clk_root", (void __iomem *)(AUD_SAI_1_LPCG), 8, FUNCTION_NAME(PD_AUD_SAI_1));
|
||||
clks[IMX8QM_AUD_SAI_1_IPG] = imx_clk_gate2_scu("aud_sai1_ipg_clk", "aud_sai1_ipg_s_clk", (void __iomem *)(AUD_SAI_1_LPCG), 0, FUNCTION_NAME(PD_AUD_SAI_1));
|
||||
clks[IMX8QM_AUD_SAI_1_MCLK] = imx_clk_gate2_scu("aud_sai1_mclk_clk", "ipg_aud_clk_root", (void __iomem *)(AUD_SAI_1_LPCG), 16, FUNCTION_NAME(PD_AUD_SAI_1));
|
||||
clks[IMX8QM_AUD_SAI_2_IPG_S] = imx_clk_gate2_scu("aud_sai2_ipg_s_clk", "ipg_aud_clk_root", (void __iomem *)(AUD_SAI_2_LPCG), 8, FUNCTION_NAME(PD_AUD_SAI_2));
|
||||
clks[IMX8QM_AUD_SAI_2_IPG] = imx_clk_gate2_scu("aud_sai2_ipg_clk", "aud_sai2_ipg_s_clk", (void __iomem *)(AUD_SAI_2_LPCG), 0, FUNCTION_NAME(PD_AUD_SAI_2));
|
||||
clks[IMX8QM_AUD_SAI_2_MCLK] = imx_clk_gate2_scu("aud_sai2_mclk_clk", "ipg_aud_clk_root", (void __iomem *)(AUD_SAI_2_LPCG), 16, FUNCTION_NAME(PD_AUD_SAI_2));
|
||||
clks[IMX8QM_AUD_SAI_3_IPG_S] = imx_clk_gate2_scu("aud_sai3_ipg_s_clk", "ipg_aud_clk_root", (void __iomem *)(AUD_SAI_3_LPCG), 8, FUNCTION_NAME(PD_AUD_SAI_3));
|
||||
clks[IMX8QM_AUD_SAI_3_IPG] = imx_clk_gate2_scu("aud_sai3_ipg_clk", "aud_sai3_ipg_s_clk", (void __iomem *)(AUD_SAI_3_LPCG), 0, FUNCTION_NAME(PD_AUD_SAI_3));
|
||||
clks[IMX8QM_AUD_SAI_3_MCLK] = imx_clk_gate2_scu("aud_sai3_mclk_clk", "ipg_aud_clk_root", (void __iomem *)(AUD_SAI_3_LPCG), 16, FUNCTION_NAME(PD_AUD_SAI_3));
|
||||
clks[IMX8QM_AUD_SAI_6_IPG_S] = imx_clk_gate2_scu("aud_sai6_ipg_s_clk", "ipg_aud_clk_root", (void __iomem *)(AUD_SAI_6_LPCG), 8, FUNCTION_NAME(PD_AUD_SAI_6));
|
||||
clks[IMX8QM_AUD_SAI_6_IPG] = imx_clk_gate2_scu("aud_sai6_ipg_clk", "aud_sai6_ipg_s_clk", (void __iomem *)(AUD_SAI_6_LPCG), 0, FUNCTION_NAME(PD_AUD_SAI_6));
|
||||
clks[IMX8QM_AUD_SAI_6_MCLK] = imx_clk_gate2_scu("aud_sai6_mclk_clk", "ipg_aud_clk_root", (void __iomem *)(AUD_SAI_6_LPCG), 16, FUNCTION_NAME(PD_AUD_SAI_6));
|
||||
clks[IMX8QM_AUD_SAI_7_IPG_S] = imx_clk_gate2_scu("aud_sai7_ipg_s_clk", "ipg_aud_clk_root", (void __iomem *)(AUD_SAI_7_LPCG), 8, FUNCTION_NAME(PD_AUD_SAI_7));
|
||||
clks[IMX8QM_AUD_SAI_7_IPG] = imx_clk_gate2_scu("aud_sai7_ipg_clk", "aud_sai7_ipg_s_clk", (void __iomem *)(AUD_SAI_7_LPCG), 0, FUNCTION_NAME(PD_AUD_SAI_7));
|
||||
clks[IMX8QM_AUD_SAI_7_MCLK] = imx_clk_gate2_scu("aud_sai7_mclk_clk", "ipg_aud_clk_root", (void __iomem *)(AUD_SAI_7_LPCG), 16, FUNCTION_NAME(PD_AUD_SAI_7));
|
||||
clks[IMX8QM_AUD_SAI_HDMIRX0_IPG_S] = imx_clk_gate2_scu("aud_sai_hdmirx0_ipg_s_clk", "ipg_aud_clk_root", (void __iomem *)(AUD_HDMI_RX_SAI_0_LPCG), 8, NULL);
|
||||
clks[IMX8QM_AUD_SAI_HDMIRX0_IPG] = imx_clk_gate2_scu("aud_sai_hdmirx0_ipg_clk", "aud_sai_hdmirx0_ipg_s_clk", (void __iomem *)(AUD_HDMI_RX_SAI_0_LPCG), 0, NULL);
|
||||
clks[IMX8QM_AUD_SAI_HDMIRX0_MCLK] = imx_clk_gate2_scu("aud_sai_hdmirx0_mclk_clk", "ipg_aud_clk_root", (void __iomem *)(AUD_HDMI_RX_SAI_0_LPCG), 16, NULL);
|
||||
clks[IMX8QM_AUD_SAI_HDMITX0_IPG_S] = imx_clk_gate2_scu("aud_sai_hdmitx0_ipg_s_clk", "ipg_aud_clk_root", (void __iomem *)(AUD_HDMI_TX_SAI_0_LPCG), 8, NULL);
|
||||
clks[IMX8QM_AUD_SAI_HDMITX0_IPG] = imx_clk_gate2_scu("aud_sai_hdmitx0_ipg_clk", "aud_sai_hdmitx0_ipg_s_clk", (void __iomem *)(AUD_HDMI_TX_SAI_0_LPCG), 0, NULL);
|
||||
clks[IMX8QM_AUD_SAI_HDMITX0_MCLK] = imx_clk_gate2_scu("aud_sai_hdmitx0_mclk_clk", "ipg_aud_clk_root", (void __iomem *)(AUD_HDMI_TX_SAI_0_LPCG), 16, NULL);
|
||||
clks[IMX8QM_AUD_MQS_IPG] = imx_clk_gate2_scu("aud_mqs_ipg", "ipg_aud_clk_root", (void __iomem *)(AUD_MQS_LPCG), 0, FUNCTION_NAME(PD_AUD_MQS_0));
|
||||
clks[IMX8QM_AUD_MQS_HMCLK] = imx_clk_gate2_scu("aud_mqs_hm_clk", "ipg_aud_clk_root", (void __iomem *)(AUD_MQS_LPCG), 16, FUNCTION_NAME(PD_AUD_MQS_0));
|
||||
clks[IMX8QM_AUD_GPT5_IPG_S] = imx_clk_gate2_scu("aud_gpt5_ipg", "ipg_aud_clk_root", (void __iomem *)(AUD_GPT_5_LPCG), 0, FUNCTION_NAME(PD_AUD_GPT_5));
|
||||
clks[IMX8QM_AUD_GPT5_24M_CLK] = imx_clk_gate2_scu("aud_gpt5_24MHz", "xtal_24MHz", (void __iomem *)(AUD_GPT_5_LPCG), 20, FUNCTION_NAME(PD_AUD_GPT_5));
|
||||
clks[IMX8QM_AUD_GPT6_IPG_S] = imx_clk_gate2_scu("aud_gpt6_ipg", "ipg_aud_clk_root", (void __iomem *)(AUD_GPT_6_LPCG), 0, FUNCTION_NAME(PD_AUD_GPT_6));
|
||||
clks[IMX8QM_AUD_GPT6_24M_CLK] = imx_clk_gate2_scu("aud_gpt6_24MHz", "xtal_24MHz", (void __iomem *)(AUD_GPT_6_LPCG), 20, FUNCTION_NAME(PD_AUD_GPT_6));
|
||||
clks[IMX8QM_AUD_GPT7_IPG_S] = imx_clk_gate2_scu("aud_gpt7_ipg", "ipg_aud_clk_root", (void __iomem *)(AUD_GPT_7_LPCG), 0, FUNCTION_NAME(PD_AUD_GPT_7));
|
||||
clks[IMX8QM_AUD_GPT7_24M_CLK] = imx_clk_gate2_scu("aud_gpt7_24MHz", "xtal_24MHz", (void __iomem *)(AUD_GPT_7_LPCG), 20, FUNCTION_NAME(PD_AUD_GPT_7));
|
||||
clks[IMX8QM_AUD_GPT8_IPG_S] = imx_clk_gate2_scu("aud_gpt8_ipg", "ipg_aud_clk_root", (void __iomem *)(AUD_GPT_8_LPCG), 0, FUNCTION_NAME(PD_AUD_GPT_8));
|
||||
clks[IMX8QM_AUD_GPT8_24M_CLK] = imx_clk_gate2_scu("aud_gpt8_24MHz", "xtal_24MHz", (void __iomem *)(AUD_GPT_8_LPCG), 20, FUNCTION_NAME(PD_AUD_GPT_8));
|
||||
clks[IMX8QM_AUD_GPT9_IPG_S] = imx_clk_gate2_scu("aud_gpt9_ipg", "ipg_aud_clk_root", (void __iomem *)(AUD_GPT_9_LPCG), 0, FUNCTION_NAME(PD_AUD_GPT_9));
|
||||
clks[IMX8QM_AUD_GPT9_24M_CLK] = imx_clk_gate2_scu("aud_gpt9_24MHz", "xtal_24MHz", (void __iomem *)(AUD_GPT_9_LPCG), 20, FUNCTION_NAME(PD_AUD_GPT_9));
|
||||
clks[IMX8QM_AUD_GPT10_IPG_S] = imx_clk_gate2_scu("aud_gpt10_ipg", "ipg_aud_clk_root", (void __iomem *)(AUD_GPT_10_LPCG), 0, FUNCTION_NAME(PD_AUD_GPT_9));
|
||||
clks[IMX8QM_AUD_GPT10_24M_CLK] = imx_clk_gate2_scu("aud_gpt10_24MHz", "xtal_24MHz", (void __iomem *)(AUD_GPT_10_LPCG), 20, FUNCTION_NAME(PD_AUD_GPT_9));
|
||||
clks[IMX8QM_AUD_MCLKOUT0] = imx_clk_gate2_scu("aud_mclkout0", "ipg_aud_clk_root", (void __iomem *)(AUD_MCLKOUT0_LPCG), 0, FUNCTION_NAME(PD_AUDIO));
|
||||
clks[IMX8QM_AUD_MCLKOUT1] = imx_clk_gate2_scu("aud_mclkout1", "ipg_aud_clk_root", (void __iomem *)(AUD_MCLKOUT1_LPCG), 0, FUNCTION_NAME(PD_AUDIO));
|
||||
clks[IMX8QM_AUD_SPDIF_0_IPG_S] = imx_clk_gate2_scu("spdif0_ipg_s", "ipg_aud_clk_root", (void __iomem *)(AUD_SPDIF_0_LPCG), 0, FUNCTION_NAME(PD_AUD_SPDIF_0));
|
||||
clks[IMX8QM_AUD_SPDIF_0_GCLKW] = imx_clk_gate2_scu("spdif0_gclkw", "spdif0_ipg_s", (void __iomem *)(AUD_SPDIF_0_LPCG), 16, FUNCTION_NAME(PD_AUD_SPDIF_0));
|
||||
clks[IMX8QM_AUD_SPDIF_0_TX_CLK] = imx_clk_gate2_scu("spdif0_tx_clk", "ipg_aud_clk_root", (void __iomem *)(AUD_SPDIF_0_LPCG), 20, FUNCTION_NAME(PD_AUD_SPDIF_0));
|
||||
clks[IMX8QM_AUD_SPDIF_1_IPG_S] = imx_clk_gate2_scu("spdif1_ipg_s", "ipg_aud_clk_root", (void __iomem *)(AUD_SPDIF_1_LPCG), 0, FUNCTION_NAME(PD_AUD_SPDIF_1));
|
||||
clks[IMX8QM_AUD_SPDIF_1_GCLKW] = imx_clk_gate2_scu("spdif1_gclkw", "spdif1_ipg_s", (void __iomem *)(AUD_SPDIF_1_LPCG), 16, FUNCTION_NAME(PD_AUD_SPDIF_1));
|
||||
clks[IMX8QM_AUD_SPDIF_1_TX_CLK] = imx_clk_gate2_scu("spdif1_tx_clk", "ipg_aud_clk_root", (void __iomem *)(AUD_SPDIF_1_LPCG), 20, FUNCTION_NAME(PD_AUD_SPDIF_1));
|
||||
clks[IMX8QM_AUD_ASRC_0_IPG] = imx_clk_gate2_scu("aud_asrc0_ipg", "ipg_aud_clk_root", (void __iomem *)(AUD_ASRC_0_LPCG), 0, FUNCTION_NAME(PD_AUD_ASRC_0));
|
||||
clks[IMX8QM_AUD_ASRC_0_MEM] = imx_clk_gate2_scu("aud_asrc0_mem", "ipg_aud_clk_root", (void __iomem *)(AUD_ASRC_0_LPCG), 8, FUNCTION_NAME(PD_AUD_ASRC_0));
|
||||
clks[IMX8QM_AUD_ASRC_1_IPG] = imx_clk_gate2_scu("aud_asrc1_ipg", "ipg_aud_clk_root", (void __iomem *)(AUD_ASRC_1_LPCG), 0, FUNCTION_NAME(PD_AUD_ASRC_1));
|
||||
clks[IMX8QM_AUD_ASRC_1_MEM] = imx_clk_gate2_scu("aud_asrc1_mem", "ipg_aud_clk_root", (void __iomem *)(AUD_ASRC_1_LPCG), 8, FUNCTION_NAME(PD_AUD_ASRC_1));
|
||||
clks[IMX8QM_ACM_ASRC0_MUX_CLK_CLK] = imx_clk_gate_scu("aud_asrc0_mux_clk", "acm_asrc0_mclk_sel", SC_R_ASRC_0, SC_PM_CLK_PER, NULL, 0, 0);
|
||||
clks[IMX8QM_ACM_ASRC1_MUX_CLK_CLK] = imx_clk_gate_scu("aud_asrc1_mux_clk", "acm_asrc1_mclk_sel", SC_R_ASRC_1, SC_PM_CLK_PER, NULL, 0, 0);
|
||||
|
||||
/* MIPI CSI */
|
||||
clks[IMX8QM_CSI0_IPG_CLK_S] = imx_clk_gate2_scu("mipi_csi0_ipg_s", "ipg_mipi_csi_clk_root", (void __iomem *)(MIPI_CSI_0_LPCG + 0x8), 16, FUNCTION_NAME(PD_MIPI_CSI0));
|
||||
clks[IMX8QM_CSI0_IPG_CLK] = imx_clk_gate2_scu("mipi_csi0_ipg", "mipi_csi0_ipg_s", (void __iomem *)(MIPI_CSI_0_LPCG), 16, FUNCTION_NAME(PD_MIPI_CSI0));
|
||||
clks[IMX8QM_CSI0_APB_CLK] = imx_clk_gate2_scu("mipi_csi0_apb_clk", "ipg_mipi_csi_clk_root", (void __iomem *)(MIPI_CSI_0_LPCG + 0x4), 16, FUNCTION_NAME(PD_MIPI_CSI0));
|
||||
clks[IMX8QM_CSI0_I2C0_IPG_CLK] = imx_clk_gate2_scu("mipi_csi0_i2c0_ipg_s", "ipg_mipi_csi_clk_root", (void __iomem *)(MIPI_CSI_0_LPCG + 0x14), 16, FUNCTION_NAME(PD_MIPI_CSI0_I2C));
|
||||
clks[IMX8QM_CSI0_I2C0_CLK] = imx_clk_gate_scu("mipi_csi0_i2c0_clk", "mipi_csi0_i2c0_div", SC_R_CSI_0_I2C_0, SC_PM_CLK_PER, (void __iomem *)(MIPI_CSI_0_LPCG + 0x14), 0, 0);
|
||||
clks[IMX8QM_CSI0_PWM0_IPG_CLK] = imx_clk_gate2_scu("mipi_csi0_pwm0_ipg_s", "ipg_mipi_csi_clk_root", (void __iomem *)(MIPI_CSI_0_LPCG + 0x10), 16, FUNCTION_NAME(PD_MIPI_CSI0_PWM));
|
||||
clks[IMX8QM_CSI0_PWM0_CLK] = imx_clk_gate_scu("mipi_csi0_pwm0_clk", "mipi_csi0_pwm0_div", SC_R_CSI_0_PWM_0, SC_PM_CLK_PER, (void __iomem *)(MIPI_CSI_0_LPCG + 0x10), 0, 0);
|
||||
clks[IMX8QM_CSI0_CORE_CLK] = imx_clk_gate_scu("mipi_csi0_core_clk", "mipi_csi0_core_div", SC_R_CSI_0, SC_PM_CLK_PER, (void __iomem *)(MIPI_CSI_0_LPCG + 0x18), 16, 0);
|
||||
clks[IMX8QM_CSI0_ESC_CLK] = imx_clk_gate_scu("mipi_csi0_esc_clk", "mipi_csi0_esc_div", SC_R_CSI_0, SC_PM_CLK_MISC, (void __iomem *)(MIPI_CSI_0_LPCG + 0x1C), 16, 0);
|
||||
clks[IMX8QM_CSI1_IPG_CLK_S] = imx_clk_gate2_scu("mipi_csi1_ipg_s", "ipg_mipi_csi_clk_root", (void __iomem *)(MIPI_CSI_1_LPCG + 0x8), 16, FUNCTION_NAME(PD_MIPI_CSI1));
|
||||
clks[IMX8QM_CSI1_IPG_CLK] = imx_clk_gate2_scu("mipi_csi1_ipg", "mipi_csi1_ipg_s", (void __iomem *)(MIPI_CSI_1_LPCG), 16, FUNCTION_NAME(PD_MIPI_CSI1));
|
||||
clks[IMX8QM_CSI1_APB_CLK] = imx_clk_gate2_scu("mipi_csi1_apb_clk", "ipg_mipi_csi_clk_root", (void __iomem *)(MIPI_CSI_1_LPCG + 0x4), 16, FUNCTION_NAME(PD_MIPI_CSI1));
|
||||
clks[IMX8QM_CSI1_I2C0_IPG_CLK] = imx_clk_gate2_scu("mipi_csi1_i2c0_ipg_s", "ipg_mipi_csi_clk_root", (void __iomem *)(MIPI_CSI_1_LPCG + 0x14), 16, FUNCTION_NAME(PD_MIPI_CSI0_I2C));
|
||||
clks[IMX8QM_CSI1_I2C0_CLK] = imx_clk_gate_scu("mipi_csi1_i2c0_clk", "mipi_csi1_i2c0_div", SC_R_CSI_1_I2C_0, SC_PM_CLK_PER, (void __iomem *)(MIPI_CSI_1_LPCG + 0x14), 0, 0);
|
||||
clks[IMX8QM_CSI1_PWM0_IPG_CLK] = imx_clk_gate2_scu("mipi_csi1_pwm0_ipg_s", "ipg_mipi_csi_clk_root", (void __iomem *)(MIPI_CSI_1_LPCG + 0x10), 16, FUNCTION_NAME(PD_MIPI_CSI0_PWM));
|
||||
clks[IMX8QM_CSI1_PWM0_CLK] = imx_clk_gate_scu("mipi_csi1_pwm0_clk", "mipi_csi1_pwm0_div", SC_R_CSI_1_PWM_0, SC_PM_CLK_PER, (void __iomem *)(MIPI_CSI_1_LPCG + 0x10), 0, 0);
|
||||
clks[IMX8QM_CSI1_CORE_CLK] = imx_clk_gate_scu("mipi_csi1_core_clk", "mipi_csi1_core_div", SC_R_CSI_1, SC_PM_CLK_PER, (void __iomem *)(MIPI_CSI_1_LPCG + 0x18), 16, 0);
|
||||
clks[IMX8QM_CSI1_ESC_CLK] = imx_clk_gate_scu("mipi_csi1_esc_clk", "mipi_csi1_esc_div", SC_R_CSI_1, SC_PM_CLK_MISC, (void __iomem *)(MIPI_CSI_1_LPCG + 0x1C), 16, 0);
|
||||
|
||||
/* RX-HDMI */
|
||||
clks[IMX8QM_HDMI_RX_GPIO_IPG_S_CLK] = imx_clk_gate2_scu("hdmi_rx_gpio_ipg_s_clk", "ipg_hdmi_rx_clk_root", (void __iomem *)(RX_HDMI_LPCG), 0, FUNCTION_NAME(PD_HDMI_RX));
|
||||
clks[IMX8QM_HDMI_RX_PWM_IPG_S_CLK] = imx_clk_gate2_scu("hdmi_rx_pwm_ipg_s_clk", "ipg_hdmi_rx_clk_root", (void __iomem *)(RX_HDMI_LPCG + 0x8), 0, FUNCTION_NAME(PD_HDMI_RX));
|
||||
clks[IMX8QM_HDMI_RX_PWM_IPG_CLK] = imx_clk_gate2_scu("hdmi_rx_pwm_ipg_clk", "hdmi_rx_pwm_ipg_s_clk", (void __iomem *)(RX_HDMI_LPCG + 0x4), 0, FUNCTION_NAME(PD_HDMI_RX));
|
||||
clks[IMX8QM_HDMI_RX_I2C_IPG_S_CLK] = imx_clk_gate2_scu("hdmi_rx_i2c_ipg_s_clk", "ipg_hdmi_rx_clk_root", (void __iomem *)(RX_HDMI_LPCG + 0x1C), 0, FUNCTION_NAME(PD_HDMI_RX_I2C));
|
||||
clks[IMX8QM_HDMI_RX_I2C_IPG_CLK] = imx_clk_gate2_scu("hdmi_rx_i2c_ipg_clk", "hdmi_rx_i2c_ipg_s_clk", (void __iomem *)(RX_HDMI_LPCG + 0x18), 0, FUNCTION_NAME(PD_HDMI_RX_I2C));
|
||||
clks[IMX8QM_HDMI_RX_I2C_DIV_CLK] = imx_clk_gate2_scu("hdmi_rx_i2c0_div_clk", "hdmi_rx_i2c0_div", (void __iomem *)(RX_HDMI_LPCG + 0x14), 0, FUNCTION_NAME(PD_HDMI_RX_I2C));
|
||||
clks[IMX8QM_HDMI_RX_I2C0_CLK] = imx_clk_gate_scu("hdmi_rx_i2c0_clk", "hdmi_rx_i2c0_div_clk", SC_R_HDMI_RX_I2C_0, SC_PM_CLK_MISC2, (void __iomem *)(RX_HDMI_LPCG + 0x10), 0, 0);
|
||||
clks[IMX8QM_HDMI_RX_SPDIF_CLK] = imx_clk_gate_scu("hdmi_rx_spdif_clk", "hdmi_rx_spdif_div", SC_R_HDMI_RX, SC_PM_CLK_MISC0, NULL, 0, 0);
|
||||
clks[IMX8QM_HDMI_RX_HD_REF_CLK] = imx_clk_gate_scu("hdmi_rx_hd_ref_clk", "hdmi_rx_hd_ref_div", SC_R_HDMI_RX, SC_PM_CLK_MISC1, NULL, 0, 0);
|
||||
clks[IMX8QM_HDMI_RX_HD_CORE_CLK] = imx_clk_gate_scu("hdmi_rx_hd_core_clk", "hdmi_rx_hd_core_div", SC_R_HDMI_RX, SC_PM_CLK_MISC2, (void __iomem *)(RX_HDMI_LPCG + 0x28), 0, 0);
|
||||
clks[IMX8QM_HDMI_RX_PXL_CLK] = imx_clk_gate_scu("hdmi_rx_pxl_clk", "hdmi_rx_pxl_div", SC_R_HDMI_RX, SC_PM_CLK_MISC3, (void __iomem *)(RX_HDMI_LPCG + 0x2C), 0, 0);
|
||||
clks[IMX8QM_HDMI_RX_I2S_CLK] = imx_clk_gate_scu("hdmi_rx_i2s_clk", "hdmi_rx_i2s_div", SC_R_HDMI_RX, SC_PM_CLK_MISC4, NULL, 0, 0);
|
||||
clks[IMX8QM_HDMI_RX_PWM_CLK] = imx_clk_gate_scu("hdmi_rx_pwm_clk", "hdmi_rx_pwm_div", SC_R_HDMI_RX_PWM_0, SC_PM_CLK_MISC2, (void __iomem *)(RX_HDMI_LPCG + 0xC), 0, 0);
|
||||
clks[IMX8QM_HDMI_RX_SINK_PCLK] = imx_clk_gate2_scu("hdmi_rx_sink_pclk", "ipg_hdmi_rx_clk_root", (void __iomem *)(RX_HDMI_LPCG + 0x20), 0, FUNCTION_NAME(PD_HDMI_RX));
|
||||
clks[IMX8QM_HDMI_RX_SINK_SCLK] = imx_clk_gate2_scu("hdmi_rx_sink_sclk", "ipg_hdmi_rx_clk_root", (void __iomem *)(RX_HDMI_LPCG + 0x24), 0, FUNCTION_NAME(PD_HDMI_RX));
|
||||
clks[IMX8QM_HDMI_RX_PXL_ENC_CLK] = imx_clk_gate2_scu("hdmi_rx_sink_enc_clk", "hdmi_rx_pxl_clk", (void __iomem *)(RX_HDMI_LPCG + 0x30), 0, FUNCTION_NAME(PD_HDMI_RX));
|
||||
|
||||
/* MIPI-DI */
|
||||
clks[IMX8QM_MIPI0_I2C0_CLK] = imx_clk_gate_scu("mipi0_i2c0_clk", "mipi0_i2c0_div", SC_R_MIPI_0_I2C_0, SC_PM_CLK_PER, NULL, 0, 0);
|
||||
clks[IMX8QM_MIPI0_I2C1_CLK] = imx_clk_gate_scu("mipi0_i2c1_clk", "mipi0_i2c1_div", SC_R_MIPI_0_I2C_1, SC_PM_CLK_PER, NULL, 0, 0);
|
||||
clks[IMX8QM_MIPI0_PWM0_CLK] = imx_clk_gate_scu("mipi0_pwm0_clk", "mipi0_pwm0_div", SC_R_MIPI_0_PWM_0, SC_PM_CLK_PER, NULL, 0, 0);
|
||||
clks[IMX8QM_MIPI0_DSI_TX_ESC_CLK] = imx_clk_gate_scu("mipi0_dsi_tx_esc_clk", "mipi0_dsi_tx_esc_div", SC_R_MIPI_0, SC_PM_CLK_MST_BUS, NULL, 0, 0);
|
||||
clks[IMX8QM_MIPI0_DSI_RX_ESC_CLK] = imx_clk_gate_scu("mipi0_dsi_rx_esc_clk", "mipi0_dsi_rx_esc_div", SC_R_MIPI_0, SC_PM_CLK_SLV_BUS, NULL, 0, 0);
|
||||
clks[IMX8QM_MIPI0_PXL_CLK] = imx_clk_gate_scu("mipi0_pxl_clk", "mipi0_pxl_div", SC_R_MIPI_0, SC_PM_CLK_PER, NULL, 0, 0);
|
||||
clks[IMX8QM_MIPI1_I2C0_CLK] = imx_clk_gate_scu("mipi1_i2c0_clk", "mipi1_i2c0_div", SC_R_MIPI_1_I2C_0, SC_PM_CLK_PER, NULL, 0, 0);
|
||||
clks[IMX8QM_MIPI1_I2C1_CLK] = imx_clk_gate_scu("mipi1_i2c1_clk", "mipi1_i2c1_div", SC_R_MIPI_1_I2C_1, SC_PM_CLK_PER, NULL, 0, 0);
|
||||
clks[IMX8QM_MIPI1_PWM0_CLK] = imx_clk_gate_scu("mipi1_pwm0_clk", "mipi1_pwm0_div", SC_R_MIPI_1_PWM_0, SC_PM_CLK_PER, NULL, 0, 0);
|
||||
clks[IMX8QM_MIPI1_DSI_TX_ESC_CLK] = imx_clk_gate_scu("mipi1_dsi_tx_esc_clk", "mipi1_dsi_tx_esc_div", SC_R_MIPI_1, SC_PM_CLK_MST_BUS, NULL, 0, 0);
|
||||
clks[IMX8QM_MIPI1_DSI_RX_ESC_CLK] = imx_clk_gate_scu("mipi1_dsi_rx_esc_clk", "mipi1_dsi_rx_esc_div", SC_R_MIPI_1, SC_PM_CLK_SLV_BUS, NULL, 0, 0);
|
||||
clks[IMX8QM_MIPI1_PXL_CLK] = imx_clk_gate_scu("mipi1_pxl_clk", "mipi1_pxl_div", SC_R_MIPI_1, SC_PM_CLK_PER, NULL, 0, 0);
|
||||
|
||||
/* Display controller */
|
||||
/* DC0 */
|
||||
clks[IMX8QM_DC0_DISP0_CLK] = imx_clk_gate_scu("dc0_disp0_clk", "dc0_disp0_div", SC_R_DC_0, SC_PM_CLK_MISC0, (void __iomem *)(DC_0_LPCG), 0, 0);
|
||||
clks[IMX8QM_DC0_DISP1_CLK] = imx_clk_gate_scu("dc0_disp1_clk", "dc0_disp1_div", SC_R_DC_0, SC_PM_CLK_MISC1, (void __iomem *)(DC_0_LPCG), 4, 0);
|
||||
clks[IMX8QM_DC0_PRG0_RTRAM_CLK] = imx_clk_gate2_scu("dc0_prg0_rtram_clk", "axi_int_dc_clk_root", (void __iomem *)(DC_0_LPCG + 0x20), 0, FUNCTION_NAME(PD_DC_0));
|
||||
clks[IMX8QM_DC0_PRG0_APB_CLK] = imx_clk_gate2_scu("dc0_prg0_apb_clk", "cfg_dc_clk_root", (void __iomem *)(DC_0_LPCG + 0x20), 16, FUNCTION_NAME(PD_DC_0));
|
||||
clks[IMX8QM_DC0_PRG1_RTRAM_CLK] = imx_clk_gate2_scu("dc0_prg1_rtram_clk", "axi_int_dc_clk_root", (void __iomem *)(DC_0_LPCG + 0x24), 0, FUNCTION_NAME(PD_DC_0));
|
||||
clks[IMX8QM_DC0_PRG1_APB_CLK] = imx_clk_gate2_scu("dc0_prg1_apb_clk", "cfg_dc_clk_root", (void __iomem *)(DC_0_LPCG + 0x24), 16, FUNCTION_NAME(PD_DC_0));
|
||||
clks[IMX8QM_DC0_PRG2_RTRAM_CLK] = imx_clk_gate2_scu("dc0_prg2_rtram_clk", "axi_int_dc_clk_root", (void __iomem *)(DC_0_LPCG + 0x28), 0, FUNCTION_NAME(PD_DC_0));
|
||||
clks[IMX8QM_DC0_PRG2_APB_CLK] = imx_clk_gate2_scu("dc0_prg2_apb_clk", "cfg_dc_clk_root", (void __iomem *)(DC_0_LPCG + 0x28), 16, FUNCTION_NAME(PD_DC_0));
|
||||
clks[IMX8QM_DC0_PRG3_RTRAM_CLK] = imx_clk_gate2_scu("dc0_prg3_rtram_clk", "axi_int_dc_clk_root", (void __iomem *)(DC_0_LPCG + 0x34), 0, FUNCTION_NAME(PD_DC_0));
|
||||
clks[IMX8QM_DC0_PRG3_APB_CLK] = imx_clk_gate2_scu("dc0_prg3_apb_clk", "cfg_dc_clk_root", (void __iomem *)(DC_0_LPCG + 0x34), 16, FUNCTION_NAME(PD_DC_0));
|
||||
clks[IMX8QM_DC0_PRG4_RTRAM_CLK] = imx_clk_gate2_scu("dc0_prg4_rtram_clk", "axi_int_dc_clk_root", (void __iomem *)(DC_0_LPCG + 0x38), 0, FUNCTION_NAME(PD_DC_0));
|
||||
clks[IMX8QM_DC0_PRG4_APB_CLK] = imx_clk_gate2_scu("dc0_prg4_apb_clk", "cfg_dc_clk_root", (void __iomem *)(DC_0_LPCG + 0x38), 16, FUNCTION_NAME(PD_DC_0));
|
||||
clks[IMX8QM_DC0_PRG5_RTRAM_CLK] = imx_clk_gate2_scu("dc0_prg5_rtram_clk", "axi_int_dc_clk_root", (void __iomem *)(DC_0_LPCG + 0x3c), 0, FUNCTION_NAME(PD_DC_0));
|
||||
clks[IMX8QM_DC0_PRG5_APB_CLK] = imx_clk_gate2_scu("dc0_prg5_apb_clk", "cfg_dc_clk_root", (void __iomem *)(DC_0_LPCG + 0x3c), 16, FUNCTION_NAME(PD_DC_0));
|
||||
clks[IMX8QM_DC0_PRG6_RTRAM_CLK] = imx_clk_gate2_scu("dc0_prg6_rtram_clk", "axi_int_dc_clk_root", (void __iomem *)(DC_0_LPCG + 0x40), 0, FUNCTION_NAME(PD_DC_0));
|
||||
clks[IMX8QM_DC0_PRG6_APB_CLK] = imx_clk_gate2_scu("dc0_prg6_apb_clk", "cfg_dc_clk_root", (void __iomem *)(DC_0_LPCG + 0x40), 16, FUNCTION_NAME(PD_DC_0));
|
||||
clks[IMX8QM_DC0_PRG7_RTRAM_CLK] = imx_clk_gate2_scu("dc0_prg7_rtram_clk", "axi_int_dc_clk_root", (void __iomem *)(DC_0_LPCG + 0x44), 0, FUNCTION_NAME(PD_DC_0));
|
||||
clks[IMX8QM_DC0_PRG7_APB_CLK] = imx_clk_gate2_scu("dc0_prg7_apb_clk", "cfg_dc_clk_root", (void __iomem *)(DC_0_LPCG + 0x44), 16, FUNCTION_NAME(PD_DC_0));
|
||||
clks[IMX8QM_DC0_PRG8_RTRAM_CLK] = imx_clk_gate2_scu("dc0_prg8_rtram_clk", "axi_int_dc_clk_root", (void __iomem *)(DC_0_LPCG + 0x48), 0, FUNCTION_NAME(PD_DC_0));
|
||||
clks[IMX8QM_DC0_PRG8_APB_CLK] = imx_clk_gate2_scu("dc0_prg8_apb_clk", "cfg_dc_clk_root", (void __iomem *)(DC_0_LPCG + 0x48), 16, FUNCTION_NAME(PD_DC_0));
|
||||
clks[IMX8QM_DC0_DPR0_APB_CLK] = imx_clk_gate2_scu("dc0_dpr0_apb_clk", "cfg_dc_clk_root", (void __iomem *)(DC_0_LPCG + 0x18), 16, FUNCTION_NAME(PD_DC_0));
|
||||
clks[IMX8QM_DC0_DPR0_B_CLK] = imx_clk_gate2_scu("dc0_dpr0_b_clk", "axi_ext_dc_clk_root", (void __iomem *)(DC_0_LPCG + 0x18), 20, FUNCTION_NAME(PD_DC_0));
|
||||
clks[IMX8QM_DC0_RTRAM0_CLK] = imx_clk_gate2_scu("dc0_rtrm0_clk", "axi_int_dc_clk_root", (void __iomem *)(DC_0_LPCG + 0x1C), 0, FUNCTION_NAME(PD_DC_0));
|
||||
clks[IMX8QM_DC0_RTRAM1_CLK] = imx_clk_gate2_scu("dc0_rtrm1_clk", "axi_int_dc_clk_root", (void __iomem *)(DC_0_LPCG + 0x30), 0, FUNCTION_NAME(PD_DC_0));
|
||||
/* DC1 */
|
||||
clks[IMX8QM_DC1_DISP0_CLK] = imx_clk_gate_scu("dc1_disp0_clk", "dc1_disp0_div", SC_R_DC_1, SC_PM_CLK_MISC0, (void __iomem *)(DC_1_LPCG), 0, 0);
|
||||
clks[IMX8QM_DC1_DISP1_CLK] = imx_clk_gate_scu("dc1_disp1_clk", "dc1_disp1_div", SC_R_DC_1, SC_PM_CLK_MISC1, (void __iomem *)(DC_1_LPCG), 4, 0);
|
||||
clks[IMX8QM_DC1_PRG0_RTRAM_CLK] = imx_clk_gate2_scu("dc1_prg0_rtram_clk", "axi_int_dc_clk_root", (void __iomem *)(DC_1_LPCG + 0x20), 0, FUNCTION_NAME(PD_DC_1));
|
||||
clks[IMX8QM_DC1_PRG0_APB_CLK] = imx_clk_gate2_scu("dc1_prg0_apb_clk", "cfg_dc_clk_root", (void __iomem *)(DC_1_LPCG + 0x20), 16, FUNCTION_NAME(PD_DC_1));
|
||||
clks[IMX8QM_DC1_PRG1_RTRAM_CLK] = imx_clk_gate2_scu("dc1_prg1_rtram_clk", "axi_int_dc_clk_root", (void __iomem *)(DC_1_LPCG + 0x24), 0, FUNCTION_NAME(PD_DC_1));
|
||||
clks[IMX8QM_DC1_PRG1_APB_CLK] = imx_clk_gate2_scu("dc1_prg1_apb_clk", "cfg_dc_clk_root", (void __iomem *)(DC_1_LPCG + 0x24), 16, FUNCTION_NAME(PD_DC_1));
|
||||
clks[IMX8QM_DC1_PRG2_RTRAM_CLK] = imx_clk_gate2_scu("dc1_prg2_rtram_clk", "axi_int_dc_clk_root", (void __iomem *)(DC_1_LPCG + 0x28), 0, FUNCTION_NAME(PD_DC_1));
|
||||
clks[IMX8QM_DC1_PRG2_APB_CLK] = imx_clk_gate2_scu("dc1_prg2_apb_clk", "cfg_dc_clk_root", (void __iomem *)(DC_1_LPCG + 0x28), 16, FUNCTION_NAME(PD_DC_1));
|
||||
clks[IMX8QM_DC1_PRG3_RTRAM_CLK] = imx_clk_gate2_scu("dc1_prg3_rtram_clk", "axi_int_dc_clk_root", (void __iomem *)(DC_1_LPCG + 0x34), 0, FUNCTION_NAME(PD_DC_1));
|
||||
clks[IMX8QM_DC1_PRG3_APB_CLK] = imx_clk_gate2_scu("dc1_prg3_apb_clk", "cfg_dc_clk_root", (void __iomem *)(DC_1_LPCG + 0x34), 16, FUNCTION_NAME(PD_DC_1));
|
||||
clks[IMX8QM_DC1_PRG4_RTRAM_CLK] = imx_clk_gate2_scu("dc1_prg4_rtram_clk", "axi_int_dc_clk_root", (void __iomem *)(DC_1_LPCG + 0x38), 0, FUNCTION_NAME(PD_DC_1));
|
||||
clks[IMX8QM_DC1_PRG4_APB_CLK] = imx_clk_gate2_scu("dc1_prg4_apb_clk", "cfg_dc_clk_root", (void __iomem *)(DC_1_LPCG + 0x38), 16, FUNCTION_NAME(PD_DC_1));
|
||||
clks[IMX8QM_DC1_PRG5_RTRAM_CLK] = imx_clk_gate2_scu("dc1_prg5_rtram_clk", "axi_int_dc_clk_root", (void __iomem *)(DC_1_LPCG + 0x3c), 0, FUNCTION_NAME(PD_DC_1));
|
||||
clks[IMX8QM_DC1_PRG5_APB_CLK] = imx_clk_gate2_scu("dc1_prg5_apb_clk", "cfg_dc_clk_root", (void __iomem *)(DC_1_LPCG + 0x3c), 16, FUNCTION_NAME(PD_DC_1));
|
||||
clks[IMX8QM_DC1_PRG6_RTRAM_CLK] = imx_clk_gate2_scu("dc1_prg6_rtram_clk", "axi_int_dc_clk_root", (void __iomem *)(DC_1_LPCG + 0x40), 0, FUNCTION_NAME(PD_DC_1));
|
||||
clks[IMX8QM_DC1_PRG6_APB_CLK] = imx_clk_gate2_scu("dc1_prg6_apb_clk", "cfg_dc_clk_root", (void __iomem *)(DC_1_LPCG + 0x40), 16, FUNCTION_NAME(PD_DC_1));
|
||||
clks[IMX8QM_DC1_PRG7_RTRAM_CLK] = imx_clk_gate2_scu("dc1_prg7_rtram_clk", "axi_int_dc_clk_root", (void __iomem *)(DC_1_LPCG + 0x44), 0, FUNCTION_NAME(PD_DC_1));
|
||||
clks[IMX8QM_DC1_PRG7_APB_CLK] = imx_clk_gate2_scu("dc1_prg7_apb_clk", "cfg_dc_clk_root", (void __iomem *)(DC_1_LPCG + 0x44), 16, FUNCTION_NAME(PD_DC_1));
|
||||
clks[IMX8QM_DC1_PRG8_RTRAM_CLK] = imx_clk_gate2_scu("dc1_prg8_rtram_clk", "axi_int_dc_clk_root", (void __iomem *)(DC_1_LPCG + 0x48), 0, FUNCTION_NAME(PD_DC_1));
|
||||
clks[IMX8QM_DC1_PRG8_APB_CLK] = imx_clk_gate2_scu("dc1_prg8_apb_clk", "cfg_dc_clk_root", (void __iomem *)(DC_1_LPCG + 0x48), 16, FUNCTION_NAME(PD_DC_1));
|
||||
clks[IMX8QM_DC1_DPR0_APB_CLK] = imx_clk_gate2_scu("dc1_dpr0_apb_clk", "cfg_dc_clk_root", (void __iomem *)(DC_1_LPCG + 0x18), 16, FUNCTION_NAME(PD_DC_1));
|
||||
clks[IMX8QM_DC1_DPR0_B_CLK] = imx_clk_gate2_scu("dc1_dpr0_b_clk", "axi_ext_dc_clk_root", (void __iomem *)(DC_1_LPCG + 0x18), 20, FUNCTION_NAME(PD_DC_1));
|
||||
clks[IMX8QM_DC1_RTRAM0_CLK] = imx_clk_gate2_scu("dc1_rtrm0_clk", "axi_int_dc_clk_root", (void __iomem *)(DC_1_LPCG + 0x1C), 0, FUNCTION_NAME(PD_DC_1));
|
||||
clks[IMX8QM_DC1_RTRAM1_CLK] = imx_clk_gate2_scu("dc1_rtrm1_clk", "axi_int_dc_clk_root", (void __iomem *)(DC_1_LPCG + 0x30), 0, FUNCTION_NAME(PD_DC_1));
|
||||
|
||||
/* HDMI SS */
|
||||
clks[IMX8QM_HDMI_I2C0_CLK] = imx_clk_gate_scu("hdmi_i2c0_clk", "hdmi_i2c0_div", SC_R_HDMI_I2C_0, SC_PM_CLK_MISC2, (void __iomem *)(DI_HDMI_LPCG + 0x14), 0, 0);
|
||||
clks[IMX8QM_HDMI_PXL_CLK] = imx_clk_gate_scu("hdmi_pxl_clk", "hdmi_pxl_div", SC_R_HDMI, SC_PM_CLK_MISC3, (void __iomem *)(DI_HDMI_LPCG + 0x14), 0, 0);
|
||||
clks[IMX8QM_HDMI_PXL_LINK_CLK] = imx_clk_gate_scu("hdmi_pxl_link_clk", "hdmi_pxl_link_div", SC_R_HDMI, SC_PM_CLK_MISC1, NULL, 0, 0);
|
||||
clks[IMX8QM_HDMI_PXL_MUX_CLK] = imx_clk_gate_scu("hdmi_pxl_mux_clk", "hdmi_pxl_mux_div", SC_R_HDMI, SC_PM_CLK_MISC0, NULL, 0, 0);
|
||||
clks[IMX8QM_HDMI_I2S_CLK] = imx_clk_gate_scu("hdmi_i2s_clk", "hdmi_i2s_div", SC_R_HDMI, SC_PM_CLK_MISC4, (void __iomem *)(DI_HDMI_LPCG + 0x58), 0, 0);
|
||||
clks[IMX8QM_HDMI_HDP_CORE_CLK] = imx_clk_gate_scu("hdmi_hdp_core_clk", "hdmi_core_div", SC_R_HDMI, SC_PM_CLK_MISC2, (void __iomem *)(DI_HDMI_LPCG + 0x44), 0, 0);
|
||||
clks[IMX8QM_HDMI_I2C_IPG_S_CLK] = imx_clk_gate2_scu("hdmi_i2c_ipg_s", "ipg_hdmi_clk_root", (void __iomem *)(DI_HDMI_LPCG + 0x4), 0, FUNCTION_NAME(PD_HDMI_I2C_0));
|
||||
clks[IMX8QM_HDMI_I2C_IPG_CLK] = imx_clk_gate2_scu("hdmi_i2c_ipg_clk", "hdmi_i2c_ipg_s", (void __iomem *)(DI_HDMI_LPCG), 0, FUNCTION_NAME(PD_HDMI_I2C_0));
|
||||
clks[IMX8QM_HDMI_PWM_IPG_S_CLK] = imx_clk_gate2_scu("hdmi_pwm_ipg_s", "ipg_hdmi_clk_root", (void __iomem *)(DI_HDMI_LPCG + 0xC), 0, FUNCTION_NAME(PD_HDMI_PWM_0));
|
||||
clks[IMX8QM_HDMI_PWM_IPG_CLK] = imx_clk_gate2_scu("hdmi_pwm_ipg_clk", "hdmi_pwm_ipg_s", (void __iomem *)(DI_HDMI_LPCG + 0x8), 0, FUNCTION_NAME(PD_HDMI_PWM_0));
|
||||
clks[IMX8QM_HDMI_PWM_32K_CLK] = imx_clk_gate2_scu("hdmi_pwm_32K_clk", "xtal_32KHz", (void __iomem *)(DI_HDMI_LPCG + 0x20), 0, FUNCTION_NAME(PD_HDMI_PWM_0));
|
||||
clks[IMX8QM_HDMI_GPIO_IPG_CLK] = imx_clk_gate2_scu("hdmi_gpio_ipg_clk", "ipg_hdmi_clk_root", (void __iomem *)(DI_HDMI_LPCG + 0x10), 0, FUNCTION_NAME(PD_HDMI_GPIO_0));
|
||||
clks[IMX8QM_HDMI_PXL_LINK_SLV_ODD_CLK] = imx_clk_gate2_scu("hdmi_pxl_lnk_slv_odd_clk", "hdmi_pxl_link_clk", (void __iomem *)(DI_HDMI_LPCG + 0x28), 0, FUNCTION_NAME(PD_HDMI));
|
||||
clks[IMX8QM_HDMI_PXL_LINK_SLV_EVEN_CLK] = imx_clk_gate2_scu("hdmi_pxl_lnk_slv_even_clk", "hdmi_pxl_link_clk", (void __iomem *)(DI_HDMI_LPCG + 0x2C), 0, FUNCTION_NAME(PD_HDMI));
|
||||
clks[IMX8QM_HDMI_LIS_IPG_CLK] = imx_clk_gate2_scu("hdmi_lis_ipg_clk", "ipg_hdmi_clk_root", (void __iomem *)(DI_HDMI_LPCG + 0x24), 0, FUNCTION_NAME(PD_HDMI));
|
||||
clks[IMX8QM_HDMI_MSI_HCLK] = imx_clk_gate2_scu("hdmi_msi_hclk_clk", "ipg_hdmi_clk_root", (void __iomem *)(DI_HDMI_LPCG + 0x40), 0, FUNCTION_NAME(PD_HDMI));
|
||||
clks[IMX8QM_HDMI_PXL_EVEN_CLK] = imx_clk_gate2_scu("hdmi_pxl_even_clk", "hdmi_pxl_link_clk", (void __iomem *)(DI_HDMI_LPCG + 0x30), 0, FUNCTION_NAME(PD_HDMI));
|
||||
clks[IMX8QM_HDMI_PXL_ODD_CLK] = imx_clk_gate2_scu("hdmi_pxl_odd_clk", "hdmi_pxl_link_clk", (void __iomem *)(DI_HDMI_LPCG + 0x34), 0, FUNCTION_NAME(PD_HDMI));
|
||||
clks[IMX8QM_HDMI_PXL_DBL_CLK] = imx_clk_gate2_scu("hdmi_pxl_dbl_clk", "hdmi_pxl_link_clk", (void __iomem *)(DI_HDMI_LPCG + 0x38), 0, FUNCTION_NAME(PD_HDMI));
|
||||
clks[IMX8QM_HDMI_APB_CLK] = imx_clk_gate2_scu("hdmi_apb_clk", "ipg_hdmi_clk_root", (void __iomem *)(DI_HDMI_LPCG + 0x3C), 0, FUNCTION_NAME(PD_HDMI));
|
||||
clks[IMX8QM_HDMI_PCLK] = imx_clk_gate2_scu("hdmi_pclk", "ipg_hdmi_clk_root", (void __iomem *)(DI_HDMI_LPCG + 0x48), 0, FUNCTION_NAME(PD_HDMI));
|
||||
clks[IMX8QM_HDMI_SCLK] = imx_clk_gate2_scu("hdmi_sclk", "ipg_hdmi_clk_root", (void __iomem *)(DI_HDMI_LPCG + 0x4C), 0, FUNCTION_NAME(PD_HDMI));
|
||||
clks[IMX8QM_HDMI_CCLK] = imx_clk_gate2_scu("hdmi_cclk", "ipg_hdmi_clk_root", (void __iomem *)(DI_HDMI_LPCG + 0x74), 0, FUNCTION_NAME(PD_HDMI));
|
||||
clks[IMX8QM_HDMI_VIF_CLK] = imx_clk_gate2_scu("hdmi_vif_clk", "hdmi_pxl_mux_clk", (void __iomem *)(DI_HDMI_LPCG + 0x54), 0, FUNCTION_NAME(PD_HDMI));
|
||||
clks[IMX8QM_HDMI_SPDIF_IN_MCLK] = imx_clk_gate2_scu("hdmi_spdif_in_clk", "ipg_hdmi_clk_root", (void __iomem *)(DI_HDMI_LPCG + 0x70), 0, FUNCTION_NAME(PD_HDMI));
|
||||
clks[IMX8QM_HDMI_REF_IN_CLK] = imx_clk_gate2_scu("hdmi_ref_in_clk", "ipg_hdmi_clk_root", (void __iomem *)(DI_HDMI_LPCG + 0x78), 0, FUNCTION_NAME(PD_HDMI));
|
||||
clks[IMX8QM_HDMI_APB_MUX_CSR_CLK] = imx_clk_gate2_scu("hdmi_apb_mux_csr_clk", "ipg_hdmi_clk_root", (void __iomem *)(DI_HDMI_LPCG + 0x7C), 0, FUNCTION_NAME(PD_HDMI));
|
||||
clks[IMX8QM_HDMI_APB_MUX_CTRL_CLK] = imx_clk_gate2_scu("hdmi_apb_mux_ctrl_clk", "ipg_hdmi_clk_root", (void __iomem *)(DI_HDMI_LPCG + 0x80), 0, FUNCTION_NAME(PD_HDMI));
|
||||
|
||||
/* lvds subsystem */
|
||||
clks[IMX8QM_LVDS0_PIXEL_CLK] = imx_clk_gate_scu("lvds0_pixel_clk", "lvds0_pixel_div", SC_R_LVDS_0, SC_PM_CLK_PER, NULL, 0, 0);
|
||||
clks[IMX8QM_LVDS0_I2C0_CLK] = imx_clk_gate_scu("lvds0_i2c0_clk", "lvds0_i2c0_div", SC_R_LVDS_0_I2C_0, SC_PM_CLK_PER, (void __iomem *)(DI_LVDS_0_LPCG + 0x10), 0, 0);
|
||||
clks[IMX8QM_LVDS0_I2C1_CLK] = imx_clk_gate_scu("lvds0_i2c1_clk", "lvds0_i2c1_div", SC_R_LVDS_0_I2C_1, SC_PM_CLK_PER, (void __iomem *)(DI_LVDS_0_LPCG + 0x14), 0, 0);
|
||||
clks[IMX8QM_LVDS0_PWM0_CLK] = imx_clk_gate_scu("lvds0_pwm0_clk", "lvds0_pwm0_div", SC_R_LVDS_0_PWM_0, SC_PM_CLK_PER, (void __iomem *)(DI_LVDS_0_LPCG + 0x0C), 0, 0);
|
||||
clks[IMX8QM_LVDS0_PHY_CLK] = imx_clk_gate_scu("lvds0_phy_clk", "lvds0_phy_div", SC_R_LVDS_0, SC_PM_CLK_PHY, NULL, 0, 0);
|
||||
clks[IMX8QM_LVDS0_I2C0_IPG_CLK] = imx_clk_gate2_scu("lvds0_i2c0_ipg_clk", "ipg_lvds_clk_root", (void __iomem *)(DI_LVDS_0_LPCG + 0x10), 16, FUNCTION_NAME(PD_LVDS0_I2C0));
|
||||
clks[IMX8QM_LVDS0_I2C1_IPG_CLK] = imx_clk_gate2_scu("lvds0_i2c1_ipg_clk", "ipg_lvds_clk_root", (void __iomem *)(DI_LVDS_0_LPCG + 0x14), 16, FUNCTION_NAME(PD_LVDS0_I2C1));
|
||||
clks[IMX8QM_LVDS0_PWM0_IPG_CLK] = imx_clk_gate2_scu("lvds0_pwm0_ipg_clk", "ipg_lvds_clk_root", (void __iomem *)(DI_LVDS_0_LPCG + 0x0C), 16, FUNCTION_NAME(PD_LVDS0_PWM));
|
||||
clks[IMX8QM_LVDS0_GPIO_IPG_CLK] = imx_clk_gate2_scu("lvds0_gpio_ipg_clk", "ipg_lvds_clk_root", (void __iomem *)(DI_LVDS_0_LPCG + 0x08), 16, FUNCTION_NAME(PD_LVDS0_GPIO));
|
||||
|
||||
clks[IMX8QM_LVDS1_PIXEL_CLK] = imx_clk_gate_scu("lvds1_pixel_clk", "lvds1_pixel_div", SC_R_LVDS_1, SC_PM_CLK_PER, NULL, 0, 0);
|
||||
clks[IMX8QM_LVDS1_I2C0_CLK] = imx_clk_gate_scu("lvds1_i2c0_clk", "lvds1_i2c0_div", SC_R_LVDS_1_I2C_0, SC_PM_CLK_PER, (void __iomem *)(DI_LVDS_1_LPCG + 0x10), 0, 0);
|
||||
clks[IMX8QM_LVDS1_I2C1_CLK] = imx_clk_gate_scu("lvds1_i2c1_clk", "lvds1_i2c1_div", SC_R_LVDS_1_I2C_1, SC_PM_CLK_PER, (void __iomem *)(DI_LVDS_1_LPCG + 0x14), 0, 0);
|
||||
clks[IMX8QM_LVDS1_PWM0_CLK] = imx_clk_gate_scu("lvds1_pwm0_clk", "lvds1_pwm0_div", SC_R_LVDS_1_PWM_0, SC_PM_CLK_PER, (void __iomem *)(DI_LVDS_1_LPCG + 0x0C), 0, 0);
|
||||
clks[IMX8QM_LVDS1_PHY_CLK] = imx_clk_gate_scu("lvds1_phy_clk", "lvds1_phy_div", SC_R_LVDS_1, SC_PM_CLK_PHY, NULL, 0, 0);
|
||||
clks[IMX8QM_LVDS1_I2C0_IPG_CLK] = imx_clk_gate2_scu("lvds1_i2c0_ipg_clk", "ipg_lvds_clk_root", (void __iomem *)(DI_LVDS_1_LPCG + 0x10), 16, FUNCTION_NAME(PD_LVDS1_I2C0));
|
||||
clks[IMX8QM_LVDS1_I2C1_IPG_CLK] = imx_clk_gate2_scu("lvds1_i2c1_ipg_clk", "ipg_lvds_clk_root", (void __iomem *)(DI_LVDS_1_LPCG + 0x14), 16, FUNCTION_NAME(PD_LVDS1_I2C1));
|
||||
clks[IMX8QM_LVDS1_PWM0_IPG_CLK] = imx_clk_gate2_scu("lvds1_pwm0_ipg_clk", "ipg_lvds_clk_root", (void __iomem *)(DI_LVDS_1_LPCG + 0x0C), 16, FUNCTION_NAME(PD_LVDS1_PWM));
|
||||
clks[IMX8QM_LVDS1_GPIO_IPG_CLK] = imx_clk_gate2_scu("lvds1_gpio_ipg_clk", "ipg_lvds_clk_root", (void __iomem *)(DI_LVDS_1_LPCG + 0x08), 16, FUNCTION_NAME(PD_LVDS1_GPIO));
|
||||
|
||||
/* vpu/zpu subsystem */
|
||||
clks[IMX8QM_VPU_DDR_CLK] = imx_clk_gate_scu("vpu_ddr_clk", "vpu_ddr_div", SC_R_VPU_PID0, SC_PM_CLK_SLV_BUS, NULL, 0, 0);
|
||||
clks[IMX8QM_VPU_SYS_CLK] = imx_clk_gate_scu("vpu_sys_clk", "vpu_sys_div", SC_R_VPU_PID0, SC_PM_CLK_MST_BUS, NULL, 0, 0);
|
||||
clks[IMX8QM_VPU_XUVI_CLK] = imx_clk_gate_scu("vpu_xuvi_clk", "vpu_xuvi_div", SC_R_VPU_PID0, SC_PM_CLK_PER, NULL, 0, 0);
|
||||
clks[IMX8QM_VPU_UART_CLK] = imx_clk_gate_scu("vpu_uart_clk", "vpu_uart_div", SC_R_VPU_UART, SC_PM_CLK_PER, NULL, 0, 0);
|
||||
clks[IMX8QM_VPU_CORE_CLK] = imx_clk_gate_scu("vpu_core_clk", "vpu_core_div", SC_R_VPUCORE, SC_PM_CLK_PER, NULL, 0, 0);
|
||||
|
||||
/* gpu */
|
||||
clks[IMX8QM_GPU0_CORE_CLK] = imx_clk_gate_scu("gpu_core0_clk", "gpu_core0_div", SC_R_GPU_0_PID0, SC_PM_CLK_PER, NULL, 0, 0);
|
||||
clks[IMX8QM_GPU0_SHADER_CLK] = imx_clk_gate_scu("gpu_shader0_clk", "gpu_shader0_div", SC_R_GPU_0_PID0, SC_PM_CLK_MISC, NULL, 0, 0);
|
||||
clks[IMX8QM_GPU1_CORE_CLK] = imx_clk_gate_scu("gpu_core1_clk", "gpu_core1_div", SC_R_GPU_1_PID0, SC_PM_CLK_PER, NULL, 0, 0);
|
||||
clks[IMX8QM_GPU1_SHADER_CLK] = imx_clk_gate_scu("gpu_shader1_clk", "gpu_shader1_div", SC_R_GPU_1_PID0, SC_PM_CLK_MISC, NULL, 0, 0);
|
||||
|
||||
/* Imaging SS */
|
||||
clks[IMX8QM_IMG_JPEG_ENC_IPG_CLK] = imx_clk_gate2_scu("img_jpeg_enc_ipg_clk", "ipg_img_clk_root", (void __iomem *)(IMG_JPEG_ENC_LPCG), 16, FUNCTION_NAME(PD_IMAGING));
|
||||
clks[IMX8QM_IMG_JPEG_ENC_CLK] = imx_clk_gate2_scu("img_jpeg_enc_clk", "img_jpeg_enc_ipg_clk", (void __iomem *)(IMG_JPEG_ENC_LPCG), 0, FUNCTION_NAME(PD_IMAGING));
|
||||
clks[IMX8QM_IMG_JPEG_DEC_IPG_CLK] = imx_clk_gate2_scu("img_jpeg_dec_ipg_clk", "ipg_img_clk_root", (void __iomem *)(IMG_JPEG_DEC_LPCG), 16, FUNCTION_NAME(PD_IMAGING));
|
||||
clks[IMX8QM_IMG_JPEG_DEC_CLK] = imx_clk_gate2_scu("img_jpeg_dec_clk", "img_jpeg_dec_ipg_clk", (void __iomem *)(IMG_JPEG_DEC_LPCG), 0, FUNCTION_NAME(PD_IMAGING));
|
||||
clks[IMX8QM_IMG_PXL_LINK_DC0_CLK] = imx_clk_gate2_scu("img_pxl_link_dc0_clk", "pxl_img_clk_root", (void __iomem *)(IMG_PXL_LINK_DC0_LPCG), 0, FUNCTION_NAME(PD_IMAGING));
|
||||
clks[IMX8QM_IMG_PXL_LINK_DC1_CLK] = imx_clk_gate2_scu("img_pxl_link_dc1_clk", "pxl_img_clk_root", (void __iomem *)(IMG_PXL_LINK_DC1_LPCG), 0, FUNCTION_NAME(PD_IMAGING));
|
||||
clks[IMX8QM_IMG_PXL_LINK_CSI0_CLK] = imx_clk_gate2_scu("img_pxl_link_csi0_clk", "pxl_img_clk_root", (void __iomem *)(IMG_PXL_LINK_CSI0_LPCG), 0, FUNCTION_NAME(PD_IMAGING));
|
||||
clks[IMX8QM_IMG_PXL_LINK_CSI1_CLK] = imx_clk_gate2_scu("img_pxl_link_csi1_clk", "pxl_img_clk_root", (void __iomem *)(IMG_PXL_LINK_CSI1_LPCG), 0, FUNCTION_NAME(PD_IMAGING));
|
||||
clks[IMX8QM_IMG_PXL_LINK_HDMI_IN_CLK] = imx_clk_gate2_scu("img_pxl_link_hdmi_in_clk", "pxl_img_clk_root", (void __iomem *)(IMG_PXL_LINK_HDMI_LPCG), 0, FUNCTION_NAME(PD_IMAGING));
|
||||
clks[IMX8QM_IMG_PDMA_0_CLK] = imx_clk_gate2_scu("img_pdma0_clk", "pxl_img_clk_root", (void __iomem *)(IMG_PDMA_0_LPCG), 0, FUNCTION_NAME(PD_IMAGING));
|
||||
clks[IMX8QM_IMG_PDMA_1_CLK] = imx_clk_gate2_scu("img_pdma1_clk", "pxl_img_clk_root", (void __iomem *)(IMG_PDMA_1_LPCG), 0, FUNCTION_NAME(PD_IMAGING));
|
||||
clks[IMX8QM_IMG_PDMA_2_CLK] = imx_clk_gate2_scu("img_pdma2_clk", "pxl_img_clk_root", (void __iomem *)(IMG_PDMA_2_LPCG), 0, FUNCTION_NAME(PD_IMAGING));
|
||||
clks[IMX8QM_IMG_PDMA_3_CLK] = imx_clk_gate2_scu("img_pdma3_clk", "pxl_img_clk_root", (void __iomem *)(IMG_PDMA_3_LPCG), 0, FUNCTION_NAME(PD_IMAGING));
|
||||
clks[IMX8QM_IMG_PDMA_4_CLK] = imx_clk_gate2_scu("img_pdma4_clk", "pxl_img_clk_root", (void __iomem *)(IMG_PDMA_4_LPCG), 0, FUNCTION_NAME(PD_IMAGING));
|
||||
clks[IMX8QM_IMG_PDMA_5_CLK] = imx_clk_gate2_scu("img_pdma5_clk", "pxl_img_clk_root", (void __iomem *)(IMG_PDMA_5_LPCG), 0, FUNCTION_NAME(PD_IMAGING));
|
||||
clks[IMX8QM_IMG_PDMA_6_CLK] = imx_clk_gate2_scu("img_pdma6_clk", "pxl_img_clk_root", (void __iomem *)(IMG_PDMA_6_LPCG), 0, FUNCTION_NAME(PD_IMAGING));
|
||||
clks[IMX8QM_IMG_PDMA_7_CLK] = imx_clk_gate2_scu("img_pdma7_clk", "pxl_img_clk_root", (void __iomem *)(IMG_PDMA_7_LPCG), 0, FUNCTION_NAME(PD_IMAGING));
|
||||
|
||||
/* HSIO */
|
||||
clks[IMX8QM_HSIO_PCIE_A_MSTR_AXI_CLK] = imx_clk_gate2_scu("hsio_pcieA_mstr_axi_clk", "axi_hsio_clk_root", (void __iomem *)(HSIO_PCIE_X2_LPCG), 16, FUNCTION_NAME(PD_HSIO_PCIE_A));
|
||||
clks[IMX8QM_HSIO_PCIE_A_SLV_AXI_CLK] = imx_clk_gate2_scu("hsio_pcieA_slv_axi_clk", "axi_hsio_clk_root", (void __iomem *)(HSIO_PCIE_X2_LPCG), 20, FUNCTION_NAME(PD_HSIO_PCIE_A));
|
||||
clks[IMX8QM_HSIO_PCIE_A_DBI_AXI_CLK] = imx_clk_gate2_scu("hsio_pcieA_dbi_axi_clk", "axi_hsio_clk_root", (void __iomem *)(HSIO_PCIE_X2_LPCG), 24, FUNCTION_NAME(PD_HSIO_PCIE_A));
|
||||
clks[IMX8QM_HSIO_PCIE_B_MSTR_AXI_CLK] = imx_clk_gate2_scu("hsio_pcieB_mstr_axi_clk", "axi_hsio_clk_root", (void __iomem *)(HSIO_PCIE_X1_LPCG), 16, FUNCTION_NAME(PD_HSIO_PCIE_B));
|
||||
clks[IMX8QM_HSIO_PCIE_B_SLV_AXI_CLK] = imx_clk_gate2_scu("hsio_pcieB_slv_axi_clk", "axi_hsio_clk_root", (void __iomem *)(HSIO_PCIE_X1_LPCG), 20, FUNCTION_NAME(PD_HSIO_PCIE_B));
|
||||
clks[IMX8QM_HSIO_PCIE_B_DBI_AXI_CLK] = imx_clk_gate2_scu("hsio_pcieB_dbi_axi_clk", "axi_hsio_clk_root", (void __iomem *)(HSIO_PCIE_X1_LPCG), 24, FUNCTION_NAME(PD_HSIO_PCIE_B));
|
||||
clks[IMX8QM_HSIO_PCIE_X1_PER_CLK] = imx_clk_gate2_scu("hsio_pcie_x1_per_clk", "per_hsio_clk_root", (void __iomem *)(HSIO_PCIE_X1_CRR3_LPCG), 16, FUNCTION_NAME(PD_HSIO_PCIE_B));
|
||||
clks[IMX8QM_HSIO_PCIE_X2_PER_CLK] = imx_clk_gate2_scu("hsio_pcie_x2_per_clk", "per_hsio_clk_root", (void __iomem *)(HSIO_PCIE_X2_CRR2_LPCG), 16, FUNCTION_NAME(PD_HSIO_PCIE_B));
|
||||
clks[IMX8QM_HSIO_SATA_PER_CLK] = imx_clk_gate2_scu("hsio_sata_per_clk", "per_hsio_clk_root", (void __iomem *)(HSIO_SATA_CRR4_LPCG), 16, FUNCTION_NAME(PD_HSIO_SATA_0));
|
||||
clks[IMX8QM_HSIO_PHY_X1_PER_CLK] = imx_clk_gate2_scu("hsio_phy_x1_per_clk", "per_hsio_clk_root", (void __iomem *)(HSIO_PHY_X1_CRR1_LPCG), 16, FUNCTION_NAME(PD_HSIO_PCIE_B));
|
||||
clks[IMX8QM_HSIO_PHY_X2_PER_CLK] = imx_clk_gate2_scu("hsio_phy_x2_per_clk", "per_hsio_clk_root", (void __iomem *)(HSIO_PHY_X2_CRR0_LPCG), 16, FUNCTION_NAME(PD_HSIO_PCIE_A));
|
||||
clks[IMX8QM_HSIO_MISC_PER_CLK] = imx_clk_gate2_scu("hsio_misc_per_clk", "per_hsio_clk_root", (void __iomem *)(HSIO_MISC_LPCG), 16, FUNCTION_NAME(PD_HSIO));
|
||||
clks[IMX8QM_HSIO_PHY_X1_APB_CLK] = imx_clk_gate2_scu("hsio_phy_x1_apb_clk", "per_hsio_clk_root", (void __iomem *)(HSIO_PHY_X1_LPCG), 16, FUNCTION_NAME(PD_HSIO_PCIE_B));
|
||||
clks[IMX8QM_HSIO_PHY_X2_APB_0_CLK] = imx_clk_gate2_scu("hsio_phy_x2_apb_0_clk", "per_hsio_clk_root", (void __iomem *)(HSIO_PHY_X2_LPCG), 16, FUNCTION_NAME(PD_HSIO_PCIE_A));
|
||||
clks[IMX8QM_HSIO_PHY_X2_APB_1_CLK] = imx_clk_gate2_scu("hsio_phy_x2_apb_1_clk", "per_hsio_clk_root", (void __iomem *)(HSIO_PHY_X2_LPCG), 20, FUNCTION_NAME(PD_HSIO_PCIE_A));
|
||||
clks[IMX8QM_HSIO_SATA_CLK] = imx_clk_gate2_scu("hsio_sata_clk", "axi_hsio_clk_root", (void __iomem *)(HSIO_SATA_LPCG), 16, FUNCTION_NAME(PD_HSIO_SATA_0));
|
||||
clks[IMX8QM_HSIO_GPIO_CLK] = imx_clk_gate2_scu("hsio_gpio_clk", "per_hsio_clk_root", (void __iomem *)(HSIO_GPIO_LPCG), 16, FUNCTION_NAME(PD_HSIO_PCIE_A));
|
||||
clks[IMX8QM_HSIO_PHY_X1_PCLK] = imx_clk_gate2_scu("hsio_phy_x1_pclk", "dummy", (void __iomem *)(HSIO_PHY_X1_LPCG), 0, FUNCTION_NAME(PD_HSIO_PCIE_B));
|
||||
clks[IMX8QM_HSIO_PHY_X2_PCLK_0] = imx_clk_gate2_scu("hsio_phy_x2_pclk_0", "dummy", (void __iomem *)(HSIO_PHY_X2_LPCG), 0, FUNCTION_NAME(PD_HSIO_PCIE_A));
|
||||
clks[IMX8QM_HSIO_PHY_X2_PCLK_1] = imx_clk_gate2_scu("hsio_phy_x2_pclk_1", "dummy", (void __iomem *)(HSIO_PHY_X2_LPCG), 4, FUNCTION_NAME(PD_HSIO_PCIE_A));
|
||||
clks[IMX8QM_HSIO_SATA_EPCS_RX_CLK] = imx_clk_gate2_scu("hsio_sata_epcs_rx_clk", "dummy", (void __iomem *)(HSIO_PHY_X1_LPCG), 8, FUNCTION_NAME(PD_HSIO_SATA_0));
|
||||
clks[IMX8QM_HSIO_SATA_EPCS_TX_CLK] = imx_clk_gate2_scu("hsio_sata_epcs_tx_clk", "dummy", (void __iomem *)(HSIO_PHY_X1_LPCG), 4, FUNCTION_NAME(PD_HSIO_SATA_0));
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(clks); i++)
|
||||
if (IS_ERR(clks[i]))
|
||||
pr_err("i.MX8QM clk %d: register failed with %ld\n",
|
||||
i, PTR_ERR(clks[i]));
|
||||
|
||||
clk_data.clks = clks;
|
||||
clk_data.clk_num = ARRAY_SIZE(clks);
|
||||
of_clk_add_provider(ccm_node, of_clk_src_onecell_get, &clk_data);
|
||||
|
||||
clk_prepare_enable(clks[IMX8QM_A53_DIV]);
|
||||
clk_prepare_enable(clks[IMX8QM_A72_DIV]);
|
||||
}
|
||||
|
||||
static int __init imx8qm_post_clk_init(void)
|
||||
{
|
||||
int i;
|
||||
|
||||
/* Initialize the clk rate for all the possible clocks now. */
|
||||
for (i = 0; i < IMX8QM_CLK_END; i++)
|
||||
clk_get_rate(clks[i]);
|
||||
|
||||
return 0;
|
||||
}
|
||||
postcore_initcall(imx8qm_post_clk_init);
|
||||
|
||||
CLK_OF_DECLARE(imx8qm, "fsl,imx8qm-clk", imx8qm_clocks_init);
|
||||
342
drivers/clk/imx/clk-mux-scu.c
Normal file
342
drivers/clk/imx/clk-mux-scu.c
Normal file
@ -0,0 +1,342 @@
|
||||
/*
|
||||
* Copyright (C) 2016 Freescale Semiconductor, Inc.
|
||||
* Copyright 2017 NXP
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License
|
||||
* as published by the Free Software Foundation; either version 2
|
||||
* of the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <linux/clk.h>
|
||||
#include <linux/clk-provider.h>
|
||||
#include <linux/err.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/pm_domain.h>
|
||||
#include <linux/slab.h>
|
||||
#include <linux/string.h>
|
||||
#include <soc/imx8/sc/sci.h>
|
||||
|
||||
#include "clk-imx8.h"
|
||||
|
||||
/*
|
||||
* DOC: basic adjustable multiplexer clock that cannot gate
|
||||
*
|
||||
* Traits of this clock:
|
||||
* prepare - clk_prepare only ensures that parents are prepared
|
||||
* enable - clk_enable only ensures that parents are enabled
|
||||
* rate - rate is only affected by parent switching. No clk_set_rate support
|
||||
* parent - parent is adjustable through clk_set_parent
|
||||
*/
|
||||
|
||||
struct clk_mux_scu {
|
||||
struct clk_hw hw;
|
||||
void __iomem *reg;
|
||||
u32 *table;
|
||||
u32 mask;
|
||||
u8 shift;
|
||||
u8 flags;
|
||||
spinlock_t *lock;
|
||||
char *pd_name;
|
||||
struct generic_pm_domain *pd;
|
||||
};
|
||||
|
||||
struct clk_mux_gpr_scu {
|
||||
struct clk_hw hw;
|
||||
spinlock_t *lock;
|
||||
sc_rsrc_t rsrc_id;
|
||||
sc_ctrl_t gpr_id;
|
||||
};
|
||||
|
||||
#define to_clk_mux_scu(_hw) container_of(_hw, struct clk_mux_scu, hw)
|
||||
#define to_clk_mux_gpr_scu(_hw) container_of(_hw, struct clk_mux_gpr_scu, hw)
|
||||
|
||||
/* Get the power domain associated with the clock from the device tree. */
|
||||
static void populate_mux_pd(struct clk_mux_scu *clk)
|
||||
{
|
||||
struct device_node *np;
|
||||
struct of_phandle_args pd_args;
|
||||
|
||||
np = of_find_node_by_name(NULL, clk->pd_name);
|
||||
if (np) {
|
||||
pd_args.np = np;
|
||||
pd_args.args_count = 0;
|
||||
of_genpd_add_provider_simple(np, clk->pd);
|
||||
}
|
||||
}
|
||||
|
||||
static u8 clk_mux_get_parent_scu(struct clk_hw *hw)
|
||||
{
|
||||
struct clk_mux_scu *mux = to_clk_mux_scu(hw);
|
||||
int num_parents = clk_hw_get_num_parents(hw);
|
||||
u32 val;
|
||||
|
||||
if (!ccm_ipc_handle)
|
||||
return 0;
|
||||
|
||||
if (mux->pd == NULL && mux->pd_name)
|
||||
populate_mux_pd(mux);
|
||||
|
||||
if (!mux->pd)
|
||||
return 0;
|
||||
|
||||
if (mux->pd->status != GPD_STATE_ACTIVE)
|
||||
return 0;
|
||||
|
||||
/*
|
||||
* FIXME need a mux-specific flag to determine if val is bitwise or numeric
|
||||
* e.g. sys_clkin_ck's clksel field is 3 bits wide, but ranges from 0x1
|
||||
* to 0x7 (index starts at one)
|
||||
* OTOH, pmd_trace_clk_mux_ck uses a separate bit for each clock, so
|
||||
* val = 0x4 really means "bit 2, index starts at bit 0"
|
||||
*/
|
||||
val = clk_readl(mux->reg) >> mux->shift;
|
||||
val &= mux->mask;
|
||||
|
||||
if (mux->table) {
|
||||
int i;
|
||||
|
||||
for (i = 0; i < num_parents; i++)
|
||||
if (mux->table[i] == val)
|
||||
return i;
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
if (val && (mux->flags & CLK_MUX_INDEX_BIT))
|
||||
val = ffs(val) - 1;
|
||||
|
||||
if (val && (mux->flags & CLK_MUX_INDEX_ONE))
|
||||
val--;
|
||||
|
||||
if (val >= num_parents)
|
||||
return -EINVAL;
|
||||
|
||||
return val;
|
||||
}
|
||||
|
||||
static int clk_mux_set_parent_scu(struct clk_hw *hw, u8 index)
|
||||
{
|
||||
struct clk_mux_scu *mux = to_clk_mux_scu(hw);
|
||||
u32 val;
|
||||
unsigned long flags = 0;
|
||||
|
||||
if (!ccm_ipc_handle)
|
||||
return -1;
|
||||
|
||||
if (mux->pd == NULL && mux->pd_name)
|
||||
populate_mux_pd(mux);
|
||||
|
||||
if (!mux->pd)
|
||||
return -1;
|
||||
|
||||
if (mux->pd->status != GPD_STATE_ACTIVE)
|
||||
return -1;
|
||||
|
||||
if (mux->table) {
|
||||
index = mux->table[index];
|
||||
} else {
|
||||
if (mux->flags & CLK_MUX_INDEX_BIT)
|
||||
index = 1 << index;
|
||||
if (mux->flags & CLK_MUX_INDEX_ONE)
|
||||
index++;
|
||||
}
|
||||
|
||||
if (mux->lock)
|
||||
spin_lock_irqsave(mux->lock, flags);
|
||||
|
||||
if (mux->flags & CLK_MUX_HIWORD_MASK) {
|
||||
val = mux->mask << (mux->shift + 16);
|
||||
} else {
|
||||
val = clk_readl(mux->reg);
|
||||
val &= ~(mux->mask << mux->shift);
|
||||
}
|
||||
val |= index << mux->shift;
|
||||
clk_writel(val, mux->reg);
|
||||
|
||||
if (mux->lock)
|
||||
spin_unlock_irqrestore(mux->lock, flags);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
const struct clk_ops clk_mux_scu_ops = {
|
||||
.get_parent = clk_mux_get_parent_scu,
|
||||
.set_parent = clk_mux_set_parent_scu,
|
||||
.determine_rate = __clk_mux_determine_rate,
|
||||
};
|
||||
|
||||
const struct clk_ops clk_mux_ro_scu_ops = {
|
||||
.get_parent = clk_mux_get_parent_scu,
|
||||
};
|
||||
|
||||
struct clk *clk_register_mux_table_scu(struct device *dev, const char *name,
|
||||
const char **parent_names, u8 num_parents, unsigned long flags,
|
||||
void __iomem *reg, u8 shift, u32 mask,
|
||||
u8 clk_mux_flags, u32 *table, spinlock_t *lock,
|
||||
const char *pd_name)
|
||||
{
|
||||
struct clk_mux_scu *mux;
|
||||
struct clk *clk;
|
||||
struct clk_init_data init;
|
||||
u8 width = 0;
|
||||
|
||||
if (clk_mux_flags & CLK_MUX_HIWORD_MASK) {
|
||||
width = fls(mask) - ffs(mask) + 1;
|
||||
if (width + shift > 16) {
|
||||
pr_err("mux value exceeds LOWORD field\n");
|
||||
return ERR_PTR(-EINVAL);
|
||||
}
|
||||
}
|
||||
|
||||
/* allocate the mux */
|
||||
mux = kzalloc(sizeof(struct clk_mux_scu), GFP_KERNEL);
|
||||
if (!mux) {
|
||||
pr_err("%s: could not allocate mux clk\n", __func__);
|
||||
return ERR_PTR(-ENOMEM);
|
||||
}
|
||||
|
||||
init.name = name;
|
||||
if (clk_mux_flags & CLK_MUX_READ_ONLY)
|
||||
init.ops = &clk_mux_ro_scu_ops;
|
||||
else
|
||||
init.ops = &clk_mux_scu_ops;
|
||||
init.flags = flags | CLK_IS_BASIC;
|
||||
init.parent_names = parent_names;
|
||||
init.num_parents = num_parents;
|
||||
|
||||
/* struct clk_mux_scu assignments */
|
||||
mux->reg = reg;
|
||||
mux->shift = shift;
|
||||
mux->mask = mask;
|
||||
mux->flags = clk_mux_flags;
|
||||
mux->lock = lock;
|
||||
mux->table = table;
|
||||
mux->hw.init = &init;
|
||||
mux->pd_name = NULL;
|
||||
if (pd_name) {
|
||||
mux->pd_name = kzalloc(strlen(pd_name) + 1, GFP_KERNEL);
|
||||
strcpy(mux->pd_name, pd_name);
|
||||
}
|
||||
|
||||
clk = clk_register(dev, &mux->hw);
|
||||
|
||||
if (IS_ERR(clk)) {
|
||||
kfree(mux->pd_name);
|
||||
kfree(mux);
|
||||
}
|
||||
|
||||
return clk;
|
||||
}
|
||||
|
||||
struct clk *clk_register_mux_scu(struct device *dev, const char *name,
|
||||
const char **parent_names, u8 num_parents, unsigned long flags,
|
||||
void __iomem *reg, u8 shift, u8 width,
|
||||
u8 clk_mux_flags, spinlock_t *lock,
|
||||
const char *pd_name)
|
||||
{
|
||||
u32 mask = BIT(width) - 1;
|
||||
|
||||
return clk_register_mux_table_scu(dev, name, parent_names, num_parents,
|
||||
flags, reg, shift, mask, clk_mux_flags,
|
||||
NULL, lock, pd_name);
|
||||
}
|
||||
|
||||
void clk_unregister_mux_scu(struct clk *clk)
|
||||
{
|
||||
struct clk_mux_scu *mux;
|
||||
struct clk_hw *hw;
|
||||
|
||||
hw = __clk_get_hw(clk);
|
||||
if (!hw)
|
||||
return;
|
||||
|
||||
mux = to_clk_mux_scu(hw);
|
||||
|
||||
clk_unregister(clk);
|
||||
kfree(mux);
|
||||
}
|
||||
|
||||
static u8 clk_mux_gpr_scu_get_parent(struct clk_hw *hw)
|
||||
{
|
||||
struct clk_mux_gpr_scu *gpr_mux = to_clk_mux_gpr_scu(hw);
|
||||
unsigned long flags = 0;
|
||||
u32 val = 0;
|
||||
|
||||
if (!ccm_ipc_handle)
|
||||
return 0;
|
||||
|
||||
spin_lock_irqsave(gpr_mux->lock, flags);
|
||||
|
||||
sc_misc_get_control(ccm_ipc_handle,
|
||||
gpr_mux->rsrc_id, gpr_mux->gpr_id, &val);
|
||||
|
||||
spin_unlock_irqrestore(gpr_mux->lock, flags);
|
||||
|
||||
return (u8)val;
|
||||
}
|
||||
|
||||
static int clk_mux_gpr_scu_set_parent(struct clk_hw *hw, u8 index)
|
||||
{
|
||||
struct clk_mux_gpr_scu *gpr_mux = to_clk_mux_gpr_scu(hw);
|
||||
unsigned long flags = 0;
|
||||
|
||||
if (!ccm_ipc_handle)
|
||||
return -1;
|
||||
|
||||
spin_lock_irqsave(gpr_mux->lock, flags);
|
||||
|
||||
sc_misc_set_control(ccm_ipc_handle,
|
||||
gpr_mux->rsrc_id, gpr_mux->gpr_id, index);
|
||||
|
||||
spin_unlock_irqrestore(gpr_mux->lock, flags);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct clk_ops clk_mux_gpr_scu_ops = {
|
||||
.get_parent = clk_mux_gpr_scu_get_parent,
|
||||
.set_parent = clk_mux_gpr_scu_set_parent,
|
||||
};
|
||||
|
||||
struct clk *clk_register_mux_gpr_scu(struct device *dev, const char *name,
|
||||
const char **parents, int num_parents, spinlock_t *lock,
|
||||
sc_rsrc_t rsrc_id, sc_ctrl_t gpr_id)
|
||||
{
|
||||
struct clk_mux_gpr_scu *gpr_scu_mux;
|
||||
struct clk *clk;
|
||||
struct clk_init_data init;
|
||||
|
||||
if (rsrc_id >= SC_R_LAST)
|
||||
return NULL;
|
||||
|
||||
if (gpr_id >= SC_C_LAST)
|
||||
return NULL;
|
||||
|
||||
gpr_scu_mux = kzalloc(sizeof(struct clk_mux_gpr_scu), GFP_KERNEL);
|
||||
if (!gpr_scu_mux)
|
||||
return ERR_PTR(-ENOMEM);
|
||||
|
||||
init.name = name;
|
||||
init.ops = &clk_mux_gpr_scu_ops;
|
||||
init.parent_names = parents;
|
||||
init.num_parents = num_parents;
|
||||
init.flags = 0;
|
||||
|
||||
gpr_scu_mux->lock = &imx_ccm_lock;
|
||||
gpr_scu_mux->hw.init = &init;
|
||||
gpr_scu_mux->rsrc_id = rsrc_id;
|
||||
gpr_scu_mux->gpr_id = gpr_id;
|
||||
|
||||
clk = clk_register(NULL, &gpr_scu_mux->hw);
|
||||
if (IS_ERR(clk))
|
||||
kfree(gpr_scu_mux);
|
||||
|
||||
return clk;
|
||||
}
|
||||
Reference in New Issue
Block a user