drm/mxsfb: Update mxsfb to support LCD reset
The eLCDIF controller has control pin for the external LCD reset pin. Add support for it and assert this pin in enable and de-assert it in disable. Signed-off-by: Robert Chiras <robert.chiras@nxp.com> Tested-by: Guido Günther <agx@sigxcpu.org>
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committed by
Dong Aisheng
parent
1d0b3c97e5
commit
cfe8597341
@ -224,9 +224,12 @@ static void mxsfb_enable_controller(struct mxsfb_drm_private *mxsfb)
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clk_prepare_enable(mxsfb->clk_disp_axi);
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clk_prepare_enable(mxsfb->clk);
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if (mxsfb->devdata->ipversion >= 4)
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if (mxsfb->devdata->ipversion >= 4) {
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writel(CTRL2_OUTSTANDING_REQS(REQ_16),
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mxsfb->base + LCDC_V4_CTRL2 + REG_SET);
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/* Assert LCD Reset bit */
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writel(CTRL2_LCD_RESET, mxsfb->base + LCDC_V4_CTRL2 + REG_SET);
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}
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/* If it was disabled, re-enable the mode again */
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writel(CTRL_DOTCLK_MODE, mxsfb->base + LCDC_CTRL + REG_SET);
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@ -244,11 +247,14 @@ static void mxsfb_disable_controller(struct mxsfb_drm_private *mxsfb)
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{
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u32 reg;
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if (mxsfb->devdata->ipversion >= 4)
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writel(CTRL_RUN, mxsfb->base + LCDC_CTRL + REG_CLR);
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if (mxsfb->devdata->ipversion >= 4) {
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writel(CTRL2_OUTSTANDING_REQS(0x7),
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mxsfb->base + LCDC_V4_CTRL2 + REG_CLR);
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writel(CTRL_RUN, mxsfb->base + LCDC_CTRL + REG_CLR);
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/* De-assert LCD Reset bit */
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writel(CTRL2_LCD_RESET, mxsfb->base + LCDC_V4_CTRL2 + REG_CLR);
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}
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/*
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* Even if we disable the controller here, it will still continue
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@ -108,6 +108,8 @@
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#define CTRL2_LINE_PATTERN_BGR 5
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#define CTRL2_LINE_PATTERN_CLR 7
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#define CTRL2_LCD_RESET BIT(0)
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#define TRANSFER_COUNT_SET_VCOUNT(x) REG_PUT((x), 31, 16)
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#define TRANSFER_COUNT_GET_VCOUNT(x) REG_GET((x), 31, 16)
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#define TRANSFER_COUNT_SET_HCOUNT(x) REG_PUT((x), 15, 0)
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