MLK-9971 Add XCBC-AES support for CAAM in i.MX6 family
Add XCBC-AES support to the CAAM crypto accelerator core in the i.MX6 family of SoC devices. Note that CAAM also goes by sec-4.0 or sec-5.0 in other product families (such as QorIQ). Thus the property names are often tied to the sec-4.0+ nomenclature. Signed-off-by: Winston Hudson (b45308) <winston.h.hudson@freescale.com> Signed-off-by: Dan Douglass <dan.douglass@freescale.com>
This commit is contained in:
Winston Hudson (b45308)
committed by
Jason Liu
Jason Liu
parent
0238df32d3
commit
eeb599a4ed
@ -62,6 +62,7 @@
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#include "error.h"
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#include "sg_sw_sec4.h"
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#include "key_gen.h"
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#include <linux/string.h>
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#define CAAM_CRA_PRIORITY 3000
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@ -111,6 +112,7 @@ struct caam_hash_ctx {
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u8 key[CAAM_MAX_HASH_KEY_SIZE];
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int ctx_len;
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struct alginfo adata;
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unsigned int key_len;
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};
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/* ahash state */
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@ -234,6 +236,68 @@ static inline int ctx_map_to_sec4_sg(u32 *desc, struct device *jrdev,
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return 0;
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}
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static inline void append_key_axcbc(u32 *desc, struct caam_hash_ctx *ctx)
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{
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append_key_as_imm(desc, ctx->key, ctx->key_len,
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ctx->key_len, CLASS_1 |
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KEY_DEST_CLASS_REG);
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}
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static inline void init_sh_desc_key_axcbc(u32 *desc, struct caam_hash_ctx *ctx)
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{
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u32 *key_jump_cmd;
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init_sh_desc(desc, HDR_SHARE_SERIAL);
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if (ctx->key_len) {
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key_jump_cmd = append_jump(desc, JUMP_JSL | JUMP_TEST_ALL |
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JUMP_COND_SHRD);
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append_key_axcbc(desc, ctx);
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set_jump_tgt_here(desc, key_jump_cmd);
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}
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/* Propagate errors from shared to job descriptor */
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append_cmd(desc, SET_OK_NO_PROP_ERRORS | CMD_LOAD);
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}
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static inline void axcbc_append_load_str(u32 *desc, int digestsize)
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{
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/* Calculate remaining bytes to read */
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append_math_add(desc, VARSEQINLEN, SEQINLEN, REG0, CAAM_CMD_SZ);
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/* Read remaining bytes */
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append_seq_fifo_load(desc, 0, FIFOLD_CLASS_CLASS1 | FIFOLD_TYPE_LAST1 |
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FIFOLD_TYPE_MSG | KEY_VLF);
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/* Store class1 context bytes */
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append_seq_store(desc, digestsize, LDST_CLASS_1_CCB |
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LDST_SRCDST_BYTE_CONTEXT);
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}
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/*
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* For ahash update, final and finup, import context, read and write to seqout
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*/
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static inline void axcbc_ctx_data_to_out(u32 *desc, u32 op, u32 state,
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int digestsize,
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struct caam_hash_ctx *ctx)
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{
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init_sh_desc_key_axcbc(desc, ctx);
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/* Import context from software */
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append_cmd(desc, CMD_SEQ_LOAD | LDST_SRCDST_BYTE_CONTEXT |
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LDST_CLASS_1_CCB | ctx->ctx_len);
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/* Class 1 operation */
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append_operation(desc, op | state | OP_ALG_ENCRYPT);
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/*
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* Load from buf and/or src and write to req->result or state->context
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*/
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axcbc_append_load_str(desc, digestsize);
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}
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/*
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* For ahash update, final and finup (import_ctx = true)
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* import context, read and write to seqout
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@ -284,6 +348,21 @@ static inline void ahash_gen_sh_desc(u32 *desc, u32 state, int digestsize,
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LDST_SRCDST_BYTE_CONTEXT);
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}
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/* For ahash firsts and digest, read and write to seqout */
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static inline void axcbc_data_to_out(u32 *desc, u32 op, u32 state,
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int digestsize, struct caam_hash_ctx *ctx)
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{
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init_sh_desc_key_axcbc(desc, ctx);
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/* Class 1 operation */
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append_operation(desc, op | state | OP_ALG_ENCRYPT);
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/*
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* Load from buf and/or src and write to req->result or state->context
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*/
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axcbc_append_load_str(desc, digestsize);
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}
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static int ahash_set_sh_desc(struct crypto_ahash *ahash)
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{
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struct caam_hash_ctx *ctx = crypto_ahash_ctx(ahash);
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@ -339,6 +418,125 @@ static int ahash_set_sh_desc(struct crypto_ahash *ahash)
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return 0;
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}
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static int axcbc_set_sh_desc(struct crypto_ahash *ahash)
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{
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struct caam_hash_ctx *ctx = crypto_ahash_ctx(ahash);
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int digestsize = crypto_ahash_digestsize(ahash);
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struct device *jrdev = ctx->jrdev;
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u32 have_key = 0;
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u32 *desc;
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/* ahash_update shared descriptor */
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desc = ctx->sh_desc_update;
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init_sh_desc(desc, HDR_SHARE_SERIAL);
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/* Import context from software */
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append_cmd(desc, CMD_SEQ_LOAD | LDST_SRCDST_BYTE_CONTEXT |
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LDST_CLASS_1_CCB | ctx->ctx_len);
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/* Class 1 operation */
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append_operation(desc, ctx->adata.algtype | OP_ALG_AS_UPDATE |
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OP_ALG_ENCRYPT);
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/* Load data and write to result or context */
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axcbc_append_load_str(desc, ctx->ctx_len);
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ctx->sh_desc_update_dma = dma_map_single(jrdev, desc, desc_bytes(desc),
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DMA_TO_DEVICE);
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if (dma_mapping_error(jrdev, ctx->sh_desc_update_dma)) {
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dev_err(jrdev, "unable to map shared descriptor\n");
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return -ENOMEM;
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}
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#ifdef DEBUG
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print_hex_dump(KERN_ERR, "ahash update shdesc@"__stringify(__LINE__)": ",
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DUMP_PREFIX_ADDRESS, 16, 4, desc, desc_bytes(desc), 1);
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#endif
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/* ahash_update_first shared descriptor */
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desc = ctx->sh_desc_update_first;
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axcbc_data_to_out(desc, have_key | ctx->adata.algtype, OP_ALG_AS_INIT,
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ctx->ctx_len, ctx);
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ctx->sh_desc_update_first_dma = dma_map_single(jrdev, desc,
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desc_bytes(desc),
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DMA_TO_DEVICE);
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if (dma_mapping_error(jrdev, ctx->sh_desc_update_first_dma)) {
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dev_err(jrdev, "unable to map shared descriptor\n");
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return -ENOMEM;
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}
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#ifdef DEBUG
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print_hex_dump(KERN_ERR, "ahash update first shdesc@"__stringify(__LINE__)": ",
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DUMP_PREFIX_ADDRESS, 16, 4, desc, desc_bytes(desc), 1);
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#endif
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dma_sync_single_for_device(jrdev, ctx->sh_desc_update_first_dma,
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desc_bytes(desc), DMA_TO_DEVICE);
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/* ahash_final shared descriptor */
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desc = ctx->sh_desc_fin;
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axcbc_ctx_data_to_out(desc, have_key | ctx->adata.algtype,
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OP_ALG_AS_FINALIZE, digestsize, ctx);
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ctx->sh_desc_fin_dma = dma_map_single(jrdev, desc, desc_bytes(desc),
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DMA_TO_DEVICE);
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if (dma_mapping_error(jrdev, ctx->sh_desc_fin_dma)) {
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dev_err(jrdev, "unable to map shared descriptor\n");
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return -ENOMEM;
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}
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#ifdef DEBUG
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print_hex_dump(KERN_ERR, "ahash final shdesc@"__stringify(__LINE__)": ",
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DUMP_PREFIX_ADDRESS, 16, 4, desc,
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desc_bytes(desc), 1);
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#endif
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dma_sync_single_for_device(jrdev, ctx->sh_desc_fin_dma,
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desc_bytes(desc), DMA_TO_DEVICE);
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/* ahash_finup shared descriptor */
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desc = ctx->sh_desc_fin;
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axcbc_ctx_data_to_out(desc, have_key | ctx->adata.algtype,
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OP_ALG_AS_FINALIZE, digestsize, ctx);
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ctx->sh_desc_fin_dma = dma_map_single(jrdev, desc, desc_bytes(desc),
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DMA_TO_DEVICE);
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if (dma_mapping_error(jrdev, ctx->sh_desc_fin_dma)) {
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dev_err(jrdev, "unable to map shared descriptor\n");
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return -ENOMEM;
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}
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#ifdef DEBUG
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print_hex_dump(KERN_ERR, "ahash finup shdesc@"__stringify(__LINE__)": ",
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DUMP_PREFIX_ADDRESS, 16, 4, desc,
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desc_bytes(desc), 1);
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#endif
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dma_sync_single_for_device(jrdev, ctx->sh_desc_fin_dma,
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desc_bytes(desc), DMA_TO_DEVICE);
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/* ahash_digest shared descriptor */
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desc = ctx->sh_desc_digest;
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axcbc_data_to_out(desc, have_key | ctx->adata.algtype, OP_ALG_AS_INITFINAL,
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digestsize, ctx);
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ctx->sh_desc_digest_dma = dma_map_single(jrdev, desc,
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desc_bytes(desc),
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DMA_TO_DEVICE);
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if (dma_mapping_error(jrdev, ctx->sh_desc_digest_dma)) {
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dev_err(jrdev, "unable to map shared descriptor\n");
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return -ENOMEM;
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}
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#ifdef DEBUG
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print_hex_dump(KERN_ERR, "ahash digest shdesc@"__stringify(__LINE__)": ",
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DUMP_PREFIX_ADDRESS, 16, 4, desc,
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desc_bytes(desc), 1);
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#endif
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dma_sync_single_for_device(jrdev, ctx->sh_desc_digest_dma,
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desc_bytes(desc), DMA_TO_DEVICE);
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return 0;
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}
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/* Digest hash size if it is too large */
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static int hash_digest_key(struct caam_hash_ctx *ctx, const u8 *key_in,
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u32 *keylen, u8 *key_out, u32 digestsize)
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@ -460,6 +658,25 @@ static int ahash_setkey(struct crypto_ahash *ahash,
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return -EINVAL;
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}
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static int axcbc_setkey(struct crypto_ahash *ahash,
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const u8 *key, unsigned int keylen)
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{
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struct caam_hash_ctx *ctx = crypto_ahash_ctx(ahash);
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int ret = 0;
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ctx->key_len = keylen;
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memcpy(ctx->key, key, keylen);
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#ifdef DEBUG
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print_hex_dump(KERN_ERR, "ctx.key@"__stringify(__LINE__)": ",
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DUMP_PREFIX_ADDRESS, 16, 4, ctx->key,
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ctx->key_len, 1);
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#endif
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ret = axcbc_set_sh_desc(ahash);
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return ret;
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}
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/*
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* ahash_edesc - s/w-extended ahash descriptor
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* @dst_dma: physical mapped address of req->result
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@ -1692,6 +1909,27 @@ static struct caam_hash_template driver_hash[] = {
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},
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.alg_type = OP_ALG_ALGSEL_MD5,
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},
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{
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.name = "xcbc(aes)",
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.driver_name = "xcbc-aes-caam",
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.hmac_name = "xcbc(aes)",
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.hmac_driver_name = "xcbc-aes-caam",
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.blocksize = XCBC_MAC_BLOCK_WORDS * 4,
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.template_ahash = {
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.init = ahash_init,
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.update = ahash_update,
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.final = ahash_final,
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.finup = ahash_finup,
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.digest = ahash_digest,
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.export = ahash_export,
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.import = ahash_import,
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.setkey = axcbc_setkey,
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.halg = {
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.digestsize = XCBC_MAC_DIGEST_SIZE,
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},
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},
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.alg_type = OP_ALG_ALGSEL_AES | OP_ALG_AAI_XCBC_MAC,
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},
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};
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struct caam_hash_alg {
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@ -1761,6 +1999,40 @@ static int caam_hash_cra_init(struct crypto_tfm *tfm)
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return ahash_set_sh_desc(ahash);
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}
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static int caam_axcbc_cra_init(struct crypto_tfm *tfm)
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{
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struct crypto_ahash *ahash = __crypto_ahash_cast(tfm);
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struct crypto_alg *base = tfm->__crt_alg;
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struct hash_alg_common *halg =
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container_of(base, struct hash_alg_common, base);
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struct ahash_alg *alg =
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container_of(halg, struct ahash_alg, halg);
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struct caam_hash_alg *caam_hash =
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container_of(alg, struct caam_hash_alg, ahash_alg);
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struct caam_hash_ctx *ctx = crypto_tfm_ctx(tfm);
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int ret = 0;
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/*
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* Get a Job ring from Job Ring driver to ensure in-order
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* crypto request processing per tfm
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*/
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ctx->jrdev = caam_jr_alloc();
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if (IS_ERR(ctx->jrdev)) {
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pr_err("Job Ring Device allocation for transform failed\n");
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return PTR_ERR(ctx->jrdev);
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}
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/* copy descriptor header template value */
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ctx->adata.algtype = OP_TYPE_CLASS1_ALG | caam_hash->alg_type;
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crypto_ahash_set_reqsize(__crypto_ahash_cast(tfm),
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sizeof(struct caam_hash_state));
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ret = axcbc_set_sh_desc(ahash);
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return ret;
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}
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static void caam_hash_cra_exit(struct crypto_tfm *tfm)
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{
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struct caam_hash_ctx *ctx = crypto_tfm_ctx(tfm);
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@ -1817,7 +2089,11 @@ caam_hash_alloc(struct caam_hash_template *template,
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t_alg->ahash_alg.setkey = NULL;
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}
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alg->cra_module = THIS_MODULE;
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alg->cra_init = caam_hash_cra_init;
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if (strstr(alg->cra_name, "xcbc") > 0)
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alg->cra_init = caam_axcbc_cra_init;
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else
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alg->cra_init = caam_hash_cra_init;
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alg->cra_exit = caam_hash_cra_exit;
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alg->cra_ctxsize = sizeof(struct caam_hash_ctx);
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alg->cra_priority = CAAM_CRA_PRIORITY;
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@ -1649,4 +1649,8 @@
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#define ARC4_MAX_KEY_SIZE 256
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#define ARC4_MIN_KEY_SIZE 1
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#define XCBC_MAC_DIGEST_SIZE 16
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#define XCBC_MAC_BLOCK_WORDS 16
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#endif /* DESC_H */
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