387a950fec
Merge CDN_1_0_38 release to HDP API. v1_0_38 release notes: DP: Added functionality for setting own PHY register values related to voltage swing and pre-emphasis. Signed-off-by: Sandor Yu <Sandor.yu@nxp.com>
475 lines
16 KiB
C
475 lines
16 KiB
C
/******************************************************************************
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*
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* Copyright (C) 2016-2017 Cadence Design Systems, Inc.
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* All rights reserved worldwide.
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*
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* Redistribution and use in source and binary forms, with or without modification,
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* are permitted provided that the following conditions are met:
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*
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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*
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation and/or
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* other materials provided with the distribution.
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*
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* 3. Neither the name of the copyright holder nor the names of its contributors
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* may be used to endorse or promote products derived from this software without
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* specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
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* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
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* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
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* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED,
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* INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
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* IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
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* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
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* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE
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* OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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*
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* Copyright 2017-2018 NXP
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*
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******************************************************************************
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*
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* API_DPTX.h
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*
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******************************************************************************
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*/
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#ifndef _API_DPTX_H_
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#define _API_DPTX_H_
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#include "API_General.h"
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#include "API_AFE.h"
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#define MAX_NUM_OF_EVENTS 4
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/* Flags for CDN_API_DPTX_SetDbg */
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#define DPTX_DBG_SET_PWR_SKIP_SLEEP (1 << 0)
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#define DPTX_DBG_SET_ALT_CIPHER_ADDR (1 << 1)
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/**
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* \addtogroup DP_TX_API
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* \{
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*/
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typedef u8 CDN_API_PWR_MODE;
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typedef u32 CDN_EVENT;
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/**
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* reply data struct for CDN_API_DPTX_READ_EDID
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* please note, buff will point to internal api buffer, user must copy it for later use
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*/
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typedef struct {
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u8 *buff;
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u8 size;
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u8 blockNo;
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} DPTX_Read_EDID_response;
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/**
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* \brief Cadence API for DP TX to get RX EDID
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* \param [in] segment - EDID segment to read
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* \param [in] extension - EDID extension to read
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* \param [out] resp - pointer to store response
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* buffer , please note, buff will point to internal api buffer, user must copy it for later use
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* \return status
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*
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*/
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CDN_API_STATUS CDN_API_DPTX_Read_EDID(state_struct *state, u8 segment,
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u8 extension,
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DPTX_Read_EDID_response *resp);
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/**
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* \brief blocking version of #CDN_API_DPTX_Read_EDID
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*/
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CDN_API_STATUS CDN_API_DPTX_Read_EDID_blocking(state_struct *state, u8 segment,
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u8 extension,
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DPTX_Read_EDID_response *resp);
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/**
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* \brief Cadence API for DP TX to set power mode of sink
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*
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* \param [in] mode - power mode
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* \return status
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*
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*/
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CDN_API_STATUS CDN_API_DPTX_SetPowerMode(state_struct *state,
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CDN_API_PWR_MODE mode);
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/**
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* \brief blocking version of #CDN_API_DPTX_SetPowerMode
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*/
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CDN_API_STATUS CDN_API_DPTX_SetPowerMode_blocking(state_struct *state,
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CDN_API_PWR_MODE mode);
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/**
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* \brief Cadence API for DP TX to set Host capabilities
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*
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* \param [in] maxLinkRate Max link rate-> 0x06=1.62Gbps 0x0A=2.7Gbps 0x14=5.4Gbps 0x1E=8.1Gbps
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* \param [in] lanesCount_SSC bit 0-3 lanes count, bit 4 SSC
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* \param [in] maxVoltageSwing - - max supported VoltageSwing
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* \param [in] maxPreemphasis - max supported Preemphasis
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* \param [in] testPatternsSupported -which test patern supportrd by phy
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* \param [in] fastLinkTraining - is it fast link training
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* \param [in] laneMapping - line mapping for USB type C
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* \param [in] enchanced - enchanced mode
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* \return status
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*
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*/
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CDN_API_STATUS CDN_API_DPTX_SetHostCap(state_struct *state, u8 maxLinkRate,
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u8 lanesCount_SSC,
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u8 maxVoltageSwing,
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u8 maxPreemphasis,
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u8 testPatternsSupported,
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u8 fastLinkTraining,
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u8 laneMapping, u8 enchanced);
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/**
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* \brief blocking version of #CDN_API_DPTX_SetHostCap
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*/
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CDN_API_STATUS CDN_API_DPTX_SetHostCap_blocking(state_struct *state,
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u8 maxLinkRate,
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u8 lanesCount_SSC,
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u8 maxVoltageSwing,
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u8 maxPreemphasis,
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u8 testPatternsSupported,
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u8 fastLinkTraining,
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u8 laneMapping, u8 enchanced);
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/**
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* reply data struct for #CDN_API_DPTX_READ_DPCD
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*/
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typedef struct {
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/** buffer where data will be stored, will become invalid after next call to API */
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u8 *buff;
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int addr;
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int size;
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} DPTX_Read_DPCD_response;
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/**
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* \brief Cadence API for DP TX to read DPCD
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*
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* \param [in] numOfBytes - num of bytes to read
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* \param [in] addr - address to read from
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* \param [out] resp - pointer to store response
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* \return status
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*
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*/
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CDN_API_STATUS CDN_API_DPTX_Read_DPCD(state_struct *state, int numOfBytes,
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int addr, DPTX_Read_DPCD_response *resp,
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CDN_BUS_TYPE bus_type);
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/**
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* blocking version of #CDN_API_DPTX_READ_DPCD
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*/
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CDN_API_STATUS CDN_API_DPTX_Read_DPCD_blocking(state_struct *state,
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int numOfBytes, int addr,
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DPTX_Read_DPCD_response *resp,
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CDN_BUS_TYPE bus_type);
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/**
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* reply data struct for CDN_API_DPTX_WRITE_DPCD
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*/
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typedef struct {
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int addr;
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int size;
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} DPTX_Write_DPCD_response;
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/**
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* \brief Cadence API for DP TX to write DPCD
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*
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* \param [in] numOfBytes - num of bytes to write
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* \param [in] addr - address to write
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* \param [in] buff - with the data to write
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* \param [out] resp - pointer to store response
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* \return status
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*
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*/
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CDN_API_STATUS CDN_API_DPTX_Write_DPCD(state_struct *state, u32 numOfBytes,
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u32 addr, u8 *buff,
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DPTX_Write_DPCD_response *resp,
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CDN_BUS_TYPE bus_type);
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/**
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* blocking version of #CDN_API_DPTX_WRITE_DPCD
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*/
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CDN_API_STATUS CDN_API_DPTX_Write_DPCD_blocking(state_struct *state,
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u32 numOfBytes, u32 addr,
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u8 *buff,
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DPTX_Write_DPCD_response *resp,
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CDN_BUS_TYPE bus_type);
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/**
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* DPTX_Read_Register response struct
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*/
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typedef struct {
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u8 base;
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u8 regNo;
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u32 val;
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} DPTX_Read_Register_response;
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/**
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* \brief Cadence API for DP TX to read register
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*
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* \param [in] base - bank numeber (MSB of bank base address)
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* \param [in] regNo - register number
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* \param [out] resp - pointer to store response
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* \return status
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*
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* this function will return #CDN_ERR if value of base is incorrect
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*/
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CDN_API_STATUS CDN_API_DPTX_Read_Register(state_struct *state, u8 base,
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u8 regNo,
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DPTX_Read_Register_response *resp);
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/**
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* blocking version of #CDN_API_DPTX_READ_REGISTER
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*/
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CDN_API_STATUS CDN_API_DPTX_Read_Register_blocking(state_struct *state,
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u8 base, u8 regNo,
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DPTX_Read_Register_response *
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resp);
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/**
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* \brief Cadence API for DP TX write register
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*
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* \param [in] base - bank numeber (MSB of bank base address)
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* \param [in] regNo - register number
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* \param [in] val - value to write
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* \return status
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*
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* this function will return #CDN_ERR if value of base is incorrect
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*/
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CDN_API_STATUS CDN_API_DPTX_Write_Register(state_struct *state, u8 base,
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u8 regNo, u32 val);
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/**
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* blocking version of #CDN_API_DPTX_Write_Register
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*/
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CDN_API_STATUS CDN_API_DPTX_Write_Register_blocking(state_struct *state,
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u8 base, u8 regNo, u32 val);
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/**
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* \brief Cadence API for DP TX write register
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*
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* \param [in] base - bank numeber (MSB of bank base address)
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* \param [in] regNo - register number
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* \param [in] startBit - first bit to write
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* \param [in] bitsNo - number of bits to write
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* \param [in] val - value to write
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* \return status
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*
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* this function will return #CDN_ERR if value of base is incorrect
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*/
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CDN_API_STATUS CDN_API_DPTX_Write_Field(state_struct *state, u8 base, u8 regNo,
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u8 startBit, u8 bitsNo, u32 val);
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/**
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* blocking version of #CDN_API_DPTX_Write_Field
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*/
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CDN_API_STATUS CDN_API_DPTX_Write_Field_blocking(state_struct *state, u8 base,
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u8 regNo,
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u8 startBit,
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u8 bitsNo, u32 val);
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/* TODO doxygen of DPTX_CONTROL API */
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CDN_API_STATUS CDN_API_DPTX_Control(state_struct *state, u32 mode);
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/**
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* blocking version of #CDN_API_DPTX_Control
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*/
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CDN_API_STATUS CDN_API_DPTX_Control_blocking(state_struct *state, u32 mode);
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/**
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* \brief Performs Fast Link Training, using LINK_RATE_SET DPCD register.
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* \param [in] mode - 0 to stop training, 1 to start it, 2 to restart it.
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* \param [in] linkRate - Link Rate to be used for training.
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* \param [in] rateId - index of selected Link Rate in DPCd registers.
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*
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* Performs Fast Link Training, selecting Link Rate using LINK_RATE_SET DPCD
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* register, characteristic to Embedded DisplayPort (eDP) v1.4 standard.
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* If requested link rate is not supported by DPTX, function will return error
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* code CDN_ERROR_NOT_SUPPORTED, and will take no further action.
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* rateId is used to select, which Link Rate supported by sink (enumerated in
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* SUPPORTED_LINK_RATES DPCD registers) is equal to rate requested. This value
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* will be written to first 3 bits of LINK_RATE_SET DPCD registers. Allowed
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* range is 0-7. If it is not known beforehand, SUPPORTED_LINK_RATES DPCD
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* registers may be read by an upper layer, and then used to determine the
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* correct value to use.
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*/
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CDN_API_STATUS CDN_API_DPTX_EDP_Training(state_struct *state, u8 mode, ENUM_AFE_LINK_RATE linkRate, u8 rateId);
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CDN_API_STATUS CDN_API_DPTX_EDP_Training_blocking(state_struct *state, u8 mode, ENUM_AFE_LINK_RATE linkRate, u8 rateId);
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/**
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* \brief send DPX_ENABLE_EVENT command
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*/
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CDN_API_STATUS CDN_API_DPTX_EnableEvent(state_struct *state, bool hpd,
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bool training);
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/**
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* blocking version of #CDN_API_DPTX_EnableEvent
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*/
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CDN_API_STATUS CDN_API_DPTX_EnableEvent_blocking(state_struct *state, bool hpd,
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bool training);
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/**
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* \brief send DPTX_READ_EVENT_REQUEST command
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*/
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CDN_API_STATUS CDN_API_DPTX_ReadEvent(state_struct *state, u8 *LinkeventId,
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u8 *HPDevents);
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/**
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* blocking version of #CDN_API_DPTX_ReadEvent
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*/
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CDN_API_STATUS CDN_API_DPTX_ReadEvent_blocking(state_struct *state,
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u8 *LinkeventId,
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u8 *HPDevents);
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/**
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* \brief set vic mode according to vic table, the input are video parameters
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*/
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CDN_API_STATUS CDN_API_DPTX_Set_VIC(state_struct *state, struct drm_display_mode *mode,
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int bitsPerPixel,
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VIC_NUM_OF_LANES NumOfLanes,
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VIC_SYMBOL_RATE rate,
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VIC_PXL_ENCODING_FORMAT pxlencformat,
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STEREO_VIDEO_ATTR steroVidAttr,
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BT_TYPE bt_type, int TU);
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/**
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* blocking version of #CDN_API_DPTX_Set_VIC
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*/
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CDN_API_STATUS CDN_API_DPTX_Set_VIC_blocking(state_struct *state,
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struct drm_display_mode *mode,
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int bitsPerPixel,
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VIC_NUM_OF_LANES NumOfLanes,
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VIC_SYMBOL_RATE rate,
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VIC_PXL_ENCODING_FORMAT
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pxlencformat,
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STEREO_VIDEO_ATTR steroVidAttr,
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BT_TYPE bt_type, int TU);
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/**
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* \brief turn on or off the video
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*/
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CDN_API_STATUS CDN_API_DPTX_SetVideo(state_struct *state, u8 mode);
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/**
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* \brief blocking version of CDN_API_DPTX_SetVideo
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*/
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CDN_API_STATUS CDN_API_DPTX_SetVideo_blocking(state_struct *state, u8 mode);
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/**
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* \brief blocking version of #CDN_API_DPTX_SetAudio
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*/
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CDN_API_STATUS CDN_API_DPTX_SetAudio_blocking(state_struct *state, u8 mode);
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typedef struct {
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u8 rate;
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u8 lanes;
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u8 swing[3];
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u8 preemphasis[3];
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} S_LINK_STAT;
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/**
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* \brief get current link status (rate, num of lanes etc), user may read it after get link finish event
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*/
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CDN_API_STATUS CDN_API_DPTX_ReadLinkStat(state_struct *state,
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S_LINK_STAT *stat);
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/**
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* \brief blocking version of #CDN_API_DPTX_ReadLinkStat
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*/
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CDN_API_STATUS CDN_API_DPTX_ReadLinkStat_blocking(state_struct *state,
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S_LINK_STAT *stat);
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/**
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* \brief start link training
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*/
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CDN_API_STATUS CDN_API_DPTX_TrainingControl(state_struct *state, u8 val);
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/**
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* \brief blocking version of #CDN_API_DPTX_TrainingControl
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*/
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CDN_API_STATUS CDN_API_DPTX_TrainingControl_blocking(state_struct *state,
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u8 val);
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/**
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* \brief check if last auxilary transaction succedd
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*/
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CDN_API_STATUS CDN_API_DPTX_GetLastAuxStatus(state_struct *state, u8 *resp);
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/**
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* \brief blocking version of #CDN_API_DPTX_GetLastAuxStatus
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*/
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CDN_API_STATUS CDN_API_DPTX_GetLastAuxStatus_blocking(state_struct *state,
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u8 *resp);
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/**
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* \brief get current hpd status
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*/
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CDN_API_STATUS CDN_API_DPTX_GetHpdStatus(state_struct *state, u8 *resp);
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/**
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* \brief blocking version of #CDN_API_DPTX_GetHpdStatus
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*/
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CDN_API_STATUS CDN_API_DPTX_GetHpdStatus_blocking(state_struct *state,
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u8 *resp);
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/**
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* \brief force the lanes to specific swing or preemphasis, with SSc or without to pattern (0=PRBS7 or 1=D10.2) for CTS or debug phy purpose
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*/
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CDN_API_STATUS CDN_API_DPTX_ForceLanes(state_struct *state, u8 linkRate,
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u8 numOfLanes,
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u8 voltageSwing_l0,
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u8 preemphasis_l0,
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u8 voltageSwing_l1,
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u8 preemphasis_l1,
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u8 voltageSwing_l2,
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u8 preemphasis_l2,
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u8 voltageSwing_l3,
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u8 preemphasis_l3, u8 pattern, u8 ssc);
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/**
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* \brief blocking version of #CDN_API_DPTX_ForceLanes
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*/
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CDN_API_STATUS CDN_API_DPTX_ForceLanes_blocking(state_struct *state,
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u8 linkRate, u8 numOfLanes,
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u8 voltageSwing_l0,
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u8 preemphasis_l0,
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u8 voltageSwing_l1,
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u8 preemphasis_l1,
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u8 voltageSwing_l2,
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u8 preemphasis_l2,
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u8 voltageSwing_l3,
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u8 preemphasis_l3, u8 pattern,
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u8 ssc);
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/**
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* \brief Set custom PHY coefficients (values) for voltage-swing and pre-emphasis related registers.
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* \param [in] mgnfsValues Array of values to use for TX_TXCC_MGNFS_MULT_000 registers
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* \param [in] cpostValues Array of values to use for TX_TXCC_CPOST_MULT_00 registers
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*
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* Each array shall contain set of values to be used for respective PHY register
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* (if used PHY has such registers). First index represents voltage swing,
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* second - pre-emphasis.
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* For example, mgnfsValues[2][0] will be used for TX_TXCC_MGNFS_MULT_000
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* register, for voltage swing level = 2 and pre-emphasis level = 0.
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* Similarly, cpostValues[1][2] will be used for TX_TXCC_CPOST_MULT_00 register,
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* for voltage swing level = 1 and pre-emphasis level = 2.
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* Default values (one that Firmware starts with) can be acquired using
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* API_DPTX_GetDefaultCoefficients() - if applicable for given PHY.
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* Values, where sum of indexes (for voltage swing and pre-emphasis) are
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* greater than 3 are ignored, as such levels are forbidden by DP standard.
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*/
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CDN_API_STATUS CDN_API_DPTX_SetPhyCoefficients(state_struct *state,
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u16 mgnfsValues[4][4],
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u16 cpostValues[4][4]);
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/**
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* \brief blocking version of #CDN_API_DPTX_SetPhyCoefficients
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*/
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CDN_API_STATUS CDN_API_DPTX_SetPhyCoefficients_blocking(state_struct *state,
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u16 mgnfsValues[4][4],
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|
u16 cpostValues[4][4]);
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|
|
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/**
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* \brief Sets DP TX debug related features.
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|
*/
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CDN_API_STATUS CDN_API_DPTX_SetDbg(state_struct *state, u32 dbg_cfg);
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|
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/**
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* \brief blocking version of #CDN_API_DPTX_SetDbg
|
|
*/
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|
CDN_API_STATUS CDN_API_DPTX_SetDbg_blocking(state_struct *state, u32 dbg_cfg);
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#endif
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