7e5cdf9ec1
perf stat -a -e ddr0/cycles/,ddr0/read-bytes/,ddr0/write-bytes/,ddr1/cycles/,d
dr1/read-bytes/,ddr1/write-bytes/ dd if=/dev/zero of=/dev/null bs=10M count=1
1+0 records in
1+0 records out
Performance counter stats for 'system wide':
7236174 ddr0/cycles/ (99.97%)
8573 ddr0/read-bytes/ (99.99%)
163628 ddr0/write-bytes/
7256543 ddr1/cycles/ (99.99%)
9308 ddr1/read-bytes/ (100.00%)
165039 ddr1/write-bytes/
0.008990125 seconds time elapsed
Signed-off-by: Frank Li <Frank.Li@nxp.com>
Signed-off-by: Tiberiu Breana <andrei-tiberiu.breana@nxp.com>
50 lines
1.2 KiB
Plaintext
50 lines
1.2 KiB
Plaintext
#
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# Performance Monitor Drivers
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#
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menu "Performance monitor support"
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depends on PERF_EVENTS
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config ARM_PMU
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depends on ARM || ARM64
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bool "ARM PMU framework"
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default y
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help
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Say y if you want to use CPU performance monitors on ARM-based
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systems.
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config ARM_PMU_ACPI
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depends on ARM_PMU && ACPI
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def_bool y
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config QCOM_L2_PMU
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bool "Qualcomm Technologies L2-cache PMU"
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depends on ARCH_QCOM && ARM64 && ACPI
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help
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Provides support for the L2 cache performance monitor unit (PMU)
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in Qualcomm Technologies processors.
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Adds the L2 cache PMU into the perf events subsystem for
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monitoring L2 cache events.
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config QCOM_L3_PMU
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bool "Qualcomm Technologies L3-cache PMU"
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depends on ARCH_QCOM && ARM64 && ACPI
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select QCOM_IRQ_COMBINER
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help
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Provides support for the L3 cache performance monitor unit (PMU)
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in Qualcomm Technologies processors.
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Adds the L3 cache PMU into the perf events subsystem for
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monitoring L3 cache events.
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config IMX8_DDR_PERF
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tristate "Freescale i.MX8 DDR perf monitor"
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config XGENE_PMU
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depends on ARCH_XGENE
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bool "APM X-Gene SoC PMU"
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default n
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help
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Say y if you want to use APM X-Gene SoC performance monitors.
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endmenu
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