aea226305e
As A9 and M4 share many resources on i.MX6SX, especially for clk and power related resource, so we need to handle the hardware conflict between these two cores, there are two cases that we need to consider currently: 1. clk management: for every clk node, only when both A9 and M4 do NOT need it, then we can disable it from hardware; 2. power management: only when both A9 and M4 agree to enter low power mode, then system can enter it. Here we use MU and hardware SEMA4 to achieve our goal, MU is for communiation between A9 and M4, SEMA4 is to protect the shared memory. For clk management, we use shared memory to maintain the clk status for both A9 and M4 side, and this shared memory is protected by hardware SEMA4, A9 and M4 will maintain their own clk tree info in their SW environment, and get other CORE's clk tree info from shared memory to decide whether to perform a hardware setting change when they plan to. For power management, M4 is treated as a high speed device in A9 side, M4 is booting up with 227MHz by default, only when M4 freq drop to below than 24MHz, then A9 is able to enter low bus mode and low power idle mode. Everytime A9 is trying to adjust bus freq, it will request M4 to stay at wfi, and once bus freq scaling is done, A9 will send message to wake up M4 to continue, this is because M4 can NOT access DDR or other important bus during bus freq scaling. Whenever M4 wants high bus freq, it can send message to A9 to increase bus freq, All these communications are done by MU module. For further use case implementation, we can define new protocol to achieve, everytime MU receives a message, it will trigger a thread to handle this request, A9 can response according to the message. Signed-off-by: Anson Huang <b20788@freescale.com>
73 lines
1.8 KiB
C
73 lines
1.8 KiB
C
/*
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* Copyright (C) 2014 Freescale Semiconductor, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef __LINUX_IMX_SEMA4_H__
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#define __LINUX_IMX_SEMA4_H__
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/* semaphore number */
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#define MCC_SHMEM_SEMAPHORE_NUMBER (1)
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#define MCC_PRINTF_SEMAPHORE_NUMBER (2)
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#define MCC_I2C_SEMAPHORE_NUMBER (3)
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#define MCC_RESERVED1_SEMAPHORE_NUMBER (4)
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#define MCC_RESERVED2_SEMAPHORE_NUMBER (5)
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#define MCC_POWER_SHMEM_NUMBER (6)
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#define SEMA4_NUM_DEVICES 1
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#define SEMA4_NUM_GATES 16
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#define SEMA4_UNLOCK 0x00
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#define SEMA4_A9_LOCK 0x01
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#define SEMA4_GATE_MASK 0x03
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#define CORE_MUTEX_VALID (('c'<<24)|('m'<<24)|('t'<<24)|'x')
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/*
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* The enumerates
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*/
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enum {
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/* sema4 registers offset */
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SEMA4_CP0INE = 0x40,
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SEMA4_CP1INE = 0x48,
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SEMA4_CP0NTF = 0x80,
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SEMA4_CP1NTF = 0x88,
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};
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static const unsigned int idx_sema4[16] = {
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1 << 7, 1 << 6, 1 << 5, 1 << 4,
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1 << 3, 1 << 2, 1 << 1, 1 << 0,
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1 << 15, 1 << 14, 1 << 13, 1 << 12,
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1 << 11, 1 << 10, 1 << 9, 1 << 8,
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};
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struct imx_sema4_mutex {
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u32 valid;
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u32 gate_num;
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unsigned char gate_val;
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wait_queue_head_t wait_q;
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};
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struct imx_sema4_mutex_device {
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struct device *dev;
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u16 cpntf_val;
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u16 cpine_val;
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void __iomem *ioaddr; /* Mapped address */
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spinlock_t lock; /* Mutex */
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int irq;
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u16 alloced;
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struct imx_sema4_mutex *mutex_ptr[16];
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};
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struct imx_sema4_mutex *
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imx_sema4_mutex_create(u32 dev_num, u32 mutex_num);
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int imx_sema4_mutex_destroy(struct imx_sema4_mutex *mutex_ptr);
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int imx_sema4_mutex_trylock(struct imx_sema4_mutex *mutex_ptr);
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int imx_sema4_mutex_lock(struct imx_sema4_mutex *mutex_ptr);
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int imx_sema4_mutex_unlock(struct imx_sema4_mutex *mutex_ptr);
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#endif /* __LINUX_IMX_SEMA4_H__ */
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