Init ENET RGMII tx clock source, set GPR5[9] to select clock from
internal PLL_enet. And set phy VDDIO to 1.8V that get better signal
quality.
Signed-off-by: Fugang Duan <B38611@freescale.com>
(cherry picked from commit: d7a171fcf5218166f558428610ca8e9cb9f7e830)