1306 lines
33 KiB
C
1306 lines
33 KiB
C
/*
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* Copyright (C) 2016 Freescale Semiconductor, Inc.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <asm/arch/clock.h>
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#include <asm/arch/iomux.h>
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#include <asm/arch/imx-regs.h>
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#include <asm/arch/crm_regs.h>
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#include <asm/arch/mx6-pins.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/gpio.h>
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#include <asm/imx-common/iomux-v3.h>
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#include <asm/imx-common/boot_mode.h>
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#include <asm/imx-common/mxc_i2c.h>
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#include <asm/io.h>
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#include <common.h>
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#include <fsl_esdhc.h>
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#include <i2c.h>
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#include <miiphy.h>
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#include <linux/sizes.h>
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#include <mmc.h>
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#include <mxsfb.h>
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#include <netdev.h>
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#include <power/pmic.h>
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#include <power/pfuze3000_pmic.h>
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#include "../../freescale/common/pfuze.h"
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#include <usb.h>
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#include <usb/ehci-fsl.h>
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#include <asm/imx-common/video.h>
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#include <pwm.h>
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#include <nand.h>
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#ifdef CONFIG_FSL_FASTBOOT
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#include <fsl_fastboot.h>
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#ifdef CONFIG_ANDROID_RECOVERY
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#include <recovery.h>
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#endif
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#endif /*CONFIG_FSL_FASTBOOT*/
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DECLARE_GLOBAL_DATA_PTR;
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#define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
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PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
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PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
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#define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
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PAD_CTL_PUS_22K_UP | PAD_CTL_SPEED_LOW | \
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PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
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#define USDHC_DAT3_CD_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
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PAD_CTL_PUS_100K_DOWN | PAD_CTL_SPEED_LOW | \
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PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
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#define I2C_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
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PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
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PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
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PAD_CTL_ODE)
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#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \
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PAD_CTL_SPEED_HIGH | \
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PAD_CTL_DSE_48ohm | PAD_CTL_SRE_FAST)
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#define LCD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \
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PAD_CTL_PKE | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm)
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#define MDIO_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \
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PAD_CTL_DSE_48ohm | PAD_CTL_SRE_FAST | PAD_CTL_ODE)
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#define ENET_CLK_PAD_CTRL (PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
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#define ENET_RX_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
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PAD_CTL_SPEED_HIGH | PAD_CTL_SRE_FAST)
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#define GPMI_PAD_CTRL0 (PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_100K_UP)
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#define GPMI_PAD_CTRL1 (PAD_CTL_DSE_40ohm | PAD_CTL_SPEED_MED | \
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PAD_CTL_SRE_FAST)
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#define GPMI_PAD_CTRL2 (GPMI_PAD_CTRL0 | GPMI_PAD_CTRL1)
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#define WEIM_NOR_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
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PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
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PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
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#define SPI_PAD_CTRL (PAD_CTL_HYS | \
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PAD_CTL_SPEED_MED | \
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PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
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#define OTG_ID_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
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PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \
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PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
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#define IOX_SDI IMX_GPIO_NR(5, 10)
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#define IOX_STCP IMX_GPIO_NR(5, 7)
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#define IOX_SHCP IMX_GPIO_NR(5, 11)
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#define IOX_OE IMX_GPIO_NR(5, 8)
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static iomux_v3_cfg_t const iox_pads[] = {
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/* IOX_SDI */
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MX6_PAD_BOOT_MODE0__GPIO5_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL),
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/* IOX_SHCP */
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MX6_PAD_BOOT_MODE1__GPIO5_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL),
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/* IOX_STCP */
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MX6_PAD_SNVS_TAMPER7__GPIO5_IO07 | MUX_PAD_CTRL(NO_PAD_CTRL),
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/* IOX_nOE */
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MX6_PAD_SNVS_TAMPER8__GPIO5_IO08 | MUX_PAD_CTRL(NO_PAD_CTRL),
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};
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/*
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* HDMI_nRST --> Q0
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* ENET1_nRST --> Q1
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* ENET2_nRST --> Q2
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* CAN1_2_STBY --> Q3
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* BT_nPWD --> Q4
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* CSI_RST --> Q5
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* CSI_PWDN --> Q6
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* LCD_nPWREN --> Q7
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*/
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enum qn {
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HDMI_NRST,
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ENET1_NRST,
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ENET2_NRST,
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CAN1_2_STBY,
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BT_NPWD,
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CSI_RST,
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CSI_PWDN,
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LCD_NPWREN,
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};
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enum qn_func {
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qn_reset,
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qn_enable,
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qn_disable,
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};
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enum qn_level {
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qn_low = 0,
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qn_high = 1,
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};
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static enum qn_level seq[3][2] = {
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{0, 1}, {1, 1}, {0, 0}
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};
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static enum qn_func qn_output[8] = {
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qn_reset, qn_reset, qn_reset, qn_enable, qn_disable, qn_reset,
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qn_disable, qn_disable
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};
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static void iox74lv_init(void)
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{
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int i;
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gpio_direction_output(IOX_OE, 0);
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for (i = 7; i >= 0; i--) {
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gpio_direction_output(IOX_SHCP, 0);
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gpio_direction_output(IOX_SDI, seq[qn_output[i]][0]);
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udelay(500);
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gpio_direction_output(IOX_SHCP, 1);
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udelay(500);
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}
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gpio_direction_output(IOX_STCP, 0);
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udelay(500);
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/*
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* shift register will be output to pins
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*/
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gpio_direction_output(IOX_STCP, 1);
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for (i = 7; i >= 0; i--) {
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gpio_direction_output(IOX_SHCP, 0);
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gpio_direction_output(IOX_SDI, seq[qn_output[i]][1]);
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udelay(500);
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gpio_direction_output(IOX_SHCP, 1);
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udelay(500);
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}
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gpio_direction_output(IOX_STCP, 0);
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udelay(500);
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/*
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* shift register will be output to pins
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*/
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gpio_direction_output(IOX_STCP, 1);
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};
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void iox74lv_set(int index)
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{
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int i;
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for (i = 7; i >= 0; i--) {
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gpio_direction_output(IOX_SHCP, 0);
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if (i == index)
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gpio_direction_output(IOX_SDI, seq[qn_output[i]][0]);
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else
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gpio_direction_output(IOX_SDI, seq[qn_output[i]][1]);
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udelay(500);
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gpio_direction_output(IOX_SHCP, 1);
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udelay(500);
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}
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gpio_direction_output(IOX_STCP, 0);
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udelay(500);
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/*
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* shift register will be output to pins
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*/
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gpio_direction_output(IOX_STCP, 1);
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for (i = 7; i >= 0; i--) {
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gpio_direction_output(IOX_SHCP, 0);
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gpio_direction_output(IOX_SDI, seq[qn_output[i]][1]);
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udelay(500);
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gpio_direction_output(IOX_SHCP, 1);
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udelay(500);
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}
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gpio_direction_output(IOX_STCP, 0);
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udelay(500);
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/*
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* shift register will be output to pins
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*/
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gpio_direction_output(IOX_STCP, 1);
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};
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#ifdef CONFIG_SYS_I2C_MXC
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#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
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/* I2C1 for PMIC and EEPROM */
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static struct i2c_pads_info i2c_pad_info1 = {
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.scl = {
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.i2c_mode = MX6_PAD_UART4_TX_DATA__I2C1_SCL | PC,
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.gpio_mode = MX6_PAD_UART4_TX_DATA__GPIO1_IO28 | PC,
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.gp = IMX_GPIO_NR(1, 28),
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},
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.sda = {
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.i2c_mode = MX6_PAD_UART4_RX_DATA__I2C1_SDA | PC,
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.gpio_mode = MX6_PAD_UART4_RX_DATA__GPIO1_IO29 | PC,
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.gp = IMX_GPIO_NR(1, 29),
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},
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};
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#ifdef CONFIG_POWER
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#define I2C_PMIC 0
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int power_init_board(void)
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{
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if (is_mx6ull_9x9_evk()) {
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struct pmic *pfuze;
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int ret;
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unsigned int reg, rev_id;
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ret = power_pfuze3000_init(I2C_PMIC);
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if (ret)
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return ret;
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pfuze = pmic_get("PFUZE3000");
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ret = pmic_probe(pfuze);
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if (ret)
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return ret;
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pmic_reg_read(pfuze, PFUZE3000_DEVICEID, ®);
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pmic_reg_read(pfuze, PFUZE3000_REVID, &rev_id);
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printf("PMIC: PFUZE3000 DEV_ID=0x%x REV_ID=0x%x\n",
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reg, rev_id);
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/* disable Low Power Mode during standby mode */
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pmic_reg_read(pfuze, PFUZE3000_LDOGCTL, ®);
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reg |= 0x1;
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pmic_reg_write(pfuze, PFUZE3000_LDOGCTL, reg);
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/* SW1B step ramp up time from 2us to 4us/25mV */
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reg = 0x40;
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pmic_reg_write(pfuze, PFUZE3000_SW1BCONF, reg);
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/* SW1B mode to APS/PFM */
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reg = 0xc;
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pmic_reg_write(pfuze, PFUZE3000_SW1BMODE, reg);
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/* SW1B standby voltage set to 0.975V */
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reg = 0xb;
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pmic_reg_write(pfuze, PFUZE3000_SW1BSTBY, reg);
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}
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return 0;
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}
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#ifdef CONFIG_LDO_BYPASS_CHECK
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void ldo_mode_set(int ldo_bypass)
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{
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unsigned int value;
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u32 vddarm;
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struct pmic *p = pmic_get("PFUZE3000");
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if (!p) {
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printf("No PMIC found!\n");
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return;
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}
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/* switch to ldo_bypass mode */
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if (ldo_bypass) {
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prep_anatop_bypass();
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/* decrease VDDARM to 1.275V */
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pmic_reg_read(p, PFUZE3000_SW1BVOLT, &value);
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value &= ~0x1f;
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value |= PFUZE3000_SW1AB_SETP(1275);
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pmic_reg_write(p, PFUZE3000_SW1BVOLT, value);
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set_anatop_bypass(1);
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vddarm = PFUZE3000_SW1AB_SETP(1175);
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pmic_reg_read(p, PFUZE3000_SW1BVOLT, &value);
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value &= ~0x1f;
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value |= vddarm;
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pmic_reg_write(p, PFUZE3000_SW1BVOLT, value);
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finish_anatop_bypass();
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printf("switch to ldo_bypass mode!\n");
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}
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}
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#endif
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#endif
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#endif
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int dram_init(void)
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{
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gd->ram_size = imx_ddr_size();
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return 0;
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}
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static iomux_v3_cfg_t const uart1_pads[] = {
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MX6_PAD_UART1_TX_DATA__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
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MX6_PAD_UART1_RX_DATA__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
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};
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/* MicroSD */
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static iomux_v3_cfg_t const usdhc1_pads[] = {
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MX6_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_SD1_DATA0__USDHC1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_SD1_DATA1__USDHC1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_SD1_DATA2__USDHC1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_SD1_DATA3__USDHC1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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/* CD */
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MX6_PAD_UART1_RTS_B__GPIO1_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL),
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};
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/*
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* i2S-6ULL has eMMC variant, it conflict with NAND signal.
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*/
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#if defined(CONFIG_SYS_BOOT_EMMC)
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static iomux_v3_cfg_t const usdhc2_emmc_pads[] = {
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MX6_PAD_NAND_RE_B__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_NAND_WE_B__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_NAND_DATA00__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_NAND_DATA01__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_NAND_DATA02__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_NAND_DATA03__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_NAND_DATA04__USDHC2_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_NAND_DATA05__USDHC2_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_NAND_DATA06__USDHC2_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_NAND_DATA07__USDHC2_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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/* RST_B */
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MX6_PAD_NAND_ALE__GPIO4_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL),
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};
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#endif
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static void setup_iomux_uart(void)
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{
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imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
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}
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#ifdef CONFIG_FSL_QSPI
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#define QSPI_PAD_CTRL1 \
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(PAD_CTL_SRE_FAST | PAD_CTL_SPEED_MED | \
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PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_47K_UP | PAD_CTL_DSE_120ohm)
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static iomux_v3_cfg_t const quadspi_pads[] = {
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MX6_PAD_NAND_WP_B__QSPI_A_SCLK | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
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MX6_PAD_NAND_READY_B__QSPI_A_DATA00 | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
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MX6_PAD_NAND_CE0_B__QSPI_A_DATA01 | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
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MX6_PAD_NAND_CE1_B__QSPI_A_DATA02 | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
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MX6_PAD_NAND_CLE__QSPI_A_DATA03 | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
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MX6_PAD_NAND_DQS__QSPI_A_SS0_B | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
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};
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static int board_qspi_init(void)
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{
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/* Set the iomux */
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imx_iomux_v3_setup_multiple_pads(quadspi_pads,
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ARRAY_SIZE(quadspi_pads));
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/* Set the clock */
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enable_qspi_clk(0);
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return 0;
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}
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#endif
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#ifdef CONFIG_FSL_ESDHC
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static struct fsl_esdhc_cfg usdhc_cfg[] = {
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{USDHC1_BASE_ADDR, 0, 4},
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#if defined(CONFIG_SYS_BOOT_EMMC)
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{USDHC2_BASE_ADDR, 0, 8},
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#endif
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};
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#define USDHC1_CD_GPIO IMX_GPIO_NR(1, 19)
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#define USDHC1_PWR_GPIO IMX_GPIO_NR(1, 9)
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#define USDHC2_CD_GPIO IMX_GPIO_NR(4, 5)
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#define USDHC2_PWR_GPIO IMX_GPIO_NR(4, 10)
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int board_mmc_get_env_dev(int devno)
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{
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if (devno == 1 && mx6_esdhc_fused(USDHC1_BASE_ADDR))
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devno = 0;
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return devno;
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}
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int mmc_map_to_kernel_blk(int devno)
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{
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if (devno == 0 && mx6_esdhc_fused(USDHC1_BASE_ADDR))
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devno = 1;
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return devno;
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}
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int board_mmc_getcd(struct mmc *mmc)
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{
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struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
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int ret = 0;
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switch (cfg->esdhc_base) {
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case USDHC1_BASE_ADDR:
|
|
ret = !gpio_get_value(USDHC1_CD_GPIO);
|
|
ret = 1;
|
|
break;
|
|
case USDHC2_BASE_ADDR:
|
|
#if defined(CONFIG_SYS_BOOT_EMMC)
|
|
ret = 1;
|
|
#endif
|
|
break;
|
|
}
|
|
|
|
return ret;
|
|
}
|
|
|
|
int board_has_emmc(void)
|
|
{
|
|
#if defined(CONFIG_SYS_BOOT_EMMC)
|
|
return 1;
|
|
#else
|
|
return 0;
|
|
#endif
|
|
}
|
|
|
|
static int check_mmc_autodetect(void)
|
|
{
|
|
char *autodetect_str = getenv("mmcautodetect");
|
|
|
|
if ((autodetect_str != NULL) &&
|
|
(strcmp(autodetect_str, "yes") == 0)) {
|
|
return 1;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
void board_late_mmc_env_init(void)
|
|
{
|
|
char cmd[32];
|
|
char mmcblk[32];
|
|
u32 dev_no = mmc_get_env_dev();
|
|
|
|
if (!check_mmc_autodetect())
|
|
return;
|
|
setenv_ulong("mmcdev", dev_no);
|
|
|
|
sprintf(cmd, "mmc dev %d", dev_no);
|
|
run_command(cmd, 0);
|
|
}
|
|
int board_mmc_init(bd_t *bis)
|
|
{
|
|
#ifdef CONFIG_SPL_BUILD
|
|
#if defined(CONFIG_SYS_BOOT_EMMC)
|
|
imx_iomux_v3_setup_multiple_pads(usdhc2_emmc_pads,
|
|
ARRAY_SIZE(usdhc2_emmc_pads));
|
|
#endif
|
|
usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
|
|
return fsl_esdhc_initialize(bis, &usdhc_cfg[1]);
|
|
#else
|
|
int i, ret;
|
|
|
|
/*
|
|
* According to the board_mmc_init() the following map is done:
|
|
* (U-Boot device node) (Physical Port)
|
|
* mmc0 USDHC1
|
|
* mmc1 USDHC2
|
|
*/
|
|
for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
|
|
switch (i) {
|
|
case 0:
|
|
imx_iomux_v3_setup_multiple_pads(
|
|
usdhc1_pads, ARRAY_SIZE(usdhc1_pads));
|
|
gpio_direction_input(USDHC1_CD_GPIO);
|
|
usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
|
|
|
|
break;
|
|
case 1:
|
|
#if defined(CONFIG_SYS_BOOT_EMMC)
|
|
imx_iomux_v3_setup_multiple_pads(
|
|
usdhc2_emmc_pads, ARRAY_SIZE(usdhc2_emmc_pads));
|
|
#endif
|
|
/*
|
|
gpio_direction_output(USDHC2_PWR_GPIO, 0);
|
|
udelay(500);
|
|
gpio_direction_output(USDHC2_PWR_GPIO, 1);
|
|
*/
|
|
usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
|
|
break;
|
|
default:
|
|
printf("Warning: you configured more USDHC controllers (%d) than supported by the board\n", i + 1);
|
|
return -EINVAL;
|
|
}
|
|
|
|
ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
|
|
if (ret) {
|
|
printf("Warning: failed to initialize mmc dev %d\n", i);
|
|
}
|
|
}
|
|
#endif
|
|
return 0;
|
|
}
|
|
#endif
|
|
|
|
#ifdef CONFIG_USB_EHCI_MX6
|
|
#define USB_OTHERREGS_OFFSET 0x800
|
|
#define UCTRL_PWR_POL (1 << 9)
|
|
|
|
static iomux_v3_cfg_t const usb_otg_pads[] = {
|
|
MX6_PAD_GPIO1_IO00__ANATOP_OTG1_ID | MUX_PAD_CTRL(OTG_ID_PAD_CTRL),
|
|
};
|
|
|
|
/* At default the 3v3 enables the MIC2026 for VBUS power */
|
|
static void setup_usb(void)
|
|
{
|
|
imx_iomux_v3_setup_multiple_pads(usb_otg_pads,
|
|
ARRAY_SIZE(usb_otg_pads));
|
|
}
|
|
|
|
int board_usb_phy_mode(int port)
|
|
{
|
|
if (port == 1)
|
|
return USB_INIT_HOST;
|
|
else
|
|
return usb_phy_mode(port);
|
|
}
|
|
|
|
int board_ehci_hcd_init(int port)
|
|
{
|
|
u32 *usbnc_usb_ctrl;
|
|
|
|
if (port > 1)
|
|
return -EINVAL;
|
|
|
|
usbnc_usb_ctrl = (u32 *)(USB_BASE_ADDR + USB_OTHERREGS_OFFSET +
|
|
port * 4);
|
|
|
|
/* Set Power polarity */
|
|
setbits_le32(usbnc_usb_ctrl, UCTRL_PWR_POL);
|
|
|
|
return 0;
|
|
}
|
|
#endif
|
|
|
|
#ifdef CONFIG_NAND_MXS
|
|
static iomux_v3_cfg_t const nand_pads[] = {
|
|
MX6_PAD_NAND_DATA00__RAWNAND_DATA00 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
|
|
MX6_PAD_NAND_DATA01__RAWNAND_DATA01 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
|
|
MX6_PAD_NAND_DATA02__RAWNAND_DATA02 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
|
|
MX6_PAD_NAND_DATA03__RAWNAND_DATA03 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
|
|
MX6_PAD_NAND_DATA04__RAWNAND_DATA04 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
|
|
MX6_PAD_NAND_DATA05__RAWNAND_DATA05 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
|
|
MX6_PAD_NAND_DATA06__RAWNAND_DATA06 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
|
|
MX6_PAD_NAND_DATA07__RAWNAND_DATA07 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
|
|
MX6_PAD_NAND_CLE__RAWNAND_CLE | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
|
|
MX6_PAD_NAND_ALE__RAWNAND_ALE | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
|
|
MX6_PAD_NAND_CE0_B__RAWNAND_CE0_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
|
|
MX6_PAD_NAND_RE_B__RAWNAND_RE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
|
|
MX6_PAD_NAND_WE_B__RAWNAND_WE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
|
|
MX6_PAD_NAND_WP_B__RAWNAND_WP_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
|
|
MX6_PAD_NAND_READY_B__RAWNAND_READY_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
|
|
MX6_PAD_NAND_DQS__RAWNAND_DQS | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
|
|
};
|
|
|
|
static void setup_gpmi_nand(void)
|
|
{
|
|
struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
|
|
|
|
/* config gpmi nand iomux */
|
|
imx_iomux_v3_setup_multiple_pads(nand_pads, ARRAY_SIZE(nand_pads));
|
|
|
|
setup_gpmi_io_clk((3 << MXC_CCM_CSCDR1_BCH_PODF_OFFSET) |
|
|
(3 << MXC_CCM_CSCDR1_GPMI_PODF_OFFSET));
|
|
|
|
/* enable apbh clock gating */
|
|
setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK);
|
|
}
|
|
#endif
|
|
|
|
#ifdef CONFIG_FEC_MXC
|
|
/*
|
|
* pin conflicts for fec1 and fec2, GPIO1_IO06 and GPIO1_IO07 can only
|
|
* be used for ENET1 or ENET2, cannot be used for both.
|
|
*/
|
|
static iomux_v3_cfg_t const fec1_pads[] = {
|
|
MX6_PAD_GPIO1_IO06__ENET1_MDIO | MUX_PAD_CTRL(MDIO_PAD_CTRL),
|
|
MX6_PAD_GPIO1_IO07__ENET1_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
|
|
MX6_PAD_ENET1_TX_DATA0__ENET1_TDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL),
|
|
MX6_PAD_ENET1_TX_DATA1__ENET1_TDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL),
|
|
MX6_PAD_ENET1_TX_EN__ENET1_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
|
|
MX6_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 | MUX_PAD_CTRL(ENET_CLK_PAD_CTRL),
|
|
MX6_PAD_ENET1_RX_DATA0__ENET1_RDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL),
|
|
MX6_PAD_ENET1_RX_DATA1__ENET1_RDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL),
|
|
MX6_PAD_ENET1_RX_ER__ENET1_RX_ER | MUX_PAD_CTRL(ENET_PAD_CTRL),
|
|
MX6_PAD_ENET1_RX_EN__ENET1_RX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
|
|
|
|
/* PHY Reset */
|
|
MX6_PAD_SNVS_TAMPER6__GPIO5_IO06 | MUX_PAD_CTRL(NO_PAD_CTRL),
|
|
};
|
|
|
|
static iomux_v3_cfg_t const fec2_pads[] = {
|
|
MX6_PAD_GPIO1_IO06__ENET2_MDIO | MUX_PAD_CTRL(MDIO_PAD_CTRL),
|
|
MX6_PAD_GPIO1_IO07__ENET2_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
|
|
|
|
MX6_PAD_ENET2_TX_DATA0__ENET2_TDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL),
|
|
MX6_PAD_ENET2_TX_DATA1__ENET2_TDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL),
|
|
MX6_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 | MUX_PAD_CTRL(ENET_CLK_PAD_CTRL),
|
|
MX6_PAD_ENET2_TX_EN__ENET2_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
|
|
|
|
MX6_PAD_ENET2_RX_DATA0__ENET2_RDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL),
|
|
MX6_PAD_ENET2_RX_DATA1__ENET2_RDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL),
|
|
MX6_PAD_ENET2_RX_EN__ENET2_RX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
|
|
MX6_PAD_ENET2_RX_ER__ENET2_RX_ER | MUX_PAD_CTRL(ENET_PAD_CTRL),
|
|
};
|
|
|
|
static void setup_iomux_fec(int fec_id)
|
|
{
|
|
if (fec_id == 0){
|
|
imx_iomux_v3_setup_multiple_pads(fec1_pads,
|
|
ARRAY_SIZE(fec1_pads));
|
|
|
|
/* Reset the PHY */
|
|
gpio_direction_output(IMX_GPIO_NR(5, 6) , 0);
|
|
udelay(100);
|
|
gpio_direction_output(IMX_GPIO_NR(5, 6) , 1);
|
|
}else
|
|
imx_iomux_v3_setup_multiple_pads(fec2_pads,
|
|
ARRAY_SIZE(fec2_pads));
|
|
}
|
|
|
|
int board_eth_init(bd_t *bis)
|
|
{
|
|
setup_iomux_fec(CONFIG_FEC_ENET_DEV);
|
|
|
|
|
|
return fecmxc_initialize_multi(bis, CONFIG_FEC_ENET_DEV,
|
|
CONFIG_FEC_MXC_PHYADDR, IMX_FEC_BASE);
|
|
}
|
|
|
|
static int setup_fec(int fec_id)
|
|
{
|
|
struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
|
|
int ret;
|
|
|
|
if (fec_id == 0) {
|
|
/*
|
|
* Use 50M anatop loopback REF_CLK1 for ENET1,
|
|
* clear gpr1[13], set gpr1[17].
|
|
*/
|
|
clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC1_MASK,
|
|
IOMUX_GPR1_FEC1_CLOCK_MUX1_SEL_MASK);
|
|
} else {
|
|
/*
|
|
* Use 50M anatop loopback REF_CLK2 for ENET2,
|
|
* clear gpr1[14], set gpr1[18].
|
|
*/
|
|
clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC2_MASK,
|
|
IOMUX_GPR1_FEC2_CLOCK_MUX1_SEL_MASK);
|
|
}
|
|
|
|
ret = enable_fec_anatop_clock(fec_id, ENET_50MHZ);
|
|
if (ret)
|
|
return ret;
|
|
|
|
enable_enet_clk(1);
|
|
|
|
return 0;
|
|
}
|
|
|
|
int board_phy_config(struct phy_device *phydev)
|
|
{
|
|
if (phydev->drv->config)
|
|
phydev->drv->config(phydev);
|
|
|
|
return 0;
|
|
}
|
|
#endif
|
|
|
|
#ifdef CONFIG_VIDEO_MXS
|
|
#ifdef CONFIG_IMX6_LCD_DAT16
|
|
static iomux_v3_cfg_t const lcd_pads_16bits[] = {
|
|
MX6_PAD_LCD_CLK__LCDIF_CLK | MUX_PAD_CTRL(LCD_PAD_CTRL),
|
|
MX6_PAD_LCD_ENABLE__LCDIF_ENABLE | MUX_PAD_CTRL(LCD_PAD_CTRL),
|
|
MX6_PAD_LCD_HSYNC__LCDIF_HSYNC | MUX_PAD_CTRL(LCD_PAD_CTRL),
|
|
MX6_PAD_LCD_VSYNC__LCDIF_VSYNC | MUX_PAD_CTRL(LCD_PAD_CTRL),
|
|
MX6_PAD_LCD_DATA00__LCDIF_DATA00 | MUX_PAD_CTRL(LCD_PAD_CTRL),
|
|
MX6_PAD_LCD_DATA01__LCDIF_DATA01 | MUX_PAD_CTRL(LCD_PAD_CTRL),
|
|
MX6_PAD_LCD_DATA02__LCDIF_DATA02 | MUX_PAD_CTRL(LCD_PAD_CTRL),
|
|
MX6_PAD_LCD_DATA03__LCDIF_DATA03 | MUX_PAD_CTRL(LCD_PAD_CTRL),
|
|
MX6_PAD_LCD_DATA04__LCDIF_DATA04 | MUX_PAD_CTRL(LCD_PAD_CTRL),
|
|
MX6_PAD_LCD_DATA05__LCDIF_DATA05 | MUX_PAD_CTRL(LCD_PAD_CTRL),
|
|
MX6_PAD_LCD_DATA06__LCDIF_DATA06 | MUX_PAD_CTRL(LCD_PAD_CTRL),
|
|
MX6_PAD_LCD_DATA07__LCDIF_DATA07 | MUX_PAD_CTRL(LCD_PAD_CTRL),
|
|
MX6_PAD_LCD_DATA08__LCDIF_DATA08 | MUX_PAD_CTRL(LCD_PAD_CTRL),
|
|
MX6_PAD_LCD_DATA09__LCDIF_DATA09 | MUX_PAD_CTRL(LCD_PAD_CTRL),
|
|
MX6_PAD_LCD_DATA10__LCDIF_DATA10 | MUX_PAD_CTRL(LCD_PAD_CTRL),
|
|
MX6_PAD_LCD_DATA11__LCDIF_DATA11 | MUX_PAD_CTRL(LCD_PAD_CTRL),
|
|
MX6_PAD_LCD_DATA12__LCDIF_DATA12 | MUX_PAD_CTRL(LCD_PAD_CTRL),
|
|
MX6_PAD_LCD_DATA13__LCDIF_DATA13 | MUX_PAD_CTRL(LCD_PAD_CTRL),
|
|
MX6_PAD_LCD_DATA14__LCDIF_DATA14 | MUX_PAD_CTRL(LCD_PAD_CTRL),
|
|
MX6_PAD_LCD_DATA15__LCDIF_DATA15 | MUX_PAD_CTRL(LCD_PAD_CTRL),
|
|
|
|
/* LCD_RST */
|
|
MX6_PAD_SNVS_TAMPER9__GPIO5_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL),
|
|
|
|
/* Use GPIO for Brightness adjustment, duty cycle = period. */
|
|
MX6_PAD_GPIO1_IO08__PWM1_OUT | MUX_PAD_CTRL(NO_PAD_CTRL),
|
|
};
|
|
#endif
|
|
|
|
#ifdef CONFIG_IMX6_LCD_DAT24
|
|
static iomux_v3_cfg_t const lcd_pads_24bits[] = {
|
|
MX6_PAD_LCD_CLK__LCDIF_CLK | MUX_PAD_CTRL(LCD_PAD_CTRL),
|
|
MX6_PAD_LCD_ENABLE__LCDIF_ENABLE | MUX_PAD_CTRL(LCD_PAD_CTRL),
|
|
MX6_PAD_LCD_HSYNC__LCDIF_HSYNC | MUX_PAD_CTRL(LCD_PAD_CTRL),
|
|
MX6_PAD_LCD_VSYNC__LCDIF_VSYNC | MUX_PAD_CTRL(LCD_PAD_CTRL),
|
|
MX6_PAD_LCD_DATA00__LCDIF_DATA00 | MUX_PAD_CTRL(LCD_PAD_CTRL),
|
|
MX6_PAD_LCD_DATA01__LCDIF_DATA01 | MUX_PAD_CTRL(LCD_PAD_CTRL),
|
|
MX6_PAD_LCD_DATA02__LCDIF_DATA02 | MUX_PAD_CTRL(LCD_PAD_CTRL),
|
|
MX6_PAD_LCD_DATA03__LCDIF_DATA03 | MUX_PAD_CTRL(LCD_PAD_CTRL),
|
|
MX6_PAD_LCD_DATA04__LCDIF_DATA04 | MUX_PAD_CTRL(LCD_PAD_CTRL),
|
|
MX6_PAD_LCD_DATA05__LCDIF_DATA05 | MUX_PAD_CTRL(LCD_PAD_CTRL),
|
|
MX6_PAD_LCD_DATA06__LCDIF_DATA06 | MUX_PAD_CTRL(LCD_PAD_CTRL),
|
|
MX6_PAD_LCD_DATA07__LCDIF_DATA07 | MUX_PAD_CTRL(LCD_PAD_CTRL),
|
|
MX6_PAD_LCD_DATA08__LCDIF_DATA08 | MUX_PAD_CTRL(LCD_PAD_CTRL),
|
|
MX6_PAD_LCD_DATA09__LCDIF_DATA09 | MUX_PAD_CTRL(LCD_PAD_CTRL),
|
|
MX6_PAD_LCD_DATA10__LCDIF_DATA10 | MUX_PAD_CTRL(LCD_PAD_CTRL),
|
|
MX6_PAD_LCD_DATA11__LCDIF_DATA11 | MUX_PAD_CTRL(LCD_PAD_CTRL),
|
|
MX6_PAD_LCD_DATA12__LCDIF_DATA12 | MUX_PAD_CTRL(LCD_PAD_CTRL),
|
|
MX6_PAD_LCD_DATA13__LCDIF_DATA13 | MUX_PAD_CTRL(LCD_PAD_CTRL),
|
|
MX6_PAD_LCD_DATA14__LCDIF_DATA14 | MUX_PAD_CTRL(LCD_PAD_CTRL),
|
|
MX6_PAD_LCD_DATA15__LCDIF_DATA15 | MUX_PAD_CTRL(LCD_PAD_CTRL),
|
|
MX6_PAD_LCD_DATA16__LCDIF_DATA16 | MUX_PAD_CTRL(LCD_PAD_CTRL),
|
|
MX6_PAD_LCD_DATA17__LCDIF_DATA17 | MUX_PAD_CTRL(LCD_PAD_CTRL),
|
|
MX6_PAD_LCD_DATA18__LCDIF_DATA18 | MUX_PAD_CTRL(LCD_PAD_CTRL),
|
|
MX6_PAD_LCD_DATA19__LCDIF_DATA19 | MUX_PAD_CTRL(LCD_PAD_CTRL),
|
|
MX6_PAD_LCD_DATA20__LCDIF_DATA20 | MUX_PAD_CTRL(LCD_PAD_CTRL),
|
|
MX6_PAD_LCD_DATA21__LCDIF_DATA21 | MUX_PAD_CTRL(LCD_PAD_CTRL),
|
|
MX6_PAD_LCD_DATA22__LCDIF_DATA22 | MUX_PAD_CTRL(LCD_PAD_CTRL),
|
|
MX6_PAD_LCD_DATA23__LCDIF_DATA23 | MUX_PAD_CTRL(LCD_PAD_CTRL),
|
|
|
|
/* LCD_RST */
|
|
MX6_PAD_SNVS_TAMPER9__GPIO5_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL),
|
|
|
|
/* Use GPIO for Brightness adjustment, duty cycle = period. */
|
|
MX6_PAD_GPIO1_IO08__GPIO1_IO08 | MUX_PAD_CTRL(NO_PAD_CTRL),
|
|
};
|
|
#endif
|
|
|
|
void do_enable_parallel_lcd(struct display_info_t const *dev)
|
|
{
|
|
enable_lcdif_clock(dev->bus);
|
|
#ifdef CONFIG_IMX6_LCD_DAT16
|
|
imx_iomux_v3_setup_multiple_pads(lcd_pads_16bits, ARRAY_SIZE(lcd_pads_16bits));
|
|
#endif
|
|
#ifdef CONFIG_IMX6_LCD_DAT24
|
|
imx_iomux_v3_setup_multiple_pads(lcd_pads_24bits, ARRAY_SIZE(lcd_pads_24bits));
|
|
#endif
|
|
/* Reset the LCD */
|
|
gpio_direction_output(IMX_GPIO_NR(5, 9) , 0);
|
|
udelay(500);
|
|
gpio_direction_output(IMX_GPIO_NR(5, 9) , 1);
|
|
|
|
/* Set Brightness to high */
|
|
#ifdef CONFIG_PWM_IMX
|
|
pwm_init(0, 0, 0);
|
|
pwm_config(0, 625000, 1250000);
|
|
pwm_enable(0);
|
|
#else
|
|
gpio_direction_output(IMX_GPIO_NR(1, 8) , 1);
|
|
#endif
|
|
}
|
|
|
|
struct display_info_t const displays[] = {{
|
|
.bus = MX6UL_LCDIF1_BASE_ADDR,
|
|
.addr = 0,
|
|
.pixfmt = 16,
|
|
.detect = NULL,
|
|
.enable = do_enable_parallel_lcd,
|
|
.mode = {
|
|
.name = "TFT43AB",
|
|
.xres = 480,
|
|
.yres = 272,
|
|
.pixclock = 108695,
|
|
.left_margin = 8,
|
|
.right_margin = 4,
|
|
.upper_margin = 2,
|
|
.lower_margin = 4,
|
|
.hsync_len = 41,
|
|
.vsync_len = 10,
|
|
.sync = 0,
|
|
.vmode = FB_VMODE_NONINTERLACED
|
|
} } };
|
|
size_t display_count = ARRAY_SIZE(displays);
|
|
#endif
|
|
|
|
#ifdef CONFIG_TARGET_I2SOM_IMX6ULL_14X14
|
|
|
|
static iomux_v3_cfg_t const wifi_pads[] = {
|
|
MX6_PAD_CSI_DATA01__GPIO4_IO22 | MUX_PAD_CTRL(NO_PAD_CTRL),
|
|
MX6_PAD_CSI_DATA03__GPIO4_IO24 | MUX_PAD_CTRL(NO_PAD_CTRL),
|
|
};
|
|
|
|
void hw_watchdog_reset(void)
|
|
{
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
#ifdef CONFIG_TARGET_I2SOM_GW102
|
|
|
|
static iomux_v3_cfg_t const gw102_wifi_pads[] = {
|
|
MX6_PAD_SNVS_TAMPER7__GPIO5_IO07 | MUX_PAD_CTRL(NO_PAD_CTRL),
|
|
};
|
|
|
|
static iomux_v3_cfg_t const wdt_pads[] = {
|
|
// WDI
|
|
MX6_PAD_SNVS_TAMPER1__GPIO5_IO01 | MUX_PAD_CTRL(NO_PAD_CTRL),
|
|
// WD_EN
|
|
MX6_PAD_CSI_DATA03__GPIO4_IO24 | MUX_PAD_CTRL(NO_PAD_CTRL),
|
|
};
|
|
|
|
void hw_watchdog_reset(void)
|
|
{
|
|
gpio_direction_output(IMX_GPIO_NR(5,1), 0);
|
|
|
|
gpio_direction_output(IMX_GPIO_NR(5,1), 1);
|
|
}
|
|
|
|
void board_gw102(void)
|
|
{
|
|
/* WiFi WIFI_PWR_EN, active High */
|
|
imx_iomux_v3_setup_multiple_pads(gw102_wifi_pads, ARRAY_SIZE(gw102_wifi_pads));
|
|
gpio_direction_output(IMX_GPIO_NR(5, 7) , 1);
|
|
|
|
// init watchdog pins
|
|
imx_iomux_v3_setup_multiple_pads(wdt_pads, ARRAY_SIZE(wdt_pads));
|
|
// WD_EN active low
|
|
gpio_direction_output(IMX_GPIO_NR(4,24), 0);
|
|
}
|
|
#endif
|
|
|
|
int board_early_init_f(void)
|
|
{
|
|
setup_iomux_uart();
|
|
|
|
return 0;
|
|
}
|
|
|
|
int board_init(void)
|
|
{
|
|
/* Address of boot parameters */
|
|
gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
|
|
#ifdef CONFIG_TARGET_I2SOM_IMX6ULL_14X14
|
|
/* WiFi WL_EN, active High */
|
|
imx_iomux_v3_setup_multiple_pads(wifi_pads, ARRAY_SIZE(wifi_pads));
|
|
gpio_direction_output(IMX_GPIO_NR(4, 22) , 1);
|
|
|
|
/* WiFi PWR_EN, active Low */
|
|
gpio_direction_output(IMX_GPIO_NR(4, 24) , 0);
|
|
#endif
|
|
|
|
#ifdef CONFIG_TARGET_I2SOM_GW102
|
|
board_gw102();
|
|
#endif
|
|
|
|
#ifdef CONFIG_SYS_I2C_MXC
|
|
setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
|
|
#endif
|
|
|
|
#ifdef CONFIG_FEC_MXC
|
|
setup_fec(CONFIG_FEC_ENET_DEV);
|
|
#endif
|
|
|
|
#ifdef CONFIG_USB_EHCI_MX6
|
|
setup_usb();
|
|
#endif
|
|
|
|
#ifdef CONFIG_FSL_QSPI
|
|
board_qspi_init();
|
|
#endif
|
|
|
|
#ifdef CONFIG_NAND_MXS
|
|
setup_gpmi_nand();
|
|
#endif
|
|
|
|
return 0;
|
|
}
|
|
|
|
#ifdef CONFIG_CMD_BMODE
|
|
static const struct boot_mode board_boot_modes[] = {
|
|
/* 4 bit bus width */
|
|
{"sd1", MAKE_CFGVAL(0x42, 0x20, 0x00, 0x00)},
|
|
{"sd2", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
|
|
{"qspi1", MAKE_CFGVAL(0x10, 0x00, 0x00, 0x00)},
|
|
{NULL, 0},
|
|
};
|
|
#endif
|
|
|
|
#ifdef CONFIG_SYS_BOOT_NAND
|
|
void create_partition_table(void)
|
|
{
|
|
struct mtd_info *nand = &nand_info[0];
|
|
uint32_t nand_size_mb = nand->size / SZ_1M;
|
|
|
|
switch (nand_size_mb) {
|
|
case 512:
|
|
setenv("mtdparts", MTDPARTS_512MB);
|
|
break;
|
|
case 256:
|
|
default:
|
|
setenv("mtdparts", MTDPARTS_256MB);
|
|
break;
|
|
}
|
|
}
|
|
#endif
|
|
|
|
#ifdef CONFIG_SYS_BOOT_EMMC
|
|
void generate_partition_table(void)
|
|
{
|
|
struct mmc *mmc = find_mmc_device(1);
|
|
unsigned int capacity_gb = 0;
|
|
#if 0
|
|
/*
|
|
* Todo: will use random uuid for gpt
|
|
*/
|
|
if(!getenv("uuid_disk"))
|
|
run_command("uuid uuid_disk", 0);
|
|
if(!getenv("part1_uuid"))
|
|
run_command("uuid part1_uuid", 0);
|
|
if(!getenv("part2_uuid"))
|
|
run_command("uuid part2_uuid", 0);
|
|
if(!getenv("part3_uuid"))
|
|
run_command("uuid part3_uuid", 0);
|
|
if(!getenv("part4_uuid"))
|
|
run_command("uuid part4_uuid", 0);
|
|
if(!getenv("part5_uuid"))
|
|
run_command("uuid part5_uuid", 0);
|
|
if(!getenv("part6_uuid"))
|
|
run_command("uuid part6_uuid", 0);
|
|
if(!getenv("part7_uuid"))
|
|
run_command("uuid part7_uuid", 0);
|
|
#endif
|
|
/* Retrieve eMMC size in GiB */
|
|
if (mmc)
|
|
capacity_gb = mmc->capacity / SZ_1G;
|
|
|
|
/* eMMC capacity is not exact, so asume 8GB if larger than 7GB */
|
|
if (capacity_gb >= 7)
|
|
setenv("parts_linux", LINUX_8GB_PARTITION_TABLE);
|
|
else
|
|
setenv("parts_linux", LINUX_4GB_PARTITION_TABLE);
|
|
}
|
|
#endif
|
|
|
|
int board_late_init(void)
|
|
{
|
|
char* parttable;
|
|
|
|
#ifdef CONFIG_CMD_BMODE
|
|
add_board_boot_modes(board_boot_modes);
|
|
#endif
|
|
|
|
#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
|
|
#ifdef CONFIG_SYS_BOOT_NAND
|
|
setenv("board_name", "I2S-6ULL-NAND");
|
|
create_partition_table();
|
|
#elif defined(CONFIG_SYS_BOOT_QSPI)
|
|
setenv("board_name", "I2S-6ULL-QSPI");
|
|
#else
|
|
setenv("board_name", "I2S-6ULL-eMMC");
|
|
#endif
|
|
|
|
if (is_mx6ull_9x9_evk())
|
|
setenv("board_rev", "9X9");
|
|
else
|
|
setenv("board_rev", "14X14");
|
|
#endif
|
|
|
|
#ifdef CONFIG_ENV_IS_IN_MMC
|
|
board_late_mmc_env_init();
|
|
#endif
|
|
|
|
set_wdog_reset((struct wdog_regs *)WDOG1_BASE_ADDR);
|
|
|
|
#ifdef CONFIG_SYS_BOOT_EMMC
|
|
/*
|
|
* If there is no defined partition table generate one dynamically
|
|
* basing on the available eMMC size.
|
|
*/
|
|
parttable = getenv("parts_linux");
|
|
if (!parttable)
|
|
generate_partition_table();
|
|
#endif
|
|
return 0;
|
|
}
|
|
|
|
int checkboard(void)
|
|
{
|
|
if (is_mx6ull_9x9_evk())
|
|
puts("Board: MX6ULL 9x9 EVK\n");
|
|
else{
|
|
puts("SOM: i2S-6ULY2 14x14\n");
|
|
puts("Board: i2C-6ULX-B\n");
|
|
printf("Boot device: %s\n", get_boot_device_name());
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
#ifdef CONFIG_FSL_FASTBOOT
|
|
void board_fastboot_setup(void)
|
|
{
|
|
switch (get_boot_device()) {
|
|
#if defined(CONFIG_FASTBOOT_STORAGE_MMC)
|
|
case SD1_BOOT:
|
|
case MMC1_BOOT:
|
|
if (!getenv("fastboot_dev"))
|
|
setenv("fastboot_dev", "mmc0");
|
|
if (!getenv("bootcmd"))
|
|
setenv("bootcmd", "boota mmc0");
|
|
break;
|
|
case SD2_BOOT:
|
|
case MMC2_BOOT:
|
|
if (!getenv("fastboot_dev"))
|
|
setenv("fastboot_dev", "mmc1");
|
|
if (!getenv("bootcmd"))
|
|
setenv("bootcmd", "boota mmc1");
|
|
break;
|
|
#endif /*CONFIG_FASTBOOT_STORAGE_MMC*/
|
|
#if defined(CONFIG_FASTBOOT_STORAGE_NAND)
|
|
case NAND_BOOT:
|
|
if (!getenv("fastboot_dev"))
|
|
setenv("fastboot_dev", "nand");
|
|
if (!getenv("fbparts"))
|
|
setenv("fbparts", ANDROID_FASTBOOT_NAND_PARTS);
|
|
if (!getenv("bootcmd"))
|
|
setenv("bootcmd",
|
|
"nand read ${loadaddr} ${boot_nand_offset} "
|
|
"${boot_nand_size};boota ${loadaddr}");
|
|
break;
|
|
#endif /*CONFIG_FASTBOOT_STORAGE_NAND*/
|
|
|
|
default:
|
|
printf("unsupported boot devices\n");
|
|
break;
|
|
}
|
|
}
|
|
|
|
#ifdef CONFIG_ANDROID_RECOVERY
|
|
int check_recovery_cmd_file(void)
|
|
{
|
|
int recovery_mode = 0;
|
|
|
|
recovery_mode = recovery_check_and_clean_flag();
|
|
|
|
return recovery_mode;
|
|
}
|
|
|
|
void board_recovery_setup(void)
|
|
{
|
|
int bootdev = get_boot_device();
|
|
|
|
switch (bootdev) {
|
|
#if defined(CONFIG_FASTBOOT_STORAGE_MMC)
|
|
case SD1_BOOT:
|
|
case MMC1_BOOT:
|
|
if (!getenv("bootcmd_android_recovery"))
|
|
setenv("bootcmd_android_recovery", "boota mmc0 recovery");
|
|
break;
|
|
case SD2_BOOT:
|
|
case MMC2_BOOT:
|
|
if (!getenv("bootcmd_android_recovery"))
|
|
setenv("bootcmd_android_recovery", "boota mmc1 recovery");
|
|
break;
|
|
#endif /*CONFIG_FASTBOOT_STORAGE_MMC*/
|
|
#if defined(CONFIG_FASTBOOT_STORAGE_NAND)
|
|
case NAND_BOOT:
|
|
if (!getenv("bootcmd_android_recovery"))
|
|
setenv("bootcmd_android_recovery",
|
|
"nand read ${loadaddr} ${recovery_nand_offset} "
|
|
"${recovery_nand_size};boota ${loadaddr}");
|
|
break;
|
|
#endif /*CONFIG_FASTBOOT_STORAGE_NAND*/
|
|
|
|
default:
|
|
printf("Unsupported bootup device for recovery: dev: %d\n",
|
|
bootdev);
|
|
return;
|
|
}
|
|
|
|
printf("setup env for recovery..\n");
|
|
setenv("bootcmd", "run bootcmd_android_recovery");
|
|
}
|
|
#endif /*CONFIG_ANDROID_RECOVERY*/
|
|
|
|
#endif /*CONFIG_FSL_FASTBOOT*/
|
|
|
|
#ifdef CONFIG_SPL_BUILD
|
|
#include <libfdt.h>
|
|
#include <spl.h>
|
|
#include <asm/arch/mx6-ddr.h>
|
|
|
|
|
|
static struct mx6ul_iomux_grp_regs mx6_grp_ioregs = {
|
|
.grp_addds = 0x00000030,
|
|
.grp_ddrmode_ctl = 0x00020000,
|
|
.grp_b0ds = 0x00000030,
|
|
.grp_ctlds = 0x00000030,
|
|
.grp_b1ds = 0x00000030,
|
|
.grp_ddrpke = 0x00000000,
|
|
.grp_ddrmode = 0x00020000,
|
|
#ifdef CONFIG_TARGET_MX6UL_9X9_EVK
|
|
.grp_ddr_type = 0x00080000,
|
|
#else
|
|
.grp_ddr_type = 0x000c0000,
|
|
#endif
|
|
};
|
|
|
|
#ifdef CONFIG_TARGET_MX6UL_9X9_EVK
|
|
static struct mx6ul_iomux_ddr_regs mx6_ddr_ioregs = {
|
|
.dram_dqm0 = 0x00000030,
|
|
.dram_dqm1 = 0x00000030,
|
|
.dram_ras = 0x00000030,
|
|
.dram_cas = 0x00000030,
|
|
.dram_odt0 = 0x00000000,
|
|
.dram_odt1 = 0x00000000,
|
|
.dram_sdba2 = 0x00000000,
|
|
.dram_sdclk_0 = 0x00000030,
|
|
.dram_sdqs0 = 0x00003030,
|
|
.dram_sdqs1 = 0x00003030,
|
|
.dram_reset = 0x00000030,
|
|
};
|
|
|
|
static struct mx6_mmdc_calibration mx6_mmcd_calib = {
|
|
.p0_mpwldectrl0 = 0x00000000,
|
|
.p0_mpdgctrl0 = 0x20000000,
|
|
.p0_mprddlctl = 0x4040484f,
|
|
.p0_mpwrdlctl = 0x40405247,
|
|
.mpzqlp2ctl = 0x1b4700c7,
|
|
};
|
|
|
|
static struct mx6_lpddr2_cfg mem_ddr = {
|
|
.mem_speed = 800,
|
|
.density = 2,
|
|
.width = 16,
|
|
.banks = 4,
|
|
.rowaddr = 14,
|
|
.coladdr = 10,
|
|
.trcd_lp = 1500,
|
|
.trppb_lp = 1500,
|
|
.trpab_lp = 2000,
|
|
.trasmin = 4250,
|
|
};
|
|
|
|
struct mx6_ddr_sysinfo ddr_sysinfo = {
|
|
.dsize = 0,
|
|
.cs_density = 18,
|
|
.ncs = 1,
|
|
.cs1_mirror = 0,
|
|
.walat = 0,
|
|
.ralat = 5,
|
|
.mif3_mode = 3,
|
|
.bi_on = 1,
|
|
.rtt_wr = 0, /* LPDDR2 does not need rtt_wr rtt_nom */
|
|
.rtt_nom = 0,
|
|
.sde_to_rst = 0, /* LPDDR2 does not need this field */
|
|
.rst_to_cke = 0x10, /* JEDEC value for LPDDR2: 200us */
|
|
.ddr_type = DDR_TYPE_LPDDR2,
|
|
};
|
|
|
|
#else
|
|
static struct mx6ul_iomux_ddr_regs mx6_ddr_ioregs = {
|
|
.dram_dqm0 = 0x00000030,
|
|
.dram_dqm1 = 0x00000030,
|
|
.dram_ras = 0x00000030,
|
|
.dram_cas = 0x00000030,
|
|
.dram_odt0 = 0x00000030,
|
|
.dram_odt1 = 0x00000030,
|
|
.dram_sdba2 = 0x00000000,
|
|
.dram_sdclk_0 = 0x00000008,
|
|
.dram_sdqs0 = 0x00000038,
|
|
.dram_sdqs1 = 0x00000030,
|
|
.dram_reset = 0x00000030,
|
|
};
|
|
|
|
static struct mx6_mmdc_calibration mx6_mmcd_calib = {
|
|
.p0_mpwldectrl0 = 0x00070007,
|
|
.p0_mpdgctrl0 = 0x41490145,
|
|
.p0_mprddlctl = 0x40404546,
|
|
.p0_mpwrdlctl = 0x4040524D,
|
|
};
|
|
|
|
struct mx6_ddr_sysinfo ddr_sysinfo = {
|
|
.dsize = 0,
|
|
.cs_density = 20,
|
|
.ncs = 1,
|
|
.cs1_mirror = 0,
|
|
.rtt_wr = 2,
|
|
.rtt_nom = 1, /* RTT_Nom = RZQ/2 */
|
|
.walat = 1, /* Write additional latency */
|
|
.ralat = 5, /* Read additional latency */
|
|
.mif3_mode = 3, /* Command prediction working mode */
|
|
.bi_on = 1, /* Bank interleaving enabled */
|
|
.sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */
|
|
.rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */
|
|
.ddr_type = DDR_TYPE_DDR3,
|
|
};
|
|
|
|
static struct mx6_ddr3_cfg mem_ddr = {
|
|
.mem_speed = 800,
|
|
.density = 4,
|
|
.width = 16,
|
|
.banks = 8,
|
|
.rowaddr = 15,
|
|
.coladdr = 10,
|
|
.pagesz = 2,
|
|
.trcd = 1375,
|
|
.trcmin = 4875,
|
|
.trasmin = 3500,
|
|
};
|
|
#endif
|
|
|
|
static void ccgr_init(void)
|
|
{
|
|
struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
|
|
|
|
writel(0xFFFFFFFF, &ccm->CCGR0);
|
|
writel(0xFFFFFFFF, &ccm->CCGR1);
|
|
writel(0xFFFFFFFF, &ccm->CCGR2);
|
|
writel(0xFFFFFFFF, &ccm->CCGR3);
|
|
writel(0xFFFFFFFF, &ccm->CCGR4);
|
|
writel(0xFFFFFFFF, &ccm->CCGR5);
|
|
writel(0xFFFFFFFF, &ccm->CCGR6);
|
|
writel(0xFFFFFFFF, &ccm->CCGR7);
|
|
}
|
|
|
|
static void spl_dram_init(void)
|
|
{
|
|
mx6ul_dram_iocfg(mem_ddr.width, &mx6_ddr_ioregs, &mx6_grp_ioregs);
|
|
mx6_dram_cfg(&ddr_sysinfo, &mx6_mmcd_calib, &mem_ddr);
|
|
}
|
|
|
|
void board_init_f(ulong dummy)
|
|
{
|
|
/* setup AIPS and disable watchdog */
|
|
arch_cpu_init();
|
|
|
|
ccgr_init();
|
|
|
|
/* iomux and setup of i2c */
|
|
board_early_init_f();
|
|
|
|
/* setup GP timer */
|
|
timer_init();
|
|
|
|
/* UART clocks enabled and gd valid - init serial console */
|
|
preloader_console_init();
|
|
|
|
/* DDR initialization */
|
|
spl_dram_init();
|
|
|
|
/* Clear the BSS. */
|
|
memset(__bss_start, 0, __bss_end - __bss_start);
|
|
|
|
/* load/boot image from boot device */
|
|
board_init_r(NULL, 0);
|
|
}
|
|
#endif
|