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Commit Graph

301 Commits

Author SHA1 Message Date
Hersen Wu
3f6d743598 drm/amd/display: DAL3 RV get DPREFCLK SpreadspectrumInfo from smu_info 
Signed-off-by: Hersen Wu <hersenxs.wu@amd.com>
Reviewed-by: Charlene Liu <Charlene.Liu@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2017-09-26 18:08:00 -04:00
Amy Zhang
9f72f51d70 drm/amd/display: Refactor to call set PSR wait loop in dce_dmcu instead of dce_clocks 
Signed-off-by: Amy Zhang <Amy.Zhang@amd.com>
Reviewed-by: Anthony Koo <Anthony.Koo@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2017-09-26 18:07:50 -04:00
Amy Zhang
7db4dede64 drm/amd/display: Add function to get PSR state 
Signed-off-by: Amy Zhang <Amy.Zhang@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2017-09-26 18:07:44 -04:00
Dmytro Laktyushkin
a7562ab35e drm/amd/display: remove GRPH_SURFACE_UPDATE_IMMEDIATE_EN field programming 
This is causing asserts for dce 8 and 10 since they do not contain this
field. It is also unnecessary for later DCEs as it is left in it's
default state of 0

Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2017-09-26 18:07:26 -04:00
Tom St Denis
0b3454b7c4 drm/amd/display: Tidy up mem_input_program_surface_flip_and_addr() 
Signed-off-by: Tom St Denis <tom.stdenis@amd.com>
Reviewed-by: Harry Wentland <Harry.Wentland@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2017-09-26 18:07:24 -04:00
Leo (Sunpeng) Li
98489c026e drm/amd/display: Refactor use_lut() from dce110 to dce 
use_lut() checks if the input surface's pixel format is compatible with
a 256 entry LUT. This function can be used across different versions and
not just dce11.

Signed-off-by: Leo (Sunpeng) Li <sunpeng.li@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2017-09-26 18:07:19 -04:00
Dmytro Laktyushkin
1185da0869 drm/amd/display: add missing GRPH_UPDATE_LOCK field macro for dce_mem_input 
Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Reviewed-by: Harry Wentland <Harry.Wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2017-09-26 18:07:15 -04:00
Dmytro Laktyushkin
c34892144d drm/amd/display: dce 8 - 12 mem_input refactor to new style 
Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2017-09-26 18:07:12 -04:00
Amy Zhang
aa7397dfd4 drm/amd/display: Disable ABM when eDP is disabled 
- Add immediate ABM disable when eDP is disabled
- Fix purple screen when ABM is mistakenly enabled
on non eDP display

Signed-off-by: Amy Zhang <Amy.Zhang@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2017-09-26 18:07:12 -04:00
Dmytro Laktyushkin
4b28b76bfe drm/amd/display: fix mpo blanking out on one of planes being set not visible 
Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2017-09-26 18:07:11 -04:00
Dmytro Laktyushkin
9037d802a9 drm/amd/display: refactor bw related variable structure in val_ctx 
Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2017-09-26 18:07:01 -04:00
Anthony Koo
fe62673471 drm/amd/display: Implement support for backlight optimization 
- Add functionality to get real hw backlight level as opposed to user
level, meaning the level that takes into account backlight ramping
over time and backlight reduction due to Varibright
- Add backlight optimization which allows for a second OS state
that is able to control ABM

Signed-off-by: Anthony Koo <Anthony.Koo@amd.com>
Reviewed-by: Aric Cyr <Aric.Cyr@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2017-09-26 18:06:59 -04:00
Harry Wentland
15a27de250 drm/amd/display: Don't call PSR func if DMCU is off 
Signed-off-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2017-09-26 18:06:54 -04:00
kbuild test robot
8e863620aa drm/amdgpu/display: fix semicolon.cocci warnings 
drivers/gpu/drm/amd/amdgpu/../display/dc/dce/dce_stream_encoder.c:411:23-24: Unneeded semicolon
drivers/gpu/drm/amd/amdgpu/../display/dc/dce/dce_stream_encoder.c:420:39-40: Unneeded semicolon

 Remove unneeded semicolon.

Generated by: scripts/coccinelle/misc/semicolon.cocci

CC: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Fengguang Wu <fengguang.wu@intel.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2017-09-26 18:06:52 -04:00
Alex Deucher
ff5ef99248 drm/amdgpu/display: Enable DCN in DC 
Enable DCN in DC.

Signed-off-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2017-09-26 18:06:51 -04:00
Hersen Wu
7d091f7a44 drm/amd/display: Get dprefclk ss percentage from vbios 
Signed-off-by: Hersen Wu <hersenxs.wu@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2017-09-26 18:06:46 -04:00
Dmytro Laktyushkin
e6303950ea drm/amd/display: dce80, 100, 110 and 112 to dce ipp refactor 
Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2017-09-26 18:06:39 -04:00
Dmytro Laktyushkin
86b6a203b9 drm/amd/display: dce120 to dce ipp refactor 
Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2017-09-26 18:06:38 -04:00
Dmytro Laktyushkin
974db151d4 drm/amd/display: remove unnecessary allocation for regamma_params inside opp 
Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Reviewed-by: Harry Wentland <Harry.Wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2017-09-26 18:06:31 -04:00
Zeyu Fan
89aed24c18 drm/amd/display: Block YCbCr formats for eDP. Revert previous change. 
Signed-off-by: Zeyu Fan <Zeyu.Fan@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2017-09-26 18:06:30 -04:00
Vitaly Prosyak
ab3c179893 drm/amd/display: Add support for programming stereo sync 
Signed-off-by: Vitaly Prosyak <vitaly.prosyak@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Reviewed-by: Charlene Liu <Charlene.Liu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2017-09-26 17:23:51 -04:00
Leon Elazar
6e5d1c829b drm/amd/display: Memory was freed twice during disable 
1. get_ss_info_from_atombios function was allocating the memory populating the provided pointer
but them freeing the memory.
Since the pointer was return as a valid value, we are trying to free the same memory during clock resource destruction

Signed-off-by: Leon Elazar <leon.elazar@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2017-09-26 17:23:19 -04:00
Jordan Lazare
7160c74cd0 drm/amd/display: Log clock source in error condition 
Signed-off-by: Jordan Lazare <Jordan.Lazare@amd.com>
Reviewed-by: Harry Wentland <Harry.Wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2017-09-26 17:22:32 -04:00
Ding Wang
4e3133c79d drm/amd/display: obtain usHBR3En bit from BP 1 
ASICs using bios parser 1 don't check HBR3 capability as there is no such
a bit usHBR3En in ATOM_ENCODER_CAP_RECORDER.
Therefore, will use ATOM_ENCODER_CAP_RECORDER_V2 and thus obtain the usHBR3En
bit.

Signed-off-by: Ding Wang <ding.wang@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2017-09-26 17:21:31 -04:00
Tony Cheng
fcbb5ad3fe drm/amd/display: use CP2520-3 for PHY compliance automation 
Signed-off-by: Tony Cheng <tony.cheng@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Reviewed-by: Hersen Wu <hersenxs.wu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2017-09-26 17:21:24 -04:00
Roman Li
940c654e64 drm/amd/display: increase timeout for dmif dealloc 
In some use-cases, e.g. multiple 4K displays,
exisitng wait time for reg update of 30msec timed out
during mode setiing that sometimes resulted in system bad state
as we continue without waiting for registry update complete.
Increasing timeout to 35msec fixes that problem.

Signed-off-by: Roman Li <Roman.Li@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2017-09-26 17:21:17 -04:00
Charlene Liu
fd8cc371ed drm/amd/display: voltage request related change 
Signed-off-by: Charlene Liu <charlene.liu@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Reviewed-by: Krunoslav Kovac <Krunoslav.Kovac@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2017-09-26 17:21:13 -04:00
Tony Cheng
0e19401f95 drm/amd/display: support PHY compliance automation for CP2520 pattern 1/2/3 
Signed-off-by: Tony Cheng <tony.cheng@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2017-09-26 17:20:19 -04:00
Tony Cheng
3f8a944016 drm/amd/display: support CP2520 pattern 2 for HBR2 compliance 
- also some clean up

Signed-off-by: Tony Cheng <tony.cheng@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Reviewed-by: Charlene Liu <Charlene.Liu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2017-09-26 17:20:16 -04:00
Alex Deucher
8fa9ca2ec6 drm/amd/display: Remove DCE12 guards 
Signed-off-by: Jordan Lazare <Jordan.Lazare@amd.com>
Reviewed-by: Harry Wentland <Harry.Wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2017-09-26 17:19:36 -04:00
Alex Deucher
2c8ad2d5a2 drm/amd/display: Enable DCE12 support 
This wires DCE12 support into DC and enables it.

Signed-off-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2017-09-26 17:19:23 -04:00
Jordan Lazare
c0bc0bd587 drm/amd/display: Less log spam 
Signed-off-by: Jordan Lazare <Jordan.Lazare@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Reviewed-by: Charlene Liu <Charlene.Liu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2017-09-26 17:18:54 -04:00
Charlene Liu
e8c963d6d9 drm/amd/display: refclock from bios firmwareInfoTable 
Signed-off-by: Charlene Liu <charlene.liu@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2017-09-26 17:18:11 -04:00
Amy Zhang
ece4f358cb drm/amd/display: Simplify some DMCU waits 
Signed-off-by: Amy Zhang <Amy.Zhang@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2017-09-26 17:18:08 -04:00
Tony Cheng
773d1bcae7 drm/amd/display: remove independent lock as we have no use case today 
Signed-off-by: Tony Cheng <tony.cheng@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Reviewed-by: Charlene Liu <Charlene.Liu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2017-09-26 17:17:56 -04:00
Tony Cheng
d98e5cc2dd drm/amd/display: clean up and simply locking logic 
always take update lock instead of using HW built in update
lock trigger with write to primary_addr_lo.

we will be a little more inefficient with the extra registers
write to lock, but this simplify code and make it always correct.

Will revisit locking optimization once update sequence mature

Signed-off-by: Tony Cheng <tony.cheng@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Reviewed-by: Charlene Liu <Charlene.Liu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2017-09-26 17:17:51 -04:00
Charlene Liu
f0828115ef drm/amd/display: freesync pipe split :VTotal_Min_Mask for Hflip/lock. 
Signed-off-by: Charlene Liu <charlene.liu@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Reviewed-by: Jordan Lazare <Jordan.Lazare@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2017-09-26 17:16:55 -04:00
Harry Wentland
c2e218dda0 drm/amd/display: Some more warning fixes 
This doesn't show with gcc6

Signed-off-by: Harry Wentland <harry.wentland@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2017-09-26 17:16:39 -04:00
Dmytro Laktyushkin
ce9c088051 drm/amd/display: move visual confirm recout adjustment to scaler 
Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2017-09-26 17:16:35 -04:00
Harry Wentland
6480136967 drm/amd/display: Fix warnings in DC 
Signed-off-by: Harry Wentland <harry.wentland@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2017-09-26 17:16:22 -04:00
Leon Elazar
1781958ff4 drm/amd/display: Surface Validation Fixes + Audio Mask 
1. dc: Adding missing mask for audio register DCCG_AUDIO_DTO_SOURCE
2. Changing the surface validation to check the limits of the clip rect instead of the source rect.

Signed-off-by: Leon Elazar <leon.elazar@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2017-09-26 17:16:14 -04:00
Dmytro Laktyushkin
227d251899 drm/amd/display: add scaler coefficients for 64 phase 5-8 taps 
Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2017-09-26 17:16:09 -04:00
Amy Zhang
3548f0731a drm/amd/display: DMCU PSR Refactor 
- Move PSR programming from link encoder to dmcu

Signed-off-by: Amy Zhang <Amy.Zhang@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2017-09-26 17:16:02 -04:00
Charlene Liu
4b679bc3ca drm/amd/display: HDMI deep color mode audio issue 
Signed-off-by: Charlene Liu <charlene.liu@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Reviewed-by: Charlene Liu <Charlene.Liu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2017-09-26 17:15:54 -04:00
Charlene Liu
181a888fcd drm/amd/display: fix incorrect programming for YCbCr422 and YCbCr420 
Signed-off-by: Charlene Liu <charlene.liu@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2017-09-26 17:15:36 -04:00
Charlene Liu
896b3cb3f4 drm/amd/display: fix 12bpc truncate to 10bpc 
Signed-off-by: Charlene Liu <charlene.liu@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2017-09-26 17:15:33 -04:00
Charlene Liu
87b58768ec drm/amd/display: audio bug fix part 1: Add missing audio ACR 
Signed-off-by: Charlene Liu <charlene.liu@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2017-09-26 17:15:30 -04:00
Jordan Lazare
beed42b5bc drm/amd/display: Don't attempt to program missing register fields on DCE8 
When moving to a common dce/ infrastructure for all asics, some register fields
do not exist in DCE8, and cause ASSERTS and debug spam.

Instead, check to see whether a register field mask is valid before attempting
to program the register field

Signed-off-by: Jordan Lazare <Jordan.Lazare@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2017-09-26 17:15:06 -04:00
Zeyu Fan
77f36b2712 drm/amd/display: Fix logic that causes segfault on DP display. 
Signed-off-by: Zeyu Fan <Zeyu.Fan@amd.com>
Acked-by: Jordan Lazare <Jordan.Lazare@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2017-09-26 17:14:38 -04:00
Zeyu Fan
27e947b0e1 drm/amd/display: Fix program pix clk logic to unblock deep color set. 
Signed-off-by: Zeyu Fan <Zeyu.Fan@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2017-09-26 17:14:27 -04:00