Fix compile warning caused by conflicting types of expand_upwards. IA64
requires it to not be static inline, as it's used outside mm/mmap.c
Signed-off-by: Matthew Wilcox <willy@parisc-linux.org>
Signed-off-by: Kyle McMartin <kyle@parisc-linux.org>
The structure ide_driver_t have a .owner field which is a duplicate
of .gendriver.owner field (.gen_driver is a struct device_driver).
This patch removes ide_driver_t's owner field.
Signed-off-by: Laurent Riffard <laurent.riffard@free.fr>
Signed-off-by: Bartlomiej Zolnierkiewicz <bzolnier@gmail.com>
This patch fixes a bug that breaks hpacucli, a command line interface
for the HP Array Config Utility. Without this fix the utility will
not detect any controllers in the system. I thought I had already fixed
this, but I guess not.
Thanks to all who reported the issue. Please consider this this inclusion.
Signed-off-by: Mike Miller <mikem@beardog.cca.cpqcorp.net>
Signed-off-by: Jens Axboe <axboe@suse.de>
include/net/ieee80211.h: In function `ieee80211_get_payload':
include/net/ieee80211.h:1046: warning: control reaches end of non-void function
Cc: Jeff Garzik <jgarzik@pobox.com>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Jeff Garzik <jgarzik@pobox.com>
With the new powerpc architecture we don't seem to be able to disable huge
pages anymore.
mm/built-in.o(.toc1+0xae0): undefined reference to `HPAGE_SHIFT'
make: *** [.tmp_vmlinux1] Error 1
We seem to need to define HPAGE_SHIFT to something when HUGETLB_PAGE isn't
defined. This patch defines it to PAGE_SHIFT when we have no support.
Signed-off-by: Andy Whitcroft <apw@shadowen.org>
Cc: Paul Mackerras <paulus@samba.org>
Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
Every other architecture define dma_cache_{inv,wback,wback_inv}
in asm/io.h and doing so brings us closer to ppc64.
Signed-off-by: Stephen Rothwell <sfr@canb.auug.org.au>
This patch merges align.c, the result isn't quite what was in ppc64 nor
what was in ppc32 :) It should implement all the functionalities of both
though. Kumar, since you played with that in the past, I suppose you
have some test cases for verifying that it works properly before I dig
out the 601 machine ? :)
Since it's likely that I won't be able to test all scenario, code
inspection is much welcome.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Paul Mackerras <paulus@samba.org>
My earlier merge of delay.h introduced a timebase-based udelay for
32-bit machines but also broke the 601, which doesn't have the
timebase register. This fixes it by using the 601's RTC register on
the 601, and also moves __delay() and udelay() to be out-of-line in
arch/powerpc/kernel/time.c. These functions aren't really performance
critical, after all.
Signed-off-by: Paul Mackerras <paulus@samba.org>
The fix to topology.h (5cfccd7f13) seems to have
a typeo, struct sched_domain has an idle_idx member but not an idle_id
member. I assume this is the fix.
Signed-off-by: Michael Ellerman <michael@ellerman.id.au>
Signed-off-by: Paul Mackerras <paulus@samba.org>
Since taking a spinlock disables preempt, and we need to spinlock tlb flush
on SMP for N class, we might as well just spinlock on uniprocessor machines
too.
Signed-off-by: Matthew Wilcox <willy@parisc-linux.org>
Signed-off-by: Kyle McMartin <kyle@parisc-linux.org>
We actually have two separate bad bugs
1. The read_lock implementation spins with disabled interrupts. This is
completely wrong
2. Our spin_lock_irqsave should check to see if interrupts were enabled
before the call and re-enable interrupts around the inner spin loop.
The problem is that if we spin with interrupts off, we can't receive
IPIs. This has resulted in a bug where SMP machines suddenly spit
smp_call_function timeout messages and hang.
The scenario I've caught is
CPU0 does a flush_tlb_all holding the vmlist_lock for write.
CPU1 tries a cat of /proc/meminfo which tries to acquire vmlist_lock for
read
CPU1 is now spinning with interrupts disabled
CPU0 tries to execute a smp_call_function to flush the local tlb caches
This is now a deadlock because CPU1 is spinning with interrupts disabled
and can never receive the IPI
Signed-off-by: James Bottomley <jejb@parisc-linux.org>
Signed-off-by: Kyle McMartin <kyle@parisc-linux.org>
This really only adds them for the machines I can check SMP on, which
is CPU interrupts and IOSAPIC (so not any of the GSC based machines).
With this patch, irqbalanced can be used to maintain irq balancing.
Unfortunately, irqbalanced is a bit x86 centric, so it doesn't do an
incredibly good job, but it does work.
Signed-off-by: James Bottomley <jejb@parisc-linux.org>
Signed-off-by: Kyle McMartin <kyle@parisc-linux.org>
Since irq.c uses smp_send_all_nop, we must define it for UP builds
as well. Make it a static inline so it gets optimized away. This forces
irq.c to include <asm/smp.h> though.
Signed-off-by: Kyle McMartin <kyle@parisc-linux.org>
Fix our interrupts not to use smp_call_function
On K and D class smp, the generic code calls this under an irq
spinlock, which causes the WARN_ON() message in smp_call_function()
(and is also illegal because it could deadlock).
The fix is to use a new scheme based on the IPI_NOP.
Signed-off-by: James Bottomley <jejb@parisc-linux.org>
Signed-off-by: Kyle McMartin <kyle@parisc-linux.org>
Due to incomplete memory constraints, gcc would miscompile code with
sigaddset on i386 if sig arg was const.
A quote form Jakub to make the issue clear:
"You need either
__asm__("btsl %1,%0" : "+m"(*set) : "Ir"(_sig-1) : "cc");
or
__asm__("btsl %1,%0" : "=m"(*set) : "Ir"(_sig-1), "m"(*set) : "cc");
because the btsl instruction doesn't just set the memory to some
value, but needs to read its previous content as well. If you don't
tell that fact to GCC, GCC is of course free to optimize as if the asm
was just setting the value and not depended on the previous value."
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
There is no definition for seadint_init() and the unprotected prototype
breaks compilation of assembler files.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
If the kernel supports both G5 and pSeries, and CONFIG_EEH is enabled,
eeh_init() is (quite reasonably) never called when we boot on a G5. Yet
eeh_check_failure() still gets called. We should avoid doing that if
!eeh_subsystem_enabled.
Signed-off-by: David Woodhouse <dwmw2@infradead.org>
Signed-off-by: Paul Mackerras <paulus@samba.org>
PowerPC's NUMA domain doesn't currently set up some of the newer
sched-domains parameters.
Brian Twichell <tbrian@us.ibm.com> discovered and diagnosed a 1.5% OLTP
database regression on a 4 core POWER5 system that was due to the use of
NUMA scheduling on ppc64.
This patch applies some saneish values to the parameters, in line with
other architectures. This solves the regression.
Signed-off-by: Nick Piggin <npiggin@suse.de>
Signed-off-by: Paul Mackerras <paulus@samba.org>
In the old days when arm26/arm32 was combined into the same
architecture, proc-fns.h provided the xchg implementation for
arm26 CPUs. Since we no longer combine these two, this include
is no longer required. Remove it.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Since atomic.h does not include types.h, u32 may not be defined.
Since atomics are supposed to work on unsigned long quantities,
use unsigned long instead.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Unfortunately, using PAGE_SHIFT in asm/arch/memory.h is unsafe, and we
can't include asm/page.h into this file because then we have a circular
dependency. Move the offending code to arch/arm/common/sa1111.c
instead.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
atomic.h, bitops.h and mmu_context.h are using likely/unlikely.
thread_info.h uses __attribute_const__. Hence these files require
linux/compiler.h to be included.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Patch from Nicolas Pitre
If 'old' and 'oldval' are different then 'res' never gets set. In that
case, if ever %0 happened to contain anything but zero (rather likely)
then the code will loop forever (or until another CPU just come along
and change the atomic value to match 'old' which is rather unlikely).
Signed-off-by: Nicolas Pitre <nico@cam.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
