Jonathan Kim c52e7ebce7 drm/amdgpu: exposing fica registers to df offsets ...

exposing fica registers to poll df pie data for xgmi error counters for
vega20.

Signed-off-by: Jonathan Kim <Jonathan.Kim@amd.com>
Reviewed-by: Alexander Deucher <Alexander.Deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

2019-07-18 14:18:07 -05:00

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asic_reg

drm/amdgpu: exposing fica registers to df offsets

2019-07-18 14:18:07 -05:00

ivsrcid

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amd_acpi.h

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amd_pcie_helpers.h

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amd_pcie.h

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amd_shared.h

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arct_ip_offset.h

drm/amdgpu: add Arcturus ip_offset header (v3)

2019-07-18 14:18:01 -05:00

atom-bits.h

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atom-names.h

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atom-types.h

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atombios.h

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atomfirmware.h

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atomfirmwareid.h

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cgs_common.h

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cik_structs.h

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discovery.h

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displayobject.h

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dm_pp_interface.h

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kgd_kfd_interface.h

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kgd_pp_interface.h

drm/amd/powerplay: correct SW SMU valid mapping check

2019-07-18 14:18:07 -05:00

navi10_enum.h

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navi10_ip_offset.h

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navi14_ip_offset.h

drm/amdgpu/soc15: initialize reg base for navi14 (v2)

2019-07-18 14:17:58 -05:00

pptable.h

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soc15_hw_ip.h

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soc15_ih_clientid.h

drm/amdgpu/: add clientID for 2nd vcn instance

2019-07-18 14:18:05 -05:00

v9_structs.h

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v10_structs.h

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vega10_enum.h

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vega10_ip_offset.h

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vega20_ip_offset.h

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vi_structs.h

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