At present this uses RGB555 format for blitting to a display. Sandbox uses
565 and that seems to be more normal for BMP as well. Update the code
accordingly and add a test.
Note that this likely breaks the theadorable board so we may need to
discuss supporting both formats.
[Backport of commit 4ea1548210 ("video: theadorable: Use RGB565 for
BMP blitting")]
Signed-off-by: Simon Glass <sjg@chromium.org>
Change-Id: Ifae9f08166f4c7c3f8a1aa41f6fc0c898c3be5b5
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-on: https://gerrit.st.com/c/mpu/oe/st/u-boot/+/265323
Reviewed-by: CIBUILD <MDG-smet-aci-builds@list.st.com>
Reviewed-by: Patrice CHOTARD <patrice.chotard@foss.st.com>
When a GPIO is secure-protected, it can't be accessed from U-Boot.
In that case, set its 'function' to GPIOF_PROTECTED.
This makes the "gpio status" command returning the "protected" status.
Example with GPIOA6 pin secure-protected
> gpio status -a
Bank GPIOA:
GPIOA0: unused: 0 [ ]
GPIOA1: func
...
GPIOA6: protected
...
Signed-off-by: Fabien Dessenne <fabien.dessenne@foss.st.com>
Change-Id: If3297d920741a6a1b915503650de1cfb69c726f9
Reviewed-on: https://gerrit.st.com/c/mpu/oe/st/u-boot/+/252040
Reviewed-by: CITOOLS <MDG-smet-aci-reviews@list.st.com>
Reviewed-by: Patrice CHOTARD <patrice.chotard@foss.st.com>
Reviewed-by: Patrick DELAUNAY <patrick.delaunay@foss.st.com>
The tests on CONFIG_DM_REGULATOR, added to avoid compilation issues, can now
be removed, they are no more needed since the commit 16cc5ad0b4 ("power:
regulator: add dummy helper").
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Change-Id: I18e4ad5947e3b321573efe2085dd4c593cabbabe
Reviewed-on: https://gerrit.st.com/c/mpu/oe/st/u-boot/+/250167
Currently, SR_TCF flag is checked in case there is data, this criteria
is not correct.
SR_TCF flags is set when programmed number of bytes have been transferred
to the memory device ("bytes" comprised command and data send to the
SPI device).
So even if there is no data, we must check SR_TCF flag.
Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Change-Id: Id4e8f33e11a972d985f29b7a4363b1622f4128c2
Reviewed-on: https://gerrit.st.com/c/mpu/oe/st/u-boot/+/250832
Reviewed-by: Christophe KERELLO <christophe.kerello@st.com>
Reviewed-by: Patrick DELAUNAY <patrick.delaunay@foss.st.com>
Fix the end address in the message for unaligned erase request in
mmc_berase() when start + blkcnt is aligned to erase_grp_size.
for example:
- start = 0x2000 - 26
- count = 26
- erase_grp_size = 0x400
Caution! Your devices Erase group is 0x400
The erase range would be change to 0x2000~0x27ff
But no issue when the end address is not aligned, for example
- start = 0x2000 - 2 * 26
- count = 26
- erase_grp_size = 0x400
Caution! Your devices Erase group is 0x400
The erase range would be change to 0x2000~0x23ff
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Change-Id: I5f92544259c3d1dad2df30c9d7762ec7860f07cf
Reviewed-on: https://gerrit.st.com/c/mpu/oe/st/u-boot/+/238835
Reviewed-by: CITOOLS <MDG-smet-aci-reviews@list.st.com>
Reviewed-by: Christophe KERELLO <christophe.kerello@st.com>
Reviewed-by: Patrice CHOTARD <patrice.chotard@foss.st.com>
On some STM32 SoC's package, GPIO bank may have hole in their GPIO bank
Example:
If GPIO bank have 16 GPIO pins [0-15].
In particular SoC's package case, some GPIO bank can have less GPIO pins:
- [0-10] => 11 pins;
- [2-7] => 6 pins.
Commit dbf928dd26 ("gpio: stm32f7: Add gpio bank holes management")
proposed a first implementation by not counting GPIO "inside" hole. GPIO
are not displaying correctly using gpio or pinmux command when GPIO holes
are located at the beginning of GPIO bank.
To simplify, consider that all GPIO have 16 GPIO and use the gpio_ranges
struct to indicate if a GPIO is mapped or not. GPIO uclass offers several
GPIO functions ("input", "output", "unused", "unknown" and "func"), use
"unknown" GPIO function to indicate that a GPIO is not mapped.
stm32_offset_to_index() is no more needed and removed.
This must be reflected using the "gpio" command to indicate to user
that a particular GPIO is not mapped (marked as "unknown") as shown below:
Example for a 16 pins GPIO bank with the [2-7] mapping (only 6 pins
mapped):
GPIOI0 : unknown
GPIOI1 : unknown
GPIOI2 : analog
GPIOI3 : analog
GPIOI4 : alt function 0 push-pull pull-down
GPIOI5 : alt function 0 push-pull pull-down
GPIOI6 : alt function 0 push-pull pull-down
GPIOI7 : analog
GPIOI8 : unknown
GPIOI9 : unknown
GPIOI10 : unknown
GPIOI11 : unknown
GPIOI12 : unknown
GPIOI13 : unknown
GPIOI14 : unknown
GPIOI15 : unknown
Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Change-Id: I55c39a2707fa8dae108d90c4a72590f1a4520ca9
Reviewed-on: https://gerrit.st.com/c/mpu/oe/st/u-boot/+/239065
Reviewed-by: CITOOLS <MDG-smet-aci-reviews@list.st.com>
Reviewed-by: Fabien DESSENNE <fabien.dessenne@foss.st.com>
Reviewed-by: Patrick DELAUNAY <patrick.delaunay@foss.st.com>
Solve a issue with AXI_WIDTH_32 on a the 64 bytes cache line platform;
in this case the requested descriptor padding length should be 12 but the
associated parameter EQOS_DMA_CH0_CONTROL.DSL is limited at 3bits = 7.
As the DMA descriptor can't be correctly aligned with the cache line,
the maintenance of each descriptor can't be guarantee by a simple cache
line operation: flush or invalid.
To avoid all the maintenance issues, these descripto need to be allocated
in a NOT CACHEABLE memory, allocated by noncached_alloc() when
CONFIG_SYS_NONCACHED_MEMORY is enable.
This patch don't change the current behavior when the descriptor
can be cache-aligned with the filed "Descriptor Skip Length" of
the DMA channel control register, when eqos->desc_pad = true.
Change-Id: Iada23492743e3af977e07c1f1b8c2f32550436f7
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-on: https://gerrit.st.com/c/mpu/oe/st/u-boot/+/236650
Reviewed-by: CITOOLS <MDG-smet-aci-reviews@list.st.com>
Reviewed-by: Christophe ROULLIER <christophe.roullier@st.com>
In clk_clean_rate_cache, clk->rate should update the private clock
struct when CCF is activated to save the cached rate value.
When clk_get_parent_rate is called, the cached information
is read from pclk->rate, with pclk = clk_get_parent(clk)
which use dev_get_clk_ptr() to access to private data.
As the cached is read from private clk data, the update should
be done also on it.
Series-cc: Tero Kristo <t-kristo@ti.com>
Series-cc: Tero Kristo <kristo@kernel.org>
Fixes: 6b7fd3128f ("clk: fix set_rate to clean up cached rates for the hierarchy")
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Change-Id: Ifa06360115ffa3f3307372e6cdd98ec16759d6ba
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-on: https://gerrit.st.com/c/mpu/oe/st/u-boot/+/236864
Reviewed-by: CITOOLS <MDG-smet-aci-reviews@list.st.com>
Some I/Os are connected to ADC input channels, when the corresponding bit
in PCSEL register are set on STM32H7 and STM32MP15.
PCSEL shouldn't be let enabled when VDDA supply is disabled, to avoid
current leakage. This may occur if the kernel disable the VDDA supply
of the ADC, while the PCSEL remains set, after leaving U-boot.
Clear PCSEL bits after each end of conversion, when relevant, to
prevent this case.
Change-Id: I147f128cd67392220a8924cf407bcdae0e1eb555
Signed-off-by: Olivier Moysan <olivier.moysan@foss.st.com>
Reviewed-on: https://gerrit.st.com/c/mpu/oe/st/u-boot/+/233126
Reviewed-by: CITOOLS <MDG-smet-aci-reviews@list.st.com>
Reviewed-by: Patrice CHOTARD <patrice.chotard@foss.st.com>
Reviewed-by: Patrick DELAUNAY <patrick.delaunay@foss.st.com>
Add smart calibration support for STM32MP1.
- STM32MP15x: both linear & offset calibration are supported
- STM32MP13x: Only offset calibration is supported
Linear calibration:
Linear calibration is SoC dependent and does not change over
time. As it is time consuming, do it only once.
Restore calibration data from environment variable to save time.
If no calibration data are found in u-boot environment variables
run a new calibration.
Offset calibration:
This calibration is fast and may vary over time.
Run offset single-ended and differential calibration on each boot.
Signed-off-by: Olivier Moysan <olivier.moysan@foss.st.com>
Change-Id: If8739d96e019d42341901c5da6a83925cc78333a
Reviewed-on: https://gerrit.st.com/c/mpu/oe/st/u-boot/+/231628
Reviewed-by: CITOOLS <MDG-smet-aci-reviews@list.st.com>
Reviewed-by: Patrice CHOTARD <patrice.chotard@foss.st.com>
Reviewed-by: Patrick DELAUNAY <patrick.delaunay@foss.st.com>
Before relying on u-boot,force-b-session-valid property presence to set
force_b_session_valid field, use typec_get_driver_from_usb() which check
if a Type-C connector is present. In this case invoke typec_get_data_role()
which indicates if current data role is DEVICE or HOST.
Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Change-Id: I3dc5da0c332c5b557a855564985317345d25458f
Reviewed-on: https://gerrit.st.com/c/mpu/oe/st/u-boot/+/232354
Reviewed-by: CITOOLS <MDG-smet-aci-reviews@list.st.com>
Reviewed-by: Patrick DELAUNAY <patrick.delaunay@foss.st.com>
The typec_get_driver_from_usb() allows to retrieve a Type-C device from
an USB device.
typec_get_driver_from_usb() checks in USB device node for port and endpoint
sub-node, if exist, retrieve the connector node, probe the associated
Type-C device and return it.
Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Change-Id: If564cdf463f3915bec26f17a4717c9ab9d42f692
Reviewed-on: https://gerrit.st.com/c/mpu/oe/st/u-boot/+/232353
Reviewed-by: CITOOLS <MDG-smet-aci-reviews@list.st.com>
Reviewed-by: Patrick DELAUNAY <patrick.delaunay@foss.st.com>
Implement a minimal UCSI uclass which allows to send request
to UCSI compatible chip. It provides the read() and write() ops.
It offers 3 services:
- ucsi_is_attached() which informs if Type-C connector is attached
or not.
- ucsi_get_data_role() which informs if the Type-C controller acts
as Device or host.
- usci_get_nb_connector() which indicates how many connector are
managed.
Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Change-Id: I319cf1f49b0980d33e2b47f1b14a513eb4466da5
Reviewed-on: https://gerrit.st.com/c/mpu/oe/st/u-boot/+/232349
Reviewed-by: CITOOLS <MDG-smet-aci-reviews@list.st.com>
Reviewed-by: Patrick DELAUNAY <patrick.delaunay@foss.st.com>
