Prepare v1.3.2-rc2 release candidate

Signed-off-by: Wolfgang Denk <wd@denx.de>

CHANGELOG

@@ -1,3 +1,360 @@
+commit 76957cb3d621bf664311908e5962e151c633c285
+Author: Stefan Roese <sr@denx.de>
+Date:	Sat Mar 1 12:11:40 2008 +0100
+
+    ppc4xx: EMAC: Fix 405EZ fifo size setup in EMAC_MR1
+
+    The 405EZ only supports 512 bytes of rx-/tx-fifo EMAC sizes. But
+    currently 4k/2k is configured. This patch fixes this issue.
+
+    Thanks to Thomas Kindler <tkindler@lenord.de> for pointing this out.
+
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit 118978c8eb43803e2794233922df4249fa278b83
+Author: Woodruff, Richard <r-woodruff2@ti.com>
+Date:	Fri Feb 29 17:34:35 2008 -0600
+
+    Fix alignment error on ARM for modules
+
+    Fix alignment fault on ARM when running modules.  With out an explicit
+    linker file gcc4.2.1 will half word align __bss_start's value.  The word
+    dereference will crash hello_world.
+
+    signed-off-by Richard Woodruff <r-woodruff2@ti.com>
+
+commit ce1120dd703e6f12c59e4eba9962356a0300b832
+Author: Dave Liu <r63238@freescale.com>
+Date:	Fri Feb 29 17:45:31 2008 +0800
+
+    fs: Fix ext2 read issue
+
+    The ext2 aligned process will corrupt the key
+    data struct, the patch fix this.
+
+    Signed-off-by: Dave Liu <daveliu@freescale.com>
+
+commit 5013c09f7a5675952a3ca88b6bc6c924e63af33e
+Author: Wolfgang Denk <wd@denx.de>
+Date:	Sun Mar 2 22:45:33 2008 +0100
+
+    Makefile: cleanup "clean" target
+
+    Make sure CDPATH settings cannot interfere.
+    Update CHANGELOG.
+
+    Signed-off-by: Wolfgang Denk <wd@denx.de>
+
+commit ffda586fc1373243c9794babde69500f6293a8d8
+Author: Li Yang <leoli@freescale.com>
+Date:	Fri Feb 29 11:46:05 2008 +0800
+
+    add cscope build target
+
+    Add cscope build target to generate cscope database for code browsing.
+
+    Signed-off-by: Li Yang <leoli@freescale.com>
+
+commit f655adef65e4cf6b929054b049ee19ae9b5ccbe2
+Author: Kim Phillips <kim.phillips@freescale.com>
+Date:	Wed Feb 27 15:06:39 2008 -0600
+
+    net: uec_phy: handle 88e1111 rev.B2 erratum 5.6
+
+    erratum 5.6 states the autoneg completion bit is functional only if the
+    autoneg bit is asserted.
+
+    This fixes any secondarily-issued networking commands on non-gigabit
+    links on the mpc8360 mds board.
+
+    Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
+
+commit 5f91db7f582ca17b1f19f10189c025696f333d2e
+Author: John Rigby <jrigby@freescale.com>
+Date:	Tue Feb 26 09:38:14 2008 -0700
+
+    MPC5121e ADS PCI support take 3
+
+    Adds PCI support for MPC5121
+
+    Tested with drivers/net/rtl8139.c
+
+    Support is conditional since PCI on old silicon does not work.
+
+    ads5121_PCI_config turns on PCI
+
+    In this version, condition compilation of PCI code has been moved
+    from ifdef in board/ads5121/pci.c to board/ads5121/Makefile as
+    suggested by Jean-Christophe PLAGNIOL-VILLARD
+
+    Signed-off-by: John Rigby <jrigby@freescale.com>
+
+commit 44b4dbed4133f657705b7c5193209da9978243a7
+Author: Anatolij Gustschin <agust@denx.de>
+Date:	Mon Feb 25 23:53:07 2008 +0100
+
+    Fix warnings while compilation of post/drivers/memory.c
+
+    Fix warnings while compilation with new gcc in eldk-4.2
+
+    Signed-off-by: Anatolij Gustschin <agust@denx.de>
+
+commit 4fae35a53b3e958254d6574a1cc7e10811fc6726
+Author: Anatolij Gustschin <agust@denx.de>
+Date:	Mon Feb 25 20:54:04 2008 +0100
+
+    ppc4xx: Fix problem in 4xx_enet.c driver
+
+    U-Boot crashes in the net loop if CONFIG_4xx_DCACHE is
+    enabled. To reproduce the problem ensure that 'ethrotate'
+    environment variable isn't set to "no" and then run
+    "tftp 200000 not_existent_file".
+    This patch tries to fix the issue.
+
+    Signed-off-by: Anatolij Gustschin <agust@denx.de>
+
+commit 60ec654c5eb80d0fe0c38a3bd42140215bc06484
+Author: Anatolij Gustschin <agust@denx.de>
+Date:	Mon Feb 25 20:04:20 2008 +0100
+
+    POST: Disable cache while SPR POST
+
+    Currently (since commit b2e2142c) u-boot crashes on
+    sequoia board while SPR test if CONFIG_4xx_DCACHE is
+    enabled. This patch disables the cache while SPR test.
+
+    Signed-off-by: Anatolij Gustschin <agust@denx.de>
+
+commit c313b2c6c555e7d89ec59bd51c59ab164ad0105d
+Author: Martin Krause <martin.krause@tqs.de>
+Date:	Mon Feb 25 17:52:40 2008 +0100
+
+    TQM5200: use automatic fdt memory fixup (part 2)
+
+    Call fdt_fixup_memory() on the boards TQM5200, TQM5200_B, TQM5200S,
+    TB5200 and TB5200_B to fixup the /memory node with the memory values
+    detected by U-Boot.
+
+    Signed-off-by: Martin Krause <martin.krause@tqs.de>
+
+commit 44ceec253ea941b301abf4b079d52324def69d92
+Author: Martin Krause <martin.krause@tqs.de>
+Date:	Mon Feb 25 15:17:05 2008 +0100
+
+    TQM5200: use automatic fdt memory fixup
+
+    Call fdt_fixup_memory() on the boards TQM5200, TQM5200_B, TQM5200S,
+    TB5200 and TB5200_B to fixup the /memory node with the memory values
+    detected by U-Boot.
+
+    Signed-off-by: Martin Krause <martin.krause@tqs.de>
+
+commit f3a329acb26017d8e10e9c93e1e726c2a5ac634a
+Author: Martin Krause <martin.krause@tqs.de>
+Date:	Mon Feb 25 13:27:52 2008 +0100
+
+    TQM5200: fix bug in SDRAM initialization code
+
+    This patch fixes a bug in the SDRAM initialization code for the
+    TQM5200. The hi_addr bit is now set correctly. Without this patch
+    the hi_addr bit is always set to 1, if the second SDRAM bank is
+    not populated.
+
+    For other MPC5200 boards a correspondig patch has already been applied
+    some time ago, see commit a63109281ad41b0fb489fdcb901171f76bcdbc2c.
+
+    Signed-off-by: Martin Krause <martin.krause@tqs.de>
+    --
+    Forget the first patch please. I confused flash with SDRAM in
+    the comment ...
+
+commit 217bf6b6a313d9ccb619a4dbc09f73f77cd48df1
+Author: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+Date:	Mon Feb 25 00:03:12 2008 +0100
+
+    mx1fs2/flash: Fix multiple compiler warnings
+
+    "pointer targets in assignment differ in signedness"
+
+    Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+
+commit 5599c28cef55be42a8ca6fa8086b1a44e56a85d2
+Author: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+Date:	Mon Feb 25 00:03:11 2008 +0100
+
+    arm-imx: Fix register definitions
+
+    Sync register definitions with linux
+
+    Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+
+commit c9bcf75fecc58886af77d2a571cff2eab39eab6f
+Author: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+Date:	Mon Feb 25 00:03:10 2008 +0100
+
+    actua1/actua2/actua3: Fix multiple unused variable warnings
+
+    - actua1:
+	actux1.c: In function 'checkboard':
+	actux1.c:92: warning: unused variable 'revision'
+
+    - actua2:
+	actux2.c: In function 'checkboard':
+	actux2.c:100: warning: unused variable 's'
+	actux2.c:99: warning: unused variable 'revision'
+	actux2.c: In function 'reset_phy':
+	actux2.c:130: warning: unused variable 'i'
+
+    - actua3:
+	actux3.c: In function 'checkboard':
+	actux3.c:114: warning: unused variable 'revision'
+
+    Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+
+commit f8fa6368a6a0c02164da8e2f52f18d457c6977bd
+Author: Shinya Kuribayashi <skuribay@ruby.dti.ne.jp>
+Date:	Sun Feb 24 11:44:29 2008 +0900
+
+    Remove the __STRICT_ANSI__ check from the __u64/__s64 declaration on 32bit targets.
+
+    The previous patch was lacking of i386, microblaze, nios and nios2. This
+    patch tries to fix them.
+
+    Signed-off-by: Shinya Kuribayashi <skuribay@ruby.dti.ne.jp>
+
+commit 2b22fa4baee51e6b467c44ea1be0d1ecd86e8775
+Author: Kumar Gala <galak@kernel.crashing.org>
+Date:	Wed Feb 27 16:30:47 2008 -0600
+
+    85xx: Don't icbi when unlocking the cache
+
+    There is no reason to icbi when invalidating the temporary stack in
+    the d-cache.  Its impossible on e500 to have the i-cache contain
+    any addresses in the temp stack and it can be problematic in generating
+    transactions on the bus to non-valid addresses.
+
+    Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
+
+commit 534ea6b6f86f8b75ef2ac061ef110a98f103d7d6
+Author: Andy Fleming <afleming@freescale.com>
+Date:	Wed Feb 27 15:50:50 2008 -0600
+
+    Fix source for ECM error IVPR
+
+    The source vector for the ECM was being set to 2,
+    but that's what the source vector for DDR was being
+    set to.  Change it to 1.
+
+    Signed-off-by: Andy Fleming <afleming@freescale.com>
+
+commit 21fae8b2b4e4e6e648796e07e20ab13e9cb18923
+Author: Andy Fleming <afleming@freescale.com>
+Date:	Wed Feb 27 14:29:58 2008 -0600
+
+    Invalidate INIT_RAM TLB mappings
+
+    Commit 0db37dc...  (and some others) changed the INIT_RAM TLB
+    mappings to be unguarded.  This collided with an existing "bug"
+    where the mappings for the INIT_RAM were being kept around.
+    This meant that speculative loads to those addresses were
+    succeeding in the TLB, and going out to the bus, where they
+    were causing an exception (there's nothing at that address). The
+    Flash code was coincidentally causing such a speculative load.
+    Rather than go back to mapping the INIT RAM as guarded, we fix
+    it so that the entries for the INIT_RAM are invalidated.  Thus
+    the speculative loads will fail in the TLB, and have no effect.
+
+    Signed-off-by: Andy Fleming <afleming@freescale.com>
+
+commit 347b7938d3e561eb215aa386c37fb5acb5a383c6
+Author: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+Date:	Sun Feb 17 22:56:17 2008 +0100
+
+    sbc8548: Fix Revision reading and unused variable 'path'
+
+    Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+
+commit 495d162374c472f46454453553382ad0735dc725
+Author: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+Date:	Sun Feb 17 22:56:16 2008 +0100
+
+    sbc8548: Fix cfi flash bank declaration
+
+    Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+
+commit 33fa5c0bfaf465de8ceb23fcd6b397f68b35a817
+Author: Jon Loeliger <jdl@freescale.com>
+Date:	Mon Feb 25 13:13:37 2008 -0600
+
+    86xx: Fix renamed GUR symbols in sbc8641d board.
+
+    Back in commit a551cee99ad1d1da20fd23ad265de47448852f56
+    (86xx: Fix GUR PCI config registers properly), we should have
+    changed the MPC86xx_PORBMSR_HA and MPC86xx_PORDEVSR_IO_SEL
+    symbols in the sbc8641d board as well.  Fix this oversight.
+
+    Signed-off-by: Jon Loeliger <jdl@freescale.com>
+
+commit 64cd594e623c39f73964d18787763e4533f791f7
+Author: Stefan Roese <sr@denx.de>
+Date:	Mon Feb 25 16:50:48 2008 +0100
+
+    ppc4xx: Fix acadia_nand build problem
+
+    Don't include testdram() on NAND-booting target acadia_nand. This saves
+    a few bytes and makes the target build clean again.
+
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit 14e099e698d41e8179d05c2b2dbcf704a236f748
+Author: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+Date:	Sun Feb 24 23:03:12 2008 +0000
+
+    mx1fs2/flash: Fix multiple pointertargets in assignment differ in signedness
+
+    Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+
+commit 724902c8464e610642b3a170278b99710325888e
+Author: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+Date:	Sun Feb 24 23:03:11 2008 +0000
+
+    arm-imx: Fix registers definition
+
+    Sync registers definition with linux
+
+    Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+
+commit 4cd288b589ea1178947c6e364453c32b3dede6b7
+Author: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+Date:	Sun Feb 24 23:03:10 2008 +0000
+
+    actua1/actua2/actua3: Fix multipleunused variable
+
+    - actua1:
+	actux1.c: In function 'checkboard':
+	actux1.c:92: warning: unused variable 'revision'
+
+    - actua2:
+	actux2.c: In function 'checkboard':
+	actux2.c:100: warning: unused variable 's'
+	actux2.c:99: warning: unused variable 'revision'
+	actux2.c: In function 'reset_phy':
+	actux2.c:130: warning: unused variable 'i'
+
+    - actua3:
+	actux3.c: In function 'checkboard':
+	actux3.c:114: warning: unused variable 'revision'
+
+    Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+
+commit b29661fc1151077776454288051bc9a488351ce8
+Author: Wolfgang Denk <wd@denx.de>
+Date:	Sun Feb 24 15:21:36 2008 +0100
+
+    Coding style cleanup. Prepare v1.3.2-rc2 release candidate
+
+    Signed-off-by: Wolfgang Denk <wd@denx.de>
+
 commit 00b48a48424894daa589d166d73277830b1c6ac4
 Author: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
 Date:	Sat Feb 23 12:15:56 2008 +0100

Makefile

@@ -24,7 +24,7 @@
 VERSION = 1
 PATCHLEVEL = 3
 SUBLEVEL = 2
-EXTRAVERSION = -rc2
+EXTRAVERSION = -rc3
 U_BOOT_VERSION = $(VERSION).$(PATCHLEVEL).$(SUBLEVEL)$(EXTRAVERSION)
 VERSION_FILE = $(obj)include/version_autogenerated.h
 
@@ -118,6 +118,9 @@ src :=
 endif
 export obj src
 
+# Make sure CDPATH settings don't interfere
+unexport CDPATH
+
 #########################################################################
 
 ifeq ($(obj)include/config.mk,$(wildcard $(obj)include/config.mk))
@@ -400,6 +403,10 @@ tags ctags:
 etags:
 		etags -a -o $(obj)etags `find $(SUBDIRS) $(TAG_SUBDIRS) \
 						-name '*.[ch]' -print`
+cscope:
+		find $(SUBDIRS) $(TAG_SUBDIRS) -name '*.[ch]' -print \
+						> cscope.files
+		cscope -b -q -k
 
 $(obj)System.map:	$(obj)u-boot
 		@$(NM) $< | \
@@ -427,7 +434,7 @@ else	# !config.mk
 all $(obj)u-boot.hex $(obj)u-boot.srec $(obj)u-boot.bin \
 $(obj)u-boot.img $(obj)u-boot.dis $(obj)u-boot \
 $(SUBDIRS) $(VERSION_FILE) gdbtools updater env depend \
-dep tags ctags etags $(obj)System.map:
+dep tags ctags etags cscope $(obj)System.map:
 	@echo "System not configured - see README" >&2
 	@ exit 1
 endif	# config.mk
@@ -733,8 +740,15 @@ motionpro_config:	unconfig
 #########################################################################
 ## MPC512x Systems
 #########################################################################
-ads5121_config: unconfig
-	@$(MKCONFIG) ads5121 ppc mpc512x ads5121
+ads5121_config \
+ads5121_PCI_config \
+	:		 unconfig
+	@echo "" >$(obj)include/config.h
+	@if [ "$(findstring _PCI_,$@)" ] ; then \
+		echo "#define CONFIG_PCI"  >>$(obj)include/config.h ; \
+		$(XECHO) "... with PCI enabled" ; \
+	fi
+	@$(MKCONFIG) -a ads5121 ppc mpc512x ads5121
 
 
 #########################################################################
@@ -2893,28 +2907,20 @@ clean:
 		\( -name 'core' -o -name '*.bak' -o -name '*~' \
 		-o -name '*.o'  -o -name '*.a'  \) -print \
 		| xargs rm -f
-	@rm -f $(obj)examples/hello_world $(obj)examples/timer \
-	      $(obj)examples/eepro100_eeprom $(obj)examples/sched \
-	      $(obj)examples/mem_to_mem_idma2intr $(obj)examples/82559_eeprom \
-	      $(obj)examples/smc91111_eeprom $(obj)examples/interrupt \
-	      $(obj)examples/test_burst
-	@rm -f $(obj)tools/img2srec $(obj)tools/mkimage $(obj)tools/envcrc \
-		$(obj)tools/gen_eth_addr $(obj)tools/ubsha1
-	@rm -f $(obj)tools/mpc86x_clk $(obj)tools/ncb
-	@rm -f $(obj)tools/easylogo/easylogo $(obj)tools/bmp_logo
-	@rm -f $(obj)tools/gdb/astest $(obj)tools/gdb/gdbcont $(obj)tools/gdb/gdbsend
-	@rm -f $(obj)tools/env/fw_printenv $(obj)tools/env/fw_setenv
-	@rm -f $(obj)board/cray/L1/bootscript.c $(obj)board/cray/L1/bootscript.image
-	@rm -f $(obj)board/netstar/eeprom $(obj)board/netstar/crcek $(obj)board/netstar/crcit
-	@rm -f $(obj)board/netstar/*.srec $(obj)board/netstar/*.bin
-	@rm -f $(obj)board/trab/trab_fkt $(obj)board/voiceblue/eeprom
-	@rm -f $(obj)board/integratorap/u-boot.lds $(obj)board/integratorcp/u-boot.lds
-	@rm -f $(obj)board/bf533-ezkit/u-boot.lds $(obj)board/bf533-stamp/u-boot.lds
-	@rm -f $(obj)board/bf537-stamp/u-boot.lds $(obj)board/bf561-ezkit/u-boot.lds
-	@rm -f $(obj)include/bmp_logo.h
-	@rm -f $(obj)nand_spl/u-boot-spl $(obj)nand_spl/u-boot-spl.map
-	@rm -f $(obj)onenand_ipl/onenand-ipl $(obj)onenand_ipl/onenand-ipl.bin \
-		$(obj)onenand_ipl/onenand-ipl-2k.bin $(obj)onenand_ipl/onenand-ipl.map
+	@cd $(obj)examples/ && rm -f hello_world timer eepro100_eeprom sched \
+	      mem_to_mem_idma2intr 82559_eeprom smc91111_eeprom interrupt \
+	      test_burst
+	@cd $(obj)tools/ && rm -f bmp_logo easylogo/easylogo \
+		env/{fw_printenv,fw_setenv} envcrc gdb/{astest,gdbcont,gdbsend} \
+		gen_eth_addr img2srec mkimage mpc86x_clk ncb ubsha1
+	@cd $(obj)board/ && rm -f cray/L1/{bootscript.c,bootscript.image} \
+		netstar/{eeprom,crcek,crcit,*.srec,*.bin} \
+		trab/trab_fkt voiceblue/eeprom \
+		{integratorap,integratorcp}/u-boot.lds integratorcp/u-boot.lds \
+		{bf533-ezkit,bf533-stamp,bf537-stamp,bf561-ezkit}/u-boot.lds
+	@rm -f $(obj)include/bmp_logo.h $(obj)nand_spl/{u-boot-spl,u-boot-spl.map}
+	@cd $(obj)onenand_ipl/ && rm -f onenand-ipl onenand-ipl.bin \
+		onenand-ipl-2k.bin onenand-ipl.map
 	@rm -f $(obj)api_examples/demo $(VERSION_FILE)
 
 clobber:	clean
@@ -2922,11 +2928,11 @@ clobber:	clean
 		-o -name '*.srec' -o -name '*.bin' -o -name u-boot.img \) \
 		-print0 \
 		| xargs -0 rm -f
-	@rm -f $(OBJS) $(obj)*.bak $(obj)ctags $(obj)etags $(obj)TAGS
-	@rm -fr $(obj)*.*~
+	@rm -f $(OBJS) $(obj)*.bak $(obj)ctags $(obj)etags $(obj)TAGS \
+		$(obj)cscope.* $(obj)*.*~
 	@rm -f $(obj)u-boot $(obj)u-boot.map $(obj)u-boot.hex $(ALL)
-	@rm -f $(obj)tools/crc32.c $(obj)tools/environment.c $(obj)tools/env/crc32.c $(obj)tools/sha1.c
-	@rm -f $(obj)tools/inca-swap-bytes $(obj)cpu/mpc824x/bedbug_603e.c
+	@rm -f $(obj)tools/{crc32.c,environment.c,env/crc32.c,sha1.c,inca-swap-bytes}
+	@rm -f $(obj)cpu/mpc824x/bedbug_603e.c
 	@rm -f $(obj)include/asm/proc $(obj)include/asm/arch $(obj)include/asm
 	@[ ! -d $(obj)nand_spl ] || find $(obj)nand_spl -lname "*" -print | xargs rm -f
 	@[ ! -d $(obj)onenand_ipl ] || find $(obj)onenand_ipl -lname "*" -print | xargs rm -f

board/actux1/actux1.c

@@ -89,7 +89,6 @@ int board_init (void)
  */
 int checkboard (void)
 {
-	char revision;
 	char *s = getenv ("serial#");
 
 	puts ("Board: AcTux-1 rev.");

board/actux2/actux2.c

@@ -96,11 +96,15 @@ int board_init (void)
  */
 int checkboard (void)
 {
-	char revision;
 	char *s = getenv ("serial#");
 
 	puts ("Board: AcTux-2 rev.");
 	putc (ACTUX2_BOARDREL + 'A' - 1);
+
+	if (s != NULL) {
+		puts (", serial# ");
+		puts (s);
+	}
 	putc ('\n');
 
 	return (0);
@@ -127,8 +131,6 @@ u32 get_board_rev (void)
 
 void reset_phy (void)
 {
-	int i;
-
 	/* init IcPlus IP175C ethernet switch to native IP175C mode */
 	miiphy_write ("NPE0", 29, 31, 0x175C);
 }

board/actux3/actux3.c

@@ -111,7 +111,6 @@ int board_init (void)
  */
 int checkboard (void)
 {
-	char revision;
 	char *s = getenv ("serial#");
 
 	puts ("Board: AcTux-3 rev.");

board/ads5121/Makefile

@@ -25,8 +25,10 @@ include $(TOPDIR)/config.mk
 
 LIB	= $(obj)lib$(BOARD).a
 
-COBJS	:= $(BOARD).o
+COBJS-y	:= $(BOARD).o
+COBJS-$(CONFIG_PCI) += pci.o
 
+COBJS	:= $(COBJS-y)
 SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
 OBJS	:= $(addprefix $(obj),$(COBJS))
 SOBJS	:= $(addprefix $(obj),$(SOBJS))

board/ads5121/ads5121.c

@@ -34,6 +34,7 @@
 			 CLOCK_SCCR1_PSCFIFO_EN |			\
 			 CLOCK_SCCR1_DDR_EN |				\
 			 CLOCK_SCCR1_FEC_EN |				\
+			 CLOCK_SCCR1_PCI_EN |				\
 			 CLOCK_SCCR1_TPR_EN)
 
 #define SCCR2_CLOCKS_EN	(CLOCK_SCCR2_MEM_EN |		\

board/ads5121/pci.c

@@ -0,0 +1,213 @@
+/*
+ * Copyright (C) Freescale Semiconductor, Inc. 2006, 2007. All rights reserved.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+
+#include <asm/mmu.h>
+#include <asm/global_data.h>
+#include <pci.h>
+#if defined(CONFIG_OF_LIBFDT)
+#include <libfdt.h>
+#include <fdt_support.h>
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* System RAM mapped to PCI space */
+#define CONFIG_PCI_SYS_MEM_BUS	CFG_SDRAM_BASE
+#define CONFIG_PCI_SYS_MEM_PHYS	CFG_SDRAM_BASE
+
+static struct pci_controller pci_hose;
+
+
+/**************************************************************************
+ * pci_init_board()
+ *
+ */
+void
+pci_init_board(void)
+{
+	volatile immap_t *immr = (immap_t *) CFG_IMMR;
+	volatile law512x_t *pci_law;
+	volatile pot512x_t *pci_pot;
+	volatile pcictrl512x_t *pci_ctrl;
+	volatile pciconf512x_t *pci_conf;
+	u16 reg16;
+	u32 reg32;
+	u32 dev;
+	struct pci_controller *hose;
+
+	/* Set PCI divider for 33MHz */
+	reg32 = immr->clk.scfr[0];
+	reg32 &= ~(SCFR1_PCI_DIV_MASK);
+	reg32 |= SCFR1_PCI_DIV << SCFR1_PCI_DIV_SHIFT;
+	immr->clk.scfr[0] = reg32;
+
+	pci_law = immr->sysconf.pcilaw;
+	pci_pot = immr->ios.pot;
+	pci_ctrl = &immr->pci_ctrl;
+	pci_conf = &immr->pci_conf;
+
+	hose = &pci_hose;
+
+	/*
+	 * Release PCI RST Output signal
+	 */
+	pci_ctrl->gcr = 0;
+	udelay(2000);
+	pci_ctrl->gcr = 1;
+
+	/* We need to wait at least a 1sec based on PCI specs */
+	{
+		int i;
+
+		for (i = 0; i < 1000; i++)
+			udelay(1000);
+	}
+
+	/*
+	 * Configure PCI Local Access Windows
+	 */
+	pci_law[0].bar = CFG_PCI_MEM_PHYS & LAWBAR_BAR;
+	pci_law[0].ar = LAWAR_EN | LAWAR_SIZE_512M;
+
+	pci_law[1].bar = CFG_PCI_IO_PHYS & LAWBAR_BAR;
+	pci_law[1].ar = LAWAR_EN | LAWAR_SIZE_16M;
+
+	/*
+	 * Configure PCI Outbound Translation Windows
+	 */
+
+	/* PCI mem space - prefetch */
+	pci_pot[0].potar = (CFG_PCI_MEM_BASE >> 12) & POTAR_TA_MASK;
+	pci_pot[0].pobar = (CFG_PCI_MEM_PHYS >> 12) & POBAR_BA_MASK;
+	pci_pot[0].pocmr = POCMR_EN | POCMR_PRE | POCMR_CM_256M;
+
+	/* PCI IO space */
+	pci_pot[1].potar = (CFG_PCI_IO_BASE >> 12) & POTAR_TA_MASK;
+	pci_pot[1].pobar = (CFG_PCI_IO_PHYS >> 12) & POBAR_BA_MASK;
+	pci_pot[1].pocmr = POCMR_EN | POCMR_IO | POCMR_CM_16M;
+
+	/* PCI mmio - non-prefetch mem space */
+	pci_pot[2].potar = (CFG_PCI_MMIO_BASE >> 12) & POTAR_TA_MASK;
+	pci_pot[2].pobar = (CFG_PCI_MMIO_PHYS >> 12) & POBAR_BA_MASK;
+	pci_pot[2].pocmr = POCMR_EN | POCMR_CM_256M;
+
+	/*
+	 * Configure PCI Inbound Translation Windows
+	 */
+
+	/* we need RAM mapped to PCI space for the devices to
+	 * access main memory */
+	pci_ctrl[0].pitar1 = 0x0;
+	pci_ctrl[0].pibar1 = 0x0;
+	pci_ctrl[0].piebar1 = 0x0;
+	pci_ctrl[0].piwar1 = PIWAR_EN | PIWAR_PF | PIWAR_RTT_SNOOP |
+	    PIWAR_WTT_SNOOP | (__ilog2(gd->ram_size) - 1);
+
+	hose->first_busno = 0;
+	hose->last_busno = 0xff;
+
+	/* PCI memory prefetch space */
+	pci_set_region(hose->regions + 0,
+		       CFG_PCI_MEM_BASE,
+		       CFG_PCI_MEM_PHYS,
+		       CFG_PCI_MEM_SIZE,
+		       PCI_REGION_MEM|PCI_REGION_PREFETCH);
+
+	/* PCI memory space */
+	pci_set_region(hose->regions + 1,
+		       CFG_PCI_MMIO_BASE,
+		       CFG_PCI_MMIO_PHYS,
+		       CFG_PCI_MMIO_SIZE,
+		       PCI_REGION_MEM);
+
+	/* PCI IO space */
+	pci_set_region(hose->regions + 2,
+		       CFG_PCI_IO_BASE,
+		       CFG_PCI_IO_PHYS,
+		       CFG_PCI_IO_SIZE,
+		       PCI_REGION_IO);
+
+	/* System memory space */
+	pci_set_region(hose->regions + 3,
+		       CONFIG_PCI_SYS_MEM_BUS,
+		       CONFIG_PCI_SYS_MEM_PHYS,
+		       gd->ram_size,
+		       PCI_REGION_MEM | PCI_REGION_MEMORY);
+
+	hose->region_count = 4;
+
+	pci_setup_indirect(hose,
+			   (CFG_IMMR + 0x8300),
+			   (CFG_IMMR + 0x8304));
+
+	pci_register_hose(hose);
+
+	/*
+	 * Write to Command register
+	 */
+	reg16 = 0xff;
+	dev = PCI_BDF(hose->first_busno, 0, 0);
+	pci_hose_read_config_word(hose, dev, PCI_COMMAND, &reg16);
+	reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
+	pci_hose_write_config_word(hose, dev, PCI_COMMAND, reg16);
+
+	/*
+	 * Clear non-reserved bits in status register.
+	 */
+	pci_hose_write_config_word(hose, dev, PCI_STATUS, 0xffff);
+	pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, 0x80);
+	pci_hose_write_config_byte(hose, dev, PCI_CACHE_LINE_SIZE, 0x08);
+
+#ifdef CONFIG_PCI_SCAN_SHOW
+	printf("PCI:   Bus Dev VenId DevId Class Int\n");
+#endif
+	/*
+	 * Hose scan.
+	 */
+	hose->last_busno = pci_hose_scan(hose);
+}
+
+#if defined(CONFIG_OF_LIBFDT)
+void ft_pci_setup(void *blob, bd_t *bd)
+{
+	int nodeoffset;
+	int tmp[2];
+	const char *path;
+
+	nodeoffset = fdt_path_offset(blob, "/aliases");
+	if (nodeoffset >= 0) {
+		path = fdt_getprop(blob, nodeoffset, "pci", NULL);
+		if (path) {
+			tmp[0] = cpu_to_be32(pci_hose.first_busno);
+			tmp[1] = cpu_to_be32(pci_hose.last_busno);
+			do_fixup_by_path(blob, path, "bus-range",
+				&tmp, sizeof(tmp), 1);
+
+			tmp[0] = cpu_to_be32(gd->pci_clk);
+			do_fixup_by_path(blob, path, "clock-frequency",
+				&tmp, sizeof(tmp[0]), 1);
+		}
+	}
+}
+#endif /* CONFIG_OF_LIBFDT */

board/amcc/acadia/memory.c

@@ -117,7 +117,9 @@ long int initdram(int board_type)
 	return (CFG_MBYTES_RAM << 20);
 }
 
+#ifndef CONFIG_NAND_SPL
 int testdram(void)
 {
 	return (0);
 }
+#endif

board/mx1fs2/flash.c

@@ -173,7 +173,7 @@ flash_print_info(flash_info_t * info)
 	int i;
 	uchar *boottype;
 	uchar *bootletter;
-	uchar *fmt;
+	char *fmt;
 	uchar botbootletter[] = "B";
 	uchar topbootletter[] = "T";
 	uchar botboottype[] = "bottom boot sector";

board/mx1fs2/mx1fs2.c

@@ -48,7 +48,7 @@ static void logo_init(void)
 	imx_gpio_mode(PD14_PF_FLM_VSYNC);
 	imx_gpio_mode(PD13_PF_LP_HSYNC);
 	imx_gpio_mode(PD6_PF_LSCLK);
-	imx_gpio_mode(GPIO_PORTD | GPIO_OUT | GPIO_GPIO);
+	imx_gpio_mode(GPIO_PORTD | GPIO_OUT | GPIO_DR);
 	imx_gpio_mode(PD11_PF_CONTRAST);
 	imx_gpio_mode(PD10_PF_SPL_SPR);
 

board/sbc8548/sbc8548.c

@@ -56,9 +56,10 @@ int checkboard (void)
 {
 	volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
 	volatile ccsr_local_ecm_t *ecm = (void *)(CFG_MPC85xx_ECM_ADDR);
+	volatile u_char *rev= (void *)CFG_BD_REV;
 
 	printf ("Board: Wind River SBC8548 Rev. 0x%01x\n",
-			(volatile)(*(u_char *)CFG_BD_REV) >> 4);
+			(*rev) >> 4);
 
 	/*
 	 * Initialize local bus.
@@ -533,12 +534,12 @@ void
 ft_pci_setup(void *blob, bd_t *bd)
 {
 	int node, tmp[2];
-	const char *path;
 
 	node = fdt_path_offset(blob, "/aliases");
 	tmp[0] = 0;
 	if (node >= 0) {
 #ifdef CONFIG_PCI1
+		const char *path;
 		path = fdt_getprop(blob, node, "pci0", NULL);
 		if (path) {
 			tmp[1] = pci1_hose.last_busno - pci1_hose.first_busno;
@@ -546,6 +547,7 @@ ft_pci_setup(void *blob, bd_t *bd)
 		}
 #endif
 #ifdef CONFIG_PCIE1
+		const char *path;
 		path = fdt_getprop(blob, node, "pci1", NULL);
 		if (path) {
 			tmp[1] = pcie1_hose.last_busno - pcie1_hose.first_busno;

board/sbc8641d/sbc8641d.c

@@ -230,7 +230,8 @@ void pci_init_board(void)
 	volatile immap_t *immap = (immap_t *) CFG_CCSRBAR;
 	volatile ccsr_gur_t *gur = &immap->im_gur;
 	uint devdisr = gur->devdisr;
-	uint io_sel = (gur->pordevsr & MPC86xx_PORDEVSR_IO_SEL) >> 16;
+	uint io_sel = (gur->pordevsr & MPC8641_PORDEVSR_IO_SEL)
+		>> MPC8641_PORDEVSR_IO_SEL_SHIFT;
 
 #ifdef CONFIG_PCI1
 {
@@ -238,7 +239,8 @@ void pci_init_board(void)
 	extern void fsl_pci_init(struct pci_controller *hose);
 	struct pci_controller *hose = &pci1_hose;
 #ifdef DEBUG
-	uint host1_agent = (gur->porbmsr & MPC86xx_PORBMSR_HA) >> 17;
+	uint host1_agent = (gur->porbmsr & MPC8641_PORBMSR_HA)
+		>> MPC8641_PORBMSR_HA_SHIFT;
 	uint pex1_agent = (host1_agent == 0) || (host1_agent == 1);
 #endif
 	if ((io_sel == 2 || io_sel == 3 || io_sel == 5

board/tqm5200/tqm5200.c

@@ -43,6 +43,10 @@
 #include "mt48lc16m16a2-75.h"
 #endif
 
+#ifdef CONFIG_OF_LIBFDT
+#include <fdt_support.h>
+#endif /* CONFIG_OF_LIBFDT */
+
 DECLARE_GLOBAL_DATA_PTR;
 
 #ifdef CONFIG_PS2MULT
@@ -155,10 +159,13 @@ long int initdram (int board_type)
 	*(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize + 0x0000001c; /* 512MB */
 
 	/* find RAM size using SDRAM CS1 only */
-	sdram_start(0);
-	test1 = get_ram_size((long *)(CFG_SDRAM_BASE + dramsize), 0x20000000);
-	sdram_start(1);
-	test2 = get_ram_size((long *)(CFG_SDRAM_BASE + dramsize), 0x20000000);
+	if (!dramsize)
+		sdram_start(0);
+	test2 = test1 = get_ram_size((long *)(CFG_SDRAM_BASE + dramsize), 0x20000000);
+	if (!dramsize) {
+		sdram_start(1);
+		test2 = get_ram_size((long *)(CFG_SDRAM_BASE + dramsize), 0x20000000);
+	}
 	if (test1 > test2) {
 		sdram_start(0);
 		dramsize2 = test1;
@@ -792,5 +799,6 @@ int board_get_height (void)
 void ft_board_setup(void *blob, bd_t *bd)
 {
 	ft_cpu_setup(blob, bd);
+	fdt_fixup_memory(blob, (u64)bd->bi_memstart, (u64)bd->bi_memsize);
 }
 #endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */

cpu/mpc512x/speed.c

@@ -67,12 +67,14 @@ int get_clocks (void)
 	u8 cpmf;
 	u8 sys_div;
 	u8 ips_div;
+	u8 pci_div;
 	u32 ref_clk = CFG_MPC512X_CLKIN;
 	u32 spll;
 	u32 sys_clk;
 	u32 core_clk;
 	u32 csb_clk;
 	u32 ips_clk;
+	u32 pci_clk;
 
 	if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im)
 		return -1;
@@ -95,8 +97,16 @@ int get_clocks (void)
 		/* in case we cannot get a sane IPS divisor, fail gracefully */
 		ips_clk = 0;
 	}
+	pci_div = (im->clk.scfr[0] & SCFR1_PCI_DIV_MASK) >> SCFR1_PCI_DIV_SHIFT;
+	if (pci_div != 0) {
+		pci_clk = csb_clk / pci_div;
+	} else {
+		/* in case we cannot get a sane IPS divisor, fail gracefully */
+		pci_clk = 333333;
+	}
 
 	gd->ips_clk = ips_clk;
+	gd->pci_clk = pci_clk;
 	gd->csb_clk = csb_clk;
 	gd->cpu_clk = core_clk;
 	gd->bus_clk = csb_clk;
@@ -115,11 +125,12 @@ ulong get_bus_freq (ulong dummy)
 
 int do_clocks (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
 {
-	printf ("Clock configuration:\n");
-	printf ("  CPU:                 %4d MHz\n", gd->cpu_clk / 1000000);
-	printf ("  Coherent System Bus: %4d MHz\n", gd->csb_clk / 1000000);
-	printf ("  IPS Bus:             %4d MHz\n", gd->ips_clk / 1000000);
-	printf ("  DDR:                 %4d MHz\n", 2 * gd->csb_clk / 1000000);
+	printf("Clock configuration:\n");
+	printf("  CPU:                 %4d MHz\n", gd->cpu_clk / 1000000);
+	printf("  Coherent System Bus: %4d MHz\n", gd->csb_clk / 1000000);
+	printf("  IPS Bus:             %4d MHz\n", gd->ips_clk / 1000000);
+	printf("  PCI:                 %4d MHz\n", gd->pci_clk / 1000000);
+	printf("  DDR:                 %4d MHz\n", 2 * gd->csb_clk / 1000000);
 	return 0;
 }
 

cpu/mpc85xx/interrupts.c

@@ -91,7 +91,7 @@ int interrupt_init (void)
 	set_msr (get_msr () | MSR_EE);
 
 #ifdef CONFIG_INTERRUPTS
-	pic->iivpr1 = 0x810002;	/* 50220 enable ecm interrupts */
+	pic->iivpr1 = 0x810001;	/* 50220 enable ecm interrupts */
 	debug("iivpr1@%x = %x\n",&pic->iivpr1, pic->iivpr1);
 
 	pic->iivpr2 = 0x810002;	/* 50240 enable ddr interrupts */

cpu/mpc85xx/start.S

@@ -992,7 +992,6 @@ trap_reloc:
 
 	blr
 
-#ifdef CFG_INIT_RAM_LOCK
 .globl unlock_ram_in_cache
 unlock_ram_in_cache:
 	/* invalidate the INIT_RAM section */
@@ -1002,11 +1001,20 @@ unlock_ram_in_cache:
 	andi.	r4,r4,0x1ff
 	slwi	r4,r4,(10 - 1 - L1_CACHE_SHIFT)
 	mtctr	r4
-1:	icbi	r0,r3
-	dcbi	r0,r3
+1:	dcbi	r0,r3
 	addi	r3,r3,CFG_CACHELINE_SIZE
 	bdnz	1b
-	sync			/* Wait for all icbi to complete on bus */
+	sync
+
+	/* Invalidate the TLB entries for the cache */
+	lis	r3,CFG_INIT_RAM_ADDR@h
+	ori	r3,r3,CFG_INIT_RAM_ADDR@l
+	tlbivax	0,r3
+	addi	r3,r3,0x1000
+	tlbivax	0,r3
+	addi	r3,r3,0x1000
+	tlbivax	0,r3
+	addi	r3,r3,0x1000
+	tlbivax	0,r3
 	isync
 	blr
-#endif

cpu/ppc4xx/4xx_enet.c

@@ -487,6 +487,9 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis)
 #endif
 	u32 bd_cached;
 	u32 bd_uncached = 0;
+#ifdef CONFIG_4xx_DCACHE
+	static u32 last_used_ea = 0;
+#endif
 
 	EMAC_4XX_HW_PST hw_p = dev->priv;
 
@@ -850,7 +853,12 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis)
 
 #ifdef CONFIG_4xx_DCACHE
 		flush_dcache_range(bd_cached, bd_cached + MAL_ALLOC_SIZE);
-		bd_uncached = bis->bi_memsize;
+		if (!last_used_ea)
+			bd_uncached = bis->bi_memsize;
+		else
+			bd_uncached = last_used_ea + MAL_ALLOC_SIZE;
+
+		last_used_ea = bd_uncached;
 		program_tlb(bd_cached, bd_uncached, MAL_ALLOC_SIZE,
 			    TLB_WORD2_I_ENABLE);
 #else
@@ -967,9 +975,10 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis)
 	/* set transmit enable & receive enable */
 	out_be32((void *)EMAC_M0 + hw_p->hw_addr, EMAC_M0_TXE | EMAC_M0_RXE);
 
-	/* set receive fifo to 4k and tx fifo to 2k */
 	mode_reg = in_be32((void *)EMAC_M1 + hw_p->hw_addr);
-	mode_reg |= EMAC_M1_RFS_4K | EMAC_M1_TX_FIFO_2K;
+
+	/* set rx-/tx-fifo size */
+	mode_reg = (mode_reg & ~EMAC_MR1_FIFO_MASK) | EMAC_MR1_FIFO_SIZE;
 
 	/* set speed */
 	if (speed == _1000BASET) {

drivers/qe/uec_phy.c

@@ -574,6 +574,7 @@ void marvell_phy_interface_mode (struct eth_device *dev,
 {
 	uec_private_t *uec = (uec_private_t *) dev->priv;
 	struct uec_mii_info *mii_info;
+	u16 status;
 
 	if (!uec->mii_info) {
 		printf ("%s: the PHY not intialized\n", __FUNCTION__);
@@ -609,6 +610,13 @@ void marvell_phy_interface_mode (struct eth_device *dev,
 		phy_write (mii_info, 0x00, 0x8100);
 		udelay (1000000);
 	}
+
+	/* handle 88e1111 rev.B2 erratum 5.6 */
+	if (mii_info->autoneg) {
+		status = phy_read (mii_info, PHY_BMCR);
+		phy_write (mii_info, PHY_BMCR, status | PHY_BMCR_AUTON);
+	}
+	/* now the B2 will correctly report autoneg completion status */
 }
 
 void change_phy_interface_mode (struct eth_device *dev, enet_interface_e mode)

examples/Makefile

@@ -30,8 +30,12 @@ LOAD_ADDR = 0x40000
 endif
 
 ifeq ($(ARCH),arm)
+ifeq ($(BOARD),omap2420h4)
+LOAD_ADDR = 0x80300000
+else
 LOAD_ADDR = 0xc100000
 endif
+endif
 
 ifeq ($(ARCH),mips)
 LOAD_ADDR = 0x80200000 -T mips.lds

examples/stubs.c

@@ -190,10 +190,10 @@ extern unsigned long __bss_start, _end;
 
 void app_startup(char **argv)
 {
-	unsigned long * cp = &__bss_start;
+	unsigned char * cp = (unsigned char *) &__bss_start;
 
 	/* Zero out BSS */
-	while (cp < &_end) {
+	while (cp < (unsigned char *)&_end) {
 		*cp++ = 0;
 	}
 

fs/ext2/dev.c

@@ -96,8 +96,23 @@ int ext2fs_devread (int sector, int byte_offset, int byte_len, char *buf) {
 		sector++;
 	}
 
+	if (byte_len == 0)
+		return 1;
+
 	/*  read sector aligned part */
 	block_len = byte_len & ~(SECTOR_SIZE - 1);
+
+	if (block_len == 0) {
+		u8 p[SECTOR_SIZE];
+
+		block_len = SECTOR_SIZE;
+		ext2fs_block_dev_desc->block_read(ext2fs_block_dev_desc->dev,
+						  part_info.start + sector,
+						  1, (unsigned long *)p);
+		memcpy(buf, p, byte_len);
+		return 1;
+	}
+
 	if (ext2fs_block_dev_desc->block_read (ext2fs_block_dev_desc->dev,
 					       part_info.start + sector,
 					       block_len / SECTOR_SIZE,
@@ -106,6 +121,7 @@ int ext2fs_devread (int sector, int byte_offset, int byte_len, char *buf) {
 		printf (" ** ext2fs_devread() read error - block\n");
 		return (0);
 	}
+	block_len = byte_len & ~(SECTOR_SIZE - 1);
 	buf += block_len;
 	byte_len -= block_len;
 	sector += block_len / SECTOR_SIZE;

include/asm-arm/arch-imx/imx-regs.h

@@ -6,11 +6,11 @@
  *
  */
 
+#define IO_ADDRESS(x) ((x) | IMX_IO_BASE)
+
 # ifndef __ASSEMBLY__
-#  define __REG(x)	(*((volatile u32 *)(x)))
-# define __REG2(x,y)	\
-	( __builtin_constant_p(y) ? (__REG((x) + (y))) \
-			  : (*(volatile u32 *)((u32)&__REG(x) + (y))) )
+# define __REG(x)	(*((volatile u32 *)IO_ADDRESS(x)))
+# define __REG2(x,y)        (*(volatile u32 *)((u32)&__REG(x) + (y)))
 # else
 #  define __REG(x) (x)
 #  define __REG2(x,y) ((x)+(y))
@@ -87,14 +87,20 @@
 
 /* PLL registers */
 #define CSCR   __REG(IMX_PLL_BASE)        /* Clock Source Control Register */
+#define CSCR_SPLL_RESTART	(1<<22)
+#define CSCR_MPLL_RESTART	(1<<21)
+#define CSCR_SYSTEM_SEL		(1<<16)
+#define CSCR_BCLK_DIV		(0xf<<10)
+#define CSCR_MPU_PRESC		(1<<15)
+#define CSCR_SPEN		(1<<1)
+#define CSCR_MPEN		(1<<0)
+
 #define MPCTL0 __REG(IMX_PLL_BASE + 0x4)  /* MCU PLL Control Register 0 */
 #define MPCTL1 __REG(IMX_PLL_BASE + 0x8)  /* MCU PLL and System Clock Register 1 */
 #define SPCTL0 __REG(IMX_PLL_BASE + 0xc)  /* System PLL Control Register 0 */
 #define SPCTL1 __REG(IMX_PLL_BASE + 0x10) /* System PLL Control Register 1 */
 #define PCDR   __REG(IMX_PLL_BASE + 0x20) /* Peripheral Clock Divider Register */
 
-#define CSCR_MPLL_RESTART (1<<21)
-
 /*
  *  GPIO Module and I/O Multiplexer
  *  x = 0..3 for reg_A, reg_B, reg_C, reg_D
@@ -117,9 +123,12 @@
 #define SWR(x)     __REG2(IMX_GPIO_BASE + 0x3c, ((x) & 3) << 8)
 #define PUEN(x)    __REG2(IMX_GPIO_BASE + 0x40, ((x) & 3) << 8)
 
+#define GPIO_PORT_MAX  3
+
 #define GPIO_PIN_MASK 0x1f
 #define GPIO_PORT_MASK (0x3 << 5)
 
+#define GPIO_PORT_SHIFT 5
 #define GPIO_PORTA (0<<5)
 #define GPIO_PORTB (1<<5)
 #define GPIO_PORTC (2<<5)
@@ -132,24 +141,37 @@
 #define GPIO_PF    (0<<9)
 #define GPIO_AF    (1<<9)
 
+#define GPIO_OCR_SHIFT 10
 #define GPIO_OCR_MASK (3<<10)
 #define GPIO_AIN   (0<<10)
 #define GPIO_BIN   (1<<10)
 #define GPIO_CIN   (2<<10)
-#define GPIO_GPIO  (3<<10)
+#define GPIO_DR    (3<<10)
 
-#define GPIO_AOUT  (1<<12)
-#define GPIO_BOUT  (1<<13)
+#define GPIO_AOUT_SHIFT 12
+#define GPIO_AOUT_MASK (3<<12)
+#define GPIO_AOUT     (0<<12)
+#define GPIO_AOUT_ISR (1<<12)
+#define GPIO_AOUT_0   (2<<12)
+#define GPIO_AOUT_1   (3<<12)
+
+#define GPIO_BOUT_SHIFT 14
+#define GPIO_BOUT_MASK (3<<14)
+#define GPIO_BOUT      (0<<14)
+#define GPIO_BOUT_ISR  (1<<14)
+#define GPIO_BOUT_0    (2<<14)
+#define GPIO_BOUT_1    (3<<14)
+
+#define GPIO_GIUS      (1<<16)
 
 /* assignements for GPIO alternate/primary functions */
 
 /* FIXME: This list is not completed. The correct directions are
  * missing on some (many) pins
  */
-#define PA0_PF_A24           ( GPIO_PORTA | GPIO_PF | 0 )
-#define PA0_AIN_SPI2_CLK     ( GPIO_PORTA | GPIO_OUT | GPIO_AIN | 0 )
+#define PA0_AIN_SPI2_CLK     ( GPIO_GIUS | GPIO_PORTA | GPIO_OUT | 0 )
 #define PA0_AF_ETMTRACESYNC  ( GPIO_PORTA | GPIO_AF | 0 )
-#define PA1_AOUT_SPI2_RXD    ( GPIO_PORTA | GPIO_IN | GPIO_AOUT | 1 )
+#define PA1_AOUT_SPI2_RXD    ( GPIO_GIUS | GPIO_PORTA | GPIO_IN | 1 )
 #define PA1_PF_TIN           ( GPIO_PORTA | GPIO_PF | 1 )
 #define PA2_PF_PWM0          ( GPIO_PORTA | GPIO_OUT | GPIO_PF | 2 )
 #define PA3_PF_CSI_MCLK      ( GPIO_PORTA | GPIO_PF | 3 )
@@ -167,7 +189,7 @@
 #define PA15_PF_I2C_SDA      ( GPIO_PORTA | GPIO_OUT | GPIO_PF | 15 )
 #define PA16_PF_I2C_SCL      ( GPIO_PORTA | GPIO_OUT | GPIO_PF | 16 )
 #define PA17_AF_ETMTRACEPKT4 ( GPIO_PORTA | GPIO_AF | 17 )
-#define PA17_AIN_SPI2_SS     ( GPIO_PORTA | GPIO_AIN | 17 )
+#define PA17_AIN_SPI2_SS     ( GPIO_GIUS | GPIO_PORTA | GPIO_OUT | 17 )
 #define PA18_AF_ETMTRACEPKT5 ( GPIO_PORTA | GPIO_AF | 18 )
 #define PA19_AF_ETMTRACEPKT6 ( GPIO_PORTA | GPIO_AF | 19 )
 #define PA20_AF_ETMTRACEPKT7 ( GPIO_PORTA | GPIO_AF | 20 )
@@ -196,11 +218,11 @@
 #define PB9_AF_MS_PI1        ( GPIO_PORTB | GPIO_AF | 9 )
 #define PB10_PF_SD_DAT2      ( GPIO_PORTB | GPIO_PF | GPIO_PUEN  | 10 )
 #define PB10_AF_MS_SCLKI     ( GPIO_PORTB | GPIO_AF | 10 )
-#define PB11_PF_SD_DAT3      ( GPIO_PORTB | GPIO_PF | GPIO_PUEN  | 11 )
+#define PB11_PF_SD_DAT3      ( GPIO_PORTB | GPIO_PF | 11 )
 #define PB11_AF_MS_SDIO      ( GPIO_PORTB | GPIO_AF | 11 )
-#define PB12_PF_SD_CLK       ( GPIO_PORTB | GPIO_PF | GPIO_OUT | 12 )
+#define PB12_PF_SD_CLK       ( GPIO_PORTB | GPIO_PF | 12 )
 #define PB12_AF_MS_SCLK0     ( GPIO_PORTB | GPIO_AF | 12 )
-#define PB13_PF_SD_CMD       ( GPIO_PORTB | GPIO_PF | GPIO_OUT | GPIO_PUEN | 13 )
+#define PB13_PF_SD_CMD       ( GPIO_PORTB | GPIO_PF | GPIO_PUEN | 13 )
 #define PB13_AF_MS_BS        ( GPIO_PORTB | GPIO_AF | 13 )
 #define PB14_AF_SSI_RXFS     ( GPIO_PORTB | GPIO_AF | 14 )
 #define PB15_AF_SSI_RXCLK    ( GPIO_PORTB | GPIO_AF | 15 )
@@ -235,19 +257,27 @@
 #define PC15_PF_SPI1_SS      ( GPIO_PORTC | GPIO_PF | 15 )
 #define PC16_PF_SPI1_MISO    ( GPIO_PORTC | GPIO_PF | 16 )
 #define PC17_PF_SPI1_MOSI    ( GPIO_PORTC | GPIO_PF | 17 )
+#define PC24_BIN_UART3_RI    ( GPIO_GIUS | GPIO_PORTC | GPIO_OUT | GPIO_BIN | 24 )
+#define PC25_BIN_UART3_DSR   ( GPIO_GIUS | GPIO_PORTC | GPIO_OUT | GPIO_BIN | 25 )
+#define PC26_AOUT_UART3_DTR  ( GPIO_GIUS | GPIO_PORTC | GPIO_IN | 26 )
+#define PC27_BIN_UART3_DCD   ( GPIO_GIUS | GPIO_PORTC | GPIO_OUT | GPIO_BIN | 27 )
+#define PC28_BIN_UART3_CTS   ( GPIO_GIUS | GPIO_PORTC | GPIO_OUT | GPIO_BIN | 28 )
+#define PC29_AOUT_UART3_RTS  ( GPIO_GIUS | GPIO_PORTC | GPIO_IN | 29 )
+#define PC30_BIN_UART3_TX    ( GPIO_GIUS | GPIO_PORTC | GPIO_BIN | 30 )
+#define PC31_AOUT_UART3_RX   ( GPIO_GIUS | GPIO_PORTC | GPIO_IN | 31)
 #define PD6_PF_LSCLK         ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 6 )
 #define PD7_PF_REV           ( GPIO_PORTD | GPIO_PF | 7 )
-#define PD7_AF_UART2_DTR     ( GPIO_PORTD | GPIO_IN | GPIO_AF | 7 )
-#define PD7_AIN_SPI2_SCLK    ( GPIO_PORTD | GPIO_AIN | 7 )
+#define PD7_AF_UART2_DTR     ( GPIO_GIUS | GPIO_PORTD | GPIO_IN | GPIO_AF | 7 )
+#define PD7_AIN_SPI2_SCLK    ( GPIO_GIUS | GPIO_PORTD | GPIO_AIN | 7 )
 #define PD8_PF_CLS           ( GPIO_PORTD | GPIO_PF | 8 )
 #define PD8_AF_UART2_DCD     ( GPIO_PORTD | GPIO_OUT | GPIO_AF | 8 )
-#define PD8_AIN_SPI2_SS      ( GPIO_PORTD | GPIO_AIN | 8 )
+#define PD8_AIN_SPI2_SS      ( GPIO_GIUS | GPIO_PORTD | GPIO_AIN | 8 )
 #define PD9_PF_PS            ( GPIO_PORTD | GPIO_PF | 9 )
 #define PD9_AF_UART2_RI      ( GPIO_PORTD | GPIO_OUT | GPIO_AF | 9 )
-#define PD9_AOUT_SPI2_RXD    ( GPIO_PORTD | GPIO_IN | GPIO_AOUT | 9 )
+#define PD9_AOUT_SPI2_RXD    ( GPIO_GIUS | GPIO_PORTD | GPIO_IN | 9 )
 #define PD10_PF_SPL_SPR      ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 10 )
 #define PD10_AF_UART2_DSR    ( GPIO_PORTD | GPIO_OUT | GPIO_AF | 10 )
-#define PD10_AIN_SPI2_TXD    ( GPIO_PORTD | GPIO_OUT | GPIO_AIN | 10 )
+#define PD10_AIN_SPI2_TXD    ( GPIO_GIUS | GPIO_PORTD | GPIO_OUT | 10 )
 #define PD11_PF_CONTRAST     ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 11 )
 #define PD12_PF_ACD_OE       ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 12 )
 #define PD13_PF_LP_HSYNC     ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 13 )
@@ -269,7 +299,31 @@
 #define PD29_PF_LD14         ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 29 )
 #define PD30_PF_LD15         ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 30 )
 #define PD31_PF_TMR2OUT      ( GPIO_PORTD | GPIO_PF | 31 )
-#define PD31_BIN_SPI2_TXD    ( GPIO_PORTD | GPIO_BIN | 31 )
+#define PD31_BIN_SPI2_TXD    ( GPIO_GIUS | GPIO_PORTD | GPIO_BIN | 31 )
+
+/*
+ * PWM controller
+ */
+#define PWMC	__REG(IMX_PWM_BASE + 0x00)	/* PWM Control Register		*/
+#define PWMS	__REG(IMX_PWM_BASE + 0x04)	/* PWM Sample Register		*/
+#define PWMP	__REG(IMX_PWM_BASE + 0x08)	/* PWM Period Register		*/
+#define PWMCNT	__REG(IMX_PWM_BASE + 0x0C)	/* PWM Counter Register		*/
+
+#define PWMC_HCTR		(0x01<<18)		/* Halfword FIFO Data Swapping	*/
+#define PWMC_BCTR		(0x01<<17)		/* Byte FIFO Data Swapping	*/
+#define PWMC_SWR		(0x01<<16)		/* Software Reset		*/
+#define PWMC_CLKSRC		(0x01<<15)		/* Clock Source			*/
+#define PWMC_PRESCALER(x)	(((x-1) & 0x7F) << 8)	/* PRESCALER			*/
+#define PWMC_IRQ		(0x01<< 7)		/* Interrupt Request		*/
+#define PWMC_IRQEN		(0x01<< 6)		/* Interrupt Request Enable	*/
+#define PWMC_FIFOAV		(0x01<< 5)		/* FIFO Available		*/
+#define PWMC_EN			(0x01<< 4)		/* Enables/Disables the PWM	*/
+#define PWMC_REPEAT(x)		(((x) & 0x03) << 2)	/* Sample Repeats		*/
+#define PWMC_CLKSEL(x)		(((x) & 0x03) << 0)	/* Clock Selection		*/
+
+#define PWMS_SAMPLE(x)		((x) & 0xFFFF)		/* Contains a two-sample word	*/
+#define PWMP_PERIOD(x)		((x) & 0xFFFF)		/* Represents the PWM's period	*/
+#define PWMC_COUNTER(x)		((x) & 0xFFFF)		/* Represents the current count value	*/
 
 /*
  *  DMA Controller
@@ -291,7 +345,7 @@
 #define SAR(x)  __REG2( IMX_DMAC_BASE + 0x80, (x) << 6)	/* Source Address Registers */
 #define DAR(x)  __REG2( IMX_DMAC_BASE + 0x84, (x) << 6)	/* Destination Address Registers */
 #define CNTR(x) __REG2( IMX_DMAC_BASE + 0x88, (x) << 6)	/* Count Registers */
-#define CCR(x)  __REG2( IMX_DMAC_BASE + 0x8c, (x) << 6)	/*<EFBFBD>Control Registers */
+#define CCR(x)  __REG2( IMX_DMAC_BASE + 0x8c, (x) << 6)	/* Control Registers */
 #define RSSR(x) __REG2( IMX_DMAC_BASE + 0x90, (x) << 6)	/* Request source select Registers */
 #define BLR(x)  __REG2( IMX_DMAC_BASE + 0x94, (x) << 6)	/* Burst length Registers */
 #define RTOR(x) __REG2( IMX_DMAC_BASE + 0x98, (x) << 6)	/* Request timeout Registers */
@@ -401,8 +455,11 @@
 #define POS_POS(x)      ((x) & 1f)
 
 #define LCDC_LSCR1	__REG(IMX_LCDC_BASE+0x28)
-#define LSCR1_GRAY1(x)  (((x) & 0xf) << 4)
-#define LSCR1_GRAY2(x)  ((x) & 0xf)
+#define LSCR1_PS_RISE_DELAY(x)    (((x) & 0x7f) << 26)
+#define LSCR1_CLS_RISE_DELAY(x)   (((x) & 0x3f) << 16)
+#define LSCR1_REV_TOGGLE_DELAY(x) (((x) & 0xf) << 8)
+#define LSCR1_GRAY2(x)            (((x) & 0xf) << 4)
+#define LSCR1_GRAY1(x)            (((x) & 0xf))
 
 #define LCDC_PWMR	__REG(IMX_LCDC_BASE+0x2C)
 #define PWMR_CLS(x)     (((x) & 0x1ff) << 16)
@@ -478,9 +535,9 @@
 #define  UCR1_UARTCLKEN  (1<<2)	 /* UART clock enabled */
 #define  UCR1_DOZE       (1<<1)	 /* Doze */
 #define  UCR1_UARTEN     (1<<0)	 /* UART enabled */
-#define  UCR2_ESCI     	 (1<<15) /* Escape seq interrupt enable */
-#define  UCR2_IRTS  	 (1<<14) /* Ignore RTS pin */
-#define  UCR2_CTSC  	 (1<<13) /* CTS pin control */
+#define  UCR2_ESCI	 (1<<15) /* Escape seq interrupt enable */
+#define  UCR2_IRTS	 (1<<14) /* Ignore RTS pin */
+#define  UCR2_CTSC	 (1<<13) /* CTS pin control */
 #define  UCR2_CTS        (1<<12) /* Clear to send */
 #define  UCR2_ESCEN      (1<<11) /* Escape enable */
 #define  UCR2_PREN       (1<<8) /* Parity enable */
@@ -490,8 +547,8 @@
 #define  UCR2_RTSEN      (1<<4)	/* Request to send interrupt enable */
 #define  UCR2_TXEN       (1<<2)	/* Transmitter enabled */
 #define  UCR2_RXEN       (1<<1)	/* Receiver enabled */
-#define  UCR2_SRST 	 (1<<0)	/* SW reset */
-#define  UCR3_DTREN 	 (1<<13) /* DTR interrupt enable */
+#define  UCR2_SRST	 (1<<0)	/* SW reset */
+#define  UCR3_DTREN	 (1<<13) /* DTR interrupt enable */
 #define  UCR3_PARERREN   (1<<12) /* Parity enable */
 #define  UCR3_FRAERREN   (1<<11) /* Frame error interrupt enable */
 #define  UCR3_DSR        (1<<10) /* Data set ready */
@@ -501,51 +558,51 @@
 #define  UCR3_RXDSEN	 (1<<6)  /* Receive status interrupt enable */
 #define  UCR3_AIRINTEN   (1<<5)  /* Async IR wake interrupt enable */
 #define  UCR3_AWAKEN	 (1<<4)  /* Async wake interrupt enable */
-#define  UCR3_REF25 	 (1<<3)  /* Ref freq 25 MHz */
-#define  UCR3_REF30 	 (1<<2)  /* Ref Freq 30 MHz */
-#define  UCR3_INVT  	 (1<<1)  /* Inverted Infrared transmission */
-#define  UCR3_BPEN  	 (1<<0)  /* Preset registers enable */
+#define  UCR3_REF25	 (1<<3)  /* Ref freq 25 MHz */
+#define  UCR3_REF30	 (1<<2)  /* Ref Freq 30 MHz */
+#define  UCR3_INVT	 (1<<1)  /* Inverted Infrared transmission */
+#define  UCR3_BPEN	 (1<<0)  /* Preset registers enable */
 #define  UCR4_CTSTL_32   (32<<10) /* CTS trigger level (32 chars) */
-#define  UCR4_INVR  	 (1<<9)  /* Inverted infrared reception */
-#define  UCR4_ENIRI 	 (1<<8)  /* Serial infrared interrupt enable */
-#define  UCR4_WKEN  	 (1<<7)  /* Wake interrupt enable */
-#define  UCR4_REF16 	 (1<<6)  /* Ref freq 16 MHz */
-#define  UCR4_IRSC  	 (1<<5) /* IR special case */
-#define  UCR4_TCEN  	 (1<<3) /* Transmit complete interrupt enable */
-#define  UCR4_BKEN  	 (1<<2) /* Break condition interrupt enable */
-#define  UCR4_OREN  	 (1<<1) /* Receiver overrun interrupt enable */
-#define  UCR4_DREN  	 (1<<0) /* Recv data ready interrupt enable */
+#define  UCR4_INVR	 (1<<9)  /* Inverted infrared reception */
+#define  UCR4_ENIRI	 (1<<8)  /* Serial infrared interrupt enable */
+#define  UCR4_WKEN	 (1<<7)  /* Wake interrupt enable */
+#define  UCR4_REF16	 (1<<6)  /* Ref freq 16 MHz */
+#define  UCR4_IRSC	 (1<<5) /* IR special case */
+#define  UCR4_TCEN	 (1<<3) /* Transmit complete interrupt enable */
+#define  UCR4_BKEN	 (1<<2) /* Break condition interrupt enable */
+#define  UCR4_OREN	 (1<<1) /* Receiver overrun interrupt enable */
+#define  UCR4_DREN	 (1<<0) /* Recv data ready interrupt enable */
 #define  UFCR_RXTL_SHF   0      /* Receiver trigger level shift */
 #define  UFCR_RFDIV      (7<<7) /* Reference freq divider mask */
 #define  UFCR_TXTL_SHF   10     /* Transmitter trigger level shift */
 #define  USR1_PARITYERR  (1<<15) /* Parity error interrupt flag */
-#define  USR1_RTSS  	 (1<<14) /* RTS pin status */
-#define  USR1_TRDY  	 (1<<13) /* Transmitter ready interrupt/dma flag */
-#define  USR1_RTSD  	 (1<<12) /* RTS delta */
-#define  USR1_ESCF  	 (1<<11) /* Escape seq interrupt flag */
+#define  USR1_RTSS	 (1<<14) /* RTS pin status */
+#define  USR1_TRDY	 (1<<13) /* Transmitter ready interrupt/dma flag */
+#define  USR1_RTSD	 (1<<12) /* RTS delta */
+#define  USR1_ESCF	 (1<<11) /* Escape seq interrupt flag */
 #define  USR1_FRAMERR    (1<<10) /* Frame error interrupt flag */
 #define  USR1_RRDY       (1<<9)	/* Receiver ready interrupt/dma flag */
 #define  USR1_TIMEOUT    (1<<7)	/* Receive timeout interrupt status */
-#define  USR1_RXDS  	 (1<<6)	/* Receiver idle interrupt flag */
+#define  USR1_RXDS	 (1<<6)	/* Receiver idle interrupt flag */
 #define  USR1_AIRINT	 (1<<5)	/* Async IR wake interrupt flag */
-#define  USR1_AWAKE 	 (1<<4)	/* Aysnc wake interrupt flag */
-#define  USR2_ADET  	 (1<<15) /* Auto baud rate detect complete */
-#define  USR2_TXFE  	 (1<<14) /* Transmit buffer FIFO empty */
-#define  USR2_DTRF  	 (1<<13) /* DTR edge interrupt flag */
-#define  USR2_IDLE  	 (1<<12) /* Idle condition */
-#define  USR2_IRINT 	 (1<<8)	/* Serial infrared interrupt flag */
-#define  USR2_WAKE  	 (1<<7)	/* Wake */
-#define  USR2_RTSF  	 (1<<4)	/* RTS edge interrupt flag */
-#define  USR2_TXDC  	 (1<<3)	/* Transmitter complete */
-#define  USR2_BRCD  	 (1<<2)	/* Break condition */
+#define  USR1_AWAKE	 (1<<4)	/* Aysnc wake interrupt flag */
+#define  USR2_ADET	 (1<<15) /* Auto baud rate detect complete */
+#define  USR2_TXFE	 (1<<14) /* Transmit buffer FIFO empty */
+#define  USR2_DTRF	 (1<<13) /* DTR edge interrupt flag */
+#define  USR2_IDLE	 (1<<12) /* Idle condition */
+#define  USR2_IRINT	 (1<<8)	/* Serial infrared interrupt flag */
+#define  USR2_WAKE	 (1<<7)	/* Wake */
+#define  USR2_RTSF	 (1<<4)	/* RTS edge interrupt flag */
+#define  USR2_TXDC	 (1<<3)	/* Transmitter complete */
+#define  USR2_BRCD	 (1<<2)	/* Break condition */
 #define  USR2_ORE        (1<<1)	/* Overrun error */
 #define  USR2_RDR        (1<<0)	/* Recv data ready */
 #define  UTS_FRCPERR	 (1<<13) /* Force parity error */
 #define  UTS_LOOP        (1<<12) /* Loop tx and rx */
 #define  UTS_TXEMPTY	 (1<<6)	/* TxFIFO empty */
 #define  UTS_RXEMPTY	 (1<<5)	/* RxFIFO empty */
-#define  UTS_TXFULL 	 (1<<4)	/* TxFIFO full */
-#define  UTS_RXFULL 	 (1<<3)	/* RxFIFO full */
+#define  UTS_TXFULL	 (1<<4)	/* TxFIFO full */
+#define  UTS_RXFULL	 (1<<3)	/* RxFIFO full */
 #define  UTS_SOFTRST	 (1<<0)	/* Software reset */
 
 /* General purpose timers registers */

include/asm-i386/types.h

@@ -17,9 +17,9 @@ typedef unsigned short __u16;
 typedef __signed__ int __s32;
 typedef unsigned int __u32;
 
-#if defined(__GNUC__) && !defined(__STRICT_ANSI__)
-typedef __signed__ long long __s64;
-typedef unsigned long long __u64;
+#if defined(__GNUC__)
+__extension__ typedef __signed__ long long __s64;
+__extension__ typedef unsigned long long __u64;
 #endif
 
 /*

include/asm-microblaze/types.h

@@ -25,9 +25,9 @@ typedef unsigned short __u16;
 typedef __signed__ int __s32;
 typedef unsigned int __u32;
 
-#if defined(__GNUC__) && !defined(__STRICT_ANSI__)
-typedef __signed__ long long __s64;
-typedef unsigned long long __u64;
+#if defined(__GNUC__)
+__extension__ typedef __signed__ long long __s64;
+__extension__ typedef unsigned long long __u64;
 #endif
 
 /*

include/asm-nios/types.h

@@ -25,9 +25,9 @@ typedef unsigned short __u16;
 typedef __signed__ int __s32;
 typedef unsigned int __u32;
 
-#if defined(__GNUC__) && !defined(__STRICT_ANSI__)
-typedef __signed__ long long __s64;
-typedef unsigned long long __u64;
+#if defined(__GNUC__)
+__extension__ typedef __signed__ long long __s64;
+__extension__ typedef unsigned long long __u64;
 #endif
 
 /*

include/asm-nios2/types.h

@@ -25,9 +25,9 @@ typedef unsigned short __u16;
 typedef __signed__ int __s32;
 typedef unsigned int __u32;
 
-#if defined(__GNUC__) && !defined(__STRICT_ANSI__)
-typedef __signed__ long long __s64;
-typedef unsigned long long __u64;
+#if defined(__GNUC__)
+__extension__ typedef __signed__ long long __s64;
+__extension__ typedef unsigned long long __u64;
 #endif
 
 /*

include/asm-ppc/global_data.h

@@ -103,6 +103,7 @@ typedef	struct	global_data {
 #if defined(CONFIG_MPC512X)
 	u32 ips_clk;
 	u32 csb_clk;
+	u32 pci_clk;
 #endif /* CONFIG_MPC512X */
 #if defined(CONFIG_MPC8220)
 	unsigned long   bExtUart;

include/asm-ppc/immap_512x.h

@@ -29,7 +29,7 @@
 typedef struct law512x {
 	u32 bar;	/* Base Addr Register */
 	u32 ar;		/* Attributes Register */
-} law521x_t;
+} law512x_t;
 
 /*
  * System configuration registers
@@ -47,9 +47,9 @@ typedef struct sysconf512x {
 	u32 lpcs6aw;		/* LP CS6 Access Window */
 	u32 lpcs7aw;		/* LP CS7 Access Window */
 	u8 res1[0x1c];
-	law521x_t pcilaw[3];	/* PCI Local Access Window 0-2 Registers */
+	law512x_t pcilaw[3];	/* PCI Local Access Window 0-2 Registers */
 	u8 res2[0x28];
-	law521x_t ddrlaw;	/* DDR Local Access Window */
+	law512x_t ddrlaw;	/* DDR Local Access Window */
 	u8 res3[0x18];
 	u32 mbxbar;		/* MBX Base Address */
 	u32 srambar;		/* SRAM Base Address */
@@ -241,21 +241,70 @@ typedef struct dma512x {
  * PCI Software Configuration Registers
  */
 typedef struct pciconf512x {
-	u8 fixme[0x80];
+	u32 config_address;
+	u32 config_data;
+	u32 int_ack;
+	u8 res[116];
 } pciconf512x_t;
 
+/*
+ * PCI Outbound Translation Register
+ */
+typedef struct pci_outbound_window {
+	u32 potar;
+	u8 res0[4];
+	u32 pobar;
+	u8 res1[4];
+	u32 pocmr;
+	u8 res2[4];
+} pot512x_t;
+
 /*
  * Sequencer
  */
 typedef struct ios512x {
-	u8 fixme[0x100];
+	pot512x_t pot[6];
+	u8 res0[0x60];
+	u32 pmcr;
+	u8 res1[4];
+	u32 dtcr;
+	u8 res2[4];
 } ios512x_t;
 
 /*
  * PCI Controller
  */
 typedef struct pcictrl512x {
-	u8 fixme[0x100];
+	u32 esr;
+	u32 ecdr;
+	u32 eer;
+	u32 eatcr;
+	u32 eacr;
+	u32 eeacr;
+	u32 edlcr;
+	u32 edhcr;
+	u32 gcr;
+	u32 ecr;
+	u32 gsr;
+	u8 res0[12];
+	u32 pitar2;
+	u8 res1[4];
+	u32 pibar2;
+	u32 piebar2;
+	u32 piwar2;
+	u8 res2[4];
+	u32 pitar1;
+	u8 res3[4];
+	u32 pibar1;
+	u32 piebar1;
+	u32 piwar1;
+	u8 res4[4];
+	u32 pitar0;
+	u8 res5[4];
+	u32 pibar0;
+	u8 res6[4];
+	u32 piwar0;
+	u8 res7[132];
 } pcictrl512x_t;
 
 

include/configs/ads5121.h

@@ -34,6 +34,9 @@
  * 0x3000_0000 - 0x3001_FFFF	SRAM (128 KB)
  * 0x8000_0000 - 0x803F_FFFF	IMMR (4 MB)
  * 0x8200_0000 - 0x8200_001F	CPLD (32 B)
+ * 0x8400_0000 - 0x82FF_FFFF	PCI I/O space (16 MB)
+ * 0xA000_0000 - 0xAFFF_FFFF	PCI memory space (256 MB)
+ * 0xB000_0000 - 0xBFFF_FFFF	PCI memory mapped I/O space (256 MB)
  * 0xFC00_0000 - 0xFFFF_FFFF	NOR Boot FLASH (64 MB)
  */
 
@@ -43,7 +46,7 @@
 #define CONFIG_E300		1	/* E300 Family */
 #define CONFIG_MPC512X		1	/* MPC512X family */
 
-#undef CONFIG_PCI
+/* CONFIG_PCI is defined at config time */
 
 #define CFG_MPC512X_CLKIN	66000000	/* in Hz */
 
@@ -217,6 +220,31 @@
 #define CFG_PROMPT_HUSH_PS2 "> "
 #endif
 
+/*
+ * PCI
+ */
+#ifdef CONFIG_PCI
+
+/*
+ * General PCI
+ */
+#define CFG_PCI_MEM_BASE	0xA0000000
+#define CFG_PCI_MEM_PHYS	CFG_PCI_MEM_BASE
+#define CFG_PCI_MEM_SIZE	0x10000000	/* 256M */
+#define CFG_PCI_MMIO_BASE	(CFG_PCI_MEM_BASE + CFG_PCI_MEM_SIZE)
+#define CFG_PCI_MMIO_PHYS	CFG_PCI_MMIO_BASE
+#define CFG_PCI_MMIO_SIZE	0x10000000	/* 256M */
+#define CFG_PCI_IO_BASE		0x00000000
+#define CFG_PCI_IO_PHYS		0x84000000
+#define CFG_PCI_IO_SIZE		0x01000000	/* 16M */
+
+
+#define CONFIG_PCI_PNP			/* do pci plug-and-play */
+
+#define CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */
+
+#endif
+
 /* I2C */
 #define CONFIG_HARD_I2C			/* I2C with hardware support */
 #undef CONFIG_SOFT_I2C			/* so disable bit-banged I2C */

include/configs/sbc8548.h

@@ -168,7 +168,7 @@
 #define	CFG_OR0_PRELIM		0xff806e65
 #define	CFG_OR6_PRELIM		0xfc006e65
 
-#define CFG_FLASH_BANKS_LIST	{0xff800000, CFG_FLASH_BASE}
+#define CFG_FLASH_BANKS_LIST	{CFG_FLASH_BASE}
 #define CFG_MAX_FLASH_BANKS	1		/* number of banks */
 #define CFG_MAX_FLASH_SECT	128		/* sectors per device */
 #undef	CFG_FLASH_CHECKSUM

include/mpc512x.h

@@ -46,6 +46,7 @@
 #define LPCS6AW			0x003C
 #define LPCA7AW			0x0040
 #define SRAMBAR			0x00C4
+#define LAWBAR_BAR		0xFFFFF000	/* Base address mask */
 
 #define LPC_OFFSET		0x10000
 
@@ -189,6 +190,10 @@
 #define SCFR1_IPS_DIV_MASK		0x03800000
 #define SCFR1_IPS_DIV_SHIFT		23
 
+#define SCFR1_PCI_DIV			0x6
+#define SCFR1_PCI_DIV_MASK		0x00700000
+#define SCFR1_PCI_DIV_SHIFT		20
+
 /* SCFR2 System Clock Frequency Register 2
  */
 #define SCFR2_SYS_DIV			0xFC000000
@@ -404,4 +409,83 @@
 #define I2C_IF		0x02
 #define I2C_RXAK	0x01
 
+/* POTAR - PCI Outbound Translation Address Register
+ */
+#define POTAR_TA_MASK			0x000fffff
+
+/* POBAR - PCI Outbound Base Address Register
+ */
+#define POBAR_BA_MASK			0x000fffff
+
+/* POCMR - PCI Outbound Comparision Mask Register
+ */
+#define POCMR_EN	0x80000000
+#define POCMR_IO	0x40000000	/* 0-memory space 1-I/O space */
+#define POCMR_PRE	0x20000000	/* prefetch enable */
+#define POCMR_SBS	0x00100000	/* special byte swap enable */
+#define POCMR_CM_MASK	0x000fffff
+#define POCMR_CM_4G	0x00000000
+#define POCMR_CM_2G	0x00080000
+#define POCMR_CM_1G	0x000C0000
+#define POCMR_CM_512M	0x000E0000
+#define POCMR_CM_256M	0x000F0000
+#define POCMR_CM_128M	0x000F8000
+#define POCMR_CM_64M	0x000FC000
+#define POCMR_CM_32M	0x000FE000
+#define POCMR_CM_16M	0x000FF000
+#define POCMR_CM_8M	0x000FF800
+#define POCMR_CM_4M	0x000FFC00
+#define POCMR_CM_2M	0x000FFE00
+#define POCMR_CM_1M	0x000FFF00
+#define POCMR_CM_512K	0x000FFF80
+#define POCMR_CM_256K	0x000FFFC0
+#define POCMR_CM_128K	0x000FFFE0
+#define POCMR_CM_64K	0x000FFFF0
+#define POCMR_CM_32K	0x000FFFF8
+#define POCMR_CM_16K	0x000FFFFC
+#define POCMR_CM_8K	0x000FFFFE
+#define POCMR_CM_4K	0x000FFFFF
+
+/* PITAR - PCI Inbound Translation Address Register
+ */
+#define PITAR_TA_MASK			0x000fffff
+
+/* PIBAR - PCI Inbound Base/Extended Address Register
+ */
+#define PIBAR_MASK			0xffffffff
+#define PIEBAR_EBA_MASK			0x000fffff
+
+/* PIWAR - PCI Inbound Windows Attributes Register
+ */
+#define PIWAR_EN			0x80000000
+#define PIWAR_SBS			0x40000000
+#define PIWAR_PF			0x20000000
+#define PIWAR_RTT_MASK			0x000f0000
+#define PIWAR_RTT_NO_SNOOP		0x00040000
+#define PIWAR_RTT_SNOOP			0x00050000
+#define PIWAR_WTT_MASK			0x0000f000
+#define PIWAR_WTT_NO_SNOOP		0x00004000
+#define PIWAR_WTT_SNOOP			0x00005000
+#define PIWAR_IWS_MASK			0x0000003F
+#define PIWAR_IWS_4K			0x0000000B
+#define PIWAR_IWS_8K			0x0000000C
+#define PIWAR_IWS_16K			0x0000000D
+#define PIWAR_IWS_32K			0x0000000E
+#define PIWAR_IWS_64K			0x0000000F
+#define PIWAR_IWS_128K			0x00000010
+#define PIWAR_IWS_256K			0x00000011
+#define PIWAR_IWS_512K			0x00000012
+#define PIWAR_IWS_1M			0x00000013
+#define PIWAR_IWS_2M			0x00000014
+#define PIWAR_IWS_4M			0x00000015
+#define PIWAR_IWS_8M			0x00000016
+#define PIWAR_IWS_16M			0x00000017
+#define PIWAR_IWS_32M			0x00000018
+#define PIWAR_IWS_64M			0x00000019
+#define PIWAR_IWS_128M			0x0000001A
+#define PIWAR_IWS_256M			0x0000001B
+#define PIWAR_IWS_512M			0x0000001C
+#define PIWAR_IWS_1G			0x0000001D
+#define PIWAR_IWS_2G			0x0000001E
+
 #endif	/* __MPC512X_H__ */

include/ppc4xx_enet.h

@@ -356,12 +356,14 @@ typedef struct emac_4xx_hw_st {
 #define EMAC_M1_IST		(0x01000000)
 #define EMAC_M1_MF_1000MBPS	(0x00800000)	/* 0's for 10MBPS */
 #define EMAC_M1_MF_100MBPS	(0x00400000)
-#define EMAC_M1_RFS_16K		(0x00280000)	/* ~4k for 512 byte */
-#define EMAC_M1_RFS_8K		(0x00200000)	/* ~4k for 512 byte */
-#define EMAC_M1_RFS_4K		(0x00180000)	/* ~4k for 512 byte */
+#define EMAC_M1_RFS_MASK	(0x00380000)
+#define EMAC_M1_RFS_16K		(0x00280000)
+#define EMAC_M1_RFS_8K		(0x00200000)
+#define EMAC_M1_RFS_4K		(0x00180000)
 #define EMAC_M1_RFS_2K		(0x00100000)
 #define EMAC_M1_RFS_1K		(0x00080000)
-#define EMAC_M1_TX_FIFO_16K	(0x00050000)	/* 0's for 512 byte */
+#define EMAC_M1_TX_FIFO_MASK	(0x00070000)
+#define EMAC_M1_TX_FIFO_16K	(0x00050000)
 #define EMAC_M1_TX_FIFO_8K	(0x00040000)
 #define EMAC_M1_TX_FIFO_4K	(0x00030000)
 #define EMAC_M1_TX_FIFO_2K	(0x00020000)
@@ -386,11 +388,15 @@ typedef struct emac_4xx_hw_st {
 #define EMAC_M1_IST		0x01000000
 #define EMAC_M1_MF_1000MBPS	0x00800000	/* 0's for 10MBPS */
 #define EMAC_M1_MF_100MBPS	0x00400000
-#define EMAC_M1_RFS_4K		0x00300000	/* ~4k for 512 byte */
+#define EMAC_M1_RFS_MASK	0x00300000
+#define EMAC_M1_RFS_4K		0x00300000
 #define EMAC_M1_RFS_2K		0x00200000
 #define EMAC_M1_RFS_1K		0x00100000
-#define EMAC_M1_TX_FIFO_2K	0x00080000	/* 0's for 512 byte */
+#define EMAC_M1_RFS_512		0x00000000
+#define EMAC_M1_TX_FIFO_MASK	0x000c0000
+#define EMAC_M1_TX_FIFO_2K	0x00080000
 #define EMAC_M1_TX_FIFO_1K	0x00040000
+#define EMAC_M1_TX_FIFO_512	0x00000000
 #define EMAC_M1_TR0_DEPEND	0x00010000	/* 0'x for single packet */
 #define EMAC_M1_TR0_MULTI	0x00008000
 #define EMAC_M1_TR1_DEPEND	0x00004000
@@ -400,6 +406,15 @@ typedef struct emac_4xx_hw_st {
 #endif /* defined(CONFIG_440EP) || defined(CONFIG_440GR) */
 #endif /* defined(CONFIG_440GX) */
 
+#define EMAC_MR1_FIFO_MASK	(EMAC_M1_RFS_MASK | EMAC_M1_TX_FIFO_MASK)
+#if defined(CONFIG_405EZ)
+/* 405EZ only supports 512 bytes fifos */
+#define EMAC_MR1_FIFO_SIZE	(EMAC_M1_RFS_512 | EMAC_M1_TX_FIFO_512)
+#else
+/* Set receive fifo to 4k and tx fifo to 2k */
+#define EMAC_MR1_FIFO_SIZE	(EMAC_M1_RFS_4K | EMAC_M1_TX_FIFO_2K)
+#endif
+
 /* Transmit Mode Register 0 */
 #define EMAC_TXM0_GNP0		(0x80000000)
 #define EMAC_TXM0_GNP1		(0x40000000)

post/cpu/ppc4xx/spr.c

@@ -43,6 +43,12 @@
 
 #include <asm/processor.h>
 
+#ifdef CONFIG_4xx_DCACHE
+#include <asm/mmu.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+#endif
+
 static struct {
 	int number;
 	char * name;
@@ -164,6 +170,10 @@ int spr_post_test (int flags)
 	};
 	unsigned long (*get_spr) (void) = (void *) code;
 
+#ifdef CONFIG_4xx_DCACHE
+	/* disable cache */
+	change_tlb(gd->bd->bi_memstart, gd->bd->bi_memsize, TLB_WORD2_I_ENABLE);
+#endif
 	for (i = 0; i < spr_test_list_size; i++) {
 		int num = spr_test_list[i].number;
 
@@ -180,6 +190,10 @@ int spr_post_test (int flags)
 			ret = -1;
 		}
 	}
+#ifdef CONFIG_4xx_DCACHE
+	/* enable cache */
+	change_tlb(gd->bd->bi_memstart, gd->bd->bi_memsize, 0);
+#endif
 
 	return ret;
 }

post/drivers/memory.c

@@ -186,7 +186,7 @@ DECLARE_GLOBAL_DATA_PTR;
  *
  * For other processors, let the compiler generate the best code it can.
  */
-static void move64(unsigned long long *src, unsigned long long *dest)
+static void move64(const unsigned long long *src, unsigned long long *dest)
 {
 #if defined(CONFIG_MPC8260) || defined(CONFIG_MPC824X)
 	asm ("lfd  0, 0(3)\n\t" /* fpr0	  =  *scr	*/
@@ -233,12 +233,12 @@ static int memory_post_dataline(unsigned long long * pmem)
 	int ret = 0;
 
 	for ( i = 0; i < num_patterns; i++) {
-		move64((unsigned long long *)&(pattern[i]), pmem++);
+		move64(&(pattern[i]), pmem++);
 		/*
 		 * Put a different pattern on the data lines: otherwise they
 		 * may float long enough to read back what we wrote.
 		 */
-		move64((unsigned long long *)&otherpattern, pmem--);
+		move64(&otherpattern, pmem--);
 		move64(pmem, &temp64);
 
 #ifdef INJECT_DATA_ERRORS