Prepare for v1.3.3-rc3

Update ChNAGELOG, minor white space cleanup.

Signed-off-by: Wolfgang Denk <wd@denx.de>

CHANGELOG

@@ -1,3 +1,810 @@
+commit 7c0773fde6100b61be2558cb5d8c442a3194aecb
+Author: Wolfgang Denk <wd@denx.de>
+Date:	Sun May 4 00:35:15 2008 +0200
+
+    drivers/net/tsec.c: Fix typo.
+
+    Signed-off-by: Wolfgang Denk <wd@denx.de>
+
+commit aa737945e6f37a5de5dbad550a7694e0cb2a8120
+Author: Mike Frysinger <vapier@gentoo.org>
+Date:	Fri May 2 21:45:12 2008 -0400
+
+    version_autogenerated.h: use printf rather than echo -n
+
+    Some systems are dumb and do not implement the -n flag to echo (like OS X).
+    Convert the Makefile to use printf as this should work everywhere.
+
+    Signed-off-by: Mike Frysinger <vapier@gentoo.org>
+    Signed-off-by: Wolfgang Denk <wd@denx.de>
+
+commit 4acc2a108ad0a669165924704a6cb083f9138242
+Author: Mike Frysinger <vapier@gentoo.org>
+Date:	Fri May 2 18:17:50 2008 -0400
+
+    fix building when saveenv is disabled in some setups
+
+    If you enable environment in the flash, but disable the embedded
+    option, and you disable the saveenv command, then the #if nested
+    logic will trigger a compile failure:
+    env_flash.c: In function 'env_relocate_spec':
+    env_flash.c:399: error: 'flash_addr' undeclared (first use in this function)
+    The fix is to add CMD_SAVEENV ifdef protection like everywhere else.
+
+    Signed-off-by: Mike Frysinger <vapier@gentoo.org>
+
+commit ccf1ad535ae1c0dc2d466235c668adbdfe3a55b7
+Author: Jeremy McNicoll <jeremy.mcnicoll@windriver.com>
+Date:	Fri May 2 16:10:04 2008 -0400
+
+    SBC8548: fix address mask to allow 64M flash
+
+    Fix incorrect mask to enable all 64MB of onboard flash.
+    Previously U-Boot incorrectly mapped only 8MB of flash, this
+    patch correctly maps all the available flash.
+
+    Signed-off-by: Jeremy McNicoll <jeremy.mcnicoll@windriver.com>
+
+commit 3648085c464c8c22ef76fab006ca4344d3796124
+Author: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+Date:	Fri May 2 19:48:56 2008 +0200
+
+    qemu_mips: add README
+
+    Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+
+commit 6fdd002689190a0022c7b3dbab37fcba724580ce
+Author: Marcel Ziswiler <marcel@ziswiler.com>
+Date:	Fri May 2 02:35:59 2008 +0200
+
+    Fix misspelled comment
+
+    Signed-off-by: Marcel Ziswiler <marcel@ziswiler.com>
+
+commit fa956fde60b7ec4dd66bd62f9910fd341b5049a1
+Author: Mike Frysinger <vapier@gentoo.org>
+Date:	Thu May 1 04:13:05 2008 -0400
+
+    mkimage: make mmap() checks consistent
+
+    The mmap() related code is full of inconsistent casts/constants when
+    it comes to error checking, and may break when building on some
+    systems (like ones that do not implicitly define the caddr_t type).
+    Let's just avoid the whole mess by writing the code nice and clean in
+    the first place.
+
+    Signed-off-by: Mike Frysinger <vapier@gentoo.org>
+
+commit 8e90cd0447a0f0ccf529ef86f0e6b56187d3b82a
+Author: Marcel Ziswiler <marcel@ziswiler.com>
+Date:	Thu May 1 09:05:34 2008 +0200
+
+    Fix defined but not used build warning
+
+    - warning: 'srom' defined but not used
+
+    Signed-off-by: Marcel Ziswiler <marcel@ziswiler.com>
+
+commit b71190f3250aaffcc81c35f6cfd3498cb7c48013
+Author: Marcel Ziswiler <marcel@ziswiler.com>
+Date:	Thu May 1 09:05:26 2008 +0200
+
+    Fix implicit declaration build warnings
+
+    - warning: implicit declaration of function ‘serial_initialize’
+
+    Signed-off-by: Marcel Ziswiler <marcel@ziswiler.com>
+
+commit 9acde129cc3f9c1b3bc11a821480dd446774d618
+Author: Andre Schwarz <andre.schwarz@matrix-vision.de>
+Date:	Tue Apr 29 19:18:32 2008 +0200
+
+    TSEC: add config options for VSC8601 RGMII PHY
+
+    The Vitesse VSC8601 RGMII PHY has internal delay for both Rx
+    and Tx clock lines. They are configured using 2 bits in extended
+    register 0x17.
+    Therefore CFG_VSC8601_SKEW_TX and CFG_VSC8601_SKEW_RX have
+    been introduced with valid values 0-3 giving 0.0, 1.4,1.7 and 2.0ns delay.
+
+    Signed-off-by: Andre Schwarz <andre.schwarz@matrix-vision.de>
+    Acked-by: Andy Fleming <afleming@freescale.com>
+    Acked-by: Ben Warren <biggerbadderben@gmail.com>
+    --
+
+     drivers/net/tsec.c |    6 ++++++
+     drivers/net/tsec.h |    3 +++
+     2 files changed, 9 insertions(+), 0 deletions(-)
+
+commit bd98ee60df43ee6dd6f5ebe32c67d03e90513ff8
+Author: Wolfgang Denk <wd@denx.de>
+Date:	Sat May 3 23:07:15 2008 +0200
+
+    Revert "ColdFire: Get information from the correct GCC"
+
+    This reverts commit b7166e05a513c0806b63b9dfb6f1d77645cede2a
+    (replaced by commit c4e5f52a58d278eebb87f476e353972c5dacea40).
+
+commit c4e5f52a58d278eebb87f476e353972c5dacea40
+Author: Wolfgang Denk <wd@denx.de>
+Date:	Sat May 3 22:25:00 2008 +0200
+
+    config.mk: use correct (cross) compiler
+
+    Some config.mk files reference $(CC) to test for specific tool chain
+    features, so make sure $(CC) gets set before including any such
+    config files.
+
+    This patch replaces commit b7166e05a5 ("ColdFire: Get information from
+    the correct GCC").
+
+    Signed-off-by: Wolfgang Denk <wd@denx.de>
+
+commit 27c38689d0cfde0e444239345f97b5eecc9f4067
+Author: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+Date:	Thu May 1 02:13:44 2008 +0200
+
+    pxa: fix previous definition on cpu init
+
+    start.S:183:1: warning: "ICMR" redefined
+    In file included from start.S:33:
+    include/asm/arch/pxa-regs.h:935:1: warning: this is the location of the previous definition
+    start.S:187:1: warning: "RCSR" redefined
+    ...
+
+    Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+
+commit 6d12e697de794d700767f22f950e3026ccf4daf6
+Author: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+Date:	Thu May 1 02:13:43 2008 +0200
+
+    pxa: fix pcmcia operation on 'i' may be undefined
+
+    Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+    Signed-off-by: Wolfgang Denk <wd@denx.de>
+
+commit 4d77f5102dfeaa36cd58d9a9f083bd2cc491526f
+Author: Kumar Gala <galak@kernel.crashing.org>
+Date:	Wed Apr 30 16:24:35 2008 -0500
+
+    MPC8610HPCD: Drop -O2 from the build flags
+
+    Make the flags use -Os like all other boards
+
+    Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
+
+commit 0072b78be2b41e5a0ca3ddc39335574dc2e855bd
+Author: Stefan Roese <sr@denx.de>
+Date:	Wed Apr 30 15:50:39 2008 +0200
+
+    RTC: Fix month offset by one problem in M41T62 RTC driver
+
+    This patch fixes a problem with the month being read and written
+    incorrectly (offset by one). This only gets visible by also using
+    the Linux driver (rtc-m41t80).
+
+    Tested on AMCC Canyonlands.
+
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit 141ba1cad8e6598a2466e7e2976c6a12285df619
+Author: Shinya Kuribayashi <skuribay@ruby.dti.ne.jp>
+Date:	Sat May 3 13:51:44 2008 +0900
+
+    [MIPS] cpu/mips/config.mk: Fix GNU assembler minor version picker
+
+    Current trick to pick up GNU assembler minor version uses a dot(.) as a
+    delimiter, and take the second field to obtain minor version number. But
+    as can be expected, this doesn't work with a version string which has
+    dots more than needs.
+
+    Here's an example:
+
+    $ mips-linux-gnu-as --version | grep 'GNU assembler'
+    GNU assembler (Sourcery G++ Lite 4.2-129) 2.18.50.20080215
+    $ mips-linux-gnu-as --version | grep 'GNU assembler' | cut -d. -f2
+    2-129) 2
+    $
+
+    This patch restricts the version format to 2.XX.XX... This will work
+    in most cases.
+
+    $ mips-linux-gnu-as --version | grep 'GNU assembler' | egrep -o '2\.[0-9\.]+'
+    2.18.50.20080215
+    $ mips-linux-gnu-as --version | grep 'GNU assembler' | egrep -o '2\.[0-9\.]+' | cut -d. -f2
+    18
+    $
+
+    Signed-off-by: Shinya Kuribayashi <skuribay@ruby.dti.ne.jp>
+
+commit ea638951acead7f1086c908c0b9f086beab82a22
+Author: Shinya Kuribayashi <skuribay@ruby.dti.ne.jp>
+Date:	Sat May 3 13:51:28 2008 +0900
+
+    [MIPS] cpu/mips/cache.S: Add dcache_enable
+
+    Recent bootelf command fixes (017e9b7925f74878d0e9475388cca9bda5ef9482,
+    "allow ports to override bootelf behavior") requires ports to have this
+    function.
+
+    Signed-off-by: Shinya Kuribayashi <skuribay@ruby.dti.ne.jp>
+    Acked-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+
+commit d2c6fbec4397c936b18cd42482b6973cd6781bdf
+Author: Wolfgang Denk <wd@denx.de>
+Date:	Thu May 1 21:30:16 2008 +0200
+
+    onenand: rename 16 bit memory copy into memcpy_16() to avoid conflicts
+
+    Onenand needs a version of memcpy() which performs 16 bit accesses
+    only; make sure the name does not conflict with the standard
+    function.
+
+    Signed-off-by: Wolfgang Denk <wd@denx.de>
+
+commit 12bc4e94251c369c529ffa505cf58b148c372f7f
+Author: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+Date:	Wed Apr 30 22:38:17 2008 +0200
+
+    cmd_nand: fix warning: str2long ncompatible pointer type
+
+    Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+
+commit 1b9ed2574a38c93cb03dad41885fc06be4bfc9dd
+Author: Timur Tabi <timur@freescale.com>
+Date:	Fri Apr 4 11:16:11 2008 -0500
+
+    Fix calculation of I2C clock for some 86xx chips
+
+    Some 86xx chips use CCB as the base clock for the I2C, and others used CCB/2.
+    There is no pattern that can be used to determine which chips use which
+    frequency, so the only way to determine is to look up the actual SOC
+    designation and use the right value for that SOC.
+
+    Signed-off-by: Timur Tabi <timur@freescale.com>
+
+commit f32f7fe7bd3a5bda3a476520f00e1aca7c2103a9
+Author: TsiChung Liew <Tsi-Chung.Liew@freescale.com>
+Date:	Wed Apr 30 12:11:19 2008 -0500
+
+    ColdFire: Fix ethernet hang issue for mcf547x_8x
+
+    The ethernet hang is caused by receiving buffer in DRAM is not
+    yet ready due to access cycles require longer time in DRAM.
+    Relocate DMA buffer descriptors from DRAM to internal SRAM.
+
+    Signed-off-by: TsiChung Liew <Tsi-Chung.Liew@freescale.com>
+
+commit 886d90176fc257e0ab4d0db05d11d0749bbed3ca
+Author: TsiChung Liew <Tsi-Chung.Liew@freescale.com>
+Date:	Wed Apr 30 12:10:47 2008 -0500
+
+    ColdFire: Fix compilation issue caused by new changes in fsl_i2c.c
+
+    Signed-off-by: Luigi Comio Mantellini <luigi.mantellini@idf-hit.com>
+    Signed-off-by: TsiChung Liew <Tsi-Chung.Liew@freescale.com>
+
+commit b7166e05a513c0806b63b9dfb6f1d77645cede2a
+Author: TsiChung Liew <Tsi-Chung.Liew@freescale.com>
+Date:	Wed Apr 30 12:10:23 2008 -0500
+
+    ColdFire: Get information from the correct GCC
+
+    Signed-off-by: Kurt Mahan <kmahan@freescale.com>
+    Signed-off-by: TsiChung Liew <Tsi-Chung.Liew@freescale.com>
+
+commit 378e7ec95da4751ec8fe461baacab2bf7d2512a9
+Author: dirk.behme@googlemail.com <dirk.behme@googlemail.com>
+Date:	Wed Apr 30 18:02:59 2008 +0200
+
+    Fix warning in env_nand.c if compiled for DaVinci Schmoogie
+
+    Fix warnings
+
+    nv_nand.c: In function 'saveenv':
+    env_nand.c:200: warning: passing argument 3 of 'nand_write' from incompatible pointer type
+    env_nand.c: In function 'env_relocate_spec':
+    env_nand.c:275: warning: passing argument 3 of 'nand_read' from incompatible pointer type
+
+    if compiled for davinci_schmoogie_config.
+
+    Signed-off-by: Dirk Behme <dirk.behme@gmail.com>
+    Ack by: Sergey Kubushyn <ksi@koi8.net>
+
+commit 33a4a70d48d622cc4950c60a84fec23b9421f23e
+Author: Anatolij Gustschin <agust@denx.de>
+Date:	Wed Apr 30 13:34:40 2008 +0200
+
+    Fix warnings while compiling net/net.c for MPC8610HPCD board
+
+    MPC8610HPCD board adds -O2 gcc option to PLATFORM_CPPFLAGS
+    causing overriding default -Os option. New gcc (ver. 4.2.2)
+    produces warnings while compiling net/net.c file with -O2
+    option. The patch is an attempt to fix this.
+
+    Signed-off-by: Anatolij Gustschin <agust@denx.de>
+
+commit 58b575e575c25fdf8c88141e145db201f3092149
+Author: Sascha Laue <Sascha.Laue@gmx.biz>
+Date:	Wed Apr 30 15:23:38 2008 +0200
+
+    lwmon5: fix offset error in sysmon0 POST
+
+    Signed-off-by: Sascha Laue <sascha.laue@liebherr.com>
+    Signed-off-by: Wolfgang Denk <wd@denx.de>
+
+commit e7419b243a373de4ee042f7d4f45f66de787240d
+Author: Sascha Laue <Sascha.Laue@gmx.biz>
+Date:	Wed Apr 30 15:16:35 2008 +0200
+
+    lwmon5: fix manual merge error in POST
+
+    Signed-off-by: Sascha Laue <sascha.laue@liebherr.com>
+
+commit 42ffcec3f9eba010a662d5b42981812b6bebfb9a
+Author: Wolfgang Denk <wd@denx.de>
+Date:	Wed Apr 30 17:46:26 2008 +0200
+
+    cmd_nand.c: fix another 'incompatible pointer type' warning.
+
+    Signed-off-by: Wolfgang Denk <wd@denx.de>
+
+commit de109d909707e2dfe806be5efc3cdb103b47c8ad
+Author: Wolfgang Denk <wd@denx.de>
+Date:	Wed Apr 30 17:25:07 2008 +0200
+
+    Makefile: fix parallel builds
+
+    This problem shows up with parallel builds only; it results in
+    somewhat cryptic error messages like
+
+	$ JOBS=-j6 MAKEALL netstar
+	Configuring for netstar board...
+	arm-linux-ld: cannot find -lgeneric
+	make[1]: *** [eeprom.srec] Error 1
+
+    A few boards (like netstar and voiceblue) need some libraries for
+    building; however, the board Makefile does not contain any such
+    dependencies which may cause problems with parallel builds. Adding
+    such dependencies is difficult as we would also have to provide build
+    rules, which already exist in the respective library Makefiles.
+
+    To solve this, we make sure that all libraries get built before the
+    board code.
+
+    Signed-off-by: Wolfgang Denk <wd@denx.de>
+
+commit 4f27098e5b0736989b13cd61d7bca94b3574cf5f
+Author: Stefan Roese <sr@denx.de>
+Date:	Wed Apr 30 14:51:36 2008 +0200
+
+    ppc4xx: Adapt Canyonlands fixed DDR2 setup to new DIMM module
+
+    This patch changes the Canyonlands/Glacier fixed DDR2 controller setup
+    used for NAND booting to match the values needed for the new 512MB
+    DIMM modules shipped with the productions boards:
+
+    Crucial: CT6464AC667.8FB
+
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit ea9202a659dc75996facf1475f1866a19a9d3129
+Author: Stefan Roese <sr@denx.de>
+Date:	Wed Apr 30 10:49:43 2008 +0200
+
+    ppc4xx: Fix problem with DIMMs with 8 banks in 44x_spd_ddr2.c
+
+    This patch fixes a problem with DIMMs that have 8 banks. Now the
+    MCIF0_MBxCF register will be setup correctly for this setup too.
+
+    This was noticed with the 512MB DIMM on Canyonlands/Glacier.
+
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit 76617299358ebba260ecc02d33e8e75d8d13dd3b
+Author: Wolfgang Denk <wd@denx.de>
+Date:	Tue Apr 29 23:41:06 2008 +0200
+
+    Prepare v1.3.3-rc2, again.
+
+    Signed-off-by: Wolfgang Denk <wd@denx.de>
+
+commit b7fcc4c13993782342cf5cd20d237a6281648a0b
+Author: Wolfgang Denk <wd@denx.de>
+Date:	Tue Apr 29 23:35:24 2008 +0200
+
+    Prepare v1.3.3-rc2
+
+    Signed-off-by: Wolfgang Denk <wd@denx.de>
+
+commit f7b16a0a4d571dd33b2b5185a54f7ddc311f89d4
+Author: Wolfgang Denk <wd@denx.de>
+Date:	Tue Apr 29 23:32:20 2008 +0200
+
+    common/env_nand.c: fix one more incompatible pointer type issue
+
+    Signed-off-by: Wolfgang Denk <wd@denx.de>
+
+commit ea6f66894f952229eebfc4ad03cd21fe5c8b3f0f
+Author: Wolfgang Denk <wd@denx.de>
+Date:	Tue Apr 29 21:33:08 2008 +0200
+
+    post/board/lwmon5/sysmon.c: fix manual merge error.
+
+    Signed-off-by: Wolfgang Denk <wd@denx.de>
+
+commit 70a0f81412b0b18a6fd0bea960451bc6c2cca49a
+Author: Kumar Gala <galak@kernel.crashing.org>
+Date:	Tue Apr 29 12:54:59 2008 -0500
+
+    85xx: Add -mno-spe to e500/85xx builds
+
+    Newer gcc's might be configured to enable autovectorization by default.
+    If we happen to build with one of those compilers we will get SPE
+    instructions in random code.
+
+    -mno-spe disables the compiler for automatically generating SPE
+    instructions without our knowledge.
+
+    Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
+
+commit 8ea08e5be69436abcc95d3da114de4a2ff8a6ab5
+Author: Kumar Gala <galak@kernel.crashing.org>
+Date:	Tue Apr 29 10:18:34 2008 -0500
+
+    Update .gitignore for zlib.h
+
+    Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
+
+commit 45239cf4152109caa925145ccd433529902df887
+Author: Kumar Gala <galak@kernel.crashing.org>
+Date:	Tue Apr 29 10:27:08 2008 -0500
+
+    85xx/86xx: Rename ext_refrec to timing_cfg_3 to match docs
+
+    All the 85xx and 86xx UM describe the register as timing_cfg_3
+    not as ext_refrec.
+
+    Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
+
+commit ef7d30b14394e4c4a153118f5845760cadada02a
+Author: Kumar Gala <galak@kernel.crashing.org>
+Date:	Tue Apr 29 10:28:34 2008 -0500
+
+    85xx/86xx: Rename DDR init address and init extended address register
+
+    Rename init_addr and init_ext_addr to match the docs between
+    85xx and 86xx.  Both now use 'init_addr' and 'init_ext_addr'.
+
+    Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
+
+commit cf6cc014270549684873a5972d2595052c468cb6
+Author: Kumar Gala <galak@kernel.crashing.org>
+Date:	Mon Apr 28 02:24:04 2008 -0500
+
+    85xx: Additional fixes and cleanup of MP code
+
+    * adjust __spin_table alignment to match ePAPR v0.94 spec
+    * loop over all cpus when determing who is up.  This fixes an issue if
+      the "boot cpu" isn't core0.  The "boot cpu" will already be in the
+      cpu_up_mask so there is no harm
+    * Added some protection in the code to ensure proper behavior.  These
+      changes are explicitly needed but don't hurt:
+      - Added eieio to ensure the "hot word" of the table is written after
+	all other table updates have occurred.
+      - Added isync to ensure we don't prefetch loading of table entries
+	until we a released
+
+    These issues we raised by Dave Liu.
+
+    Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
+
+commit b2d527a8b9fb50afccbaf79b5540952585cdc760
+Author: Yuri Tikhonov <yur@emcraft.com>
+Date:	Tue Apr 29 15:06:41 2008 +0200
+
+    lwmon5: minor clean-up to include/configs/lwmon5.h
+
+    LWMON5 DSPIC POST uses the watch-dog scratch register. So, make
+    the CFG_DSPIC_TEST_ADDR definition more readable.
+
+    Signed-off-by: Yuri Tikhonov <yur@emcraft.com>
+
+commit f4c4d21a885ccc222fd0acdf653b683249e85117
+Author: Stefan Roese <sr@denx.de>
+Date:	Tue Apr 29 16:08:05 2008 +0200
+
+    ppc4xx: Fix CFG_MONITOR_LEN on Katmai failsave this time
+
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit 138105efe1d2b1a40a3a97b4c1f85c2111bea2d8
+Author: Yuri Tikhonov <yur@emcraft.com>
+Date:	Tue Apr 29 13:32:45 2008 +0200
+
+    ppc flush_cache: add watch-dog triggering into the loops.
+
+    Some boards (e.g. lwmon5) need rather a frequent watch-dog
+    kicking. Since the time it takes for the flush_cache() function
+    to complete its job depends on the size of data being flushed, one
+    may encounter watch-dog resets on such boards when, for example,
+    download big files over ethernet.
+
+    Signed-off-by: Yuri Tikhonov <yur@emcraft.com>
+
+commit cab99d6f3281ab6784feccf98b9b425daa58418a
+Author: Stefan Roese <sr@denx.de>
+Date:	Tue Apr 29 14:44:54 2008 +0200
+
+    ppc4xx: Fix compilation warning in denali_spd_ddr2.c
+
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit 4ec9d78fe5cd585d2868731fa108ca1e62730e70
+Author: Stefan Roese <sr@denx.de>
+Date:	Tue Apr 29 14:12:07 2008 +0200
+
+    ppc4xx: Fix Katmai CFG_MONITOR_LEN
+
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit 85ad184b3b2b0f8af9228477303c55dca1b52ed7
+Author: Stefan Roese <sr@denx.de>
+Date:	Tue Apr 29 13:57:07 2008 +0200
+
+    ppc4xx: Complete remove bogus dflush()
+
+    Since the current dflush() implementation is know to have some problems
+    (as seem on lwmon5 ECC init) this patch removes it completely and replaces
+    it by using clean_dcache_range().
+
+    Tested on Katmai with ECC DIMM.
+
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit 135846d6ecaad255ad28d93ebbb78b3d5da68cdc
+Author: Stefan Roese <sr@denx.de>
+Date:	Tue Apr 29 13:36:51 2008 +0200
+
+    ppc4xx: Change ECC initialization on lwmon5 to use clean_dcache_range()
+
+    As it seems the "old" ECC initialization routine by using dflush() didn't
+    write all lines in the dcache back to memory on lwmon5. This could lead
+    to ECC error upon Linux booting. This patch changes the program_ecc()
+    routine to now use clean_dcache_range() instead of dflush().
+    clean_dcache_range() uses dcbst which is exactly what we want in this
+    case.
+
+    Since dflush() is known is cause problems, this routine will be
+    removed completely and replaced by clean_dcache_range() with an
+    additional patch.
+
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit 18ec19e4aa1a045dfbf2c7c2e33963488e92d757
+Author: Yuri Tikhonov <yur@emcraft.com>
+Date:	Mon Apr 28 18:19:34 2008 +0200
+
+    POST: fix Makefiles for mpc8xx, lwmon, and netta POSTs.
+
+    Signed-off-by: Yuri Tikhonov <yur@emcraft.com>
+
+commit eea5a743a2193ef2a05b9bc6dc447ba241416f35
+Author: Markus Brunner <super.firetwister@googlemail.com>
+Date:	Mon Apr 28 08:47:47 2008 +0200
+
+    ppc4xx: Fixup ebc clock in FDT for 405GP/EP
+
+    On ppc405EP and ppc405GP (at least) the ebc is directly attached to the plb
+    and not to the opb. This patch will try to fixup /plb/ebc if /plb/opb/ebc
+    doesn't exist.
+
+    Signed-off-by: Markus Brunner <super.firetwister@gmail.com>
+
+commit 2ef7503a593c77a80c2a054011970227c4b62774
+Author: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+Date:	Thu Apr 24 07:57:17 2008 +0200
+
+    NE2000: Fix regresssion introduced by e710185aae90 on non AX88796
+
+    Move non-inlied functions into specific drivers file
+    Set get_prom as weak
+
+    Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+    Signed-off-by: Vlad Lungu <vlad@comsys.ro>
+    Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
+
+commit 40cb90ee2b97db1f697e1b54f19a548ffc96d71b
+Author: Guennadi Liakhovetski <lg@denx.de>
+Date:	Thu Apr 3 17:04:19 2008 +0200
+
+    net: make ARP timeout configurable
+
+    Currently the timeout waiting for an ARP reply is hard set to 5 seconds.
+    On i.MX31ADS due to a hardware "strangeness" up to four first IP packets
+    to the boards get lost, which typically are ARP replies. By configuring
+    the timeout to a lower value we significantly improve the first network
+    transfer time on this board. The timeout is specified in milliseconds,
+    later internally it is converted to deciseconds, because it has to be
+    converted to hardware ticks, and CFG_HZ ranges from 900 to 27000000 on
+    different boards.
+
+    Signed-off-by: Guennadi Liakhovetski <lg@denx.de>
+    Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
+
+commit 13e0b8f7ca9d29267bf01d7a01e521a0517adce1
+Author: Guennadi Liakhovetski <lg@denx.de>
+Date:	Thu Apr 3 13:36:18 2008 +0200
+
+    minor cs8900 driver clean up
+
+    Remove a redundant register definition, clean up some coding style
+    violations.
+
+    Signed-off-by: Guennadi Liakhovetski <lg@denx.de>
+    Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
+
+commit 707fa917cca24c0f22776f48ac4a6fa5e5189b10
+Author: Wolfgang Denk <wd@denx.de>
+Date:	Mon Apr 28 22:01:04 2008 +0200
+
+    jffs2_1pass.c: fix incompatible pointer type warning
+
+    Signed-off-by: Wolfgang Denk <wd@denx.de>
+
+commit 6aee00f5e6a1cf29d8fe8fdc9b7252fbd31115d9
+Author: Sascha Laue <Sascha.Laue@gmx.biz>
+Date:	Tue Apr 1 10:10:18 2008 +0200
+
+    lwmon5: update dsPIC POST spezification
+
+    The specification for the lwmon5 board dsPIC POST got changed.
+    Also add defines for the temperatures  and voltages.
+
+    Signed-off-by: Sascha Laue <sascha.laue@liebherr.com>
+
+commit 3e4615ab7ff38781a5dd80d0f49b9af55b4fe0b7
+Author: Sascha Laue <Sascha.Laue@gmx.biz>
+Date:	Tue Apr 1 15:13:03 2008 +0200
+
+    Fix watchdog POST for lwmon5
+
+    If the hardware watchdog detects a voltage error, the watchdog sets
+    GPIO62 to low. The watchdog POST has to detect this low level.
+
+    Signed-off-by: Sascha Laue <leglas0@legpc180.leg.liebherr.i>
+    Signed-off-by: Wolfgang Denk <wd@denx.de>
+
+commit dd5748bcd669f46aeb6686c1b341323843738ccc
+Author: Guennadi Liakhovetski <g.liakhovetski@gmx.de>
+Date:	Mon Apr 28 14:37:14 2008 +0200
+
+    rtl8169: fix compiler warnings
+
+    Fix multiple compiler warnings related to argument type mismatch.
+
+    Signed-off-by: Guennadi Liakhovetski <g.liakhovetski@gmx.de>
+
+commit 413bf586266f86c6bdbc6c6d140f67a15af4c4f1
+Author: Guennadi Liakhovetski <g.liakhovetski@gmx.de>
+Date:	Mon Apr 28 14:36:06 2008 +0200
+
+    IDE: fix compiler warnings
+
+    The IDE driver can use 32-bit addresses in LBA mode, in which case it
+    spits multiple warnings during compilation. Fix them.
+
+    Signed-off-by: Guennadi Liakhovetski <g.liakhovetski@gmx.de>
+
+commit db9084de28c46ac81c8f681722cb0d7411be4d7f
+Author: Guennadi Liakhovetski <g.liakhovetski@gmx.de>
+Date:	Mon Apr 28 14:35:57 2008 +0200
+
+    LinkStation: fix compiler warning, add a maintainer
+
+    out_8 wants a pointer to an unsigned as the first argument. Add a
+    maintainer for Linkstation boards.
+
+    Signed-off-by: Guennadi Liakhovetski <g.liakhovetski@gmx.de>
+
+commit c71abba3cb67b063f789f17abf6c7447727c0cd5
+Author: Wolfgang Denk <wd@denx.de>
+Date:	Mon Apr 28 14:55:12 2008 +0200
+
+    cmd_nand.c: fix "differ in signedness" problem
+
+    Signed-off-by: Wolfgang Denk <wd@denx.de>
+
+commit f2c288a35341ad02ac03b1563d786763c9c8f159
+Author: Wolfgang Denk <wd@denx.de>
+Date:	Mon Apr 28 12:48:47 2008 +0200
+
+    pcnet.c: fix a merge issue
+
+    Signed-off-by: Wolfgang Denk <wd@denx.de>
+
+commit 4ca79f477ebd25a6872e6196d80e2f5eff441376
+Author: Wolfgang Denk <wd@denx.de>
+Date:	Mon Apr 28 12:08:18 2008 +0200
+
+    NAND: fix some strict-aliasing compiler warnings
+
+    Signed-off-by: Wolfgang Denk <wd@denx.de>
+
+commit 5cd0130ecc79d6dcde1b1ac253abc457ca8c3115
+Author: Stefan Roese <sr@denx.de>
+Date:	Mon Apr 28 11:37:14 2008 +0200
+
+    ppc4xx: Fix compile warning of hcu4 board
+
+    Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit 5379cd15dd6c74ac51499bce3455bf6e0cdbe9f1
+Author: Wolfgang Denk <wd@denx.de>
+Date:	Mon Apr 28 11:31:23 2008 +0200
+
+    MPC8323ERDB: fix implicit declaration of function 'mac_read_from_eeprom'
+
+    Signed-off-by: Wolfgang Denk <wd@denx.de>
+
+commit 7602ed50a2f0ef3dc8d7da93f116de50288f5b59
+Author: Guennadi Liakhovetski <lg@denx.de>
+Date:	Mon Apr 28 00:25:32 2008 +0200
+
+    mx31ads: fix loadaddr environment variable define
+
+    Arithmetic expressions do not get evaluated under stringification. Remove
+    default network configuration, add DHCP command support. Thanks to Felix
+    Radensky for reporting.
+
+    Signed-off-by: Guennadi Liakhovetski <lg@denx.de>
+
+commit 144eec777ac07bcb12bd38245a5a289f694a7f98
+Author: Wolfgang Denk <wd@denx.de>
+Date:	Mon Apr 28 10:55:24 2008 +0200
+
+    katmai: fix section overlap problem
+
+    Since we didn't want to remove features from the configuration, we
+    decided to increase the U-Boot image size (add one flash sector).
+
+    Also changed the default environment definition to make it
+    independent of such changes.
+
+    Signed-off-by: Wolfgang Denk <wd@denx.de>
+    Acked-by: Stefan Roese <sr@denx.de>
+
+commit 941d696d25624e3cc65ebf924199541acf52d74e
+Author: Wolfgang Denk <wd@denx.de>
+Date:	Mon Apr 28 10:55:24 2008 +0200
+
+    katmai: fix section overlap problem
+
+    Since we didn't want to remove features from the configuration, we
+    decided to increase the U-Boot image size (add one flash sector).
+
+    Also changed the default environment definition to make it
+    independent of such changes.
+
+    Signed-off-by: Wolfgang Denk <wd@denx.de>
+    Acked-by: Stefan Roese <sr@denx.de>
+
+commit 03c6cd39f9184143fd8c537872b3d4b2e03f1466
+Author: Kumar Gala <galak@kernel.crashing.org>
+Date:	Sat Apr 26 11:44:44 2008 -0500
+
+    post: Fix building with O=
+
+    Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
+
+commit fd7531c1e9d56b9e5e06d2c0e02b798dab72f70c
+Author: Wolfgang Denk <wd@denx.de>
+Date:	Sat Apr 26 01:55:00 2008 +0200
+
+    Prepare v1.3.3-rc1
+
+    Signed-off-by: Wolfgang Denk <wd@denx.de>
+
 commit 19cf2ec90d8ce52da60c1693693c4048cb810967
 Author: Wolfgang Denk <wd@denx.de>
 Date:	Sat Apr 26 01:25:39 2008 +0200

MAINTAINERS

@@ -408,6 +408,10 @@ John Zhan <zhanz@sinovee.com>
 
 	svm_sc8xx		MPC8xx
 
+Guennadi Liakhovetski <g.liakhovetski@gmx.de>
+
+	linkstation		MPC8241
+
 -------------------------------------------------------------------------
 
 Unknown / orphaned boards:

Makefile

@@ -24,7 +24,7 @@
 VERSION = 1
 PATCHLEVEL = 3
 SUBLEVEL = 3
-EXTRAVERSION = -rc1
+EXTRAVERSION = -rc3
 U_BOOT_VERSION = $(VERSION).$(PATCHLEVEL).$(SUBLEVEL)$(EXTRAVERSION)
 VERSION_FILE = $(obj)include/version_autogenerated.h
 
@@ -201,7 +201,6 @@ OBJS := $(addprefix $(obj),$(OBJS))
 LIBS  = lib_generic/libgeneric.a
 LIBS += $(shell if [ -f board/$(VENDOR)/common/Makefile ]; then echo \
 	"board/$(VENDOR)/common/lib$(VENDOR).a"; fi)
-LIBS += board/$(BOARDDIR)/lib$(BOARD).a
 LIBS += cpu/$(CPU)/lib$(CPU).a
 ifdef SOC
 LIBS += cpu/$(CPU)/$(SOC)/lib$(SOC).a
@@ -248,6 +247,9 @@ LIBS += post/libpost.a
 LIBS := $(addprefix $(obj),$(LIBS))
 .PHONY : $(LIBS) $(VERSION_FILE)
 
+LIBBOARD = board/$(BOARDDIR)/lib$(BOARD).a
+LIBBOARD := $(addprefix $(obj),$(LIBBOARD))
+
 # Add GCC lib
 PLATFORM_LIBS += -L $(shell dirname `$(CC) $(CFLAGS) -print-libgcc-file-name`) -lgcc
 
@@ -270,7 +272,7 @@ U_BOOT_ONENAND = $(obj)u-boot-onenand.bin
 endif
 
 __OBJS := $(subst $(obj),,$(OBJS))
-__LIBS := $(subst $(obj),,$(LIBS))
+__LIBS := $(subst $(obj),,$(LIBS)) $(subst $(obj),,$(LIBBOARD))
 
 #########################################################################
 #########################################################################
@@ -313,8 +315,9 @@ $(obj)u-boot.sha1:	$(obj)u-boot.bin
 $(obj)u-boot.dis:	$(obj)u-boot
 		$(OBJDUMP) -d $< > $@
 
-$(obj)u-boot:		depend $(SUBDIRS) $(OBJS) $(LIBS) $(LDSCRIPT)
-		UNDEF_SYM=`$(OBJDUMP) -x $(LIBS) |sed  -n -e 's/.*\($(SYM_PREFIX)__u_boot_cmd_.*\)/-u\1/p'|sort|uniq`;\
+$(obj)u-boot:		depend $(SUBDIRS) $(OBJS) $(LIBBOARD) $(LIBS) $(LDSCRIPT)
+		UNDEF_SYM=`$(OBJDUMP) -x $(LIBBOARD) $(LIBS) | \
+		sed  -n -e 's/.*\($(SYM_PREFIX)__u_boot_cmd_.*\)/-u\1/p'|sort|uniq`;\
 		cd $(LNDIR) && $(LD) $(LDFLAGS) $$UNDEF_SYM $(__OBJS) \
 			--start-group $(__LIBS) --end-group $(PLATFORM_LIBS) \
 			-Map u-boot.map -o u-boot
@@ -325,6 +328,9 @@ $(OBJS):	depend $(obj)include/autoconf.mk
 $(LIBS):	depend $(obj)include/autoconf.mk
 		$(MAKE) -C $(dir $(subst $(obj),,$@))
 
+$(LIBBOARD):	depend $(LIBS) $(obj)include/autoconf.mk
+		$(MAKE) -C $(dir $(subst $(obj),,$@))
+
 $(SUBDIRS):	depend $(obj)include/autoconf.mk
 		$(MAKE) -C $@ all
 
@@ -346,11 +352,9 @@ $(U_BOOT_ONENAND):	$(ONENAND_IPL) $(obj)u-boot.bin $(obj)include/autoconf.mk
 		cat $(obj)onenand_ipl/onenand-ipl-4k.bin $(obj)u-boot.bin > $(obj)u-boot-flexonenand.bin
 
 $(VERSION_FILE):
-		@( echo -n "#define U_BOOT_VERSION \"U-Boot " ; \
-		echo -n "$(U_BOOT_VERSION)" ; \
-		echo -n $(shell $(CONFIG_SHELL) $(TOPDIR)/tools/setlocalversion \
-			 $(TOPDIR)) ; \
-		echo "\"" ) > $@.tmp
+		@( printf '#define U_BOOT_VERSION "U-Boot %s%s"\n' "$(U_BOOT_VERSION)" \
+		 '$(shell $(CONFIG_SHELL) $(TOPDIR)/tools/setlocalversion $(TOPDIR))' \
+		 ) > $@.tmp
 		@cmp -s $@ $@.tmp && rm -f $@.tmp || mv -f $@.tmp $@
 
 gdbtools:

README

@@ -1561,6 +1561,10 @@ The following options need to be configured:
 		before giving up the operation. If not defined, a
 		default value of 5 is used.
 
+		CONFIG_ARP_TIMEOUT
+
+		Timeout waiting for an ARP reply in milliseconds.
+
 - Command Interpreter:
 		CONFIG_AUTO_COMPLETE
 

board/amcc/katmai/config.mk

@@ -25,7 +25,7 @@
 # AMCC 440SPe Evaluation (Katmai) board
 #
 
-TEXT_BASE = 0xfffc0000
+TEXT_BASE = 0xFFFA0000
 
 PLATFORM_CPPFLAGS += -DCONFIG_440=1
 

board/freescale/mpc8610hpcd/config.mk

@@ -22,4 +22,4 @@
 TEXT_BASE = 0xfff00000
 
 PLATFORM_CPPFLAGS += -DCONFIG_MPC86xx=1
-PLATFORM_CPPFLAGS += -DCONFIG_MPC8610=1 -maltivec -mabi=altivec -msoft-float -O2
+PLATFORM_CPPFLAGS += -DCONFIG_MPC8610=1 -maltivec -mabi=altivec -msoft-float

board/freescale/mpc8610hpcd/mpc8610hpcd.c

@@ -192,7 +192,7 @@ long int fixed_sdram(void)
 	ddr->cs0_bnds = 0x0000001f;
 	ddr->cs0_config = 0x80010202;
 
-	ddr->ext_refrec = 0x00000000;
+	ddr->timing_cfg_3 = 0x00000000;
 	ddr->timing_cfg_0 = 0x00260802;
 	ddr->timing_cfg_1 = 0x3935d322;
 	ddr->timing_cfg_2 = 0x14904cc8;

board/freescale/mpc8641hpcn/mpc8641hpcn.c

@@ -130,7 +130,7 @@ fixed_sdram(void)
 
 	ddr->cs0_bnds = CFG_DDR_CS0_BNDS;
 	ddr->cs0_config = CFG_DDR_CS0_CONFIG;
-	ddr->ext_refrec = CFG_DDR_EXT_REFRESH;
+	ddr->timing_cfg_3 = CFG_DDR_TIMING_3;
 	ddr->timing_cfg_0 = CFG_DDR_TIMING_0;
 	ddr->timing_cfg_1 = CFG_DDR_TIMING_1;
 	ddr->timing_cfg_2 = CFG_DDR_TIMING_2;

board/linkstation/hwctl.c

@@ -27,7 +27,7 @@
 /*--------------------------------------------------------------*/
 static inline void miconCntl_SendUart(unsigned char dat)
 {
-	out_8((char *)AVR_PORT, dat);
+	out_8((unsigned char *)AVR_PORT, dat);
 	mdelay(1);
 }
 

board/lwmon5/sdram.c

@@ -34,6 +34,7 @@
 #include <asm/processor.h>
 #include <asm/mmu.h>
 #include <asm/io.h>
+#include <asm/cache.h>
 #include <ppc440.h>
 #include <watchdog.h>
 
@@ -59,7 +60,6 @@
 extern int denali_wait_for_dlllock(void);
 extern void denali_core_search_data_eye(void);
 extern void dcbz_area(u32 start_address, u32 num_bytes);
-extern void dflush(void);
 
 static u32 is_ecc_enabled(void)
 {
@@ -106,6 +106,7 @@ static void program_ecc(u32 start_address,
 {
 	u32 val;
 	u32 current_addr = start_address;
+	u32 size;
 	int bytes_remaining;
 
 	sync();
@@ -123,12 +124,18 @@ static void program_ecc(u32 start_address,
 	 * watchdog.
 	 */
 	while (bytes_remaining > 0) {
-		dcbz_area(current_addr, min((64 << 20), bytes_remaining));
+		size = min((64 << 20), bytes_remaining);
+
+		/* Write zero's to SDRAM */
+		dcbz_area(current_addr, size);
+
+		/* Write modified dcache lines back to memory */
+		clean_dcache_range(current_addr, current_addr + size);
+
 		current_addr += 64 << 20;
 		bytes_remaining -= 64 << 20;
 		WATCHDOG_RESET();
 	}
-	dflush();
 
 	sync();
 	wait_ddr_idle();

board/netstal/hcu5/sdram.c

@@ -34,11 +34,11 @@
 #include <asm/processor.h>
 #include <asm/io.h>
 #include <asm/mmu.h>
+#include <asm/cache.h>
 #include <ppc440.h>
 
 void hcu_led_set(u32 value);
 void dcbz_area(u32 start_address, u32 num_bytes);
-void dflush(void);
 
 #define DDR_DCR_BASE 0x10
 #define ddrcfga  (DDR_DCR_BASE+0x0)   /* DDR configuration address reg */
@@ -185,14 +185,14 @@ static void program_ecc(unsigned long start_address, unsigned long num_bytes)
 #endif
 
 	sync();
-	eieio();
 
 	puts(str);
 
 	/* ECC bit set method for cached memory */
 	/* Fast method, no noticeable delay */
 	dcbz_area(start_address, num_bytes);
-	dflush();
+	/* Write modified dcache lines back to memory */
+	clean_dcache_range(start_address, start_address + num_bytes);
 	blank_string(strlen(str));
 
 	/* Clear error status */

board/sbc8548/sbc8548.c

@@ -299,7 +299,7 @@ long int fixed_sdram (void)
 	ddr->cs1_config		= 0x80010101;
 	ddr->cs2_config		= 0x00000000;
 	ddr->cs3_config		= 0x00000000;
-	ddr->ext_refrec		= 0x00000000;
+	ddr->timing_cfg_3		= 0x00000000;
 	ddr->timing_cfg_0	= 0x00220802;
 	ddr->timing_cfg_1	= 0x38377322;
 	ddr->timing_cfg_2	= 0x0fa044C7;

board/sbc8641d/sbc8641d.c

@@ -135,7 +135,7 @@ long int fixed_sdram (void)
 	ddr->cs1_config = CFG_DDR_CS1_CONFIG;
 	ddr->cs2_config = CFG_DDR_CS2_CONFIG;
 	ddr->cs3_config = CFG_DDR_CS3_CONFIG;
-	ddr->ext_refrec = CFG_DDR_EXT_REFRESH;
+	ddr->timing_cfg_3 = CFG_DDR_TIMING_3;
 	ddr->timing_cfg_0 = CFG_DDR_TIMING_0;
 	ddr->timing_cfg_1 = CFG_DDR_TIMING_1;
 	ddr->timing_cfg_2 = CFG_DDR_TIMING_2;
@@ -166,7 +166,7 @@ long int fixed_sdram (void)
 	ddr->cs1_config = CFG_DDR2_CS1_CONFIG;
 	ddr->cs2_config = CFG_DDR2_CS2_CONFIG;
 	ddr->cs3_config = CFG_DDR2_CS3_CONFIG;
-	ddr->ext_refrec = CFG_DDR2_EXT_REFRESH;
+	ddr->timing_cfg_3 = CFG_DDR2_EXT_REFRESH;
 	ddr->timing_cfg_0 = CFG_DDR2_TIMING_0;
 	ddr->timing_cfg_1 = CFG_DDR2_TIMING_1;
 	ddr->timing_cfg_2 = CFG_DDR2_TIMING_2;

board/trizepsiv/eeprom.c

@@ -24,7 +24,6 @@
 #include <common.h>
 #include <command.h>
 
-static unsigned char srom[128];
 extern u16 read_srom_word(int);
 extern void write_srom_word(int offset, u16 val);
 

common/cmd_ide.c

@@ -1264,7 +1264,7 @@ ulong ide_read (int device, lbaint_t blknr, ulong blkcnt, void *buffer)
 #ifdef CONFIG_LBA48
 	unsigned char lba48 = 0;
 
-	if (blknr & 0x0000fffff0000000) {
+	if (blknr & 0x0000fffff0000000ULL) {
 		/* more than 28 bits used, use 48bit mode */
 		lba48 = 1;
 	}
@@ -1318,8 +1318,13 @@ ulong ide_read (int device, lbaint_t blknr, ulong blkcnt, void *buffer)
 			/* write high bits */
 			ide_outb (device, ATA_SECT_CNT, 0);
 			ide_outb (device, ATA_LBA_LOW,	(blknr >> 24) & 0xFF);
+#ifdef CFG_64BIT_LBA
 			ide_outb (device, ATA_LBA_MID,	(blknr >> 32) & 0xFF);
 			ide_outb (device, ATA_LBA_HIGH, (blknr >> 40) & 0xFF);
+#else
+			ide_outb (device, ATA_LBA_MID,	0);
+			ide_outb (device, ATA_LBA_HIGH, 0);
+#endif
 		}
 #endif
 		ide_outb (device, ATA_SECT_CNT, 1);
@@ -1383,7 +1388,7 @@ ulong ide_write (int device, lbaint_t blknr, ulong blkcnt, void *buffer)
 #ifdef CONFIG_LBA48
 	unsigned char lba48 = 0;
 
-	if (blknr & 0x0000fffff0000000) {
+	if (blknr & 0x0000fffff0000000ULL) {
 		/* more than 28 bits used, use 48bit mode */
 		lba48 = 1;
 	}
@@ -1408,8 +1413,13 @@ ulong ide_write (int device, lbaint_t blknr, ulong blkcnt, void *buffer)
 			/* write high bits */
 			ide_outb (device, ATA_SECT_CNT, 0);
 			ide_outb (device, ATA_LBA_LOW,	(blknr >> 24) & 0xFF);
+#ifdef CFG_64BIT_LBA
 			ide_outb (device, ATA_LBA_MID,	(blknr >> 32) & 0xFF);
 			ide_outb (device, ATA_LBA_HIGH, (blknr >> 40) & 0xFF);
+#else
+			ide_outb (device, ATA_LBA_MID,	0);
+			ide_outb (device, ATA_LBA_HIGH, 0);
+#endif
 		}
 #endif
 		ide_outb (device, ATA_SECT_CNT, 1);

common/cmd_nand.c

@@ -93,7 +93,7 @@ static inline int str2long(char *p, ulong *num)
 }
 
 static int
-arg_off_size(int argc, char *argv[], nand_info_t *nand, ulong *off, ulong *size)
+arg_off_size(int argc, char *argv[], nand_info_t *nand, ulong *off, size_t *size)
 {
 	int idx = nand_curr_device;
 #if defined(CONFIG_CMD_JFFS2) && defined(CONFIG_JFFS2_CMDLINE)
@@ -110,7 +110,7 @@ arg_off_size(int argc, char *argv[], nand_info_t *nand, ulong *off, ulong *size)
 			}
 			*off = part->offset;
 			if (argc >= 2) {
-				if (!(str2long(argv[1], size))) {
+				if (!(str2long(argv[1], (ulong *)size))) {
 					printf("'%s' is not a number\n", argv[1]);
 					return -1;
 				}
@@ -136,7 +136,7 @@ arg_off_size(int argc, char *argv[], nand_info_t *nand, ulong *off, ulong *size)
 	}
 
 	if (argc >= 2) {
-		if (!(str2long(argv[1], size))) {
+		if (!(str2long(argv[1], (ulong *)size))) {
 			printf("'%s' is not a number\n", argv[1]);
 			return -1;
 		}
@@ -158,7 +158,8 @@ out:
 int do_nand(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
 {
 	int i, dev, ret;
-	ulong addr, off, size;
+	ulong addr, off;
+	size_t size;
 	char *cmd, *s;
 	nand_info_t *nand;
 #ifdef CFG_NAND_QUIET
@@ -350,10 +351,10 @@ int do_nand(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
 		} else if (s != NULL && !strcmp(s, ".oob")) {
 			/* read out-of-band data */
 			if (read)
-				ret = nand->read_oob(nand, off, size, (size_t *) &size,
+				ret = nand->read_oob(nand, off, size, &size,
 						     (u_char *) addr);
 			else
-				ret = nand->write_oob(nand, off, size, (size_t *) &size,
+				ret = nand->write_oob(nand, off, size, &size,
 						      (u_char *) addr);
 		} else {
 			if (read)
@@ -481,7 +482,7 @@ static int nand_load_image(cmd_tbl_t *cmdtp, nand_info_t *nand,
 {
 	int r;
 	char *ep, *s;
-	ulong cnt;
+	size_t cnt;
 	image_header_t *hdr;
 	int jffs2 = 0;
 #if defined(CONFIG_FIT)
@@ -839,23 +840,24 @@ int do_nand (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
 
 		if (strncmp (argv[1], "read", 4) == 0 ||
 		    strncmp (argv[1], "write", 5) == 0) {
-			ulong addr = simple_strtoul (argv[2], NULL, 16);
-			ulong off = simple_strtoul (argv[3], NULL, 16);
-			ulong size = simple_strtoul (argv[4], NULL, 16);
-			int cmd = (strncmp (argv[1], "read", 4) == 0) ?
-				NANDRW_READ : NANDRW_WRITE;
-			int ret, total;
+			ulong	addr = simple_strtoul (argv[2], NULL, 16);
+			off_t	off  = simple_strtoul (argv[3], NULL, 16);
+			size_t	size = simple_strtoul (argv[4], NULL, 16);
+			int	cmd = (strncmp (argv[1], "read", 4) == 0) ?
+					NANDRW_READ : NANDRW_WRITE;
+			size_t total;
+			int ret;
 			char *cmdtail = strchr (argv[1], '.');
 
 			if (cmdtail && !strncmp (cmdtail, ".oob", 2)) {
 				/* read out-of-band data */
 				if (cmd & NANDRW_READ) {
 					ret = nand_read_oob (nand_dev_desc + curr_device,
-							     off, size, (size_t *) & total,
+							     off, size, &total,
 							     (u_char *) addr);
 				} else {
 					ret = nand_write_oob (nand_dev_desc + curr_device,
-							      off, size, (size_t *) & total,
+							      off, size, &total,
 							      (u_char *) addr);
 				}
 				return ret;
@@ -891,7 +893,7 @@ int do_nand (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
 
 			ret = nand_legacy_rw (nand_dev_desc + curr_device,
 					      cmd, off, size,
-					      (size_t *) & total,
+					      &total,
 					      (u_char *) addr);
 
 			printf (" %d bytes %s: %s\n", total,

common/env_flash.c

@@ -378,7 +378,9 @@ void env_relocate_spec (void)
 		puts ("*** Warning - some problems detected "
 		      "reading environment; recovered successfully\n\n");
 #endif /* CFG_ENV_ADDR_REDUND */
+#ifdef CMD_SAVEENV
 	memcpy (env_ptr, (void*)flash_addr, CFG_ENV_SIZE);
+#endif
 #endif /* ! ENV_IS_EMBEDDED || CFG_ENV_ADDR_REDUND */
 }
 

common/env_nand.c

@@ -102,7 +102,7 @@ uchar env_get_char_spec (int index)
 int env_init(void)
 {
 #if defined(ENV_IS_EMBEDDED)
-	ulong total;
+	size_t total;
 	int crc1_ok = 0, crc2_ok = 0;
 	env_t *tmp_env1, *tmp_env2;
 
@@ -154,7 +154,7 @@ int env_init(void)
 #ifdef CFG_ENV_OFFSET_REDUND
 int saveenv(void)
 {
-	ulong total;
+	size_t total;
 	int ret = 0;
 
 	env_ptr->flags++;
@@ -188,7 +188,7 @@ int saveenv(void)
 #else /* ! CFG_ENV_OFFSET_REDUND */
 int saveenv(void)
 {
-	ulong total;
+	size_t total;
 	int ret = 0;
 
 	puts ("Erasing Nand...");
@@ -211,7 +211,7 @@ int saveenv(void)
 void env_relocate_spec (void)
 {
 #if !defined(ENV_IS_EMBEDDED)
-	ulong total;
+	size_t total;
 	int crc1_ok = 0, crc2_ok = 0;
 	env_t *tmp_env1, *tmp_env2;
 
@@ -268,7 +268,7 @@ void env_relocate_spec (void)
 void env_relocate_spec (void)
 {
 #if !defined(ENV_IS_EMBEDDED)
-	ulong total;
+	size_t total;
 	int ret;
 
 	total = CFG_ENV_SIZE;

config.mk

@@ -69,27 +69,6 @@ PLATFORM_CPPFLAGS+= -D__ARM__
 endif
 endif
 
-# Load generated board configuration
-sinclude $(OBJTREE)/include/autoconf.mk
-
-ifdef	ARCH
-sinclude $(TOPDIR)/$(ARCH)_config.mk	# include architecture dependend rules
-endif
-ifdef	CPU
-sinclude $(TOPDIR)/cpu/$(CPU)/config.mk	# include  CPU	specific rules
-endif
-ifdef	SOC
-sinclude $(TOPDIR)/cpu/$(CPU)/$(SOC)/config.mk	# include  SoC	specific rules
-endif
-ifdef	VENDOR
-BOARDDIR = $(VENDOR)/$(BOARD)
-else
-BOARDDIR = $(BOARD)
-endif
-ifdef	BOARD
-sinclude $(TOPDIR)/board/$(BOARDDIR)/config.mk	# include board specific rules
-endif
-
 #########################################################################
 
 CONFIG_SHELL	:= $(shell if [ -x "$$BASH" ]; then echo $$BASH; \
@@ -127,6 +106,31 @@ OBJCOPY = $(CROSS_COMPILE)objcopy
 OBJDUMP = $(CROSS_COMPILE)objdump
 RANLIB	= $(CROSS_COMPILE)RANLIB
 
+#########################################################################
+
+# Load generated board configuration
+sinclude $(OBJTREE)/include/autoconf.mk
+
+ifdef	ARCH
+sinclude $(TOPDIR)/$(ARCH)_config.mk	# include architecture dependend rules
+endif
+ifdef	CPU
+sinclude $(TOPDIR)/cpu/$(CPU)/config.mk	# include  CPU	specific rules
+endif
+ifdef	SOC
+sinclude $(TOPDIR)/cpu/$(CPU)/$(SOC)/config.mk	# include  SoC	specific rules
+endif
+ifdef	VENDOR
+BOARDDIR = $(VENDOR)/$(BOARD)
+else
+BOARDDIR = $(BOARD)
+endif
+ifdef	BOARD
+sinclude $(TOPDIR)/board/$(BOARDDIR)/config.mk	# include board specific rules
+endif
+
+#########################################################################
+
 ifneq (,$(findstring s,$(MAKEFLAGS)))
 ARFLAGS = cr
 else

cpu/mips/cache.S

@@ -285,6 +285,22 @@ LEAF(dcache_disable)
 	jr	ra
 	END(dcache_disable)
 
+/*******************************************************************************
+*
+* dcache_enable - enable cache
+*
+* RETURNS: N/A
+*
+*/
+LEAF(dcache_enable)
+	mfc0	t0, CP0_CONFIG
+	ori	t0, CONF_CM_CMASK
+	xori	t0, CONF_CM_CMASK
+	ori	t0, CONF_CM_CACHABLE_NONCOHERENT
+	mtc0	t0, CP0_CONFIG
+	jr	ra
+	END(dcache_enable)
+
 #ifdef CFG_INIT_RAM_LOCK_MIPS
 /*******************************************************************************
 *

cpu/mips/config.mk

@@ -20,7 +20,7 @@
 # Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 # MA 02111-1307 USA
 #
-v=$(shell $(AS) --version |grep "GNU assembler" |cut -d. -f2)
+v=$(shell $(AS) --version | grep 'GNU assembler' | egrep -o '2\.[0-9\.]+' | cut -d. -f2)
 MIPSFLAGS:=$(shell \
 if [ "$v" -lt "14" ]; then \
 	echo "-mcpu=4kc"; \

cpu/mpc85xx/config.mk

@@ -25,3 +25,4 @@ PLATFORM_RELFLAGS += -fPIC -ffixed-r14 -meabi
 
 PLATFORM_CPPFLAGS += -DCONFIG_MPC85xx -DCONFIG_E500 -ffixed-r2 \
 			-Wa,-me500 -msoft-float -mno-string
+PLATFORM_CPPFLAGS +=$(call cc-option,-mno-spe)

cpu/mpc85xx/mp.c

@@ -103,6 +103,10 @@ int cpu_release(int nr, int argc, char *argv[])
 	}
 
 	table[BOOT_ENTRY_ADDR_UPPER] = (u32)(boot_addr >> 32);
+
+	/* ensure all table updates complete before final address write */
+	eieio();
+
 	table[BOOT_ENTRY_ADDR_LOWER] = (u32)(boot_addr & 0xffffffff);
 
 	return 0;
@@ -153,7 +157,7 @@ static void pq3_mp_up(unsigned long bootpg)
 	/* wait for everyone */
 	while (timeout) {
 		int i;
-		for (i = 1; i < CONFIG_NR_CPUS; i++) {
+		for (i = 0; i < CONFIG_NR_CPUS; i++) {
 			if (table[i * NUM_BOOT_ENTRY + BOOT_ENTRY_ADDR_LOWER])
 				cpu_up_mask |= (1 << i);
 		};

cpu/mpc85xx/release.S

@@ -114,6 +114,7 @@ __secondary_start_page:
 	lwz	r4,ENTRY_ADDR_LOWER(r10)
 	andi.	r11,r4,1
 	bne	2b
+	isync
 
 	/* get the upper bits of the addr */
 	lwz	r11,ENTRY_ADDR_UPPER(r10)
@@ -169,7 +170,7 @@ __secondary_start_page:
 	mtspr	SPRN_SRR1,r13
 	rfi
 
-	.align 3
+	.align L1_CACHE_SHIFT
 	.globl __spin_table
 __spin_table:
 	.space CONFIG_NR_CPUS*ENTRY_SIZE

cpu/mpc85xx/spd_sdram.c

@@ -610,8 +610,8 @@ spd_sdram(void)
 	/*
 	 * Sneak in some Extended Refresh Recovery.
 	 */
-	ddr->ext_refrec = (trfc_high << 16);
-	debug("DDR: ext_refrec = 0x%08x\n", ddr->ext_refrec);
+	ddr->timing_cfg_3 = (trfc_high << 16);
+	debug("DDR: timing_cfg_3 = 0x%08x\n", ddr->timing_cfg_3);
 
 	ddr->timing_cfg_1 =
 	    (0

cpu/mpc86xx/spd_sdram.c

@@ -644,8 +644,8 @@ spd_init(unsigned char i2c_address, unsigned int ddr_num,
 	/*
 	 * Sneak in some Extended Refresh Recovery.
 	 */
-	ddr->ext_refrec = (trfc_high << 16);
-	debug("DDR: ext_refrec = 0x%08x\n", ddr->ext_refrec);
+	ddr->timing_cfg_3 = (trfc_high << 16);
+	debug("DDR: timing_cfg_3 = 0x%08x\n", ddr->timing_cfg_3);
 
 	ddr->timing_cfg_1 =
 	    (0

cpu/mpc86xx/speed.c

@@ -105,8 +105,20 @@ int get_clocks(void)
 	get_sys_info(&sys_info);
 	gd->cpu_clk = sys_info.freqProcessor;
 	gd->bus_clk = sys_info.freqSystemBus;
+
+	/*
+	 * The base clock for I2C depends on the actual SOC.  Unfortunately,
+	 * there is no pattern that can be used to determine the frequency, so
+	 * the only choice is to look up the actual SOC number and use the value
+	 * for that SOC. This information is taken from application note
+	 * AN2919.
+	 */
+#ifdef CONFIG_MPC8610
 	gd->i2c1_clk = sys_info.freqSystemBus;
-	gd->i2c2_clk = sys_info.freqSystemBus;
+#else
+	gd->i2c1_clk = sys_info.freqSystemBus / 2;
+#endif
+	gd->i2c2_clk = gd->i2c1_clk;
 
 	if (gd->cpu_clk != 0)
 		return 0;

cpu/ppc4xx/44x_spd_ddr2.c

@@ -1,7 +1,10 @@
 /*
  * cpu/ppc4xx/44x_spd_ddr2.c
  * This SPD SDRAM detection code supports AMCC PPC44x cpu's with a
- * DDR2 controller (non Denali Core). Those are 440SP/SPe.
+ * DDR2 controller (non Denali Core). Those currently are:
+ *
+ * 405:		405EX
+ * 440/460:	440SP/440SPe/460EX/460GT
  *
  * (C) Copyright 2007-2008
  * Stefan Roese, DENX Software Engineering, sr@denx.de.
@@ -40,6 +43,7 @@
 #include <asm/io.h>
 #include <asm/processor.h>
 #include <asm/mmu.h>
+#include <asm/cache.h>
 
 #if defined(CONFIG_SPD_EEPROM) &&				\
 	(defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
@@ -237,7 +241,6 @@ static void	DQS_calibration_process(void);
 static void ppc440sp_sdram_register_dump(void);
 int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]);
 void dcbz_area(u32 start_address, u32 num_bytes);
-void dflush(void);
 
 static u32 mfdcr_any(u32 dcr)
 {
@@ -2078,7 +2081,7 @@ static void program_bxcf(unsigned long *dimm_populated,
 				if (num_banks == 4)
 					ind = 0;
 				else
-					ind = 5;
+					ind = 5 << 8;
 				switch (num_col_addr) {
 				case 0x08:
 					mode |= (SDRAM_BXCF_M_AM_0 + ind);
@@ -2355,7 +2358,8 @@ static void program_ecc_addr(unsigned long start_address,
 		} else {
 			/* ECC bit set method for cached memory */
 			dcbz_area(start_address, num_bytes);
-			dflush();
+			/* Write modified dcache lines back to memory */
+			clean_dcache_range(start_address, start_address + num_bytes);
 		}
 
 		blank_string(strlen(str));

cpu/ppc4xx/denali_spd_ddr2.c

@@ -45,6 +45,7 @@
 #include <asm/io.h>
 #include <asm/processor.h>
 #include <asm/mmu.h>
+#include <asm/cache.h>
 
 #if defined(CONFIG_SPD_EEPROM) &&				\
 	(defined(CONFIG_440EPX) || defined(CONFIG_440GRX))
@@ -92,7 +93,6 @@
 extern int denali_wait_for_dlllock(void);
 extern void denali_core_search_data_eye(void);
 extern void dcbz_area(u32 start_address, u32 num_bytes);
-extern void dflush(void);
 
 /*
  * Board-specific Platform code can reimplement spd_ddr_init_hang () if needed
@@ -1201,7 +1201,8 @@ long int initdram(int board_type)
 #else
 #error Please define CFG_MEM_TOP_HIDE (see README) in your board config file
 #endif
-	dflush();
+	/* Write modified dcache lines back to memory */
+	clean_dcache_range(CFG_SDRAM_BASE, CFG_SDRAM_BASE + dram_size - CFG_MEM_TOP_HIDE);
 	debug("Completed\n");
 	sync();
 	remove_tlb(CFG_SDRAM_BASE, dram_size);

cpu/ppc4xx/fdt.c

@@ -83,8 +83,14 @@ void ft_cpu_setup(void *blob, bd_t *bd)
 			     bd->bi_intfreq, 1);
 	do_fixup_by_path_u32(blob, "/plb", "clock-frequency", sys_info.freqPLB, 1);
 	do_fixup_by_path_u32(blob, "/plb/opb", "clock-frequency", sys_info.freqOPB, 1);
-	do_fixup_by_path_u32(blob, "/plb/opb/ebc", "clock-frequency",
-			     sys_info.freqEBC, 1);
+
+	if (fdt_path_offset(blob, "/plb/opb/ebc") >= 0)
+		do_fixup_by_path_u32(blob, "/plb/opb/ebc", "clock-frequency",
+			sys_info.freqEBC, 1);
+	else
+		do_fixup_by_path_u32(blob, "/plb/ebc", "clock-frequency",
+			sys_info.freqEBC, 1);
+
 	fdt_fixup_memory(blob, (u64)bd->bi_memstart, (u64)bd->bi_memsize);
 
 	/*

cpu/ppc4xx/start.S

@@ -1675,35 +1675,6 @@ trap_reloc:
 	sync
 	blr
 	function_epilog(dcbz_area)
-
-/*----------------------------------------------------------------------------+
-| dflush.  Assume 32K at vector address is cachable.
-+----------------------------------------------------------------------------*/
-	function_prolog(dflush)
-	mfmsr	r9
-	rlwinm	r8,r9,0,15,13
-	rlwinm	r8,r8,0,17,15
-	mtmsr	r8
-	mfspr	r8,dvlim
-	addi	r3,r0,0x0000
-	mtspr	dvlim,r3
-	mfspr	r3,ivpr
-	addi	r4,r0,1024
-	mtctr	r4
-..dflush_loop:
-	lwz	r6,0x0(r3)
-	addi	r3,r3,32
-	bdnz	..dflush_loop
-	addi	r3,r3,-32
-	mtctr	r4
-..ag:	dcbf	r0,r3
-	addi	r3,r3,-32
-	bdnz	..ag
-	mtspr	dvlim,r8
-	sync
-	mtmsr	r9
-	blr
-	function_epilog(dflush)
 #endif /* CONFIG_440 */
 #endif /* CONFIG_NAND_SPL */
 

cpu/pxa/start.S

@@ -166,17 +166,13 @@ _start_armboot: .word start_armboot
 /*									    */
 /****************************************************************************/
 /* mk@tbd: Fix this! */
-#if defined(CONFIG_PXA250) || defined(CONFIG_CPU_MONAHANS)
+#undef RCSR
 #undef ICMR
 #undef OSMR3
 #undef OSCR
 #undef OWER
 #undef OIER
-#endif /* CONFIG_PXA250 || CONFIG_CPU_MONAHANS */
-#ifdef CONFIG_PXA250
-#undef RCSR
 #undef CCCR
-#endif /* CONFIG_PXA250 */
 
 /* Interrupt-Controller base address					    */
 IC_BASE:	   .word	   0x40d00000

doc/README.qemu_mips

@@ -0,0 +1,18 @@
+
+Notes for the Qemu MIPS port
+
+Example usage:
+
+# ln -s u-boot.bin mips_bios.bin
+start it:
+qemu-system-mips -L . /dev/null -nographic
+
+or
+
+if you use a qemu version after commit 4224
+
+create image:
+# dd of=flash bs=1k count=4k if=/dev/zero
+# dd of=flash bs=1k conv=notrunc if=u-boot.bin
+start it:
+# qemu-system-mips -pflash flash -monitor null -nographic

drivers/mtd/onenand/onenand_base.c

@@ -21,7 +21,7 @@
 #include <asm/errno.h>
 
 /* It should access 16-bit instead of 8-bit */
-static inline void *memcpy(void *dst, const void *src, unsigned int len)
+static inline void *memcpy_16(void *dst, const void *src, unsigned int len)
 {
 	void *ret = dst;
 	short *d = dst;
@@ -358,7 +358,7 @@ static int onenand_read_bufferram(struct mtd_info *mtd, int area,
 	bufferram = this->base + area;
 	bufferram += onenand_bufferram_offset(mtd, area);
 
-	memcpy(buffer, bufferram + offset, count);
+	memcpy_16(buffer, bufferram + offset, count);
 
 	return 0;
 }
@@ -385,7 +385,7 @@ static int onenand_sync_read_bufferram(struct mtd_info *mtd, int area,
 
 	this->mmcontrol(mtd, ONENAND_SYS_CFG1_SYNC_READ);
 
-	memcpy(buffer, bufferram + offset, count);
+	memcpy_16(buffer, bufferram + offset, count);
 
 	this->mmcontrol(mtd, 0);
 
@@ -412,7 +412,7 @@ static int onenand_write_bufferram(struct mtd_info *mtd, int area,
 	bufferram = this->base + area;
 	bufferram += onenand_bufferram_offset(mtd, area);
 
-	memcpy(bufferram + offset, buffer, count);
+	memcpy_16(bufferram + offset, buffer, count);
 
 	return 0;
 }

drivers/net/Makefile

@@ -42,7 +42,10 @@ COBJS-y += lan91c96.o
 COBJS-y += macb.o
 COBJS-y += mcffec.o
 COBJS-y += natsemi.o
-COBJS-$(CONFIG_DRIVER_NE2000) += ne2000.o
+ifeq ($(CONFIG_DRIVER_NE2000),y)
+COBJS-y += ne2000.o
+COBJS-$(CONFIG_DRIVER_AX88796L) += ax88796.o
+endif
 COBJS-y += netarm_eth.o
 COBJS-y += netconsole.o
 COBJS-y += ns7520_eth.o

drivers/net/ax88796.c

@@ -0,0 +1,156 @@
+/*
+ * (c) 2007 Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+#include <common.h>
+#include "ax88796.h"
+
+/*
+ * Set 1 bit data
+ */
+static void ax88796_bitset(u32 bit)
+{
+	/* DATA1 */
+	if( bit )
+		EEDI_HIGH;
+	else
+		EEDI_LOW;
+
+	EECLK_LOW;
+	udelay(1000);
+	EECLK_HIGH;
+	udelay(1000);
+	EEDI_LOW;
+}
+
+/*
+ * Get 1 bit data
+ */
+static u8 ax88796_bitget(void)
+{
+	u8 bit;
+
+	EECLK_LOW;
+	udelay(1000);
+	/* DATA */
+	bit = EEDO;
+	EECLK_HIGH;
+	udelay(1000);
+
+	return bit;
+}
+
+/*
+ * Send COMMAND to EEPROM
+ */
+static void ax88796_eep_cmd(u8 cmd)
+{
+	ax88796_bitset(BIT_DUMMY);
+	switch(cmd){
+		case MAC_EEP_READ:
+			ax88796_bitset(1);
+			ax88796_bitset(1);
+			ax88796_bitset(0);
+			break;
+
+		case MAC_EEP_WRITE:
+			ax88796_bitset(1);
+			ax88796_bitset(0);
+			ax88796_bitset(1);
+			break;
+
+		case MAC_EEP_ERACE:
+			ax88796_bitset(1);
+			ax88796_bitset(1);
+			ax88796_bitset(1);
+			break;
+
+		case MAC_EEP_EWEN:
+			ax88796_bitset(1);
+			ax88796_bitset(0);
+			ax88796_bitset(0);
+			break;
+
+		case MAC_EEP_EWDS:
+			ax88796_bitset(1);
+			ax88796_bitset(0);
+			ax88796_bitset(0);
+			break;
+		default:
+			break;
+	}
+}
+
+static void ax88796_eep_setaddr(u16 addr)
+{
+	int i ;
+
+	for( i = 7 ; i >= 0 ; i-- )
+		ax88796_bitset(addr & (1 << i));
+}
+
+/*
+ * Get data from EEPROM
+ */
+static u16 ax88796_eep_getdata(void)
+{
+	ushort data = 0;
+	int i;
+
+	ax88796_bitget();	/* DUMMY */
+	for( i = 0 ; i < 16 ; i++ ){
+		data <<= 1;
+		data |= ax88796_bitget();
+	}
+	return data;
+}
+
+static void ax88796_mac_read(u8 *buff)
+{
+	int i ;
+	u16 data;
+	u16 addr = 0;
+
+	for( i = 0 ; i < 3; i++ )
+	{
+		EECS_HIGH;
+		EEDI_LOW;
+		udelay(1000);
+		/* READ COMMAND */
+		ax88796_eep_cmd(MAC_EEP_READ);
+		/* ADDRESS */
+		ax88796_eep_setaddr(addr++);
+		/* GET DATA */
+		data = ax88796_eep_getdata();
+		*buff++ = (uchar)(data & 0xff);
+		*buff++ = (uchar)((data >> 8) & 0xff);
+		EECLK_LOW;
+		EEDI_LOW;
+		EECS_LOW;
+	}
+}
+
+int get_prom(u8* mac_addr)
+{
+	u8 prom[32];
+	int i;
+
+	ax88796_mac_read(prom);
+	for (i = 0; i < 6; i++){
+		mac_addr[i] = prom[i];
+	}
+	return 1;
+}

drivers/net/ax88796.h

@@ -78,140 +78,4 @@
 #define DP_OUT_DATA(_b_, _d_)	*( (vu_short *) ((_b_)+ISA_OFFSET)) = (_d_)
 #endif
 
-
-/*
- * Set 1 bit data
- */
-static void ax88796_bitset(u32 bit)
-{
-	/* DATA1 */
-	if( bit )
-		EEDI_HIGH;
-	else
-		EEDI_LOW;
-
-	EECLK_LOW;
-	udelay(1000);
-	EECLK_HIGH;
-	udelay(1000);
-	EEDI_LOW;
-}
-
-/*
- * Get 1 bit data
- */
-static u8 ax88796_bitget(void)
-{
-	u8 bit;
-
-	EECLK_LOW;
-	udelay(1000);
-	/* DATA */
-	bit = EEDO;
-	EECLK_HIGH;
-	udelay(1000);
-
-	return bit;
-}
-
-/*
- * Send COMMAND to EEPROM
- */
-static void ax88796_eep_cmd(u8 cmd)
-{
-	ax88796_bitset(BIT_DUMMY);
-	switch(cmd){
-		case MAC_EEP_READ:
-			ax88796_bitset(1);
-			ax88796_bitset(1);
-			ax88796_bitset(0);
-			break;
-
-		case MAC_EEP_WRITE:
-			ax88796_bitset(1);
-			ax88796_bitset(0);
-			ax88796_bitset(1);
-			break;
-
-		case MAC_EEP_ERACE:
-			ax88796_bitset(1);
-			ax88796_bitset(1);
-			ax88796_bitset(1);
-			break;
-
-		case MAC_EEP_EWEN:
-			ax88796_bitset(1);
-			ax88796_bitset(0);
-			ax88796_bitset(0);
-			break;
-
-		case MAC_EEP_EWDS:
-			ax88796_bitset(1);
-			ax88796_bitset(0);
-			ax88796_bitset(0);
-			break;
-		default:
-			break;
-	}
-}
-
-static void ax88796_eep_setaddr(u16 addr)
-{
-	int i ;
-	for( i = 7 ; i >= 0 ; i-- )
-		ax88796_bitset(addr & (1 << i));
-}
-
-/*
- * Get data from EEPROM
- */
-static u16 ax88796_eep_getdata(void)
-{
-	ushort data = 0;
-	int i;
-
-	ax88796_bitget();	/* DUMMY */
-	for( i = 0 ; i < 16 ; i++ ){
-		data <<= 1;
-		data |= ax88796_bitget();
-	}
-	return data;
-}
-
-static void ax88796_mac_read(u8 *buff)
-{
-	int i ;
-	u16 data, addr = 0;
-
-	for( i = 0 ; i < 3; i++ )
-	{
-		EECS_HIGH;
-		EEDI_LOW;
-		udelay(1000);
-		/* READ COMMAND */
-		ax88796_eep_cmd(MAC_EEP_READ);
-		/* ADDRESS */
-		ax88796_eep_setaddr(addr++);
-		/* GET DATA */
-		data = ax88796_eep_getdata();
-		*buff++ = (uchar)(data & 0xff);
-		*buff++ = (uchar)((data >> 8) & 0xff);
-		EECLK_LOW;
-		EEDI_LOW;
-		EECS_LOW;
-	}
-}
-
-int get_prom(u8* mac_addr)
-{
-	u8 prom[32];
-	int i;
-
-	ax88796_mac_read(prom);
-	for (i = 0; i < 6; i++){
-		mac_addr[i] = prom[i];
-	}
-	return 1;
-}
-
 #endif /* __DRIVERS_AX88796L_H__ */

drivers/net/cs8900.c

@@ -65,14 +65,14 @@ static unsigned short get_reg_init_bus (int regno)
 	c = CS8900_BUS16_0;
 
 	CS8900_PPTR = regno;
-	return (unsigned short) CS8900_PDATA;
+	return CS8900_PDATA;
 }
 #endif
 
 static unsigned short get_reg (int regno)
 {
 	CS8900_PPTR = regno;
-	return (unsigned short) CS8900_PDATA;
+	return CS8900_PDATA;
 }
 
 
@@ -131,7 +131,7 @@ void cs8900_get_enetaddr (uchar * addr)
 	if (get_reg_init_bus (PP_ChipID) != 0x630e)
 		return;
 	eth_reset ();
-	if ((get_reg (PP_SelfST) & (PP_SelfSTAT_EEPROM | PP_SelfSTAT_EEPROM_OK)) ==
+	if ((get_reg (PP_SelfSTAT) & (PP_SelfSTAT_EEPROM | PP_SelfSTAT_EEPROM_OK)) ==
 			(PP_SelfSTAT_EEPROM | PP_SelfSTAT_EEPROM_OK)) {
 
 		/* Load the MAC from EEPROM */
@@ -168,7 +168,6 @@ void cs8900_get_enetaddr (uchar * addr)
 			debug ("### Set environment from HW MAC addr = \"%s\"\n", ethaddr);
 			setenv ("ethaddr", ethaddr);
 		}
-
 	}
 }
 
@@ -183,7 +182,6 @@ void eth_halt (void)
 
 int eth_init (bd_t * bd)
 {
-
 	/* verify chip id */
 	if (get_reg_init_bus (PP_ChipID) != 0x630e) {
 		printf ("CS8900 Ethernet chip not found?!\n");
@@ -201,7 +199,7 @@ int eth_init (bd_t * bd)
 }
 
 /* Get a data block via Ethernet */
-extern int eth_rx (void)
+int eth_rx (void)
 {
 	int i;
 	unsigned short rxlen;
@@ -233,7 +231,7 @@ extern int eth_rx (void)
 }
 
 /* Send a data block via Ethernet. */
-extern int eth_send (volatile void *packet, int length)
+int eth_send (volatile void *packet, int length)
 {
 	volatile unsigned short *addr;
 	int tmo;
@@ -281,7 +279,8 @@ retry:
 
 static void cs8900_e2prom_ready(void)
 {
-	while(get_reg(PP_SelfST) & SI_BUSY);
+	while (get_reg(PP_SelfSTAT) & SI_BUSY)
+		;
 }
 
 /***********************************************************/

drivers/net/cs8900.h

@@ -243,7 +243,6 @@
 
 /* EEPROM Kram */
 #define SI_BUSY 0x0100
-#define PP_SelfST 0x0136	/*  Self State register */
 #define PP_EECMD 0x0040		/*  NVR Interface Command register */
 #define PP_EEData 0x0042	/*  NVR Interface Data Register */
 #define EEPROM_WRITE_EN		0x00F0

drivers/net/fsl_mcdmafec.c

@@ -95,7 +95,11 @@ struct fec_info_dma fec_info[] = {
 	 0,			/* duplex and speed */
 	 0,			/* phy name */
 	 0,			/* phy name init */
+#ifdef CFG_DMA_USE_INTSRAM
+	 DBUF_LENGTH,		/* RX BD */
+#else
 	 0,			/* RX BD */
+#endif
 	 0,			/* TX BD */
 	 0,			/* rx Index */
 	 0,			/* tx Index */
@@ -164,7 +168,8 @@ static void dbg_fec_regs(struct eth_device *dev)
 }
 #endif
 
-static void set_fec_duplex_speed(volatile fecdma_t * fecp, bd_t * bd, int dup_spd)
+static void set_fec_duplex_speed(volatile fecdma_t * fecp, bd_t * bd,
+				 int dup_spd)
 {
 	if ((dup_spd >> 16) == FULL) {
 		/* Set maximum frame length */
@@ -513,6 +518,9 @@ int mcdmafec_initialize(bd_t * bis)
 {
 	struct eth_device *dev;
 	int i;
+#ifdef CFG_DMA_USE_INTSRAM
+	u32 tmp = CFG_INTSRAM + 0x2000;
+#endif
 
 	for (i = 0; i < sizeof(fec_info) / sizeof(fec_info[0]); i++) {
 
@@ -533,6 +541,17 @@ int mcdmafec_initialize(bd_t * bis)
 		dev->recv = fec_recv;
 
 		/* setup Receive and Transmit buffer descriptor */
+#ifdef CFG_DMA_USE_INTSRAM
+		fec_info[i].rxbd = (int)fec_info[i].rxbd + tmp;
+		tmp = fec_info[i].rxbd;
+		fec_info[i].txbd =
+		    (int)fec_info[i].txbd + tmp + (PKTBUFSRX * sizeof(cbd_t));
+		tmp = fec_info[i].txbd;
+		fec_info[i].txbuf =
+		    (int)fec_info[i].txbuf + tmp +
+		    (CFG_TX_ETH_BUFFER * sizeof(cbd_t));
+		tmp = fec_info[i].txbuf;
+#else
 		fec_info[i].rxbd =
 		    (cbd_t *) memalign(CFG_CACHELINE_SIZE,
 				       (PKTBUFSRX * sizeof(cbd_t)));
@@ -541,6 +560,7 @@ int mcdmafec_initialize(bd_t * bis)
 				       (CFG_TX_ETH_BUFFER * sizeof(cbd_t)));
 		fec_info[i].txbuf =
 		    (char *)memalign(CFG_CACHELINE_SIZE, DBUF_LENGTH);
+#endif
 
 #ifdef ET_DEBUG
 		printf("rxbd %x txbd %x\n",

drivers/net/ne2000.c

@@ -126,6 +126,9 @@ dp83902a_init(void)
 {
 	dp83902a_priv_data_t *dp = &nic;
 	u8* base;
+#if defined(NE2000_BASIC_INIT)
+	int i;
+#endif
 
 	DEBUG_FUNCTION();
 
@@ -755,8 +758,6 @@ static hw_info_t hw_info[] = {
 
 #define NR_INFO		(sizeof(hw_info)/sizeof(hw_info_t))
 
-static hw_info_t default_info = { 0, 0, 0, 0, 0 };
-
 u8 dev_addr[6];
 
 #define PCNET_CMD	0x00
@@ -764,6 +765,93 @@ u8 dev_addr[6];
 #define PCNET_RESET	0x1f	/* Issue a read to reset, a write to clear. */
 #define PCNET_MISC	0x18	/* For IBM CCAE and Socket EA cards */
 
+static void pcnet_reset_8390(void)
+{
+	int i, r;
+
+	PRINTK("nic base is %lx\n", nic_base);
+
+	n2k_outb(E8390_NODMA + E8390_PAGE0+E8390_STOP, E8390_CMD);
+	PRINTK("cmd (at %lx) is %x\n", nic_base + E8390_CMD, n2k_inb(E8390_CMD));
+	n2k_outb(E8390_NODMA+E8390_PAGE1+E8390_STOP, E8390_CMD);
+	PRINTK("cmd (at %lx) is %x\n", nic_base + E8390_CMD, n2k_inb(E8390_CMD));
+	n2k_outb(E8390_NODMA+E8390_PAGE0+E8390_STOP, E8390_CMD);
+	PRINTK("cmd (at %lx) is %x\n", nic_base + E8390_CMD, n2k_inb(E8390_CMD));
+	n2k_outb(E8390_NODMA+E8390_PAGE0+E8390_STOP, E8390_CMD);
+
+	n2k_outb(n2k_inb(PCNET_RESET), PCNET_RESET);
+
+	for (i = 0; i < 100; i++) {
+		if ((r = (n2k_inb(EN0_ISR) & ENISR_RESET)) != 0)
+			break;
+		PRINTK("got %x in reset\n", r);
+		udelay(100);
+	}
+	n2k_outb(ENISR_RESET, EN0_ISR); /* Ack intr. */
+
+	if (i == 100)
+		printf("pcnet_reset_8390() did not complete.\n");
+} /* pcnet_reset_8390 */
+
+int get_prom(u8* mac_addr) __attribute__ ((weak, alias ("__get_prom")));
+int __get_prom(u8* mac_addr)
+{
+	u8 prom[32];
+	int i, j;
+	struct {
+		u_char value, offset;
+	} program_seq[] = {
+		{E8390_NODMA+E8390_PAGE0+E8390_STOP, E8390_CMD}, /* Select page 0*/
+		{0x48, EN0_DCFG},		/* Set byte-wide (0x48) access. */
+		{0x00, EN0_RCNTLO},		/* Clear the count regs. */
+		{0x00, EN0_RCNTHI},
+		{0x00, EN0_IMR},		/* Mask completion irq. */
+		{0xFF, EN0_ISR},
+		{E8390_RXOFF, EN0_RXCR},	/* 0x20 Set to monitor */
+		{E8390_TXOFF, EN0_TXCR},	/* 0x02 and loopback mode. */
+		{32, EN0_RCNTLO},
+		{0x00, EN0_RCNTHI},
+		{0x00, EN0_RSARLO},		/* DMA starting at 0x0000. */
+		{0x00, EN0_RSARHI},
+		{E8390_RREAD+E8390_START, E8390_CMD},
+	};
+
+	PRINTK ("trying to get MAC via prom reading\n");
+
+	pcnet_reset_8390 ();
+
+	mdelay (10);
+
+	for (i = 0; i < sizeof (program_seq) / sizeof (program_seq[0]); i++)
+		n2k_outb (program_seq[i].value, program_seq[i].offset);
+
+	PRINTK ("PROM:");
+	for (i = 0; i < 32; i++) {
+		prom[i] = n2k_inb (PCNET_DATAPORT);
+		PRINTK (" %02x", prom[i]);
+	}
+	PRINTK ("\n");
+	for (i = 0; i < NR_INFO; i++) {
+		if ((prom[0] == hw_info[i].a0) &&
+			(prom[2] == hw_info[i].a1) &&
+			(prom[4] == hw_info[i].a2)) {
+			PRINTK ("matched board %d\n", i);
+			break;
+		}
+	}
+	if ((i < NR_INFO) || ((prom[28] == 0x57) && (prom[30] == 0x57))) {
+		PRINTK ("on exit i is %d/%ld\n", i, NR_INFO);
+		PRINTK ("MAC address is ");
+		for (j = 0; j < 6; j++) {
+			mac_addr[j] = prom[j << 1];
+			PRINTK ("%02x:", mac_addr[i]);
+		}
+		PRINTK ("\n");
+		return (i < NR_INFO) ? i : 0;
+	}
+	return 0;
+}
+
 u32 nic_base;
 
 /* U-boot specific routines */
@@ -790,7 +878,7 @@ void uboot_push_tx_done(int key, int val) {
 }
 
 int eth_init(bd_t *bd) {
-	static hw_info_t * r;
+	int r;
 	char ethaddr[20];
 
 	PRINTK("### eth_init\n");

drivers/net/ne2000.h

@@ -81,6 +81,7 @@ are GPL, so this is, of course, GPL.
 
 #define DP_DATA		0x10
 #define START_PG	0x50	/* First page of TX buffer */
+#define START_PG2	0x48
 #define STOP_PG		0x80	/* Last page +1 of RX ring */
 
 #define RX_START	0x50
@@ -90,90 +91,4 @@ are GPL, so this is, of course, GPL.
 #define DP_OUT(_b_, _o_, _d_)	*( (vu_char *) ((_b_)+(_o_))) = (_d_)
 #define DP_IN_DATA(_b_, _d_)	(_d_) = *( (vu_char *) ((_b_)))
 #define DP_OUT_DATA(_b_, _d_)	*( (vu_char *) ((_b_))) = (_d_)
-
-static void pcnet_reset_8390(void)
-{
-	int i, r;
-
-	PRINTK("nic base is %lx\n", nic_base);
-
-	n2k_outb(E8390_NODMA+E8390_PAGE0+E8390_STOP, E8390_CMD);
-	PRINTK("cmd (at %lx) is %x\n", nic_base+ E8390_CMD, n2k_inb(E8390_CMD));
-	n2k_outb(E8390_NODMA+E8390_PAGE1+E8390_STOP, E8390_CMD);
-	PRINTK("cmd (at %lx) is %x\n", nic_base+ E8390_CMD, n2k_inb(E8390_CMD));
-	n2k_outb(E8390_NODMA+E8390_PAGE0+E8390_STOP, E8390_CMD);
-	PRINTK("cmd (at %lx) is %x\n", nic_base+ E8390_CMD, n2k_inb(E8390_CMD));
-	n2k_outb(E8390_NODMA+E8390_PAGE0+E8390_STOP, E8390_CMD);
-
-	n2k_outb(n2k_inb(PCNET_RESET), PCNET_RESET);
-
-	for (i = 0; i < 100; i++) {
-		if ((r = (n2k_inb(EN0_ISR) & ENISR_RESET)) != 0)
-			break;
-		PRINTK("got %x in reset\n", r);
-		udelay(100);
-	}
-	n2k_outb(ENISR_RESET, EN0_ISR); /* Ack intr. */
-
-	if (i == 100)
-		printf("pcnet_reset_8390() did not complete.\n");
-} /* pcnet_reset_8390 */
-
-int get_prom(u8* mac_addr)
-{
-	u8 prom[32];
-	int i, j;
-	struct {
-		u_char value, offset;
-	} program_seq[] = {
-		{E8390_NODMA+E8390_PAGE0+E8390_STOP, E8390_CMD}, /* Select page 0*/
-		{0x48,  EN0_DCFG},		/* Set byte-wide (0x48) access. */
-		{0x00,  EN0_RCNTLO},		/* Clear the count regs. */
-		{0x00,  EN0_RCNTHI},
-		{0x00,  EN0_IMR},		/* Mask completion irq. */
-		{0xFF,  EN0_ISR},
-		{E8390_RXOFF, EN0_RXCR},	/* 0x20  Set to monitor */
-		{E8390_TXOFF, EN0_TXCR},	/* 0x02  and loopback mode. */
-		{32,    EN0_RCNTLO},
-		{0x00,  EN0_RCNTHI},
-		{0x00,  EN0_RSARLO},		/* DMA starting at 0x0000. */
-		{0x00,  EN0_RSARHI},
-		{E8390_RREAD+E8390_START, E8390_CMD},
-	};
-
-	PRINTK ("trying to get MAC via prom reading\n");
-
-	pcnet_reset_8390 ();
-
-	mdelay (10);
-
-	for (i = 0; i < sizeof (program_seq) / sizeof (program_seq[0]); i++)
-		n2k_outb (program_seq[i].value, program_seq[i].offset);
-
-	PRINTK ("PROM:");
-	for (i = 0; i < 32; i++) {
-		prom[i] = n2k_inb (PCNET_DATAPORT);
-		PRINTK (" %02x", prom[i]);
-	}
-	PRINTK ("\n");
-	for (i = 0; i < NR_INFO; i++) {
-		if ((prom[0] == hw_info[i].a0) &&
-		    (prom[2] == hw_info[i].a1) &&
-		    (prom[4] == hw_info[i].a2)) {
-			PRINTK ("matched board %d\n", i);
-			break;
-		}
-	}
-	if ((i < NR_INFO) || ((prom[28] == 0x57) && (prom[30] == 0x57))) {
-		PRINTK ("on exit i is %d/%ld\n", i, NR_INFO);
-		PRINTK ("MAC address is ");
-		for (j = 0; j < 6; j++) {
-			mac_addr[j] = prom[j << 1];
-			PRINTK ("%02x:", mac_addr[i]);
-		}
-		PRINTK ("\n");
-		return (i < NR_INFO) ? i : 0;
-	}
-	return NULL;
-}
 #endif /* __DRIVERS_NE2000_H__ */

drivers/net/ne2000_base.h

@@ -122,7 +122,6 @@ typedef struct dp83902a_priv_data {
 /*
  * Some forward declarations
  */
-int get_prom( u8* mac_addr);
 static void dp83902a_poll(void);
 
 /* ------------------------------------------------------------------------ */

drivers/net/pcnet.c

@@ -169,7 +169,6 @@ static struct pci_device_id supported[] = {
 
 int pcnet_initialize (bd_t * bis)
 {
-<<<<<<< HEAD:drivers/net/pcnet.c
 	pci_dev_t devbusfn;
 	struct eth_device *dev;
 	u16 command, status;
@@ -232,59 +231,6 @@ int pcnet_initialize (bd_t * bis)
 		dev->recv = pcnet_recv;
 
 		eth_register (dev);
-=======
-    pci_dev_t devbusfn;
-    struct eth_device* dev;
-    u16 command, status;
-    int dev_nr = 0;
-
-    PCNET_DEBUG1("\npcnet_initialize...\n");
-
-    for (dev_nr = 0; ; dev_nr++) {
-
-	/*
-	 * Find the PCnet PCI device(s).
-	 */
-	if ((devbusfn = pci_find_devices(supported, dev_nr)) < 0) {
-	    break;
-	}
-
-	/*
-	 * Allocate and pre-fill the device structure.
-	 */
-	dev = (struct eth_device*) malloc(sizeof *dev);
-	dev->priv = (void *)devbusfn;
-	sprintf(dev->name, "pcnet#%d", dev_nr);
-
-	/*
-	 * Setup the PCI device.
-	 */
-	pci_read_config_dword(devbusfn, PCI_BASE_ADDRESS_0, (unsigned int *)&dev->iobase);
-	dev->iobase=pci_io_to_phys(devbusfn,dev->iobase);
-	dev->iobase &= ~0xf;
-
-	PCNET_DEBUG1("%s: devbusfn=0x%x iobase=0x%x: ",
-	       dev->name, devbusfn, dev->iobase);
-
-	command = PCI_COMMAND_IO | PCI_COMMAND_MASTER;
-	pci_write_config_word(devbusfn, PCI_COMMAND, command);
-	pci_read_config_word(devbusfn, PCI_COMMAND, &status);
-	if ((status & command) != command) {
-	    printf("%s: Couldn't enable IO access or Bus Mastering\n",
-		   dev->name);
-	    free(dev);
-	    continue;
-	}
-
-	pci_write_config_byte(devbusfn, PCI_LATENCY_TIMER, 0x40);
-
-	/*
-	 * Probe the PCnet chip.
-	 */
-	if (pcnet_probe(dev, bis, dev_nr) < 0) {
-	    free(dev);
-	    continue;
->>>>>>> Fixed pcnet io_base:drivers/net/pcnet.c
 	}
 
 	udelay (10 * 1000);

drivers/net/rtl8169.c

@@ -435,7 +435,7 @@ static int rtl_recv(struct eth_device *dev)
 				tpc->RxDescArray[cur_rx].status =
 					cpu_to_le32(OWNbit + RX_BUF_SIZE);
 			tpc->RxDescArray[cur_rx].buf_addr =
-				cpu_to_le32(tpc->RxBufferRing[cur_rx]);
+				cpu_to_le32((unsigned long)tpc->RxBufferRing[cur_rx]);
 		} else {
 			puts("Error Rx");
 		}
@@ -481,7 +481,7 @@ static int rtl_send(struct eth_device *dev, volatile void *packet, int length)
 	while (len < ETH_ZLEN)
 		ptxb[len++] = '\0';
 
-	tpc->TxDescArray[entry].buf_addr = cpu_to_le32(ptxb);
+	tpc->TxDescArray[entry].buf_addr = cpu_to_le32((unsigned long)ptxb);
 	if (entry != (NUM_TX_DESC - 1)) {
 		tpc->TxDescArray[entry].status =
 			cpu_to_le32((OWNbit | FSbit | LSbit) |
@@ -579,8 +579,8 @@ static void rtl8169_hw_start(struct eth_device *dev)
 
 	tpc->cur_rx = 0;
 
-	RTL_W32(TxDescStartAddr, tpc->TxDescArray);
-	RTL_W32(RxDescStartAddr, tpc->RxDescArray);
+	RTL_W32(TxDescStartAddr, (unsigned long)tpc->TxDescArray);
+	RTL_W32(RxDescStartAddr, (unsigned long)tpc->RxDescArray);
 	RTL_W8(Cfg9346, Cfg9346_Lock);
 	udelay(10);
 
@@ -625,7 +625,7 @@ static void rtl8169_init_ring(struct eth_device *dev)
 
 		tpc->RxBufferRing[i] = &rxb[i * RX_BUF_SIZE];
 		tpc->RxDescArray[i].buf_addr =
-			cpu_to_le32(tpc->RxBufferRing[i]);
+			cpu_to_le32((unsigned long)tpc->RxBufferRing[i]);
 	}
 
 #ifdef DEBUG_RTL8169

drivers/net/tsec.c

@@ -1277,6 +1277,12 @@ struct phy_info phy_info_VSC8601 = {
 				{MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init},
 #ifdef CFG_VSC8601_SKEWFIX
 				{MIIM_VSC8601_EPHY_CON,MIIM_VSC8601_EPHY_CON_INIT_SKEW,NULL},
+#if defined(CFG_VSC8601_SKEW_TX) && defined(CFG_VSC8601_SKEW_RX)
+				{MIIM_EXT_PAGE_ACCESS,1,NULL},
+#define VSC8101_SKEW	(CFG_VSC8601_SKEW_TX<<14)|(CFG_VSC8601_SKEW_RX<<12)
+				{MIIM_VSC8601_SKEW_CTRL,VSC8101_SKEW,NULL},
+				{MIIM_EXT_PAGE_ACCESS,0,NULL},
+#endif
 #endif
 				{miim_end,}
 				 },

drivers/net/tsec.h

@@ -112,6 +112,8 @@
 #define MIIM_GBIT_CONTROL	0x9
 #define MIIM_GBIT_CONTROL_INIT	0xe00
 
+#define MIIM_EXT_PAGE_ACCESS	0x1f
+
 /* Broadcom BCM54xx -- taken from linux sungem_phy */
 #define MIIM_BCM54xx_AUXSTATUS			0x19
 #define MIIM_BCM54xx_AUXSTATUS_LINKMODE_MASK	0x0700
@@ -161,8 +163,9 @@
 
 /* Entry for Vitesse VSC8601 regs starts here (Not complete) */
 /* Vitesse VSC8601 Extended PHY Control Register 1 */
-#define MIIM_VSC8601_EPHY_CON			0x17
+#define MIIM_VSC8601_EPHY_CON		0x17
 #define MIIM_VSC8601_EPHY_CON_INIT_SKEW	0x1120
+#define MIIM_VSC8601_SKEW_CTRL		0x1c
 
 /* 88E1011 PHY Status Register */
 #define MIIM_88E1011_PHY_STATUS         0x11
@@ -177,9 +180,9 @@
 #define MIIM_88E1011_PHY_MDI_X_AUTO	0x0060
 
 /* 88E1111 PHY LED Control Register */
-#define MIIM_88E1111_PHY_LED_CONTROL   24
-#define MIIM_88E1111_PHY_LED_DIRECT    0x4100
-#define MIIM_88E1111_PHY_LED_COMBINE   0x411C
+#define MIIM_88E1111_PHY_LED_CONTROL	24
+#define MIIM_88E1111_PHY_LED_DIRECT	0x4100
+#define MIIM_88E1111_PHY_LED_COMBINE	0x411C
 
 /* 88E1145 Extended PHY Specific Control Register */
 #define MIIM_88E1145_PHY_EXT_CR 20

drivers/pcmcia/pxa_pcmcia.c

@@ -35,8 +35,10 @@ int pcmcia_on (void)
 	debug ("%s\n", __FUNCTION__);
 
 	i = 0;
-	while (reg_arr[i])
-		*((volatile unsigned int *) reg_arr[i++]) |= reg_arr[i++];
+	while (reg_arr[i]) {
+		(*(volatile unsigned int *) reg_arr[i]) |= reg_arr[i + 1];
+		i += 2;
+	}
 	udelay (1000);
 
 	debug ("%s: programmed mem controller \n", __FUNCTION__);
@@ -44,7 +46,7 @@ int pcmcia_on (void)
 #ifdef CONFIG_EXADRON1
 
 /*define useful BCR masks */
-#define BCR_CF_INIT_VAL  		    0x00007230
+#define BCR_CF_INIT_VAL			    0x00007230
 #define BCR_CF_PWRON_BUSOFF_RESETOFF_VAL    0x00007231
 #define BCR_CF_PWRON_BUSOFF_RESETON_VAL     0x00007233
 #define BCR_CF_PWRON_BUSON_RESETON_VAL      0x00007213

drivers/rtc/m41t62.c

@@ -81,7 +81,7 @@ int rtc_get(struct rtc_time *tm)
 	tm->tm_hour = BCD2BIN(buf[M41T62_REG_HOUR] & 0x3f);
 	tm->tm_mday = BCD2BIN(buf[M41T62_REG_DAY] & 0x3f);
 	tm->tm_wday = buf[M41T62_REG_WDAY] & 0x07;
-	tm->tm_mon = BCD2BIN(buf[M41T62_REG_MON] & 0x1f) - 1;
+	tm->tm_mon = BCD2BIN(buf[M41T62_REG_MON] & 0x1f);
 
 	/* assume 20YY not 19YY, and ignore the Century Bit */
 	/* U-Boot needs to add 1900 here */
@@ -119,7 +119,7 @@ void rtc_set(struct rtc_time *tm)
 	buf[M41T62_REG_DAY] =
 		BIN2BCD(tm->tm_mday) | (buf[M41T62_REG_DAY] & ~0x3f);
 	buf[M41T62_REG_MON] =
-		BIN2BCD(tm->tm_mon + 1) | (buf[M41T62_REG_MON] & ~0x1f);
+		BIN2BCD(tm->tm_mon) | (buf[M41T62_REG_MON] & ~0x1f);
 	/* assume 20YY not 19YY */
 	buf[M41T62_REG_YEAR] = BIN2BCD(tm->tm_year % 100);
 

fs/jffs2/jffs2_1pass.c

@@ -185,11 +185,7 @@ static int read_nand_cached(u32 off, u32 size, u_char *buf)
 {
 	struct mtdids *id = current_part->dev->id;
 	u32 bytes_read = 0;
-#if defined(CFG_NAND_LEGACY)
 	size_t retlen;
-#else
-	ulong retlen;
-#endif
 	int cpy_bytes;
 
 	while (bytes_read < size) {

include/asm-arm/io.h

@@ -123,7 +123,7 @@ extern void __raw_readsl(unsigned int addr, void *data, int longlen);
  * only.  Their primary purpose is to access PCI and ISA peripherals.
  *
  * Note that for a big endian machine, this implies that the following
- * big endian mode connectivity is in place, as described by numerious
+ * big endian mode connectivity is in place, as described by numerous
  * ARM documents:
  *
  *    PCI:  D0-D7   D8-D15 D16-D23 D24-D31

include/asm-m68k/global_data.h

@@ -46,6 +46,10 @@ typedef	struct	global_data {
 	unsigned long	inp_clk;
 	unsigned long	vco_clk;
 	unsigned long	flb_clk;
+#endif
+#ifdef CONFIG_FSL_I2C
+	unsigned long	i2c1_clk;
+	unsigned long	i2c2_clk;
 #endif
 	unsigned long	ram_size;	/* RAM size */
 	unsigned long	reloc_off;	/* Relocation Offset */

include/asm-ppc/4xx_pcie.h

@@ -12,6 +12,7 @@
 #define __4XX_PCIE_H
 
 #include <ppc4xx.h>
+#include <pci.h>
 
 #define DCRN_SDR0_CFGADDR	0x00e
 #define DCRN_SDR0_CFGDATA	0x00f

include/asm-ppc/immap_85xx.h

@@ -92,7 +92,7 @@ typedef struct ccsr_ddr {
 	uint	cs2_config_2;		/* 0x20c8 - DDR Chip Select Configuration 2 */
 	uint	cs3_config_2;		/* 0x20cc - DDR Chip Select Configuration 2 */
 	char	res5[48];
-	uint	ext_refrec;		/* 0x2100 - DDR SDRAM Extended Refresh Recovery */
+	uint	timing_cfg_3;		/* 0x2100 - DDR SDRAM Timing Configuration Register 3 */
 	uint	timing_cfg_0;		/* 0x2104 - DDR SDRAM Timing Configuration Register 0 */
 	uint	timing_cfg_1;		/* 0x2108 - DDR SDRAM Timing Configuration Register 1 */
 	uint	timing_cfg_2;		/* 0x210c - DDR SDRAM Timing Configuration Register 2 */
@@ -106,8 +106,8 @@ typedef struct ccsr_ddr {
 	char	res6[4];
 	uint	sdram_clk_cntl;		/* 0x2130 - DDR SDRAM Clock Control */
 	char	res7[20];
-	uint	init_address;		/* 0x2148 - DDR training initialization address */
-	uint	init_ext_address;	/* 0x214C - DDR training initialization extended address */
+	uint	init_addr;		/* 0x2148 - DDR training initialization address */
+	uint	init_ext_addr;		/* 0x214C - DDR training initialization extended address */
 	char	res8_1[16];
 	uint	timing_cfg_4;		/* 0x2160 - DDR SDRAM Timing Configuration Register 4 */
 	uint	timing_cfg_5;		/* 0x2164 - DDR SDRAM Timing Configuration Register 5 */

include/asm-ppc/immap_86xx.h

@@ -109,7 +109,7 @@ typedef struct ccsr_ddr {
 	uint	cs4_config;		/* 0x2090 - DDR Chip Select Configuration */
 	uint	cs5_config;		/* 0x2094 - DDR Chip Select Configuration */
 	char	res7[104];
-	uint    ext_refrec;             /* 0x2100 - DDR SDRAM extended refresh recovery */
+	uint	timing_cfg_3;		/* 0x2100 - DDR SDRAM Timing Configuration Register 3 */
 	uint	timing_cfg_0;		/* 0x2104 - DDR SDRAM Timing Configuration Register 0 */
 	uint	timing_cfg_1;		/* 0x2108 - DDR SDRAM Timing Configuration Register 1 */
 	uint	timing_cfg_2;		/* 0x210c - DDR SDRAM Timing Configuration Register 2 */
@@ -126,7 +126,7 @@ typedef struct ccsr_ddr {
 	uint    sdram_ocd_cntl;		/* 0x2140 - DDR SDRAM OCD Control */
 	uint    sdram_ocd_status;	/* 0x2144 - DDR SDRAM OCD Status */
 	uint    init_addr;		/* 0x2148 - DDR training initialzation address */
-	uint    init_addr_ext;		/* 0x214C - DDR training initialzation extended address */
+	uint    init_ext_addr;		/* 0x214C - DDR training initialzation extended address */
 	char    res10[2728];
 	uint    ip_rev1;		/* 0x2BF8 - DDR IP Block Revision 1 */
 	uint    ip_rev2;		/* 0x2BFC - DDR IP Block Revision 2 */

include/common.h

@@ -214,9 +214,7 @@ int	checkdram     (void);
 char *	strmhz(char *buf, long hz);
 int	last_stage_init(void);
 extern ulong monitor_flash_len;
-#ifdef CFG_ID_EEPROM
 int mac_read_from_eeprom(void);
-#endif
 
 /* common/flash.c */
 void flash_perror (int);

include/configs/M5475EVB.h

@@ -72,6 +72,7 @@
 #	define CONFIG_MII_INIT		1
 #	define CONFIG_HAS_ETH1
 
+#	define CFG_DMA_USE_INTSRAM	1
 #	define CFG_DISCOVER_PHY
 #	define CFG_RX_ETH_BUFFER	32
 #	define CFG_TX_ETH_BUFFER	48

include/configs/M5485EVB.h

@@ -72,6 +72,7 @@
 #	define CONFIG_MII_INIT		1
 #	define CONFIG_HAS_ETH1
 
+#	define CFG_DMA_USE_INTSRAM	1
 #	define CFG_DISCOVER_PHY
 #	define CFG_RX_ETH_BUFFER	32
 #	define CFG_TX_ETH_BUFFER	48

include/configs/MPC8610HPCD.h

@@ -114,7 +114,7 @@
 #if 0 /* TODO */
 #define CFG_DDR_CS0_BNDS	0x0000000F
 #define CFG_DDR_CS0_CONFIG	0x80010202	/* Enable, no interleaving */
-#define CFG_DDR_EXT_REFRESH	0x00000000
+#define CFG_DDR_TIMING_3	0x00000000
 #define CFG_DDR_TIMING_0	0x00260802
 #define CFG_DDR_TIMING_1	0x3935d322
 #define CFG_DDR_TIMING_2	0x14904cc8

include/configs/katmai.h

@@ -48,12 +48,8 @@
  * Base addresses -- Note these are effective addresses where the
  * actual resources get mapped (not physical addresses)
  *----------------------------------------------------------------------*/
-#define CFG_MONITOR_LEN		(256 * 1024)	/* Reserve 256 kB for Mon */
-#define CFG_MALLOC_LEN		(512 * 1024)	/* Reserve 512 kB for malloc */
-
 #define CFG_SDRAM_BASE		0x00000000	/* _must_ be 0		*/
 #define CFG_FLASH_BASE		0xff000000	/* start of FLASH	*/
-#define CFG_MONITOR_BASE	TEXT_BASE
 #define CFG_PERIPHERAL_BASE	0xa0000000	/* internal peripherals	*/
 #define CFG_ISRAM_BASE		0x90000000	/* internal SRAM	*/
 
@@ -82,6 +78,10 @@
 
 #define CFG_ACE_BASE		0xfe000000	/* Xilinx ACE controller - Compact Flash */
 
+#define CFG_MONITOR_BASE	TEXT_BASE
+#define CFG_MONITOR_LEN		(0xFFFFFFFF - CFG_MONITOR_LEN + 1)
+#define CFG_MALLOC_LEN		(512 * 1024)	/* Reserve 512 kB for malloc */
+
 /*-----------------------------------------------------------------------
  * Initial RAM & stack pointer (placed in internal SRAM)
  *----------------------------------------------------------------------*/
@@ -178,6 +178,9 @@
 
 #undef	CONFIG_BOOTARGS
 
+#define xstr(s) str(s)
+#define str(s) #s
+
 #define	CONFIG_EXTRA_ENV_SETTINGS					\
 	"netdev=eth0\0"							\
 	"hostname=katmai\0"						\
@@ -206,8 +209,9 @@
 	"ramdisk_addr=fff20000\0"					\
 	"initrd_high=30000000\0"					\
 	"load=tftp 200000 katmai/u-boot.bin\0"				\
-	"update=protect off fffc0000 ffffffff;era fffc0000 ffffffff;"	\
-		"cp.b ${fileaddr} fffc0000 ${filesize};"		\
+	"update=protect off " xstr(CFG_MONITOR_BASE) " FFFFFFFF;"	\
+		"era " xstr(CFG_MONITOR_BASE) " FFFFFFFF;"		\
+		"cp.b ${fileaddr} " xstr(CFG_MONITOR_BASE) " ${filesize};" \
 		"setenv filesize;saveenv\0"				\
 	"upd=run load update\0"						\
 	"kozio=bootm ffc60000\0"					\

include/configs/lwmon5.h

@@ -91,9 +91,9 @@
 
 /* Additional registers for watchdog timer post test */
 
-#define CFG_DSPIC_TEST_ADDR	(CFG_PERIPHERAL_BASE + GPT0_MASK1)
 #define CFG_WATCHDOG_TIME_ADDR	(CFG_PERIPHERAL_BASE + GPT0_MASK2)
 #define CFG_WATCHDOG_FLAGS_ADDR	(CFG_PERIPHERAL_BASE + GPT0_MASK1)
+#define CFG_DSPIC_TEST_ADDR	CFG_WATCHDOG_FLAGS_ADDR
 #define CFG_WATCHDOG_MAGIC	0x12480000
 #define CFG_WATCHDOG_MAGIC_MASK	0xFFFF0000
 #define CFG_DSPIC_TEST_MASK	0x00000001

include/configs/mx31ads.h

@@ -79,15 +79,13 @@
 #include <config_cmd_default.h>
 
 #define CONFIG_CMD_PING
+#define CONFIG_CMD_DHCP
 #define CONFIG_CMD_SPI
 #define CONFIG_CMD_DATE
 
 #define CONFIG_BOOTDELAY	3
 
-#define CONFIG_NETMASK		255.255.255.0
-#define CONFIG_IPADDR		192.168.23.168
-#define CONFIG_SERVERIP		192.168.23.2
-#define CONFIG_LOADADDR		(CSD0_BASE + 0x800000)	/* loadaddr env var */
+#define CONFIG_LOADADDR		0x80800000	/* loadaddr env var */
 
 #define	CONFIG_EXTRA_ENV_SETTINGS					\
 	"netdev=eth0\0"							\

include/configs/sbc8548.h

@@ -148,7 +148,7 @@
  * 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65    OR0
  *
  * OR6:
- *    Addr Mask = 64M = OR6[0:16] = 1111 1100 0000 0000 0
+ *    Addr Mask = 64M = OR6[0:16] = 1111 1000 0000 0000 0
  *    XAM = OR6[17:18] = 11
  *    CSNT = OR6[20] = 1
  *    ACS = half cycle delay = OR6[21:22] = 11
@@ -157,7 +157,7 @@
  *    EAD = use external address latch delay = OR6[31] = 1
  *
  * 0    4    8    12   16   20   24   28
- * 1111 1100 0000 0000 0110 1110 0110 0101 = fc006e65    OR6
+ * 1111 1000 0000 0000 0110 1110 0110 0101 = f8006e65    OR6
  */
 
 #define CFG_BOOT_BLOCK		0xff800000	/* start of 8MB Flash */
@@ -167,7 +167,7 @@
 #define CFG_BR6_PRELIM		0xfb801801
 
 #define	CFG_OR0_PRELIM		0xff806e65
-#define	CFG_OR6_PRELIM		0xfc006e65
+#define	CFG_OR6_PRELIM		0xf8006e65
 
 #define CFG_FLASH_BANKS_LIST	{CFG_FLASH_BASE}
 #define CFG_MAX_FLASH_BANKS	1		/* number of banks */

include/configs/sbc8641d.h

@@ -136,7 +136,7 @@
     #define CFG_DDR_CS1_CONFIG	0x00000000
     #define CFG_DDR_CS2_CONFIG	0x00000000
     #define CFG_DDR_CS3_CONFIG	0x00000000
-    #define CFG_DDR_EXT_REFRESH 0x00000000
+    #define CFG_DDR_TIMING_3 0x00000000
     #define CFG_DDR_TIMING_0	0x00220802
     #define CFG_DDR_TIMING_1	0x38377322
     #define CFG_DDR_TIMING_2	0x002040c7

include/nand.h

@@ -34,22 +34,22 @@ extern int nand_curr_device;
 extern nand_info_t nand_info[];
 extern void nand_init(void);
 
-static inline int nand_read(nand_info_t *info, ulong ofs, ulong *len, u_char *buf)
+static inline int nand_read(nand_info_t *info, off_t ofs, size_t *len, u_char *buf)
 {
 	return info->read(info, ofs, *len, (size_t *)len, buf);
 }
 
-static inline int nand_write(nand_info_t *info, ulong ofs, ulong *len, u_char *buf)
+static inline int nand_write(nand_info_t *info, off_t ofs, size_t *len, u_char *buf)
 {
 	return info->write(info, ofs, *len, (size_t *)len, buf);
 }
 
-static inline int nand_block_isbad(nand_info_t *info, ulong ofs)
+static inline int nand_block_isbad(nand_info_t *info, off_t ofs)
 {
 	return info->block_isbad(info, ofs);
 }
 
-static inline int nand_erase(nand_info_t *info, ulong off, ulong size)
+static inline int nand_erase(nand_info_t *info, off_t off, size_t size)
 {
 	struct erase_info instr;
 

include/net.h

@@ -412,10 +412,10 @@ extern void	print_IPaddr (IPaddr_t);
  * footprint in our tests.
  */
 /* return IP *in network byteorder* */
-static inline IPaddr_t NetReadIP(void *from)
+static inline IPaddr_t NetReadIP(volatile void *from)
 {
 	IPaddr_t ip;
-	memcpy((void*)&ip, from, sizeof(ip));
+	memcpy((void*)&ip, (void*)from, sizeof(ip));
 	return ip;
 }
 
@@ -434,9 +434,9 @@ static inline void NetWriteIP(void *to, IPaddr_t ip)
 }
 
 /* copy IP */
-static inline void NetCopyIP(void *to, void *from)
+static inline void NetCopyIP(volatile void *to, void *from)
 {
-	memcpy(to, from, sizeof(IPaddr_t));
+	memcpy((void*)to, from, sizeof(IPaddr_t));
 }
 
 /* copy ulong */

lib_arm/board.c

@@ -44,6 +44,7 @@
 #include <devices.h>
 #include <version.h>
 #include <net.h>
+#include <serial.h>
 
 #ifdef CONFIG_DRIVER_SMC91111
 #include "../drivers/net/smc91111.h"

lib_m68k/board.c

@@ -45,6 +45,7 @@
 #include <status_led.h>
 #endif
 #include <net.h>
+#include <serial.h>
 #if defined(CONFIG_CMD_BEDBUG)
 #include <cmd_bedbug.h>
 #endif

lib_ppc/cache.c

@@ -23,6 +23,7 @@
 
 #include <common.h>
 #include <asm/cache.h>
+#include <watchdog.h>
 
 void flush_cache (ulong start_addr, ulong size)
 {
@@ -35,6 +36,7 @@ void flush_cache (ulong start_addr, ulong size)
 		     addr < end_addr;
 		     addr += CFG_CACHELINE_SIZE) {
 			asm ("dcbst 0,%0": :"r" (addr));
+			WATCHDOG_RESET();
 		}
 		asm ("sync");	/* Wait for all dcbst to complete on bus */
 
@@ -42,6 +44,7 @@ void flush_cache (ulong start_addr, ulong size)
 		     addr < end_addr;
 		     addr += CFG_CACHELINE_SIZE) {
 			asm ("icbi 0,%0": :"r" (addr));
+			WATCHDOG_RESET();
 		}
 	}
 	asm ("sync");		/* Always flush prefetch queue in any case */

nand_spl/board/amcc/canyonlands/ddr2_fixed.c

@@ -49,20 +49,21 @@ long int initdram(int board_type)
 	 * enabled. This will only work for the same memory
 	 * configuration as used here:
 	 *
-	 * Crucial CT6464AC53E.4FE - 512MB SO-DIMM
+	 * Crucial CT6464AC667.8FB - 512MB SO-DIMM
 	 *
 	 */
 	mtsdram(SDRAM_MCOPT2, 0x00000000);
-	mtsdram(SDRAM_MCOPT1, 0x05322000);
+	mtsdram(SDRAM_MCOPT1, 0x05122000);
 	mtsdram(SDRAM_MODT0, 0x01000000);
-	mtsdram(SDRAM_CODT, 0x00800021);
+	mtsdram(SDRAM_CODT, 0x02800021);
 	mtsdram(SDRAM_WRDTR, 0x82000823);
 	mtsdram(SDRAM_CLKTR, 0x40000000);
 	mtsdram(SDRAM_MB0CF, 0x00000201);
+	mtsdram(SDRAM_MB1CF, 0x00000201);
 	mtsdram(SDRAM_RTR, 0x06180000);
 	mtsdram(SDRAM_SDTR1, 0x80201000);
 	mtsdram(SDRAM_SDTR2, 0x42103243);
-	mtsdram(SDRAM_SDTR3, 0x0A0D0D1A);
+	mtsdram(SDRAM_SDTR3, 0x0A0D0D16);
 	mtsdram(SDRAM_MMODE, 0x00000632);
 	mtsdram(SDRAM_MEMODE, 0x00000040);
 	mtsdram(SDRAM_INITPLR0, 0xB5380000);
@@ -86,7 +87,8 @@ long int initdram(int board_type)
 
 	wait_init_complete();
 
-	mtdcr(SDRAM_R0BAS, 0x0000F000);		/* MQ0_B0BAS */
+	mtdcr(SDRAM_R0BAS, 0x0000F800);		/* MQ0_B0BAS */
+	mtdcr(SDRAM_R1BAS, 0x0400F800);		/* MQ0_B1BAS */
 
 	mtsdram(SDRAM_RDCC, 0x40000000);
 	mtsdram(SDRAM_RQDC, 0x80000038);

net/net.c

@@ -94,11 +94,22 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-#define ARP_TIMEOUT		5UL		/* Seconds before trying ARP again */
-#ifndef	CONFIG_NET_RETRY_COUNT
-# define ARP_TIMEOUT_COUNT	5		/* # of timeouts before giving up  */
+#ifndef	CONFIG_ARP_TIMEOUT
+# define ARP_TIMEOUT		50UL	/* Deciseconds before trying ARP again */
+#elif (CONFIG_ARP_TIMEOUT < 100)
+# error "Due to possible overflow CONFIG_ARP_TIMEOUT must be greater than 100ms"
 #else
-# define ARP_TIMEOUT_COUNT  (CONFIG_NET_RETRY_COUNT)
+# if (CONFIG_ARP_TIMEOUT % 100)
+#  warning "Supported ARP_TIMEOUT precision is 100ms"
+# endif
+# define ARP_TIMEOUT		(CONFIG_ARP_TIMEOUT / 100)
+#endif
+
+
+#ifndef	CONFIG_NET_RETRY_COUNT
+# define ARP_TIMEOUT_COUNT	5	/* # of timeouts before giving up  */
+#else
+# define ARP_TIMEOUT_COUNT	CONFIG_NET_RETRY_COUNT
 #endif
 
 #if 0
@@ -129,7 +140,7 @@ uchar		NetOurEther[6];		/* Our ethernet address			*/
 uchar		NetServerEther[6] =	/* Boot server enet address		*/
 			{ 0, 0, 0, 0, 0, 0 };
 IPaddr_t	NetOurIP;		/* Our IP addr (0 = unknown)		*/
-IPaddr_t	NetServerIP;		/* Our IP addr (0 = unknown)		*/
+IPaddr_t	NetServerIP;		/* Server IP addr (0 = unknown)		*/
 volatile uchar *NetRxPkt;		/* Current receive packet		*/
 int		NetRxPktLen;		/* Current rx packet length		*/
 unsigned	NetIPID;		/* IP packet ID				*/
@@ -253,7 +264,7 @@ void ArpTimeoutCheck(void)
 	t = get_timer(0);
 
 	/* check for arp timeout */
-	if ((t - NetArpWaitTimerStart) > ARP_TIMEOUT * CFG_HZ) {
+	if ((t - NetArpWaitTimerStart) > ARP_TIMEOUT * CFG_HZ / 10) {
 		NetArpWaitTry++;
 
 		if (NetArpWaitTry >= ARP_TIMEOUT_COUNT) {
@@ -494,7 +505,7 @@ restart:
 		 *	Check the ethernet for a new packet.  The ethernet
 		 *	receive routine will process it.
 		 */
-			eth_rx();
+		eth_rx();
 
 		/*
 		 *	Abort if ctrl-c was pressed.

post/Makefile

@@ -22,7 +22,7 @@
 #
 
 include $(TOPDIR)/config.mk
-include $(TOPDIR)/include/autoconf.mk
+include $(OBJTREE)/include/autoconf.mk
 
 LIB				= libpost.a
 GPLIB-$(CONFIG_HAS_POST)	+= libgenpost.a
@@ -38,8 +38,8 @@ SPLIB-$(CONFIG_HAS_POST) += $(shell if [ -d cpu/$(CPU) ]; then echo \
 SPLIB-$(CONFIG_HAS_POST) += $(shell if [ -d board/$(BOARD) ]; then echo \
 			    "board/$(BOARD)/libpost$(BOARD).a"; fi)
 
-GPLIB	:= $(GPLIB-y)
-SPLIB	:= $(SPLIB-y)
+GPLIB	:= $(addprefix $(obj),$(GPLIB-y))
+SPLIB	:= $(addprefix $(obj),$(SPLIB-y))
 COBJS	:= $(COBJS-y)
 SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
 OBJS	:= $(addprefix $(obj),$(COBJS))

post/board/lwmon/Makefile

@@ -20,10 +20,10 @@
 # Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 # MA 02111-1307 USA
 #
-
+include $(OBJTREE)/include/autoconf.mk
 
 LIB	= libpostlwmon.a
 
-COBJS	= sysmon.o
+COBJS-$(CONFIG_HAS_POST)	+= sysmon.o
 
 include $(TOPDIR)/post/rules.mk

post/board/lwmon5/Makefile

@@ -20,7 +20,7 @@
 # along with this program; if not, write to the Free Software
 # Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 # MA 02111-1307 USA
-include $(TOPDIR)/include/autoconf.mk
+include $(OBJTREE)/include/autoconf.mk
 
 LIB	= libpostlwmon5.a
 

post/board/lwmon5/sysmon.c

@@ -32,9 +32,9 @@
  * The test passes when all the following voltages and temperatures
  * are within allowed ranges:
  *
- * Temperature		      -40 .. +85 C
- * +5V			    +4.75 .. +5.25 V
- * +5V standby		    +4.75 .. +5.25 V
+ * Temperature		  -40 .. +90 C
+ * +5V			+4.50 .. +5.50 V
+ * +5V standby		+3.50 .. +5.50 V
  *
  * LCD backlight is not enabled if temperature values are not within
  * allowed ranges (-30 .. + 80). The brightness of backlite can be
@@ -60,6 +60,21 @@ extern int dspic_read(ushort reg);
 
 #define	RELOC(x) if (x != NULL) x = (void *) ((ulong) (x) + gd->reloc_off)
 
+#define REG_TEMPERATURE			0x12BC
+#define REG_VOLTAGE_5V			0x12CA
+#define REG_VOLTAGE_5V_STANDBY		0x12C6
+
+#define TEMPERATURE_MIN			(-40)	/* degr. C */
+#define TEMPERATURE_MAX			(+90)	/* degr. C */
+#define TEMPERATURE_DISPLAY_MIN		(-35)	/* degr. C */
+#define TEMPERATURE_DISPLAY_MAX		(+85)	/* degr. C */
+
+#define VOLTAGE_5V_MIN			(+4500)	/* mV */
+#define VOLTAGE_5V_MAX			(+5500)	/* mV */
+
+#define VOLTAGE_5V_STANDBY_MIN		(+3500)	/* mV */
+#define VOLTAGE_5V_STANDBY_MAX		(+5500)	/* mV */
+
 typedef struct sysmon_s sysmon_t;
 typedef struct sysmon_table_s sysmon_table_t;
 
@@ -107,17 +122,29 @@ struct sysmon_table_s
 
 static sysmon_table_t sysmon_table[] =
 {
-	{"Temperature", " C", &sysmon_dspic, NULL, sysmon_backlight_disable,
-	1, 1, -32768, 32767, 0xFFFF, 0x8000-40, 0x8000+85, 0,
-				     0x8000-30, 0x8000+80, 0, 0x12BC},
+	{
+	"Temperature", " C", &sysmon_dspic, NULL, sysmon_backlight_disable,
+	1, 1, -32768, 32767, 0xFFFF,
+	0x8000 + TEMPERATURE_MIN,	  0x8000 + TEMPERATURE_MAX,	    0,
+	0x8000 + TEMPERATURE_DISPLAY_MIN, 0x8000 + TEMPERATURE_DISPLAY_MAX, 0,
+	REG_TEMPERATURE,
+	},
 
-	{"+ 5 V", "V", &sysmon_dspic, NULL, NULL,
-	100, 1000, -0x8000, 0x7FFF, 0xFFFF, 0x8000+4750, 0x8000+5250, 0,
-					    0x8000+4750, 0x8000+5250, 0, 0x12CA},
+	{
+	"+ 5 V", "V", &sysmon_dspic, NULL, NULL,
+	100, 1000, -0x8000, 0x7FFF, 0xFFFF,
+	0x8000 + VOLTAGE_5V_MIN, 0x8000 + VOLTAGE_5V_MAX, 0,
+	0x8000 + VOLTAGE_5V_MIN, 0x8000 + VOLTAGE_5V_MAX, 0,
+	REG_VOLTAGE_5V,
+	},
 
-	{"+ 5 V standby", "V", &sysmon_dspic, NULL, NULL,
-	100, 1000, -0x8000, 0x7FFF, 0xFFFF, 0x8000+4750, 0x8000+5250, 0,
-					    0x8000+4750, 0x8000+5250, 0, 0x12C6},
+	{
+	"+ 5 V standby", "V", &sysmon_dspic, NULL, NULL,
+	100, 1000, -0x8000, 0x7FFF, 0xFFFF,
+	0x8000 + VOLTAGE_5V_STANDBY_MIN, 0x8000 + VOLTAGE_5V_STANDBY_MAX, 0,
+	0x8000 + VOLTAGE_5V_STANDBY_MIN, 0x8000 + VOLTAGE_5V_STANDBY_MAX, 0,
+	REG_VOLTAGE_5V_STANDBY,
+	},
 };
 static int sysmon_table_size = sizeof(sysmon_table) / sizeof(sysmon_table[0]);
 

post/board/lwmon5/watchdog.c

@@ -52,8 +52,9 @@ static void watchdog_magic_write(uint value)
 
 int sysmon1_post_test(int flags)
 {
-	if (gpio_read_in_bit(CFG_GPIO_SYSMON_STATUS)) {
-		/* 3.1. GPIO62 is low
+	if (gpio_read_in_bit(CFG_GPIO_SYSMON_STATUS) == 0) {
+		/*
+		 * 3.1. GPIO62 is low
 		 * Assuming system voltage failure.
 		 */
 		post_log("Abnormal voltage detected (GPIO62)\n");

post/board/netta/Makefile

@@ -20,10 +20,10 @@
 # Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 # MA 02111-1307 USA
 #
-
+include $(OBJTREE)/include/autoconf.mk
 
 LIB	= libpostnetta.a
 
-COBJS	= codec.o dsp.o
+COBJS-$(CONFIG_HAS_POST)	+= codec.o dsp.o
 
 include $(TOPDIR)/post/rules.mk

post/cpu/mpc8xx/Makefile

@@ -20,10 +20,11 @@
 # Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 # MA 02111-1307 USA
 #
+include $(OBJTREE)/include/autoconf.mk
 
 LIB	= libpostmpc8xx.a
 
-AOBJS	= cache_8xx.o
-COBJS	= cache.o ether.o spr.o uart.o usb.o watchdog.o
+AOBJS-$(CONFIG_HAS_POST)	+= cache_8xx.o
+COBJS-$(CONFIG_HAS_POST)	+= cache.o ether.o spr.o uart.o usb.o watchdog.o
 
 include $(TOPDIR)/post/rules.mk

post/cpu/ppc4xx/Makefile

@@ -20,7 +20,7 @@
 # Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 # MA 02111-1307 USA
 #
-include $(TOPDIR)/include/autoconf.mk
+include $(OBJTREE)/include/autoconf.mk
 
 LIB	= libpostppc4xx.a
 

tools/.gitignore

@@ -15,3 +15,4 @@
 /fdt_strerror.c
 /fdt_wip.c
 /libfdt_internal.h
+/zlib.h

tools/mkimage.c

@@ -28,7 +28,7 @@
 extern int errno;
 
 #ifndef MAP_FAILED
-#define MAP_FAILED (-1)
+#define MAP_FAILED (void *)(-1)
 #endif
 
 extern	unsigned long	crc32 (unsigned long crc, const char *buf, unsigned int len);
@@ -218,9 +218,8 @@ NXTARG:		;
 			exit (EXIT_FAILURE);
 		}
 
-		ptr = (unsigned char *)mmap(0, sbuf.st_size,
-					    PROT_READ, MAP_SHARED, ifd, 0);
-		if ((caddr_t)ptr == (caddr_t)-1) {
+		ptr = mmap(0, sbuf.st_size, PROT_READ, MAP_SHARED, ifd, 0);
+		if (ptr == MAP_FAILED) {
 			fprintf (stderr, "%s: Can't read %s: %s\n",
 				cmdname, imagefile, strerror(errno));
 			exit (EXIT_FAILURE);
@@ -330,9 +329,8 @@ NXTARG:		;
 		exit (EXIT_FAILURE);
 	}
 
-	ptr = (unsigned char *)mmap(0, sbuf.st_size,
-				    PROT_READ|PROT_WRITE, MAP_SHARED, ifd, 0);
-	if (ptr == (unsigned char *)MAP_FAILED) {
+	ptr = mmap(0, sbuf.st_size, PROT_READ|PROT_WRITE, MAP_SHARED, ifd, 0);
+	if (ptr == MAP_FAILED) {
 		fprintf (stderr, "%s: Can't map %s: %s\n",
 			cmdname, imagefile, strerror(errno));
 		exit (EXIT_FAILURE);
@@ -410,9 +408,8 @@ copy_file (int ifd, const char *datafile, int pad)
 		exit (EXIT_FAILURE);
 	}
 
-	ptr = (unsigned char *)mmap(0, sbuf.st_size,
-				    PROT_READ, MAP_SHARED, dfd, 0);
-	if (ptr == (unsigned char *)MAP_FAILED) {
+	ptr = mmap(0, sbuf.st_size, PROT_READ, MAP_SHARED, dfd, 0);
+	if (ptr == MAP_FAILED) {
 		fprintf (stderr, "%s: Can't read %s: %s\n",
 			cmdname, datafile, strerror(errno));
 		exit (EXIT_FAILURE);
@@ -594,9 +591,8 @@ static void fit_handle_file (void)
 		exit (EXIT_FAILURE);
 	}
 
-	ptr = (unsigned char *)mmap (0, sbuf.st_size,
-			PROT_READ|PROT_WRITE, MAP_SHARED, tfd, 0);
-	if ((caddr_t)ptr == (caddr_t)-1) {
+	ptr = mmap (0, sbuf.st_size, PROT_READ|PROT_WRITE, MAP_SHARED, tfd, 0);
+	if (ptr == MAP_FAILED) {
 		fprintf (stderr, "%s: Can't read %s: %s\n",
 				cmdname, tmpfile, strerror(errno));
 		unlink (tmpfile);