Update CHANGELOG, prepare 2008-10-rc1 release

Signed-off-by: Wolfgang Denk <wd@denx.de>

.gitignore

@@ -11,6 +11,7 @@
 *.a
 *.o
 *~
+*.swp
 *.patch
 
 #
@@ -49,6 +50,10 @@ series
 # cscope files
 cscope.*
 
+# tags files
+/ctags
+/etags
+
 # OneNAND IPL files
 /onenand_ipl/onenand-ipl*
 /onenand_ipl/board/*/onenand*

CREDITS

@@ -217,6 +217,10 @@ H: Rich Ireland
 E: r.ireland@computer.org
 D: FPGA device configuration driver
 
+H: Mark Jackson
+E: mpfj@mimc.co.uk
+D: Port to MIMC200 board
+
 N: Gary Jennejohn
 E: garyj@jennejohn.org, gj@denx.de
 D: Support for Samsung ARM920T S3C2400X, ARM920T "TRAB"
@@ -399,6 +403,12 @@ N: Stelian Pop
 E: stelian.pop@leadtechdesign.com
 D: Atmel AT91CAP9ADK support
 
+N: Ricardo Ribalda Delgado
+E: ricardo.ribalda@uam.es
+D: PPC440x5 (Virtex5), ML507 Board, eeprom_simul, adt7460, v5fx30teval
+D: Virtex ppc440 generic architecture
+W: http://www.ii.uam.es/~rribalda
+
 N: Stefan Roese
 E: sr@denx.de
 D: AMCC PPC4xx Support

MAINTAINERS

@@ -189,10 +189,6 @@ Wolfgang Grandegger <wg@denx.de>
 	IPHASE4539	MPC8260
 	SCM		MPC8260
 
-Howard Gray <mvsensor@matrix-vision.de>
-
-	MVS1		MPC823
-
 Joe Hamman <joe.hamman@embeddedspecialties.com>
 
 	sbc8548		MPC8548
@@ -315,6 +311,12 @@ Daniel Poirot <dan.poirot@windriver.com>
 	sbc8240		MPC8240
 	sbc405		PPC405GP
 
+Ricardo Ribalda <ricardo.ribalda@uam.es>
+
+	ml507 		PPC440x5
+	v5fx30teval	PPC440x5
+	xilinx-pp440-generic	PPC440x5
+
 Stefan Roese <sr@denx.de>
 
 	P3M7448		MPC7448
@@ -365,6 +367,8 @@ Heiko Schocher <hs@denx.de>
 	jupiter		MPC5200
 	mgcoge		MPC8247
 	mgsuvd		MPC852
+	mucmc52		MPC5200
+	muas3001	MPC8270
 	municse		MPC5200
 	sc3		PPC405GP
 	uc101		MPC5200
@@ -424,6 +428,9 @@ John Zhan <zhanz@sinovee.com>
 
 	svm_sc8xx	MPC8xx
 
+Feng Kan <fkan@amcc.com>
+
+	redwood			PPC4xx
 -------------------------------------------------------------------------
 
 Unknown / orphaned boards:
@@ -496,6 +503,11 @@ Kshitij Gupta <kshitij@ti.com>
 	omap1510inn	ARM925T
 	omap1610inn	ARM926EJS
 
+Sascha Hauer <s.hauer@pengutronix.de>
+
+	imx31_litekit	i.MX31
+	imx31_phycore	i.MX31
+
 Gary Jennejohn <gj@denx.de>
 
 	smdk2400	ARM920T
@@ -518,6 +530,11 @@ Prakash Kumar <prakash@embedx.com>
 
 	cerf250		xscale
 
+Guennadi Liakhovetski <g.liakhovetski@gmx.de>
+
+	mx31ads		i.MX31
+	SMDK6400	S3C6400
+
 David M<>ller <d.mueller@elsoft.ch>
 
 	smdk2410	ARM920T
@@ -691,6 +708,7 @@ TsiChung Liew <Tsi-Chung.Liew@freescale.com>
 
 	M52277EVB	mcf5227x
 	M5235EVB	mcf52x2
+	M5253DEMO	mcf52x2
 	M5329EVB	mcf532x
 	M5373EVB	mcf532x
 	M54455EVB	mcf5445x
@@ -704,7 +722,20 @@ TsiChung Liew <Tsi-Chung.Liew@freescale.com>
 #	Board		CPU						#
 #########################################################################
 
-Haavard Skinnemoen <hskinnemoen@atmel.com>
+Hans-Christian Egtvedt <hans-christian.egtvedt@atmel.com>
+
+	FAVR-32-EZKIT		AT32AP7000
+
+Mark Jackson <mpfj@mimc.co.uk>
+
+	MIMC200			AT32AP7000
+
+Alex Raimondi <alex.raimondi@miromico.ch>
+Julien May <julien.may@miromico.ch>
+
+	HAMMERHEAD		AT32AP7000
+
+Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
 
 	ATSTK1000	AT32AP7xxx
 	ATSTK1002	AT32AP7000
@@ -725,12 +756,15 @@ Yusuke Goda <goda.yusuke@renesas.com>
 	MIGO-R		SH7722
 
 Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+		  <iwamatsu.nobuhiro@renesas.com>
 
 	MS7750SE	SH7750
 	MS7722SE	SH7722
 	R7780MP		SH7780
 	R2DPlus		SH7751R
 	SH7763RDP	SH7763
+	RSK7203		SH7203
+	AP325RXA	SH7723
 
 Mark Jonas <mark.jonas@de.bosch.com>
 
@@ -739,6 +773,11 @@ Mark Jonas <mark.jonas@de.bosch.com>
 Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
 
 	MS7720SE	SH7720
+	R0P77850011RL	SH7785
+
+Yusuke Goda <goda.yusuke@renesas.com>
+
+	MIGO-R		SH7722
 
 #########################################################################
 # Blackfin Systems:							#

MAKEALL

@@ -114,7 +114,6 @@ LIST_8xx="		\
 	MHPC		\
 	MPC86xADS	\
 	MPC885ADS	\
-	MVS1		\
 	NETPHONE	\
 	NETTA		\
 	NETTA2		\
@@ -209,6 +208,8 @@ LIST_4xx="		\
 	MIP405T		\
 	ML2		\
 	ml300		\
+	ml507		\
+	ml507_flash	\
 	ocotea		\
 	OCRTC		\
 	ORSG		\
@@ -222,18 +223,23 @@ LIST_4xx="		\
 	PPChameleonEVB	\
 	quad100hd	\
 	rainier		\
+	redwood		\
 	sbc405		\
 	sc3		\
 	sequoia		\
 	sequoia_nand	\
 	taihu		\
 	taishan		\
+	v5fx30teval	\
+	v5fx30teval_flash \
 	VOH405		\
 	VOM405		\
 	W7OLMC		\
 	W7OLMG		\
 	walnut		\
 	WUH405		\
+	xilinx-ppc440-generic \
+	xilinx-ppc440-generic_flash \
 	XPEDITE1K	\
 	yellowstone	\
 	yosemite	\
@@ -318,7 +324,7 @@ LIST_8260="		\
 
 LIST_83xx="		\
 	MPC8313ERDB_33	\
-	MPC8313ERDB_66	\
+	MPC8313ERDB_NAND_66	\
 	MPC8315ERDB	\
 	MPC8323ERDB	\
 	MPC832XEMDS	\
@@ -344,6 +350,7 @@ LIST_83xx="		\
 
 LIST_85xx="		\
 	ATUM8548	\
+	MPC8536DS	\
 	MPC8540ADS	\
 	MPC8540EVAL	\
 	MPC8541CDS	\
@@ -352,6 +359,7 @@ LIST_85xx="		\
 	MPC8555CDS	\
 	MPC8560ADS	\
 	MPC8568MDS	\
+	MPC8572DS	\
 	PM854		\
 	PM856		\
 	sbc8540		\
@@ -515,6 +523,7 @@ LIST_ARM11="		\
 	imx31_litekit	\
 	imx31_phycore	\
 	mx31ads		\
+	smdk6400	\
 "
 
 #########################################################################
@@ -691,6 +700,7 @@ LIST_coldfire="			\
 	M52277EVB		\
 	M5235EVB		\
 	M5249EVB		\
+	M5253DEMO		\
 	M5253EVBE		\
 	M5271EVB		\
 	M5272C3			\
@@ -698,6 +708,7 @@ LIST_coldfire="			\
 	M5282EVB		\
 	M5329AFEE		\
 	M5373EVB		\
+	M54451EVB		\
 	M54455EVB		\
 	M5475AFE		\
 	M5485AFE		\
@@ -714,6 +725,9 @@ LIST_avr32="		\
 	atstk1004	\
 	atstk1006	\
 	atngw100	\
+	favr-32-ezkit	\
+	hammerhead	\
+	mimc200		\
 "
 
 #########################################################################
@@ -731,6 +745,9 @@ LIST_blackfin="		\
 ## SH Systems
 #########################################################################
 
+LIST_sh2="		\
+	rsk7203		\
+"
 LIST_sh3="		\
 	mpr2		\
 	ms7720se	\
@@ -743,9 +760,12 @@ LIST_sh4="		\
 	r7780mp		\
 	r2dplus		\
 	sh7763rdp	\
+	sh7785lcr	\
+	ap325rxa	\
 "
 
 LIST_sh="		\
+	${LIST_sh2}	\
 	${LIST_sh3}	\
 	${LIST_sh4}	\
 "
@@ -790,7 +810,7 @@ do
 	|mips|mips_el \
 	|nios|nios2 \
 	|ppc|5xx|5xxx|512x|8xx|8220|824x|8260|83xx|85xx|86xx|4xx|7xx|74xx|TSEC \
-	|sh|sh3|sh4 \
+	|sh|sh2|sh3|sh4 \
 	|sparc \
 	|x86|I486 \
 	)

Makefile

@@ -21,11 +21,15 @@
 # MA 02111-1307 USA
 #
 
-VERSION = 1
-PATCHLEVEL = 3
-SUBLEVEL = 4
-EXTRAVERSION =
+VERSION = 2008
+PATCHLEVEL = 10
+SUBLEVEL =
+EXTRAVERSION = -rc1
+ifneq "$(SUBLEVEL)" ""
 U_BOOT_VERSION = $(VERSION).$(PATCHLEVEL).$(SUBLEVEL)$(EXTRAVERSION)
+else
+U_BOOT_VERSION = $(VERSION).$(PATCHLEVEL)$(EXTRAVERSION)
+endif
 VERSION_FILE = $(obj)include/version_autogenerated.h
 
 HOSTARCH := $(shell uname -m | \
@@ -210,7 +214,7 @@ LIBS += cpu/ixp/npe/libnpe.a
 endif
 LIBS += lib_$(ARCH)/lib$(ARCH).a
 LIBS += fs/cramfs/libcramfs.a fs/fat/libfat.a fs/fdos/libfdos.a fs/jffs2/libjffs2.a \
-	fs/reiserfs/libreiserfs.a fs/ext2/libext2fs.a
+	fs/reiserfs/libreiserfs.a fs/ext2/libext2fs.a fs/yaffs2/libyaffs2.a
 LIBS += net/libnet.a
 LIBS += disk/libdisk.a
 LIBS += drivers/bios_emulator/libatibiosemu.a
@@ -227,6 +231,7 @@ LIBS += drivers/mtd/nand_legacy/libnand_legacy.a
 LIBS += drivers/mtd/onenand/libonenand.a
 LIBS += drivers/mtd/spi/libspi_flash.a
 LIBS += drivers/net/libnet.a
+LIBS += drivers/net/phy/libphy.a
 LIBS += drivers/net/sk98lin/libsk98lin.a
 LIBS += drivers/pci/libpci.a
 LIBS += drivers/pcmcia/libpcmcia.a
@@ -236,6 +241,10 @@ LIBS += drivers/qe/qe.a
 endif
 ifeq ($(CPU),mpc85xx)
 LIBS += drivers/qe/qe.a
+LIBS += cpu/mpc8xxx/ddr/libddr.a
+endif
+ifeq ($(CPU),mpc86xx)
+LIBS += cpu/mpc8xxx/ddr/libddr.a
 endif
 LIBS += drivers/rtc/librtc.a
 LIBS += drivers/serial/libserial.a
@@ -290,7 +299,7 @@ $(obj)u-boot.hex:	$(obj)u-boot
 		$(OBJCOPY) ${OBJCFLAGS} -O ihex $< $@
 
 $(obj)u-boot.srec:	$(obj)u-boot
-		$(OBJCOPY) ${OBJCFLAGS} -O srec $< $@
+		$(OBJCOPY) -O srec $< $@
 
 $(obj)u-boot.bin:	$(obj)u-boot
 		$(OBJCOPY) ${OBJCFLAGS} -O binary $< $@
@@ -378,6 +387,7 @@ TAG_SUBDIRS += fs/cramfs
 TAG_SUBDIRS += fs/fat
 TAG_SUBDIRS += fs/fdos
 TAG_SUBDIRS += fs/jffs2
+TAG_SUBDIRS += fs/yaffs2
 TAG_SUBDIRS += net
 TAG_SUBDIRS += disk
 TAG_SUBDIRS += common
@@ -458,6 +468,8 @@ CHANGELOG:
 	git log --no-merges U-Boot-1_1_5.. | \
 	unexpand -a | sed -e 's/\s\s*$$//' > $@
 
+include/license.h: tools/bin2header COPYING
+	 cat COPYING | gzip -9 -c | ./tools/bin2header license_gzip > include/license.h
 #########################################################################
 
 unconfig:
@@ -619,6 +631,9 @@ mecp5200_config:  unconfig
 motionpro_config:	unconfig
 	@$(MKCONFIG) motionpro ppc mpc5xxx motionpro
 
+mucmc52_config:		unconfig
+	@$(MKCONFIG) mucmc52 ppc mpc5xxx mucmc52
+
 munices_config:	unconfig
 	@$(MKCONFIG) munices ppc mpc5xxx munices
 
@@ -911,9 +926,6 @@ mgsuvd_config:		unconfig
 MHPC_config:		unconfig
 	@$(MKCONFIG) $(@:_config=) ppc mpc8xx mhpc eltec
 
-MVS1_config :		unconfig
-	@$(MKCONFIG) $(@:_config=) ppc mpc8xx mvs1
-
 xtract_NETVIA = $(subst _V2,,$(subst _config,,$1))
 
 NETVIA_V2_config \
@@ -1234,12 +1246,15 @@ CMS700_config:	unconfig
 CPCI2DP_config:	unconfig
 	@$(MKCONFIG) $(@:_config=) ppc ppc4xx cpci2dp esd
 
-CPCI405_config	\
-CPCI4052_config	\
+CPCI405_config:		unconfig
+	@$(MKCONFIG) $(@:_config=) ppc ppc4xx cpci405 esd
+
+CPCI4052_config		\
 CPCI405DT_config	\
 CPCI405AB_config:	unconfig
+	@mkdir -p $(obj)board/esd/cpci405
+	@echo "TEXT_BASE = 0xFFFC0000" > $(obj)board/esd/cpci405/config.tmp
 	@$(MKCONFIG) $(@:_config=) ppc ppc4xx cpci405 esd
-	@echo "BOARD_REVISION = $(@:_config=)"	>> $(obj)include/config.mk
 
 CPCIISER4_config:	unconfig
 	@$(MKCONFIG) $(@:_config=) ppc ppc4xx cpciiser4 esd
@@ -1348,6 +1363,24 @@ ML2_config:	unconfig
 ml300_config:	unconfig
 	@$(MKCONFIG) $(@:_config=) ppc ppc4xx ml300 xilinx
 
+ml507_flash_config: unconfig
+	@mkdir -p $(obj)include $(obj)board/xilinx/ppc440-generic
+	@mkdir -p $(obj)include $(obj)board/xilinx/ml507
+	@echo "LDSCRIPT:=$(SRCTREE)/board/xilinx/ppc440-generic/u-boot-rom.lds"\
+		> $(obj)board/xilinx/ml507/config.tmp
+	@echo "TEXT_BASE := 0xFE360000" \
+		>> $(obj)board/xilinx/ml507/config.tmp
+	@$(MKCONFIG) ml507 ppc ppc4xx ml507 xilinx
+
+ml507_config: unconfig
+	@mkdir -p $(obj)include $(obj)board/xilinx/ppc440-generic
+	@mkdir -p $(obj)include $(obj)board/xilinx/ml507
+	@echo "LDSCRIPT:=$(SRCTREE)/board/xilinx/ppc440-generic/u-boot-ram.lds"\
+		> $(obj)board/xilinx/ml507/config.tmp
+	@echo "TEXT_BASE := 0x04000000"  \
+		>> $(obj)board/xilinx/ml507/config.tmp
+	@$(MKCONFIG) ml507 ppc ppc4xx ml507 xilinx
+
 ocotea_config:	unconfig
 	@$(MKCONFIG) $(@:_config=) ppc ppc4xx ocotea amcc
 
@@ -1409,6 +1442,9 @@ PPChameleonEVB_HI_33_config:	unconfig
 quad100hd_config:	unconfig
 	@$(MKCONFIG) $(@:_config=) ppc ppc4xx quad100hd
 
+redwood_config: unconfig
+	@$(MKCONFIG) $(@:_config=) ppc ppc4xx redwood amcc
+
 sbc405_config:	unconfig
 	@$(MKCONFIG) $(@:_config=) ppc ppc4xx sbc405
 
@@ -1439,6 +1475,24 @@ taihu_config:	unconfig
 taishan_config:	unconfig
 	@$(MKCONFIG) $(@:_config=) ppc ppc4xx taishan amcc
 
+v5fx30teval_config: unconfig
+	@mkdir -p $(obj)include $(obj)board/xilinx/ppc440-generic
+	@mkdir -p $(obj)include $(obj)board/avnet/v5fx30teval
+	@echo "LDSCRIPT:=$(SRCTREE)/board/xilinx/ppc440-generic/u-boot-ram.lds"\
+		> $(obj)board/avnet/v5fx30teval/config.tmp
+	@echo "TEXT_BASE := 0x03000000" \
+		>> $(obj)board/avnet/v5fx30teval/config.tmp
+	@$(MKCONFIG) v5fx30teval ppc ppc4xx v5fx30teval avnet
+
+v5fx30teval_flash_config: unconfig
+	@mkdir -p $(obj)include $(obj)board/xilinx/ppc440-generic
+	@mkdir -p $(obj)include $(obj)board/avnet/v5fx30teval
+	@echo "LDSCRIPT:=$(SRCTREE)/board/xilinx/ppc440-generic/u-boot-rom.lds"\
+		> $(obj)/board/avnet/v5fx30teval/config.tmp
+	@echo "TEXT_BASE := 0xFF1C0000" \
+		>> $(obj)/board/avnet/v5fx30teval/config.tmp
+	@$(MKCONFIG) v5fx30teval ppc ppc4xx v5fx30teval avnet
+
 VOH405_config:	unconfig
 	@$(MKCONFIG) $(@:_config=) ppc ppc4xx voh405 esd
 
@@ -1457,6 +1511,22 @@ sycamore_config: unconfig
 WUH405_config:	unconfig
 	@$(MKCONFIG) $(@:_config=) ppc ppc4xx wuh405 esd
 
+xilinx-ppc440-generic_flash_config: unconfig
+	@mkdir -p $(obj)include $(obj)board/xilinx/ppc440-generic
+	@echo "LDSCRIPT:=$(SRCTREE)/board/xilinx/ppc440-generic/u-boot-rom.lds"\
+		> $(obj)board/xilinx/ppc440-generic/config.tmp
+	@echo "TEXT_BASE := 0xFE360000" \
+		>> $(obj)board/xilinx/ppc440-generic/config.tmp
+	@$(MKCONFIG) xilinx-ppc440-generic ppc ppc4xx ppc440-generic xilinx
+
+xilinx-ppc440-generic_config: unconfig
+	@mkdir -p $(obj)include $(obj)board/xilinx/ppc440-generic
+	@echo "LDSCRIPT:=$(SRCTREE)/board/xilinx/ppc440-generic/u-boot-ram.lds"\
+		> $(obj)board/xilinx/ppc440-generic/config.tmp
+	@echo "TEXT_BASE := 0x04000000" \
+		>> $(obj)board/xilinx/ppc440-generic/config.tmp
+	@$(MKCONFIG) xilinx-ppc440-generic ppc ppc4xx ppc440-generic xilinx
+
 XPEDITE1K_config:	unconfig
 	@$(MKCONFIG) $(@:_config=) ppc ppc4xx xpedite1k
 
@@ -1672,6 +1742,15 @@ PQ2FADS-ZU_66MHz_lowboot_config	\
 MPC8266ADS_config:	unconfig
 	@$(MKCONFIG) $(@:_config=) ppc mpc8260 mpc8266ads freescale
 
+muas3001_dev_config \
+muas3001_config	:	unconfig
+	@mkdir -p $(obj)include
+	@mkdir -p $(obj)board/muas3001
+	@if [ "$(findstring dev,$@)" ] ; then \
+		echo "#define CONFIG_MUAS_DEV_BOARD" > $(obj)include/config.h ; \
+	fi
+	@$(MKCONFIG) -a muas3001 ppc mpc8260 muas3001
+
 # PM825/PM826 default configuration:  small (= 8 MB) Flash / boot from 64-bit flash
 PM825_config	\
 PM825_ROMBOOT_config	\
@@ -1836,6 +1915,9 @@ M5235EVB_Flash32_config:	unconfig
 M5249EVB_config :		unconfig
 	@$(MKCONFIG) $(@:_config=) m68k mcf52x2 m5249evb freescale
 
+M5253DEMO_config :		unconfig
+	@$(MKCONFIG) $(@:_config=) m68k mcf52x2 m5253demo freescale
+
 M5253EVBE_config :		unconfig
 	@$(MKCONFIG) $(@:_config=) m68k mcf52x2 m5253evbe freescale
 
@@ -1858,16 +1940,16 @@ idmr_config :			unconfig
 	@$(MKCONFIG) $(@:_config=) m68k mcf52x2 idmr
 
 M5271EVB_config :		unconfig
-	@$(MKCONFIG) $(@:_config=) m68k mcf52x2 m5271evb
+	@$(MKCONFIG) $(@:_config=) m68k mcf52x2 m5271evb freescale
 
 M5272C3_config :		unconfig
-	@$(MKCONFIG) $(@:_config=) m68k mcf52x2 m5272c3
+	@$(MKCONFIG) $(@:_config=) m68k mcf52x2 m5272c3 freescale
 
 M5275EVB_config :		unconfig
 	@$(MKCONFIG) $(@:_config=) m68k mcf52x2 m5275evb freescale
 
 M5282EVB_config :		unconfig
-	@$(MKCONFIG) $(@:_config=) m68k mcf52x2 m5282evb
+	@$(MKCONFIG) $(@:_config=) m68k mcf52x2 m5282evb freescale
 
 M5329AFEE_config \
 M5329BFEE_config :	unconfig
@@ -1889,13 +1971,38 @@ M5373EVB_config :	unconfig
 	fi
 	@$(MKCONFIG) -a M5373EVB m68k mcf532x m5373evb freescale
 
+M54451EVB_config \
+M54451EVB_spansion_config \
+M54451EVB_stmicro_config :	unconfig
+	@case "$@" in \
+	M54451EVB_config)		FLASH=SPANSION;; \
+	M54451EVB_spansion_config)	FLASH=SPANSION;; \
+	M54451EVB_stmicro_config)	FLASH=STMICRO;; \
+	esac; \
+	if [ "$${FLASH}" = "SPANSION" ] ; then \
+		echo "#define CFG_SPANSION_BOOT"	>> $(obj)include/config.h ; \
+		echo "TEXT_BASE = 0x00000000" > $(obj)board/freescale/m54451evb/config.tmp ; \
+		cp $(obj)board/freescale/m54451evb/u-boot.spa $(obj)board/freescale/m54451evb/u-boot.lds ; \
+		$(XECHO) "... with SPANSION boot..." ; \
+	fi; \
+	if [ "$${FLASH}" = "STMICRO" ] ; then \
+		echo "#define CONFIG_CF_SBF"	>> $(obj)include/config.h ; \
+		echo "#define CFG_STMICRO_BOOT"	>> $(obj)include/config.h ; \
+		echo "TEXT_BASE = 0x47E00000" > $(obj)board/freescale/m54451evb/config.tmp ; \
+		cp $(obj)board/freescale/m54451evb/u-boot.stm $(obj)board/freescale/m54451evb/u-boot.lds ; \
+		$(XECHO) "... with ST Micro boot..." ; \
+	fi; \
+	echo "#define CFG_INPUT_CLKSRC 24000000" >> $(obj)include/config.h ;
+	@$(MKCONFIG) -a M54451EVB m68k mcf5445x m54451evb freescale
+
 M54455EVB_config \
 M54455EVB_atmel_config \
 M54455EVB_intel_config \
 M54455EVB_a33_config \
 M54455EVB_a66_config \
 M54455EVB_i33_config \
-M54455EVB_i66_config :	unconfig
+M54455EVB_i66_config \
+M54455EVB_stm33_config :	unconfig
 	@case "$@" in \
 	M54455EVB_config)		FLASH=ATMEL; FREQ=33333333;; \
 	M54455EVB_atmel_config)		FLASH=ATMEL; FREQ=33333333;; \
@@ -1904,18 +2011,27 @@ M54455EVB_i66_config :	unconfig
 	M54455EVB_a66_config)		FLASH=ATMEL; FREQ=66666666;; \
 	M54455EVB_i33_config)		FLASH=INTEL; FREQ=33333333;; \
 	M54455EVB_i66_config)		FLASH=INTEL; FREQ=66666666;; \
+	M54455EVB_stm33_config)		FLASH=STMICRO; FREQ=33333333;; \
 	esac; \
 	if [ "$${FLASH}" = "INTEL" ] ; then \
-		echo "#undef CFG_ATMEL_BOOT" >> $(obj)include/config.h ; \
+		echo "#define CFG_INTEL_BOOT" >> $(obj)include/config.h ; \
 		echo "TEXT_BASE = 0x00000000" > $(obj)board/freescale/m54455evb/config.tmp ; \
 		cp $(obj)board/freescale/m54455evb/u-boot.int $(obj)board/freescale/m54455evb/u-boot.lds ; \
 		$(XECHO) "... with INTEL boot..." ; \
-	else \
+	fi; \
+	if [ "$${FLASH}" = "ATMEL" ] ; then \
 		echo "#define CFG_ATMEL_BOOT"	>> $(obj)include/config.h ; \
 		echo "TEXT_BASE = 0x04000000" > $(obj)board/freescale/m54455evb/config.tmp ; \
 		cp $(obj)board/freescale/m54455evb/u-boot.atm $(obj)board/freescale/m54455evb/u-boot.lds ; \
 		$(XECHO) "... with ATMEL boot..." ; \
 	fi; \
+	if [ "$${FLASH}" = "STMICRO" ] ; then \
+		echo "#define CONFIG_CF_SBF"	>> $(obj)include/config.h ; \
+		echo "#define CFG_STMICRO_BOOT"	>> $(obj)include/config.h ; \
+		echo "TEXT_BASE = 0x4FE00000" > $(obj)board/freescale/m54455evb/config.tmp ; \
+		cp $(obj)board/freescale/m54455evb/u-boot.stm $(obj)board/freescale/m54455evb/u-boot.lds ; \
+		$(XECHO) "... with ST Micro boot..." ; \
+	fi; \
 	echo "#define CFG_INPUT_CLKSRC $${FREQ}" >> $(obj)include/config.h ; \
 	$(XECHO) "... with $${FREQ}Hz input clock"
 	@$(MKCONFIG) -a M54455EVB m68k mcf5445x m54455evb freescale
@@ -1996,8 +2112,11 @@ TASREG_config :		unconfig
 #########################################################################
 
 MPC8313ERDB_33_config \
-MPC8313ERDB_66_config: unconfig
+MPC8313ERDB_66_config \
+MPC8313ERDB_NAND_33_config \
+MPC8313ERDB_NAND_66_config: unconfig
 	@mkdir -p $(obj)include
+	@mkdir -p $(obj)board/freescale/mpc8313erdb
 	@if [ "$(findstring _33_,$@)" ] ; then \
 		$(XECHO) -n "...33M ..." ; \
 		echo "#define CFG_33MHZ" >>$(obj)include/config.h ; \
@@ -2005,8 +2124,16 @@ MPC8313ERDB_66_config: unconfig
 	if [ "$(findstring _66_,$@)" ] ; then \
 		$(XECHO) -n "...66M..." ; \
 		echo "#define CFG_66MHZ" >>$(obj)include/config.h ; \
+	fi ; \
+	if [ "$(findstring _NAND_,$@)" ] ; then \
+		$(XECHO) -n "...NAND..." ; \
+		echo "TEXT_BASE = 0x00100000" > $(obj)board/freescale/mpc8313erdb/config.tmp ; \
+		echo "#define CONFIG_NAND_U_BOOT" >>$(obj)include/config.h ; \
 	fi ;
 	@$(MKCONFIG) -a MPC8313ERDB ppc mpc83xx mpc8313erdb freescale
+	@if [ "$(findstring _NAND_,$@)" ] ; then \
+		echo "CONFIG_NAND_U_BOOT = y" >> $(obj)include/config.mk ; \
+	fi ;
 
 MPC8315ERDB_config: unconfig
 	@$(MKCONFIG) -a MPC8315ERDB ppc mpc83xx mpc8315erdb freescale
@@ -2118,7 +2245,7 @@ MPC837XERDB_config:	unconfig
 	@$(MKCONFIG) -a MPC837XERDB ppc mpc83xx mpc837xerdb freescale
 
 MVBLM7_config: unconfig
-	@$(MKCONFIG) $(@:_config=) ppc mpc83xx mvblm7
+	@$(MKCONFIG) $(@:_config=) ppc mpc83xx mvblm7 matrix_vision
 
 sbc8349_config:		unconfig
 	@$(MKCONFIG) $(@:_config=) ppc mpc83xx sbc8349
@@ -2134,6 +2261,9 @@ TQM834x_config:	unconfig
 ATUM8548_config:	unconfig
 	@$(MKCONFIG) $(@:_config=) ppc mpc85xx atum8548
 
+MPC8536DS_config:       unconfig
+	@$(MKCONFIG) $(@:_config=) ppc mpc85xx mpc8536ds freescale
+
 MPC8540ADS_config:	unconfig
 	@$(MKCONFIG) $(@:_config=) ppc mpc85xx mpc8540ads freescale
 
@@ -2193,6 +2323,9 @@ MPC8555CDS_config:	unconfig
 MPC8568MDS_config:	unconfig
 	@$(MKCONFIG) $(@:_config=) ppc mpc85xx mpc8568mds freescale
 
+MPC8572DS_config:       unconfig
+	@$(MKCONFIG) $(@:_config=) ppc mpc85xx mpc8572ds freescale
+
 PM854_config:	unconfig
 	@$(MKCONFIG) $(@:_config=) ppc mpc85xx pm854
 
@@ -2354,13 +2487,13 @@ at91rm9200dk_config	:	unconfig
 	@$(MKCONFIG) $(@:_config=) arm arm920t at91rm9200dk atmel at91rm9200
 
 at91sam9261ek_config	:	unconfig
-	@$(MKCONFIG) $(@:_config=) arm arm926ejs at91sam9261ek atmel at91sam9
+	@$(MKCONFIG) $(@:_config=) arm arm926ejs at91sam9261ek atmel at91
 
 at91sam9263ek_config	:	unconfig
-	@$(MKCONFIG) $(@:_config=) arm arm926ejs at91sam9263ek atmel at91sam9
+	@$(MKCONFIG) $(@:_config=) arm arm926ejs at91sam9263ek atmel at91
 
 at91sam9rlek_config	:	unconfig
-	@$(MKCONFIG) $(@:_config=) arm arm926ejs at91sam9rlek atmel at91sam9
+	@$(MKCONFIG) $(@:_config=) arm arm926ejs at91sam9rlek atmel at91
 
 cmc_pu2_config	:	unconfig
 	@$(MKCONFIG) $(@:_config=) arm arm920t cmc_pu2 NULL at91rm9200
@@ -2382,10 +2515,10 @@ mp2usb_config	:	unconfig
 #########################################################################
 
 at91cap9adk_config	:	unconfig
-	@$(MKCONFIG) $(@:_config=) arm arm926ejs at91cap9adk atmel at91sam9
+	@$(MKCONFIG) $(@:_config=) arm arm926ejs at91cap9adk atmel at91
 
 at91sam9260ek_config	:	unconfig
-	@$(MKCONFIG) $(@:_config=) arm arm926ejs at91sam9260ek atmel at91sam9
+	@$(MKCONFIG) $(@:_config=) arm arm926ejs at91sam9260ek atmel at91
 
 ########################################################################
 ## ARM Integrator boards - see doc/README-integrator for more info.
@@ -2414,7 +2547,7 @@ cp1026_config: unconfig
 	@board/integratorcp/split_by_variant.sh $@
 
 davinci_dvevm_config :	unconfig
-	@$(MKCONFIG) $(@:_config=) arm arm926ejs dv-evm davinci davinci
+	@$(MKCONFIG) $(@:_config=) arm arm926ejs dvevm davinci davinci
 
 davinci_schmoogie_config :	unconfig
 	@$(MKCONFIG) $(@:_config=) arm arm926ejs schmoogie davinci davinci
@@ -2672,11 +2805,28 @@ imx31_phycore_config	: unconfig
 	@$(MKCONFIG) $(@:_config=) arm arm1136 imx31_phycore NULL mx31
 
 mx31ads_config		: unconfig
-	@$(MKCONFIG) $(@:_config=) arm arm1136 mx31ads NULL mx31
+	@$(MKCONFIG) $(@:_config=) arm arm1136 mx31ads freescale mx31
 
 omap2420h4_config	: unconfig
 	@$(MKCONFIG) $(@:_config=) arm arm1136 omap2420h4 NULL omap24xx
 
+#########################################################################
+## ARM1176 Systems
+#########################################################################
+smdk6400_noUSB_config	\
+smdk6400_config	:	unconfig
+	@mkdir -p $(obj)include $(obj)board/samsung/smdk6400
+	@mkdir -p $(obj)nand_spl/board/samsung/smdk6400
+	@echo "#define CONFIG_NAND_U_BOOT" > $(obj)include/config.h
+	@if [ -z "$(findstring smdk6400_noUSB_config,$@)" ]; then			\
+		echo "RAM_TEXT = 0x57e00000" >> $(obj)board/samsung/smdk6400/config.tmp;\
+		$(MKCONFIG) $(@:_config=) arm arm1176 smdk6400 samsung s3c64xx;		\
+	else										\
+		echo "RAM_TEXT = 0xc7e00000" >> $(obj)board/samsung/smdk6400/config.tmp;\
+		$(MKCONFIG) $(@:_noUSB_config=) arm arm1176 smdk6400 samsung s3c64xx;	\
+	fi
+	@echo "CONFIG_NAND_U_BOOT = y" >> $(obj)include/config.mk
+
 #========================================================================
 # i386
 #========================================================================
@@ -2911,10 +3061,27 @@ atstk1004_config	:	unconfig
 atstk1006_config	:	unconfig
 	@$(MKCONFIG) $(@:_config=) avr32 at32ap atstk1000 atmel at32ap700x
 
+favr-32-ezkit_config	:	unconfig
+	@$(MKCONFIG) $(@:_config=) avr32 at32ap favr-32-ezkit earthlcd at32ap700x
+
+hammerhead_config	:	unconfig
+	@$(MKCONFIG) $(@:_config=) avr32 at32ap hammerhead miromico at32ap700x
+
+mimc200_config		:	unconfig
+	@$(MKCONFIG) $(@:_config=) avr32 at32ap mimc200 mimc at32ap700x
+
 #========================================================================
 # SH3 (SuperH)
 #========================================================================
 
+#########################################################################
+## sh2 (Renesas SuperH)
+#########################################################################
+rsk7203_config: unconfig
+	@ >include/config.h
+	@echo "#define CONFIG_RSK7203 1" >> include/config.h
+	@./mkconfig -a $(@:_config=) sh sh2 rsk7203
+
 #########################################################################
 ## sh3 (Renesas SuperH)
 #########################################################################
@@ -2951,17 +3118,27 @@ ms7722se_config :	unconfig
 r2dplus_config  :   unconfig
 	@mkdir -p $(obj)include
 	@echo "#define CONFIG_R2DPLUS 1" > $(obj)include/config.h
-	@./mkconfig -a $(@:_config=) sh sh4 r2dplus
+	@$(MKCONFIG) -a $(@:_config=) sh sh4 r2dplus
 
 r7780mp_config: unconfig
 	@mkdir -p $(obj)include
 	@echo "#define CONFIG_R7780MP 1" > $(obj)include/config.h
-	@./mkconfig -a $(@:_config=) sh sh4 r7780mp
+	@$(MKCONFIG) -a $(@:_config=) sh sh4 r7780mp
 
 sh7763rdp_config  :   unconfig
 	@mkdir -p $(obj)include
 	@echo "#define CONFIG_SH7763RDP 1" > $(obj)include/config.h
-	@./mkconfig -a $(@:_config=) sh sh4 sh7763rdp
+	@$(MKCONFIG) -a $(@:_config=) sh sh4 sh7763rdp
+
+sh7785lcr_config  :   unconfig
+	@ >include/config.h
+	@echo "#define CONFIG_SH7785LCR 1" >> include/config.h
+	@$(MKCONFIG) -a $(@:_config=) sh sh4 sh7785lcr
+
+ap325rxa_config  :   unconfig
+	@mkdir -p $(obj)include
+	@echo "#define CONFIG_AP325RXA 1" > $(obj)include/config.h
+	@$(MKCONFIG) -a $(@:_config=) sh sh4 ap325rxa
 
 #========================================================================
 # SPARC
@@ -3041,9 +3218,9 @@ clobber:	clean
 	@rm -f $(obj)tools/{fdt_wip.c,libfdt_internal.h}
 	@rm -f $(obj)cpu/mpc824x/bedbug_603e.c
 	@rm -f $(obj)include/asm/proc $(obj)include/asm/arch $(obj)include/asm
-	@[ ! -d $(obj)nand_spl ] || find $(obj)nand_spl -lname "*" -print | xargs rm -f
-	@[ ! -d $(obj)onenand_ipl ] || find $(obj)onenand_ipl -lname "*" -print | xargs rm -f
-	@[ ! -d $(obj)api_examples ] || find $(obj)api_examples -lname "*" -print | xargs rm -f
+	@[ ! -d $(obj)nand_spl ] || find $(obj)nand_spl -name "*" -type l -print | xargs rm -f
+	@[ ! -d $(obj)onenand_ipl ] || find $(obj)onenand_ipl -name "*" -type l -print | xargs rm -f
+	@[ ! -d $(obj)api_examples ] || find $(obj)api_examples -name "*" -type l -print | xargs rm -f
 
 ifeq ($(OBJTREE),$(SRCTREE))
 mrproper \

README

@@ -380,11 +380,11 @@ The following options need to be configured:
 		param header, the default value is zero if undefined.
 
 - Serial Ports:
-		CFG_PL010_SERIAL
+		CONFIG_PL010_SERIAL
 
 		Define this if you want support for Amba PrimeCell PL010 UARTs.
 
-		CFG_PL011_SERIAL
+		CONFIG_PL011_SERIAL
 
 		Define this if you want support for Amba PrimeCell PL011 UARTs.
 
@@ -2064,7 +2064,7 @@ Configuration Settings:
 		Define if the flash driver uses extra elements in the
 		common flash structure for storing flash geometry.
 
-- CFG_FLASH_CFI_DRIVER
+- CONFIG_FLASH_CFI_DRIVER
 		This option also enables the building of the cfi_flash driver
 		in the drivers directory
 
@@ -3030,8 +3030,9 @@ details; basically, the header defines the following image properties:
 
 * Target Operating System (Provisions for OpenBSD, NetBSD, FreeBSD,
   4.4BSD, Linux, SVR4, Esix, Solaris, Irix, SCO, Dell, NCR, VxWorks,
-  LynxOS, pSOS, QNX, RTEMS, ARTOS;
-  Currently supported: Linux, NetBSD, VxWorks, QNX, RTEMS, ARTOS, LynxOS).
+  LynxOS, pSOS, QNX, RTEMS, INTEGRITY;
+  Currently supported: Linux, NetBSD, VxWorks, QNX, RTEMS, LynxOS,
+  INTEGRITY).
 * Target CPU Architecture (Provisions for Alpha, ARM, AVR32, Intel x86,
   IA64, MIPS, NIOS, PowerPC, IBM S390, SuperH, Sparc, Sparc 64 Bit;
   Currently supported: ARM, AVR32, Intel x86, MIPS, NIOS, PowerPC).
@@ -3089,9 +3090,9 @@ But now you can ignore ALL boot loader code (in arch/ppc/mbxboot).
 
 Just make sure your machine specific header file (for instance
 include/asm-ppc/tqm8xx.h) includes the same definition of the Board
-Information structure as we define in include/u-boot.h, and make
-sure that your definition of IMAP_ADDR uses the same value as your
-U-Boot configuration in CFG_IMMR.
+Information structure as we define in include/asm-<arch>/u-boot.h,
+and make sure that your definition of IMAP_ADDR uses the same value
+as your U-Boot configuration in CFG_IMMR.
 
 
 Configuring the Linux kernel:

board/MAI/AmigaOneG3SE/AmigaOneG3SE.c

@@ -26,6 +26,7 @@
 #include <common.h>
 #include <command.h>
 #include <pci.h>
+#include <netdev.h>
 #include "articiaS.h"
 #include "memio.h"
 #include "via686.h"
@@ -111,3 +112,11 @@ void pci_init_board (void)
 	articiaS_pci_init ();
 #endif
 }
+
+int board_eth_init(bd_t *bis)
+{
+#if defined(CONFIG_3COM)
+	eth_3com_initialize(bis);
+#endif
+	return 0;
+}

board/MAI/AmigaOneG3SE/enet.c

@@ -28,6 +28,7 @@
 #include <common.h>
 #include <malloc.h>
 #include <net.h>
+#include <netdev.h>
 #include <asm/io.h>
 #include <pci.h>
 

board/Marvell/db64360/db64360.c

@@ -33,6 +33,7 @@
 #include "../include/pci.h"
 #include "../include/mv_gen_reg.h"
 #include <net.h>
+#include <netdev.h>
 
 #include "eth.h"
 #include "mpsc.h"
@@ -51,9 +52,6 @@
 #define DP(x)
 #endif
 
-extern void flush_data_cache (void);
-extern void invalidate_l1_instruction_cache (void);
-
 /* ------------------------------------------------------------------------- */
 
 /* this is the current GT register space location */
@@ -930,7 +928,10 @@ void board_prebootm_init ()
 	my_remap_gt_regs_bootm (CFG_GT_REGS, BRIDGE_REG_BASE_BOOTM);
 
 	icache_disable ();
-	invalidate_l1_instruction_cache ();
-	flush_data_cache ();
 	dcache_disable ();
 }
+
+int board_eth_init(bd_t *bis)
+{
+	return pci_eth_init(bis);
+}

board/Marvell/db64460/db64460.c

@@ -33,6 +33,7 @@
 #include "../include/pci.h"
 #include "../include/mv_gen_reg.h"
 #include <net.h>
+#include <netdev.h>
 
 #include "eth.h"
 #include "mpsc.h"
@@ -51,9 +52,6 @@
 #define DP(x)
 #endif
 
-extern void flush_data_cache (void);
-extern void invalidate_l1_instruction_cache (void);
-
 /* ------------------------------------------------------------------------- */
 
 /* this is the current GT register space location */
@@ -930,7 +928,10 @@ void board_prebootm_init ()
 	my_remap_gt_regs_bootm (CFG_GT_REGS, BRIDGE_REG_BASE_BOOTM);
 
 	icache_disable ();
-	invalidate_l1_instruction_cache ();
-	flush_data_cache ();
 	dcache_disable ();
 }
+
+int board_eth_init(bd_t *bis)
+{
+	return pci_eth_init(bis);
+}

board/a3000/a3000.c

@@ -27,6 +27,7 @@
 #include <common.h>
 #include <mpc824x.h>
 #include <pci.h>
+#include <netdev.h>
 
 int checkboard (void)
 {
@@ -109,3 +110,9 @@ void pci_init_board(void)
 {
 	pci_mpc824x_init(&hose);
 }
+
+int board_eth_init(bd_t *bis)
+{
+	return pci_eth_init(bis);
+}
+

board/ads5121/ads5121.c

@@ -25,6 +25,7 @@
 #include <mpc512x.h>
 #include <asm/bitops.h>
 #include <command.h>
+#include <asm/processor.h>
 #include <fdt_support.h>
 #ifdef CONFIG_MISC_INIT_R
 #include <i2c.h>
@@ -92,6 +93,9 @@ int board_early_init_f (void)
 	 * Configure Flash Speed
 	 */
 	*((volatile u32 *)(CFG_IMMR + LPC_OFFSET + CS0_CONFIG)) = CFG_CS0_CFG;
+	if (SVR_MJREV (im->sysconf.spridr) >= 2) {
+		*((volatile u32 *)(CFG_IMMR + LPC_OFFSET + CS_ALE_TIMING_CONFIG)) = CFG_CS_ALETIMING;
+	}
 	/*
 	 * Enable clocks
 	 */

board/amcc/katmai/katmai.c

@@ -27,6 +27,7 @@
 #include <i2c.h>
 #include <libfdt.h>
 #include <fdt_support.h>
+#include <netdev.h>
 #include <asm/processor.h>
 #include <asm/io.h>
 #include <asm/gpio.h>
@@ -349,7 +350,7 @@ int is_pci_host(struct pci_controller *hose)
 	return 1;
 }
 
-int katmai_pcie_card_present(int port)
+static int katmai_pcie_card_present(int port)
 {
 	u32 val;
 
@@ -437,76 +438,6 @@ void pcie_setup_hoses(int busno)
 }
 #endif	/* defined(CONFIG_PCI) */
 
-int misc_init_f (void)
-{
-	uint reg;
-#if defined(CONFIG_STRESS)
-	uint i ;
-	uint disp;
-#endif
-
-	/* minimal init for PCIe */
-#if 0 /* test-only: test endpoint at some time, for now rootpoint only */
-	/* pci express 0 Endpoint Mode */
-	mfsdr(SDR0_PE0DLPSET, reg);
-	reg &= (~0x00400000);
-	mtsdr(SDR0_PE0DLPSET, reg);
-#else
-	/* pci express 0 Rootpoint  Mode */
-	mfsdr(SDR0_PE0DLPSET, reg);
-	reg |= 0x00400000;
-	mtsdr(SDR0_PE0DLPSET, reg);
-#endif
-	/* pci express 1 Rootpoint  Mode */
-	mfsdr(SDR0_PE1DLPSET, reg);
-	reg |= 0x00400000;
-	mtsdr(SDR0_PE1DLPSET, reg);
-	/* pci express 2 Rootpoint  Mode */
-	mfsdr(SDR0_PE2DLPSET, reg);
-	reg |= 0x00400000;
-	mtsdr(SDR0_PE2DLPSET, reg);
-
-#if defined(CONFIG_STRESS)
-	/*
-	 * All this setting done by linux only needed by stress an charac. test
-	 * procedure
-	 * PCIe 1 Rootpoint PCIe2 Endpoint
-	 * PCIe 0 FIR Pre-emphasis Filter Coefficients & Transmit Driver Power Level
-	 */
-	for (i=0,disp=0; i<8; i++,disp+=3) {
-		mfsdr(SDR0_PE0HSSSET1L0+disp, reg);
-		reg |= 0x33000000;
-		mtsdr(SDR0_PE0HSSSET1L0+disp, reg);
-	}
-
-	/*PCIe 1 FIR Pre-emphasis Filter Coefficients & Transmit Driver Power Level */
-	for (i=0,disp=0; i<4; i++,disp+=3) {
-		mfsdr(SDR0_PE1HSSSET1L0+disp, reg);
-		reg |= 0x33000000;
-		mtsdr(SDR0_PE1HSSSET1L0+disp, reg);
-	}
-
-	/*PCIE 2 FIR Pre-emphasis Filter Coefficients & Transmit Driver Power Level */
-	for (i=0,disp=0; i<4; i++,disp+=3) {
-		mfsdr(SDR0_PE2HSSSET1L0+disp, reg);
-		reg |= 0x33000000;
-		mtsdr(SDR0_PE2HSSSET1L0+disp, reg);
-	}
-
-	reg = 0x21242222;
-	mtsdr(SDR0_PE2UTLSET1, reg);
-	reg = 0x11000000;
-	mtsdr(SDR0_PE2UTLSET2, reg);
-	/* pci express 1 Endpoint  Mode */
-	reg = 0x00004000;
-	mtsdr(SDR0_PE2DLPSET, reg);
-
-	mtsdr(SDR0_UART1, 0x2080005a);	/* patch for TG */
-#endif
-
-	return 0;
-}
-
 #ifdef CONFIG_POST
 /*
  * Returns 1 if keys pressed to start the power-on long-running tests
@@ -517,3 +448,8 @@ int post_hotkeys_pressed(void)
 	return (ctrlc());
 }
 #endif
+
+int board_eth_init(bd_t *bis)
+{
+	return pci_eth_init(bis);
+}

board/amcc/ocotea/ocotea.c

@@ -147,36 +147,48 @@ int board_early_init_f (void)
 	/*--------------------------------------------------------------------
 	 * Setup the interrupt controller polarities, triggers, etc.
 	 *-------------------------------------------------------------------*/
-	mtdcr (uic0sr, 0xffffffff);	/* clear all */
-	mtdcr (uic0er, 0x00000000);	/* disable all */
-	mtdcr (uic0cr, 0x00000009);	/* SMI & UIC1 crit are critical */
-	mtdcr (uic0pr, 0xfffffe13);	/* per ref-board manual */
-	mtdcr (uic0tr, 0x01c00008);	/* per ref-board manual */
-	mtdcr (uic0vr, 0x00000001);	/* int31 highest, base=0x000 */
-	mtdcr (uic0sr, 0xffffffff);	/* clear all */
-
+	/*
+	 * Because of the interrupt handling rework to handle 440GX interrupts
+	 * with the common code, we needed to change names of the UIC registers.
+	 * Here the new relationship:
+	 *
+	 * U-Boot name	440GX name
+	 * -----------------------
+	 * UIC0		UICB0
+	 * UIC1		UIC0
+	 * UIC2		UIC1
+	 * UIC3		UIC2
+	 */
 	mtdcr (uic1sr, 0xffffffff);	/* clear all */
 	mtdcr (uic1er, 0x00000000);	/* disable all */
-	mtdcr (uic1cr, 0x00000000);	/* all non-critical */
-	mtdcr (uic1pr, 0xffffe0ff);	/* per ref-board manual */
-	mtdcr (uic1tr, 0x00ffc000);	/* per ref-board manual */
+	mtdcr (uic1cr, 0x00000009);	/* SMI & UIC1 crit are critical */
+	mtdcr (uic1pr, 0xfffffe13);	/* per ref-board manual */
+	mtdcr (uic1tr, 0x01c00008);	/* per ref-board manual */
 	mtdcr (uic1vr, 0x00000001);	/* int31 highest, base=0x000 */
 	mtdcr (uic1sr, 0xffffffff);	/* clear all */
 
 	mtdcr (uic2sr, 0xffffffff);	/* clear all */
 	mtdcr (uic2er, 0x00000000);	/* disable all */
 	mtdcr (uic2cr, 0x00000000);	/* all non-critical */
-	mtdcr (uic2pr, 0xffffffff);	/* per ref-board manual */
-	mtdcr (uic2tr, 0x00ff8c0f);	/* per ref-board manual */
+	mtdcr (uic2pr, 0xffffe0ff);	/* per ref-board manual */
+	mtdcr (uic2tr, 0x00ffc000);	/* per ref-board manual */
 	mtdcr (uic2vr, 0x00000001);	/* int31 highest, base=0x000 */
 	mtdcr (uic2sr, 0xffffffff);	/* clear all */
 
-	mtdcr (uicb0sr, 0xfc000000); /* clear all */
-	mtdcr (uicb0er, 0x00000000); /* disable all */
-	mtdcr (uicb0cr, 0x00000000); /* all non-critical */
-	mtdcr (uicb0pr, 0xfc000000); /* */
-	mtdcr (uicb0tr, 0x00000000); /* */
-	mtdcr (uicb0vr, 0x00000001); /* */
+	mtdcr (uic3sr, 0xffffffff);	/* clear all */
+	mtdcr (uic3er, 0x00000000);	/* disable all */
+	mtdcr (uic3cr, 0x00000000);	/* all non-critical */
+	mtdcr (uic3pr, 0xffffffff);	/* per ref-board manual */
+	mtdcr (uic3tr, 0x00ff8c0f);	/* per ref-board manual */
+	mtdcr (uic3vr, 0x00000001);	/* int31 highest, base=0x000 */
+	mtdcr (uic3sr, 0xffffffff);	/* clear all */
+
+	mtdcr (uic0sr, 0xfc000000); /* clear all */
+	mtdcr (uic0er, 0x00000000); /* disable all */
+	mtdcr (uic0cr, 0x00000000); /* all non-critical */
+	mtdcr (uic0pr, 0xfc000000); /* */
+	mtdcr (uic0tr, 0x00000000); /* */
+	mtdcr (uic0vr, 0x00000001); /* */
 	mfsdr (sdr_mfr, mfr);
 	mfr &= ~SDR0_MFR_ECS_MASK;
 /*	mtsdr(sdr_mfr, mfr); */

board/amcc/redwood/Makefile

@@ -0,0 +1,50 @@
+#
+# (C) Copyright 2008
+# Feng Kan, Applied Micro Circuits Corp., fkan@amcc.com.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).a
+
+COBJS	= $(BOARD).o
+SOBJS	= init.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(AR) $(ARFLAGS) $@ $(OBJS)
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend *~
+
+#########################################################################
+
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################

board/amcc/redwood/config.mk

@@ -0,0 +1,42 @@
+#
+# (C) Copyright 2008
+# Feng Kan, Applied Micro Circuits Corp., fkan@amcc.com.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# AMCC 460SX Reference Platform (redwood) board
+#
+
+ifeq ($(ramsym),1)
+TEXT_BASE = 0x07FD0000
+else
+TEXT_BASE = 0xfffb0000
+endif
+
+PLATFORM_CPPFLAGS += -DCONFIG_440=1
+
+ifeq ($(debug),1)
+PLATFORM_CPPFLAGS += -DDEBUG
+endif
+
+ifeq ($(dbcr),1)
+PLATFORM_CPPFLAGS += -DCFG_INIT_DBCR=0x8cff0000
+endif

board/amcc/redwood/init.S

@@ -0,0 +1,77 @@
+/*
+ * (C) Copyright 2008
+ * Feng Kan, Applied Micro Circuits Corp., fkan@amcc.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <ppc_asm.tmpl>
+#include <config.h>
+#include <asm-ppc/mmu.h>
+
+/**************************************************************************
+ * TLB TABLE
+ *
+ * This table is used by the cpu boot code to setup the initial tlb
+ * entries. Rather than make broad assumptions in the cpu source tree,
+ * this table lets each board set things up however they like.
+ *
+ *  Pointer to the table is returned in r1
+ *
+ *************************************************************************/
+
+	.section .bootpg,"ax"
+	.globl tlbtab
+tlbtab:
+	tlbtab_start
+
+	/*
+	 * BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to use the
+	 * speed up boot process. It is patched after relocation to enable SA_I
+	 */
+	tlbentry(0xff000000, SZ_16M, 0xff000000, 4, AC_R|AC_W|AC_X|SA_G)
+
+	/*
+	 * TLB entries for SDRAM are not needed on this platform.
+	 * They are dynamically generated in the SPD DDR(2) detection
+	 * routine.
+	 */
+
+	/* Although 512 KB, map 256k at a time */
+	tlbentry(CFG_ISRAM_BASE, SZ_256K, 0x00000000, 4, AC_R|AC_W|AC_X|SA_I)
+	tlbentry(CFG_ISRAM_BASE + 0x40000, SZ_256K, 0x00040000, 4, AC_R|AC_W|AC_X|SA_I)
+
+	tlbentry(CFG_OPER_FLASH, SZ_16M, 0xE7000000, 4,AC_R|AC_W|AC_X|SA_G|SA_I)
+
+	/*
+	 * Peripheral base
+	 */
+	tlbentry(CFG_PERIPHERAL_BASE, SZ_16K, 0xEF600000, 4, AC_R|AC_W|SA_G|SA_I)
+
+	tlbentry(CFG_PCIE0_XCFGBASE,SZ_16M, 0x00000000, 0xC, AC_R|AC_W|SA_G|SA_I)
+	tlbentry(CFG_PCIE1_XCFGBASE,SZ_16M, 0x10000000, 0xC, AC_R|AC_W|SA_G|SA_I)
+	tlbentry(CFG_PCIE2_XCFGBASE,SZ_16M, 0x20000000, 0xC, AC_R|AC_W|SA_G|SA_I)
+
+	tlbentry(CFG_PCIE0_MEMBASE, SZ_256M, 0x00000000, 0xD, AC_R|AC_W|SA_G|SA_I)
+	tlbentry(CFG_PCIE1_MEMBASE, SZ_256M, 0x00000000, 0xE, AC_R|AC_W|SA_G|SA_I)
+
+	tlbentry(CFG_PCIE0_REGBASE, SZ_64K, 0x30000000, 0xC, AC_R|AC_W|SA_G|SA_I)
+	tlbentry(CFG_PCIE1_REGBASE, SZ_64K, 0x30010000, 0xC, AC_R|AC_W|SA_G|SA_I)
+	tlbentry(CFG_PCIE2_REGBASE, SZ_64K, 0x30020000, 0xC, AC_R|AC_W|SA_G|SA_I)
+	tlbtab_end

board/amcc/redwood/redwood.c

@@ -0,0 +1,456 @@
+/*
+ * This is the main board level file for the Redwood AMCC board.
+ *
+ * (C) Copyright 2008
+ * Feng Kan, Applied Micro Circuits Corp., fkan@amcc.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#include <common.h>
+#include "redwood.h"
+#include <ppc4xx.h>
+#include <asm/processor.h>
+#include <i2c.h>
+#include <asm-ppc/io.h>
+
+int compare_to_true(char *str);
+char *remove_l_w_space(char *in_str);
+char *remove_t_w_space(char *in_str);
+int get_console_port(void);
+
+static void early_init_EBC(void);
+static int bootdevice_selected(void);
+static void early_reinit_EBC(int);
+static void early_init_UIC(void);
+
+/*
+ * Define Boot devices
+ */
+#define BOOT_FROM_8BIT_SRAM			0x00
+#define BOOT_FROM_16BIT_SRAM			0x01
+#define BOOT_FROM_32BIT_SRAM			0x02
+#define BOOT_FROM_8BIT_NAND			0x03
+#define BOOT_FROM_16BIT_NOR			0x04
+#define BOOT_DEVICE_UNKNOWN			0xff
+
+/*
+ * EBC Devices Characteristics
+ *   Peripheral Bank Access Parameters       -   EBC_BxAP
+ *   Peripheral Bank Configuration Register  -   EBC_BxCR
+ */
+
+/*
+ * 8 bit width SRAM
+ * BU Value
+ * BxAP : 0x03800000  - 0 00000111 0 00 00 00 00 00 000 0 0 0 0 00000
+ * B0CR : 0xff098000  - BAS = ff0 - 100 11 00 0000000000000
+ * B2CR : 0xe7098000  - BAS = e70 - 100 11 00 0000000000000
+ */
+#define EBC_BXAP_8BIT_SRAM					\
+	EBC_BXAP_BME_DISABLED   | EBC_BXAP_TWT_ENCODE(7)  |	\
+	EBC_BXAP_BCE_DISABLE    | EBC_BXAP_BCT_2TRANS     |	\
+	EBC_BXAP_CSN_ENCODE(0)  | EBC_BXAP_OEN_ENCODE(0)  |	\
+	EBC_BXAP_WBN_ENCODE(0)  | EBC_BXAP_WBF_ENCODE(0)  |	\
+	EBC_BXAP_TH_ENCODE(0)   | EBC_BXAP_RE_DISABLED    |	\
+	EBC_BXAP_SOR_DELAYED    | EBC_BXAP_BEM_WRITEONLY  |	\
+	EBC_BXAP_PEN_DISABLED
+
+#define EBC_BXAP_16BIT_SRAM	EBC_BXAP_8BIT_SRAM
+#define EBC_BXAP_32BIT_SRAM	EBC_BXAP_8BIT_SRAM
+
+/*
+ * NAND flash
+ * BU Value
+ * BxAP : 0x048ff240  - 0 00000111 0 00 00 00 00 00 000 0 0 0 0 00000
+ * B0CR : 0xff09a000  - BAS = ff0 - 100 11 01 0000000000000
+ * B2CR : 0xe709a000  - BAS = e70 - 100 11 01 0000000000000
+*/
+#define EBC_BXAP_NAND						\
+	EBC_BXAP_BME_DISABLED   | EBC_BXAP_TWT_ENCODE(7)  |	\
+	EBC_BXAP_BCE_DISABLE    | EBC_BXAP_BCT_2TRANS     |	\
+	EBC_BXAP_CSN_ENCODE(0)  | EBC_BXAP_OEN_ENCODE(0)  |	\
+	EBC_BXAP_WBN_ENCODE(0)  | EBC_BXAP_WBF_ENCODE(0)  |	\
+	EBC_BXAP_TH_ENCODE(0)   | EBC_BXAP_RE_DISABLED    |	\
+	EBC_BXAP_SOR_DELAYED    | EBC_BXAP_BEM_WRITEONLY  |	\
+	EBC_BXAP_PEN_DISABLED
+
+/*
+ * NOR flash
+ * BU Value
+ * BxAP : 0x048ff240  - 0 00000111 0 00 00 00 00 00 000 0 0 0 0 00000
+ * B0CR : 0xff09a000  - BAS = ff0 - 100 11 01 0000000000000
+ * B2CR : 0xe709a000  - BAS = e70 - 100 11 01 0000000000000
+*/
+#define EBC_BXAP_NOR						\
+	EBC_BXAP_BME_DISABLED   | EBC_BXAP_TWT_ENCODE(7)  |	\
+	EBC_BXAP_BCE_DISABLE    | EBC_BXAP_BCT_2TRANS     |	\
+	EBC_BXAP_CSN_ENCODE(0)  | EBC_BXAP_OEN_ENCODE(0)  |	\
+	EBC_BXAP_WBN_ENCODE(0)  | EBC_BXAP_WBF_ENCODE(0)  |	\
+	EBC_BXAP_TH_ENCODE(0)   | EBC_BXAP_RE_DISABLED    |	\
+	EBC_BXAP_SOR_DELAYED    | EBC_BXAP_BEM_WRITEONLY  |	\
+	EBC_BXAP_PEN_DISABLED
+
+/*
+ * FPGA
+ * BU value :
+ * B1AP = 0x05895240  - 0 00001011 0 00 10 01 01 01 001 0 0 1 0 00000
+ * B1CR = 0xe201a000  - BAS = e20 - 000 11 01 00000000000000
+ */
+#define EBC_BXAP_FPGA						\
+	EBC_BXAP_BME_DISABLED   | EBC_BXAP_TWT_ENCODE(11) |	\
+	EBC_BXAP_BCE_DISABLE    | EBC_BXAP_BCT_2TRANS     |	\
+	EBC_BXAP_CSN_ENCODE(10) | EBC_BXAP_OEN_ENCODE(1)  |	\
+	EBC_BXAP_WBN_ENCODE(1)  | EBC_BXAP_WBF_ENCODE(1)  |	\
+	EBC_BXAP_TH_ENCODE(1)   | EBC_BXAP_RE_DISABLED    |	\
+	EBC_BXAP_SOR_DELAYED    | EBC_BXAP_BEM_RW         |	\
+	EBC_BXAP_PEN_DISABLED
+
+#define EBC_BXCR_8BIT_SRAM_CS0						\
+	EBC_BXCR_BAS_ENCODE(0xFFE00000) | EBC_BXCR_BS_1MB           |	\
+	EBC_BXCR_BU_RW                  | EBC_BXCR_BW_8BIT
+
+#define EBC_BXCR_32BIT_SRAM_CS0						\
+	EBC_BXCR_BAS_ENCODE(0xFFC00000) | EBC_BXCR_BS_1MB           |	\
+	EBC_BXCR_BU_RW                  | EBC_BXCR_BW_32BIT
+
+#define EBC_BXCR_NAND_CS0						\
+	EBC_BXCR_BAS_ENCODE(0xFF000000) | EBC_BXCR_BS_16MB          |	\
+	EBC_BXCR_BU_RW                  | EBC_BXCR_BW_8BIT
+
+#define EBC_BXCR_16BIT_SRAM_CS0						\
+	EBC_BXCR_BAS_ENCODE(0xFFE00000) | EBC_BXCR_BS_2MB           |	\
+	EBC_BXCR_BU_RW                  | EBC_BXCR_BW_16BIT
+
+#define EBC_BXCR_NOR_CS0						\
+	EBC_BXCR_BAS_ENCODE(0xFF000000) | EBC_BXCR_BS_16MB          |	\
+	EBC_BXCR_BU_RW                  | EBC_BXCR_BW_16BIT
+
+#define EBC_BXCR_NOR_CS1						\
+	EBC_BXCR_BAS_ENCODE(0xE0000000) | EBC_BXCR_BS_128MB         |	\
+	EBC_BXCR_BU_RW                  | EBC_BXCR_BW_16BIT
+
+#define EBC_BXCR_NAND_CS1						\
+	EBC_BXCR_BAS_ENCODE(0xE0000000) | EBC_BXCR_BS_128MB         |	\
+	EBC_BXCR_BU_RW                  | EBC_BXCR_BW_8BIT
+
+#define EBC_BXCR_NAND_CS2						\
+	EBC_BXCR_BAS_ENCODE(0xC0000000) | EBC_BXCR_BS_128MB         |	\
+	EBC_BXCR_BU_RW                  | EBC_BXCR_BW_8BIT
+
+#define EBC_BXCR_SRAM_CS2						\
+	EBC_BXCR_BAS_ENCODE(0xC0000000) | EBC_BXCR_BS_4MB           |	\
+	EBC_BXCR_BU_RW                  | EBC_BXCR_BW_32BIT
+
+#define EBC_BXCR_LARGE_FLASH_CS2					\
+	EBC_BXCR_BAS_ENCODE(0xE7000000) | EBC_BXCR_BS_16MB          |	\
+	EBC_BXCR_BU_RW                  | EBC_BXCR_BW_16BIT
+
+#define EBC_BXCR_FPGA_CS3						\
+	EBC_BXCR_BAS_ENCODE(0xE2000000) | EBC_BXCR_BS_1MB           |	\
+	EBC_BXCR_BU_RW                  | EBC_BXCR_BW_16BIT
+
+/*****************************************************************************
+ * UBOOT initiated board specific function calls
+ ****************************************************************************/
+
+int board_early_init_f(void)
+{
+	int computed_boot_device = BOOT_DEVICE_UNKNOWN;
+
+	/*
+	 * Initialise EBC
+	 */
+	early_init_EBC();
+
+	/*
+	 * Determine which boot device was selected
+	 */
+	computed_boot_device = bootdevice_selected();
+
+	/*
+	 * Reinit EBC based on selected boot device
+	 */
+	early_reinit_EBC(computed_boot_device);
+
+	/*
+	 * Setup for UIC on 460SX redwood board
+	 */
+	early_init_UIC();
+
+	return 0;
+}
+
+int checkboard(void)
+{
+	char *s = getenv("serial#");
+
+	printf("Board: Redwood - AMCC 460SX Reference Board");
+	if (s != NULL) {
+		puts(", serial# ");
+		puts(s);
+	}
+	putc('\n');
+
+	return 0;
+}
+
+static void early_init_EBC(void)
+{
+	/*
+	 * Initialize EBC CONFIG -
+	 * Keep the Default value, but the bit PDT which has to be set to 1 ?TBC
+	 * default value :
+	 *      0x07C00000 - 0 0 000 1 1 1 1 1 0000 0 00000 000000000000
+	 */
+	mtebc(xbcfg, EBC_CFG_LE_UNLOCK |
+	      EBC_CFG_PTD_ENABLE |
+	      EBC_CFG_RTC_16PERCLK |
+	      EBC_CFG_ATC_PREVIOUS |
+	      EBC_CFG_DTC_PREVIOUS |
+	      EBC_CFG_CTC_PREVIOUS |
+	      EBC_CFG_OEO_PREVIOUS |
+	      EBC_CFG_EMC_DEFAULT | EBC_CFG_PME_DISABLE | EBC_CFG_PR_16);
+
+	/*
+	 * PART 1 : Initialize EBC Bank 3
+	 * ==============================
+	 * Bank1 is always associated to the EPLD.
+	 * It has to be initialized prior to other banks settings computation
+	 * since some board registers values may be needed to determine the
+	 * boot type
+	 */
+	mtebc(pb1ap, EBC_BXAP_FPGA);
+	mtebc(pb1cr, EBC_BXCR_FPGA_CS3);
+
+}
+
+static int bootdevice_selected(void)
+{
+	unsigned long sdr0_pinstp;
+	unsigned long bootstrap_settings;
+	int computed_boot_device = BOOT_DEVICE_UNKNOWN;
+
+	/*
+	 *  Determine which boot device was selected
+	 *  =================================================
+	 *
+	 *  Read Pin Strap Register in PPC460SX
+	 *  Result can either be :
+	 *   - Boot strap = boot from EBC 8bits     => Small Flash
+	 *   - Boot strap = boot from PCI
+	 *   - Boot strap = IIC
+	 *  In case of boot from IIC, read Serial Device Strap Register1
+	 *
+	 *  Result can either be :
+	 *   - Boot from EBC  - EBC Bus Width = 8bits    => Small Flash
+	 *   - Boot from EBC  - EBC Bus Width = 16bits   => Large Flash or SRAM
+	 *   - Boot from PCI
+	 */
+
+	/* Read Pin Strap Register in PPC460SX */
+	mfsdr(SDR0_PINSTP, sdr0_pinstp);
+	bootstrap_settings = sdr0_pinstp & SDR0_PSTRP0_BOOTSTRAP_MASK;
+
+	switch (bootstrap_settings) {
+	case SDR0_PSTRP0_BOOTSTRAP_SETTINGS0:
+		/*
+		 * Boot from SRAM, 8bit width
+		 */
+		computed_boot_device = BOOT_FROM_8BIT_SRAM;
+		break;
+	case SDR0_PSTRP0_BOOTSTRAP_SETTINGS1:
+		/*
+		 * Boot from SRAM, 32bit width
+		 */
+		computed_boot_device = BOOT_FROM_32BIT_SRAM;
+		break;
+	case SDR0_PSTRP0_BOOTSTRAP_SETTINGS2:
+		/*
+		 * Boot from NAND, 8bit width
+		 */
+		computed_boot_device = BOOT_FROM_8BIT_NAND;
+		break;
+	case SDR0_PSTRP0_BOOTSTRAP_SETTINGS4:
+		/*
+		 * Boot from SRAM, 16bit width
+		 * Boot setting in IIC EEPROM 0x50
+		 */
+		computed_boot_device = BOOT_FROM_16BIT_SRAM;
+		break;
+	case SDR0_PSTRP0_BOOTSTRAP_SETTINGS5:
+		/*
+		 * Boot from NOR, 16bit width
+		 * Boot setting in IIC EEPROM 0x54
+		 */
+		computed_boot_device = BOOT_FROM_16BIT_NOR;
+		break;
+	default:
+		/* should not be */
+		computed_boot_device = BOOT_DEVICE_UNKNOWN;
+		break;
+	}
+
+	return computed_boot_device;
+}
+
+static void early_reinit_EBC(int computed_boot_device)
+{
+	/*
+	 *  Compute EBC settings depending on selected boot device
+	 *  ======================================================
+	 *
+	 * Resulting EBC init will be among following configurations :
+	 *
+	 *  - Boot from EBC 8bits => boot from Small Flash selected
+	 *            EBC-CS0     = Small Flash
+	 *            EBC-CS2     = Large Flash and SRAM
+	 *
+	 *  - Boot from EBC 16bits => boot from Large Flash or SRAM
+	 *            EBC-CS0     = Large Flash or SRAM
+	 *            EBC-CS2     = Small Flash
+	 *
+	 *  - Boot from PCI
+	 *            EBC-CS0     = not initialized to avoid address contention
+	 *            EBC-CS2     = same as boot from Small Flash selected
+	 */
+
+	unsigned long ebc0_cs0_bxap_value = 0, ebc0_cs0_bxcr_value = 0;
+	unsigned long ebc0_cs1_bxap_value = 0, ebc0_cs1_bxcr_value = 0;
+	unsigned long ebc0_cs2_bxap_value = 0, ebc0_cs2_bxcr_value = 0;
+
+	switch (computed_boot_device) {
+		/*-------------------------------------------------------------------*/
+	case BOOT_FROM_8BIT_SRAM:
+		/*-------------------------------------------------------------------*/
+		ebc0_cs0_bxap_value = EBC_BXAP_8BIT_SRAM;
+		ebc0_cs0_bxcr_value = EBC_BXCR_8BIT_SRAM_CS0;
+		ebc0_cs1_bxap_value = EBC_BXAP_NOR;
+		ebc0_cs1_bxcr_value = EBC_BXCR_NOR_CS1;
+		ebc0_cs2_bxap_value = EBC_BXAP_NAND;
+		ebc0_cs2_bxcr_value = EBC_BXCR_NAND_CS2;
+		break;
+
+		/*-------------------------------------------------------------------*/
+	case BOOT_FROM_16BIT_SRAM:
+		/*-------------------------------------------------------------------*/
+		ebc0_cs0_bxap_value = EBC_BXAP_16BIT_SRAM;
+		ebc0_cs0_bxcr_value = EBC_BXCR_16BIT_SRAM_CS0;
+		ebc0_cs1_bxap_value = EBC_BXAP_NOR;
+		ebc0_cs1_bxcr_value = EBC_BXCR_NOR_CS1;
+		ebc0_cs2_bxap_value = EBC_BXAP_NAND;
+		ebc0_cs2_bxcr_value = EBC_BXCR_NAND_CS2;
+		break;
+
+		/*-------------------------------------------------------------------*/
+	case BOOT_FROM_32BIT_SRAM:
+		/*-------------------------------------------------------------------*/
+		ebc0_cs0_bxap_value = EBC_BXAP_32BIT_SRAM;
+		ebc0_cs0_bxcr_value = EBC_BXCR_32BIT_SRAM_CS0;
+		ebc0_cs1_bxap_value = EBC_BXAP_NOR;
+		ebc0_cs1_bxcr_value = EBC_BXCR_NOR_CS1;
+		ebc0_cs2_bxap_value = EBC_BXAP_NAND;
+		ebc0_cs2_bxcr_value = EBC_BXCR_NAND_CS2;
+		break;
+
+		/*-------------------------------------------------------------------*/
+	case BOOT_FROM_16BIT_NOR:
+		/*-------------------------------------------------------------------*/
+		ebc0_cs0_bxap_value = EBC_BXAP_NOR;
+		ebc0_cs0_bxcr_value = EBC_BXCR_NOR_CS0;
+		ebc0_cs1_bxap_value = EBC_BXAP_NAND;
+		ebc0_cs1_bxcr_value = EBC_BXCR_NAND_CS1;
+		ebc0_cs2_bxap_value = EBC_BXAP_32BIT_SRAM;
+		ebc0_cs2_bxcr_value = EBC_BXCR_SRAM_CS2;
+		break;
+
+		/*-------------------------------------------------------------------*/
+	case BOOT_FROM_8BIT_NAND:
+		/*-------------------------------------------------------------------*/
+		ebc0_cs0_bxap_value = EBC_BXAP_NAND;
+		ebc0_cs0_bxcr_value = EBC_BXCR_NAND_CS0;
+		ebc0_cs1_bxap_value = EBC_BXAP_NOR;
+		ebc0_cs1_bxcr_value = EBC_BXCR_NOR_CS1;
+		ebc0_cs2_bxap_value = EBC_BXAP_32BIT_SRAM;
+		ebc0_cs2_bxcr_value = EBC_BXCR_SRAM_CS2;
+		break;
+
+		/*-------------------------------------------------------------------*/
+	default:
+		/*-------------------------------------------------------------------*/
+		/* BOOT_DEVICE_UNKNOWN */
+		break;
+	}
+
+	mtebc(pb0ap, ebc0_cs0_bxap_value);
+	mtebc(pb0cr, ebc0_cs0_bxcr_value);
+	mtebc(pb1ap, ebc0_cs1_bxap_value);
+	mtebc(pb1cr, ebc0_cs1_bxcr_value);
+	mtebc(pb2ap, ebc0_cs2_bxap_value);
+	mtebc(pb2cr, ebc0_cs2_bxcr_value);
+}
+
+static void early_init_UIC(void)
+{
+	/*
+	 * Initialise UIC registers.  Clear all interrupts.  Disable all
+	 * interrupts.
+	 * Set critical interrupt values.  Set interrupt polarities.  Set
+	 * interrupt trigger levels.  Make bit 0 High  priority.  Clear all
+	 * interrupts again.
+	 */
+	mtdcr(uic3sr, 0xffffffff);	/* Clear all interrupts */
+	mtdcr(uic3er, 0x00000000);	/* disable all interrupts */
+	mtdcr(uic3cr, 0x00000000);	/* Set Critical / Non Critical
+					 * interrupts */
+	mtdcr(uic3pr, 0xffffffff);	/* Set Interrupt Polarities */
+	mtdcr(uic3tr, 0x001fffff);	/* Set Interrupt Trigger Levels */
+	mtdcr(uic3vr, 0x00000000);	/* int31 highest, base=0x000 */
+	mtdcr(uic3sr, 0xffffffff);	/* clear all  interrupts */
+
+	mtdcr(uic2sr, 0xffffffff);	/* Clear all interrupts */
+	mtdcr(uic2er, 0x00000000);	/* disable all interrupts */
+	mtdcr(uic2cr, 0x00000000);	/* Set Critical / Non Critical
+					 * interrupts */
+	mtdcr(uic2pr, 0xebebebff);	/* Set Interrupt Polarities */
+	mtdcr(uic2tr, 0x74747400);	/* Set Interrupt Trigger Levels */
+	mtdcr(uic2vr, 0x00000000);	/* int31 highest, base=0x000 */
+	mtdcr(uic2sr, 0xffffffff);	/* clear all interrupts */
+
+	mtdcr(uic1sr, 0xffffffff);	/* Clear all interrupts */
+	mtdcr(uic1er, 0x00000000);	/* disable all interrupts */
+	mtdcr(uic1cr, 0x00000000);	/* Set Critical / Non Critical
+					 * interrupts */
+	mtdcr(uic1pr, 0xffffffff);	/* Set Interrupt Polarities */
+	mtdcr(uic1tr, 0x001fc0ff);	/* Set Interrupt Trigger Levels */
+	mtdcr(uic1vr, 0x00000000);	/* int31 highest, base=0x000 */
+	mtdcr(uic1sr, 0xffffffff);	/* clear all interrupts */
+
+	mtdcr(uic0sr, 0xffffffff);	/* Clear all interrupts */
+	mtdcr(uic0er, 0x00000000);	/* disable all interrupts excepted
+					 * cascade to be checked */
+	mtdcr(uic0cr, 0x00104001);	/* Set Critical / Non Critical
+					 * interrupts */
+	mtdcr(uic0pr, 0xffffffff);	/* Set Interrupt Polarities */
+	mtdcr(uic0tr, 0x000f003c);	/* Set Interrupt Trigger Levels */
+	mtdcr(uic0vr, 0x00000000);	/* int31 highest, base=0x000 */
+	mtdcr(uic0sr, 0xffffffff);	/* clear all interrupts */
+
+}

board/amcc/redwood/redwood.h

@@ -0,0 +1,50 @@
+/*
+ * (C) Copyright 2008
+ * Feng Kan, Applied Micro Circuit Corp., fkan@amcc.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __REDWOOD_H_
+#define __REDWOOD_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*----------------------------------------------------------------------------+
+| Defines
++----------------------------------------------------------------------------*/
+/* Pin Straps Reg */
+#define SDR0_PSTRP0			0x0040
+#define SDR0_PSTRP0_BOOTSTRAP_MASK	0xE0000000	/* Strap Bits */
+
+#define SDR0_PSTRP0_BOOTSTRAP_SETTINGS0	0x00000000	/* Default strap settings 0 */
+#define SDR0_PSTRP0_BOOTSTRAP_SETTINGS1	0x20000000	/* Default strap settings 1 */
+#define SDR0_PSTRP0_BOOTSTRAP_SETTINGS2	0x40000000	/* Default strap settings 2 */
+#define SDR0_PSTRP0_BOOTSTRAP_SETTINGS3	0x60000000	/* Default strap settings 3 */
+#define SDR0_PSTRP0_BOOTSTRAP_SETTINGS4	0x80000000	/* Default strap settings 4 */
+#define SDR0_PSTRP0_BOOTSTRAP_SETTINGS5	0xA0000000	/* Default strap settings 5 */
+#define SDR0_PSTRP0_BOOTSTRAP_SETTINGS6	0xC0000000	/* Default strap settings 6 */
+#define SDR0_PSTRP0_BOOTSTRAP_SETTINGS7	0xE0000000	/* Default strap settings 7 */
+
+#ifdef __cplusplus
+}
+#endif
+#endif				/* __REDWOOD_H_ */

board/amcc/redwood/u-boot.lds

@@ -1,5 +1,5 @@
 /*
- * (C) Copyright 2000
+ * (C) Copyright 2004
  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  *
  * See file CREDITS for list of people who contributed to this
@@ -22,10 +22,21 @@
  */
 
 OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
 /* Do we need any of these for elf?
    __DYNAMIC = 0;    */
 SECTIONS
 {
+  .resetvec 0xFFFFFFFC :
+  {
+    *(.resetvec)
+  } = 0xffff
+
+  .bootpg 0xFFFFF000 :
+  {
+    cpu/ppc4xx/start.o	(.bootpg)
+  } = 0xffff
+
   /* Read-only sections, merged into text segment: */
   . = + SIZEOF_HEADERS;
   .interp : { *(.interp) }
@@ -55,19 +66,11 @@ SECTIONS
     /* WARNING - the following is hand-optimized to fit within	*/
     /* the sector layout of our flash chips!	XXX FIXME XXX	*/
 
-    cpu/mpc8xx/start.o		(.text)
-    common/dlmalloc.o		(.text)
-    lib_ppc/ppcstring.o		(.text)
-    lib_generic/vsprintf.o	(.text)
-    lib_generic/crc32.o		(.text)
-    lib_generic/zlib.o		(.text)
-    lib_generic/ctype.o		(.text)
-    lib_generic/string.o	(.text)
-    lib_ppc/extable.o		(.text)
-    lib_ppc/kgdb.o		(.text)
+    cpu/ppc4xx/start.o		(.text)
+    board/amcc/redwood/init.o	(.text)
 
-  . = env_offset;
-    common/environment.o(.text)
+/*    . = env_offset;*/
+/*    common/environment.o(.text)*/
 
     *(.text)
     *(.fixup)
@@ -132,7 +135,7 @@ SECTIONS
   __init_end = .;
 
   __bss_start = .;
-  .bss (NOLOAD)       :
+  .bss       :
   {
    *(.sbss) *(.scommon)
    *(.dynbss)

board/amcc/sequoia/sequoia.c

@@ -25,12 +25,11 @@
 #include <common.h>
 #include <libfdt.h>
 #include <fdt_support.h>
-#include <ppc440.h>
+#include <ppc4xx.h>
 #include <asm/gpio.h>
 #include <asm/processor.h>
 #include <asm/io.h>
 #include <asm/bitops.h>
-#include <asm/ppc4xx-intvec.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -340,7 +339,7 @@ int checkboard(void)
  */
 void sequoia_pci_fixup_irq(struct pci_controller *hose, pci_dev_t dev)
 {
-	pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE, VECNUM_EIR2);
+	pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE, VECNUM_EIRQ2);
 }
 #endif
 

board/amcc/taihu/taihu.c

@@ -28,6 +28,7 @@
 #include <asm/processor.h>
 #include <asm/io.h>
 #include <spi.h>
+#include <netdev.h>
 #include <asm/gpio.h>
 
 extern int lcd_init(void);
@@ -200,3 +201,8 @@ int pci_pre_init(struct pci_controller *hose)
 	return 1;
 }
 #endif /* CONFIG_PCI */
+
+int board_eth_init(bd_t *bis)
+{
+	return pci_eth_init(bis);
+}

board/amcc/taishan/taishan.c

@@ -27,6 +27,7 @@
 #include <asm/processor.h>
 #include <spd_sdram.h>
 #include <ppc4xx_enet.h>
+#include <netdev.h>
 
 #ifdef CFG_INIT_SHOW_RESET_REG
 void show_reset_reg(void);
@@ -119,36 +120,48 @@ int board_early_init_f (void)
 	/*--------------------------------------------------------------------
 	 * Setup the interrupt controller polarities, triggers, etc.
 	 *-------------------------------------------------------------------*/
-	mtdcr (uic0sr, 0xffffffff);	/* clear all */
-	mtdcr (uic0er, 0x00000000);	/* disable all */
-	mtdcr (uic0cr, 0x00000009);	/* SMI & UIC1 crit are critical */
-	mtdcr (uic0pr, 0xfffffe13);	/* per ref-board manual */
-	mtdcr (uic0tr, 0x01c00008);	/* per ref-board manual */
-	mtdcr (uic0vr, 0x00000001);	/* int31 highest, base=0x000 */
-	mtdcr (uic0sr, 0xffffffff);	/* clear all */
-
+	/*
+	 * Because of the interrupt handling rework to handle 440GX interrupts
+	 * with the common code, we needed to change names of the UIC registers.
+	 * Here the new relationship:
+	 *
+	 * U-Boot name	440GX name
+	 * -----------------------
+	 * UIC0		UICB0
+	 * UIC1		UIC0
+	 * UIC2		UIC1
+	 * UIC3		UIC2
+	 */
 	mtdcr (uic1sr, 0xffffffff);	/* clear all */
 	mtdcr (uic1er, 0x00000000);	/* disable all */
-	mtdcr (uic1cr, 0x00000000);	/* all non-critical */
-	mtdcr (uic1pr, 0xffffe0ff);	/* per ref-board manual */
-	mtdcr (uic1tr, 0x00ffc000);	/* per ref-board manual */
+	mtdcr (uic1cr, 0x00000009);	/* SMI & UIC1 crit are critical */
+	mtdcr (uic1pr, 0xfffffe13);	/* per ref-board manual */
+	mtdcr (uic1tr, 0x01c00008);	/* per ref-board manual */
 	mtdcr (uic1vr, 0x00000001);	/* int31 highest, base=0x000 */
 	mtdcr (uic1sr, 0xffffffff);	/* clear all */
 
 	mtdcr (uic2sr, 0xffffffff);	/* clear all */
 	mtdcr (uic2er, 0x00000000);	/* disable all */
 	mtdcr (uic2cr, 0x00000000);	/* all non-critical */
-	mtdcr (uic2pr, 0xffffffff);	/* per ref-board manual */
-	mtdcr (uic2tr, 0x00ff8c0f);	/* per ref-board manual */
+	mtdcr (uic2pr, 0xffffe0ff);	/* per ref-board manual */
+	mtdcr (uic2tr, 0x00ffc000);	/* per ref-board manual */
 	mtdcr (uic2vr, 0x00000001);	/* int31 highest, base=0x000 */
 	mtdcr (uic2sr, 0xffffffff);	/* clear all */
 
-	mtdcr (uicb0sr, 0xfc000000);	/* clear all */
-	mtdcr (uicb0er, 0x00000000);	/* disable all */
-	mtdcr (uicb0cr, 0x00000000);	/* all non-critical */
-	mtdcr (uicb0pr, 0xfc000000);	/* */
-	mtdcr (uicb0tr, 0x00000000);	/* */
-	mtdcr (uicb0vr, 0x00000001);	/* */
+	mtdcr (uic3sr, 0xffffffff);	/* clear all */
+	mtdcr (uic3er, 0x00000000);	/* disable all */
+	mtdcr (uic3cr, 0x00000000);	/* all non-critical */
+	mtdcr (uic3pr, 0xffffffff);	/* per ref-board manual */
+	mtdcr (uic3tr, 0x00ff8c0f);	/* per ref-board manual */
+	mtdcr (uic3vr, 0x00000001);	/* int31 highest, base=0x000 */
+	mtdcr (uic3sr, 0xffffffff);	/* clear all */
+
+	mtdcr (uic0sr, 0xfc000000);	/* clear all */
+	mtdcr (uic0er, 0x00000000);	/* disable all */
+	mtdcr (uic0cr, 0x00000000);	/* all non-critical */
+	mtdcr (uic0pr, 0xfc000000);	/* */
+	mtdcr (uic0tr, 0x00000000);	/* */
+	mtdcr (uic0vr, 0x00000001);	/* */
 
 	/* Enable two GPIO 10~11 and TraceA signal */
 	mfsdr(sdr_pfc0,reg);
@@ -299,3 +312,8 @@ int post_hotkeys_pressed(void)
 	return (ctrlc());
 }
 #endif
+
+int board_eth_init(bd_t *bis)
+{
+	return pci_eth_init(bis);
+}

board/amcc/yucca/yucca.c

@@ -28,6 +28,7 @@
 #include <common.h>
 #include <ppc4xx.h>
 #include <i2c.h>
+#include <netdev.h>
 #include <asm/processor.h>
 #include <asm/io.h>
 #include <asm/4xx_pcie.h>
@@ -677,7 +678,7 @@ int is_pci_host(struct pci_controller *hose)
 	return 1;
 }
 
-int yucca_pcie_card_present(int port)
+static int yucca_pcie_card_present(int port)
 {
 	u16 reg;
 
@@ -879,10 +880,6 @@ void pcie_setup_hoses(int busno)
 int misc_init_f (void)
 {
 	uint reg;
-#if defined(CONFIG_STRESS)
-	uint i ;
-	uint disp;
-#endif
 
 	out16(FPGA_REG10, (in16(FPGA_REG10) &
 			~(FPGA_REG10_AUTO_NEG_DIS|FPGA_REG10_RESET_ETH)) |
@@ -897,67 +894,23 @@ int misc_init_f (void)
 
 	/* minimal init for PCIe */
 	/* pci express 0 Endpoint Mode */
-	mfsdr(SDR0_PE0DLPSET, reg);
+	mfsdr(SDRN_PESDR_DLPSET(0), reg);
 	reg &= (~0x00400000);
-	mtsdr(SDR0_PE0DLPSET, reg);
+	mtsdr(SDRN_PESDR_DLPSET(0), reg);
 	/* pci express 1 Rootpoint  Mode */
-	mfsdr(SDR0_PE1DLPSET, reg);
+	mfsdr(SDRN_PESDR_DLPSET(1), reg);
 	reg |= 0x00400000;
-	mtsdr(SDR0_PE1DLPSET, reg);
+	mtsdr(SDRN_PESDR_DLPSET(1), reg);
 	/* pci express 2 Rootpoint  Mode */
-	mfsdr(SDR0_PE2DLPSET, reg);
+	mfsdr(SDRN_PESDR_DLPSET(2), reg);
 	reg |= 0x00400000;
-	mtsdr(SDR0_PE2DLPSET, reg);
+	mtsdr(SDRN_PESDR_DLPSET(2), reg);
 
 	out16(FPGA_REG1C,(in16 (FPGA_REG1C) &
 				~FPGA_REG1C_PE0_ROOTPOINT &
 				~FPGA_REG1C_PE1_ENDPOINT  &
 				~FPGA_REG1C_PE2_ENDPOINT));
 
-#if defined(CONFIG_STRESS)
-	/*
-	 * all this setting done by linux only needed by stress an charac. test
-	 * procedure
-	 * PCIe 1 Rootpoint PCIe2 Endpoint
-	 * PCIe 0 FIR Pre-emphasis Filter Coefficients & Transmit Driver
-	 * Power Level
-	 */
-	for (i = 0, disp = 0; i < 8; i++, disp += 3) {
-		mfsdr(SDR0_PE0HSSSET1L0 + disp, reg);
-		reg |= 0x33000000;
-		mtsdr(SDR0_PE0HSSSET1L0 + disp, reg);
-	}
-
-	/*
-	 * PCIe 1 FIR Pre-emphasis Filter Coefficients & Transmit Driver
-	 * Power Level
-	 */
-	for (i = 0, disp = 0; i < 4; i++, disp += 3) {
-		mfsdr(SDR0_PE1HSSSET1L0 + disp, reg);
-		reg |= 0x33000000;
-		mtsdr(SDR0_PE1HSSSET1L0 + disp, reg);
-	}
-
-	/*
-	 * PCIE 2 FIR Pre-emphasis Filter Coefficients & Transmit Driver
-	 * Power Level
-	 */
-	for (i = 0, disp = 0; i < 4; i++, disp += 3) {
-		mfsdr(SDR0_PE2HSSSET1L0 + disp, reg);
-		reg |= 0x33000000;
-		mtsdr(SDR0_PE2HSSSET1L0 + disp, reg);
-	}
-
-	reg = 0x21242222;
-	mtsdr(SDR0_PE2UTLSET1, reg);
-	reg = 0x11000000;
-	mtsdr(SDR0_PE2UTLSET2, reg);
-	/* pci express 1 Endpoint  Mode */
-	reg = 0x00004000;
-	mtsdr(SDR0_PE2DLPSET, reg);
-
-	mtsdr(SDR0_UART1, 0x2080005a);	/* patch for TG */
-#endif
 	return 0;
 }
 
@@ -1000,3 +953,8 @@ int onboard_pci_arbiter_selected(int core_pci)
 #endif
 	return (BOARD_OPTION_NOT_SELECTED);
 }
+
+int board_eth_init(bd_t *bis)
+{
+	return pci_eth_init(bis);
+}

board/amirix/ap1000/ap1000.c

@@ -23,6 +23,7 @@
 
 #include <common.h>
 #include <command.h>
+#include <netdev.h>
 #include <asm/processor.h>
 
 #include "powerspan.h"
@@ -697,3 +698,9 @@ U_BOOT_CMD (swrecon, 1, 0, do_swreconfig,
 	    "swrecon - trigger a board reconfigure to the software selected configuration\n",
 	    "\n"
 	    "    - trigger a board reconfigure to the software selected configuration\n");
+
+int board_eth_init(bd_t *bis)
+{
+	return pci_eth_init(bis);
+}
+

board/ap325rxa/Makefile

@@ -0,0 +1,51 @@
+#########################################################################
+#
+# Copyright (C) 2008 Renesas Solutions Corp.
+# Copyright (C) 2008 Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>
+#
+# board/ap325rxa/Makefile
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).a
+
+COBJS	:= ap325rxa.o cpld-ap325rxa.o
+SOBJS	:= lowlevel_init.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################

board/ap325rxa/ap325rxa.c

@@ -0,0 +1,162 @@
+/*
+ * Copyright (C) 2008 Renesas Solutions Corp.
+ * Copyright (C) 2008 Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/processor.h>
+
+/* PRI control register */
+#define PRPRICR5	0xFF800048 /* LMB */
+#define PRPRICR5_D	0x2a
+
+/* FPGA control */
+#define FPGA_NAND_CTL	0xB410020C
+#define FPGA_NAND_RST	0x0008
+#define FPGA_NAND_INIT	0x0000
+#define FPGA_NAND_RST_WAIT	10000
+
+/* I/O port data */
+#define PACR_D	0x0000
+#define PBCR_D	0x0000
+#define PCCR_D	0x1000
+#define PDCR_D	0x0000
+#define PECR_D	0x0410
+#define PFCR_D	0xffff
+#define PGCR_D	0x0000
+#define PHCR_D	0x5011
+#define PJCR_D	0x4400
+#define PKCR_D	0x7c00
+#define PLCR_D	0x0000
+#define PMCR_D	0x0000
+#define PNCR_D	0x0000
+#define PQCR_D	0x0000
+#define PRCR_D	0x0000
+#define PSCR_D	0x0000
+#define PTCR_D	0x0010
+#define PUCR_D	0x0fff
+#define PVCR_D	0xffff
+#define PWCR_D	0x0000
+#define PXCR_D	0x7500
+#define PYCR_D	0x0000
+#define PZCR_D	0x5540
+
+/* Pin Function Controler data */
+#define PSELA_D	0x1410
+#define PSELB_D	0x0140
+#define PSELC_D	0x0000
+#define PSELD_D	0x0400
+
+/* I/O Buffer Hi-Z data */
+#define	HIZCRA_D	0x0000
+#define HIZCRB_D	0x1000
+#define HIZCRC_D	0x0000
+#define HIZCRD_D	0x0000
+
+/* Module select reg data */
+#define MSELCRA_D	0x0014
+#define MSELCRB_D	0x0018
+
+/* Module Stop reg Data */
+#define MSTPCR2_D	0xFFD9F280
+
+/* CPLD loader */
+extern void init_cpld(void);
+
+int checkboard(void)
+{
+	puts("BOARD: AP325RXA\n");
+	return 0;
+}
+
+int board_init(void)
+{
+	/* Pin Function Controler Init */
+	outw(PSELA_D, PSELA);
+	outw(PSELB_D, PSELB);
+	outw(PSELC_D, PSELC);
+	outw(PSELD_D, PSELD);
+
+	/* I/O Buffer Hi-Z Init */
+	outw(HIZCRA_D, HIZCRA);
+	outw(HIZCRB_D, HIZCRB);
+	outw(HIZCRC_D, HIZCRC);
+	outw(HIZCRD_D, HIZCRD);
+
+	/* Module select reg Init */
+	outw(MSELCRA_D, MSELCRA);
+	outw(MSELCRB_D, MSELCRB);
+
+	/* Module Stop reg Init */
+	outl(MSTPCR2_D, MSTPCR2);
+
+	/* I/O ports */
+	outw(PACR_D, PACR);
+	outw(PBCR_D, PBCR);
+	outw(PCCR_D, PCCR);
+	outw(PDCR_D, PDCR);
+	outw(PECR_D, PECR);
+	outw(PFCR_D, PFCR);
+	outw(PGCR_D, PGCR);
+	outw(PHCR_D, PHCR);
+	outw(PJCR_D, PJCR);
+	outw(PKCR_D, PKCR);
+	outw(PLCR_D, PLCR);
+	outw(PMCR_D, PMCR);
+	outw(PNCR_D, PNCR);
+	outw(PQCR_D, PQCR);
+	outw(PRCR_D, PRCR);
+	outw(PSCR_D, PSCR);
+	outw(PTCR_D, PTCR);
+	outw(PUCR_D, PUCR);
+	outw(PVCR_D, PVCR);
+	outw(PWCR_D, PWCR);
+	outw(PXCR_D, PXCR);
+	outw(PYCR_D, PYCR);
+	outw(PZCR_D, PZCR);
+
+	/* PRI control register Init */
+	outl(PRPRICR5_D, PRPRICR5);
+
+	/* cpld init */
+	init_cpld();
+
+	return 0;
+}
+
+int dram_init(void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+
+	gd->bd->bi_memstart = CFG_SDRAM_BASE;
+	gd->bd->bi_memsize = CFG_SDRAM_SIZE;
+	printf("DRAM:  %dMB\n", CFG_SDRAM_SIZE / (1024 * 1024));
+	return 0;
+}
+
+void led_set_state(unsigned short value)
+{
+}
+
+void ide_set_reset(int idereset)
+{
+	outw(FPGA_NAND_RST, FPGA_NAND_CTL);	/* NAND RESET */
+	udelay(FPGA_NAND_RST_WAIT);
+	outw(FPGA_NAND_INIT, FPGA_NAND_CTL);
+}

board/ap325rxa/config.mk

@@ -0,0 +1,26 @@
+#
+# Copyright (C) 2007
+# Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+
+#
+# TEXT_BASE refers to image _after_ relocation.
+#
+# NOTE: Must match value used in u-boot.lds (in this directory).
+#
+
+TEXT_BASE = 0x8FFC0000

board/ap325rxa/cpld-ap325rxa.c

@@ -0,0 +1,206 @@
+/***************************************************************
+ * Project:
+ *	  CPLD SlaveSerial Configuration via embedded microprocessor.
+ *
+ * Copyright info:
+ *
+ *	  This is free software; you can redistribute it and/or modify
+ *	  it as you like.
+ *
+ *	  This program is distributed in the hope that it will be useful,
+ *	  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *	  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ *
+ * Description:
+ *
+ *      This is the main source file that will allow a microprocessor
+ *      to configure Xilinx Virtex, Virtex-E, Virtex-EM, Virtex-II,
+ *      and Spartan-II devices via the SlaveSerial Configuration Mode.
+ *      This code is discussed in Xilinx Application Note, XAPP502.
+ *
+ * History:
+ *	  3-October-2001  MN/MP  - Created
+ *	  20-August-2008  Renesas Solutions - Modified to SH7723
+ ****************************************************************/
+
+#include <common.h>
+
+/* Serial */
+#define SCIF_BASE 0xffe00000 /* SCIF0 */
+#define SCSMR	(vu_short *)(SCIF_BASE + 0x00)
+#define SCBRR	(vu_char *)(SCIF_BASE + 0x04)
+#define SCSCR	(vu_short *)(SCIF_BASE + 0x08)
+#define SC_TDR	(vu_char *)(SCIF_BASE + 0x0C)
+#define SC_SR	(vu_short *)(SCIF_BASE + 0x10)
+#define SCFCR	(vu_short *)(SCIF_BASE + 0x18)
+#define	RFCR	(vu_long *)0xFE400020
+
+#define SCSCR_INIT		0x0038
+#define SCSCR_CLR		0x0000
+#define SCFCR_INIT		0x0006
+#define SCSMR_INIT		0x0080
+#define RFCR_CLR		0xA400
+#define SCI_TD_E		0x0020
+#define SCI_TDRE_CLEAR	0x00df
+
+#define BPS_SETTING_VALUE	1 /* 12.5MHz */
+#define WAIT_RFCR_COUNTER	500
+
+/* CPLD data size */
+#define CPLD_DATA_SIZE	169216
+
+/* out */
+#define CPLD_PFC_ADR	((vu_short *)0xA4050112)
+
+#define CPLD_PROG_ADR	((vu_char *)0xA4050132)
+#define CPLD_PROG_DAT	0x80
+
+/* in */
+#define CPLD_INIT_ADR	((vu_char *)0xA4050132)
+#define CPLD_INIT_DAT	0x40
+#define CPLD_DONE_ADR	((vu_char *)0xA4050132)
+#define CPLD_DONE_DAT	0x20
+
+#define	HIZCRB			((vu_short *)0xA405015A)
+
+/* data */
+#define CPLD_NOMAL_START	0xA0A80000
+#define CPLD_SAFE_START		0xA0AC0000
+#define MODE_SW				(vu_char *)0xA405012A
+
+static void init_cpld_loader(void)
+{
+
+	*SCSCR = SCSCR_CLR;
+	*SCFCR = SCFCR_INIT;
+	*SCSMR = SCSMR_INIT;
+
+	*SCBRR = BPS_SETTING_VALUE;
+
+	*RFCR = RFCR_CLR; /* Refresh counter clear */
+
+	while (*RFCR < WAIT_RFCR_COUNTER)
+		;
+
+	*SCFCR = 0x0; /* RTRG=00, TTRG=00 */
+				  /* MCE=0,TFRST=0,RFRST=0,LOOP=0 */
+	*SCSCR = SCSCR_INIT;
+}
+
+static int check_write_ready(void)
+{
+	u16 status = *SC_SR;
+	return status & SCI_TD_E;
+}
+
+static void write_cpld_data(char ch)
+{
+	while (!check_write_ready())
+		;
+
+	*SC_TDR = ch;
+	*SC_SR;
+	*SC_SR = SCI_TDRE_CLEAR;
+}
+
+static int delay(void)
+{
+	int i;
+	int c = 0;
+	for (i = 0; i < 200; i++) {
+		c = *(volatile int *)0xa0000000;
+	}
+	return c;
+}
+
+/***********************************************************************
+ *
+ * Function:     slave_serial
+ *
+ * Description:  Initiates SlaveSerial Configuration.
+ *               Calls ShiftDataOut() to output serial data
+ *
+ ***********************************************************************/
+static void slave_serial(void)
+{
+	int i;
+	unsigned char *flash;
+
+	*CPLD_PROG_ADR |= CPLD_PROG_DAT; /* PROGRAM_OE HIGH */
+	delay();
+
+	/*
+	 * Toggle Program Pin by Toggling Program_OE bit
+	 * This is accomplished by writing to the Program Register in the CPLD
+	 *
+	 * NOTE: The Program_OE bit should be driven high to bring the Virtex
+	 *      Program Pin low. Likewise, it should be driven low
+	 *      to bring the Virtex Program Pin to High-Z
+	 */
+
+	*CPLD_PROG_ADR &= ~CPLD_PROG_DAT; /* PROGRAM_OE LOW */
+	delay();
+
+	/*
+	 * Bring Program High-Z
+	 * (Drive Program_OE bit low to bring Virtex Program Pin to High-Z
+	 */
+
+	/* Program_OE bit Low brings the Virtex Program Pin to High Z: */
+	*CPLD_PROG_ADR |= CPLD_PROG_DAT; /* PROGRAM_OE HIGH */
+
+	while ((*CPLD_INIT_ADR & CPLD_INIT_DAT) == 0)
+		delay();
+
+	/* Begin Slave-Serial Configuration */
+	flash = (unsigned char *)CPLD_NOMAL_START;
+
+	for (i = 0; i < CPLD_DATA_SIZE; i++)
+		write_cpld_data(*flash++);
+}
+
+/***********************************************************************
+ *
+ * Function: check_done_bit
+ *
+ * Description: This function takes monitors the CPLD Input Register
+ * 		   by checking the status of the DONE bit in that Register.
+ *               By doing so, it monitors the Xilinx Virtex device's DONE
+ *               Pin to see if configuration bitstream has been properly
+ *               loaded
+ *
+ ***********************************************************************/
+static void check_done_bit(void)
+{
+	while (!(*CPLD_DONE_ADR & CPLD_DONE_DAT))
+		;
+}
+
+/***********************************************************************
+ *
+ * Function: init_cpld
+ *
+ * Description: Begins Slave Serial configuration of Xilinx FPGA
+ *
+ ***********************************************************************/
+void init_cpld(void)
+{
+	/* Init serial device */
+	init_cpld_loader();
+
+	if (*CPLD_DONE_ADR & CPLD_DONE_DAT)	/* Already DONE */
+		return;
+
+	*HIZCRB = 0x0000;
+	*CPLD_PFC_ADR = 0x7c00;			/* FPGA PROG = OUTPUT */
+
+	/* write CPLD data from NOR flash to device */
+	slave_serial();
+
+	/*
+	 * Monitor the DONE bit in the CPLD Input Register to see if
+	 * configuration successful
+	 */
+
+	check_done_bit();
+}

board/ap325rxa/lowlevel_init.S

@@ -0,0 +1,243 @@
+/*
+ * Copyright (C) 2008 Renesas Solutions Corp.
+ * Copyright (C) 2008 Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>
+ *
+ * board/ap325rxa/lowlevel_init.S
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <version.h>
+#include <asm/processor.h>
+
+/*
+ * Board specific low level init code, called _very_ early in the
+ * startup sequence. Relocation to SDRAM has not happened yet, no
+ * stack is available, bss section has not been initialised, etc.
+ *
+ * (Note: As no stack is available, no subroutines can be called...).
+ */
+
+	.global	lowlevel_init
+
+	.text
+	.align	2
+
+lowlevel_init:
+	mov.l	DRVCRA_A, r1
+	mov.l 	DRVCRA_D, r0
+	mov.w	r0, @r1
+
+	mov.l	DRVCRB_A, r1
+	mov.l 	DRVCRB_D, r0
+	mov.w	r0, @r1
+
+	mov.l	RWTCSR_A, r1
+	mov.l 	RWTCSR_D1, r0
+	mov.w	r0, @r1
+
+	mov.l	RWTCNT_A, r1
+	mov.l 	RWTCNT_D, r0
+	mov.w	r0, @r1
+
+	mov.l	RWTCSR_A, r1
+	mov.l 	RWTCSR_D2, r0
+	mov.w	r0, @r1
+
+	mov.l	FRQCR_A, r1
+	mov.l 	FRQCR_D, r0
+	mov.l	r0, @r1
+
+	mov.l	CMNCR_A, r1
+	mov.l	CMNCR_D, r0
+	mov.l	r0, @r1
+
+	mov.l	CS0BCR_A ,r1
+	mov.l	CS0BCR_D ,r0
+	mov.l	r0, @r1
+
+	mov.l	CS4BCR_A ,r1
+	mov.l	CS4BCR_D ,r0
+	mov.l	r0, @r1
+
+	mov.l	CS5ABCR_A ,r1
+	mov.l	CS5ABCR_D ,r0
+	mov.l	r0, @r1
+
+	mov.l	CS5BBCR_A ,r1
+	mov.l	CS5BBCR_D ,r0
+	mov.l	r0, @r1
+
+	mov.l	CS6ABCR_A ,r1
+	mov.l	CS6ABCR_D ,r0
+	mov.l	r0, @r1
+
+	mov.l	CS6BBCR_A ,r1
+	mov.l	CS6BBCR_D ,r0
+	mov.l	r0, @r1
+
+	mov.l	CS0WCR_A ,r1
+	mov.l	CS0WCR_D ,r0
+	mov.l	r0, @r1
+
+	mov.l	CS4WCR_A ,r1
+	mov.l	CS4WCR_D ,r0
+	mov.l	r0, @r1
+
+	mov.l	CS5AWCR_A ,r1
+	mov.l	CS5AWCR_D ,r0
+	mov.l	r0, @r1
+
+	mov.l	CS5BWCR_A ,r1
+	mov.l	CS5BWCR_D ,r0
+	mov.l	r0, @r1
+
+	mov.l	CS6AWCR_A ,r1
+	mov.l	CS6AWCR_D ,r0
+	mov.l	r0, @r1
+
+	mov.l	CS6BWCR_A ,r1
+	mov.l	CS6BWCR_D ,r0
+	mov.l	r0, @r1
+
+	mov.l	SBSC_SDCR_A, r1
+	mov.l 	SBSC_SDCR_D1, r0
+	mov.l	r0, @r1
+
+	mov.l	SBSC_SDWCR_A, r1
+	mov.l 	SBSC_SDWCR_D, r0
+	mov.l	r0, @r1
+
+	mov.l	SBSC_SDPCR_A, r1
+	mov.l 	SBSC_SDPCR_D, r0
+	mov.l	r0, @r1
+
+	mov.l	SBSC_RTCSR_A, r1
+	mov.l 	SBSC_RTCSR_D, r0
+	mov.l	r0, @r1
+
+	mov.l	SBSC_RTCNT_A, r1
+	mov.l 	SBSC_RTCNT_D, r0
+	mov.l	r0, @r1
+
+	mov.l	SBSC_RTCOR_A, r1
+	mov.l 	SBSC_RTCOR_D, r0
+	mov.l	r0, @r1
+
+	mov.l	SBSC_SDMR3_A1, r1
+	mov.l 	SBSC_SDMR3_D, r0
+	mov.b	r0, @r1
+
+	mov.l	SBSC_SDMR3_A2, r1
+	mov.l 	SBSC_SDMR3_D, r0
+	mov.b	r0, @r1
+
+	mov.l	SLEEP_CNT, r1
+2:	tst	r1, r1
+	nop
+	bf/s	2b
+	dt	r1
+
+	mov.l	SBSC_SDMR3_A3, r1
+	mov.l 	SBSC_SDMR3_D, r0
+	mov.b	r0, @r1
+
+	mov.l	SBSC_SDCR_A, r1
+	mov.l 	SBSC_SDCR_D2, r0
+	mov.l	r0, @r1
+
+	mov.l	CCR_A, r1
+	mov.l 	CCR_D, r0
+	mov.l	r0, @r1
+
+	! BL bit off (init = ON)  (?!?)
+
+	stc	sr, r0				! BL bit off(init=ON)
+	mov.l	SR_MASK_D, r1
+	and	r1, r0
+	ldc	r0, sr
+
+	rts
+	 mov	#0, r0
+
+	.align	2
+
+DRVCRA_A:	.long	DRVCRA
+DRVCRB_A:	.long	DRVCRB
+DRVCRA_D:	.long	0x4555
+DRVCRB_D:	.long	0x0005
+
+RWTCSR_A:	.long	RWTCSR
+RWTCNT_A:	.long	RWTCNT
+FRQCR_A:	.long	FRQCR
+RWTCSR_D1:	.long	0xa507
+RWTCSR_D2:	.long	0xa504
+RWTCNT_D:	.long	0x5a00
+FRQCR_D:	.long	0x0b04474a
+
+SBSC_SDCR_A:	.long	SBSC_SDCR
+SBSC_SDWCR_A:	.long	SBSC_SDWCR
+SBSC_SDPCR_A:	.long	SBSC_SDPCR
+SBSC_RTCSR_A:	.long	SBSC_RTCSR
+SBSC_RTCNT_A:	.long	SBSC_RTCNT
+SBSC_RTCOR_A:	.long	SBSC_RTCOR
+SBSC_SDMR3_A1:	.long	0xfe510000
+SBSC_SDMR3_A2:	.long	0xfe500242
+SBSC_SDMR3_A3:	.long	0xfe5c0042
+
+SBSC_SDCR_D1:	.long	0x92810112
+SBSC_SDCR_D2:	.long	0x92810912
+SBSC_SDWCR_D:	.long	0x05162482
+SBSC_SDPCR_D:	.long	0x00300087
+SBSC_RTCSR_D:	.long	0xa55a0212
+SBSC_RTCNT_D:	.long	0xa55a0000
+SBSC_RTCOR_D:	.long	0xa55a0040
+SBSC_SDMR3_D:	.long	0x00
+
+CMNCR_A:	.long	CMNCR
+CS0BCR_A:	.long	CS0BCR
+CS4BCR_A:	.long	CS4BCR
+CS5ABCR_A:	.long 	CS5ABCR
+CS5BBCR_A:	.long	CS5BBCR
+CS6ABCR_A:	.long	CS6ABCR
+CS6BBCR_A:	.long	CS6BBCR
+CS0WCR_A:	.long	CS0WCR
+CS4WCR_A:	.long	CS4WCR
+CS5AWCR_A:	.long	CS5AWCR
+CS5BWCR_A:	.long	CS5BWCR
+CS6AWCR_A:	.long	CS6AWCR
+CS6BWCR_A:	.long	CS6BWCR
+
+CMNCR_D:	.long	0x00000013
+CS0BCR_D:	.long	0x24920400
+CS4BCR_D:	.long	0x24920400
+CS5ABCR_D:	.long	0x24920400
+CS5BBCR_D:	.long	0x7fff0600
+CS6ABCR_D:	.long	0x24920400
+CS6BBCR_D:	.long	0x24920600
+CS0WCR_D:	.long	0x00000480
+CS4WCR_D:	.long	0x00000480
+CS5AWCR_D:	.long	0x00000380
+CS5BWCR_D:	.long	0x00000600
+CS6AWCR_D:	.long	0x00000300
+CS6BWCR_D:	.long	0x00000540
+
+CCR_A:		.long	0xff00001c
+CCR_D:		.long	0x0000090d
+
+SLEEP_CNT:	.long	0x00000800
+SR_MASK_D:	.long	0xEFFFFF0F

board/ap325rxa/u-boot.lds

@@ -0,0 +1,106 @@
+/*
+ * Copyrigth (c) 2007
+ * Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-sh-linux", "elf32-sh-linux", "elf32-sh-linux")
+OUTPUT_ARCH(sh)
+ENTRY(_start)
+
+SECTIONS
+{
+	/*
+	   Base address of internal SDRAM is 0x88000000.
+	   Although size of SDRAM can be either 16 or 32 MBytes,
+	   we assume 16 MBytes (ie ignore upper half if the full
+	   32 MBytes is present).
+
+	   NOTE: This address must match with the definition of
+	   TEXT_BASE in config.mk (in this directory).
+
+	*/
+	. = 0x88000000 + (128*1024*1024) - (256*1024);
+
+	PROVIDE (reloc_dst = .);
+
+	PROVIDE (_ftext = .);
+	PROVIDE (_fcode = .);
+	PROVIDE (_start = .);
+
+	.text :
+	{
+		cpu/sh4/start.o		(.text)
+		. = ALIGN(8192);
+		common/environment.o	(.ppcenv)
+		. = ALIGN(8192);
+		common/environment.o	(.ppcenvr)
+		. = ALIGN(8192);
+		*(.text)
+		. = ALIGN(4);
+	} =0xFF
+	PROVIDE (_ecode = .);
+	.rodata :
+	{
+		*(.rodata)
+		. = ALIGN(4);
+	}
+	PROVIDE (_etext = .);
+
+
+	PROVIDE (_fdata = .);
+	.data :
+	{
+		*(.data)
+		. = ALIGN(4);
+	}
+	PROVIDE (_edata = .);
+
+	PROVIDE (_fgot = .);
+	.got :
+	{
+		*(.got)
+		. = ALIGN(4);
+	}
+	PROVIDE (_egot = .);
+
+	PROVIDE (__u_boot_cmd_start = .);
+	.u_boot_cmd :
+	{
+		*(.u_boot_cmd)
+		. = ALIGN(4);
+	}
+	PROVIDE (__u_boot_cmd_end = .);
+
+	PROVIDE (reloc_dst_end = .);
+	/* _reloc_dst_end = .; */
+
+	PROVIDE (bss_start = .);
+	PROVIDE (__bss_start = .);
+	.bss :
+	{
+		*(.bss)
+		. = ALIGN(4);
+	}
+	PROVIDE (bss_end = .);
+
+	PROVIDE (_end = .);
+}
+

board/apollon/config.mk

@@ -13,7 +13,7 @@
 # Linux-Kernel is expected to be at 8000'8000, entry 8000'8000
 # (mem base + reserved)
 # For use with external or internal boots.
-TEXT_BASE = 0x80e80000
+TEXT_BASE = 0x83e80000
 
 # Used with full SRAM boot.
 # This is either with a GP system or a signed boot image.

board/atc/atc.c

@@ -380,7 +380,6 @@ phys_size_t initdram (int board_type)
 }
 
 #if defined(CONFIG_CMD_DOC)
-extern void doc_probe (ulong physadr);
 void doc_init (void)
 {
 	doc_probe (CFG_DOC_BASE);

board/atmel/at91cap9adk/at91cap9adk.c

@@ -30,11 +30,13 @@
 #include <asm/arch/at91_rstc.h>
 #include <asm/arch/gpio.h>
 #include <asm/arch/io.h>
+#include <asm/arch/hardware.h>
 #include <lcd.h>
 #include <atmel_lcdc.h>
 #if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB)
 #include <net.h>
 #endif
+#include <netdev.h>
 
 #define MP_BLOCK_3_BASE	0xFDF00000
 
@@ -376,3 +378,12 @@ void reset_phy(void)
 #endif
 }
 #endif
+
+int board_eth_init(bd_t *bis)
+{
+	int rc = 0;
+#ifdef CONFIG_MACB
+	rc = macb_eth_initialize(0, (void *)AT91_BASE_EMAC, 0x00);
+#endif
+	return rc;
+}

board/atmel/at91cap9adk/nand.c

@@ -37,36 +37,35 @@
 #define	MASK_ALE	(1 << 21)	/* our ALE is AD21 */
 #define	MASK_CLE	(1 << 22)	/* our CLE is AD22 */
 
-static void at91cap9adk_nand_hwcontrol(struct mtd_info *mtd, int cmd)
+static void at91cap9adk_nand_hwcontrol(struct mtd_info *mtd,
+				       int cmd, unsigned int ctrl)
 {
 	struct nand_chip *this = mtd->priv;
-	ulong IO_ADDR_W = (ulong) this->IO_ADDR_W;
 
-	IO_ADDR_W &= ~(MASK_ALE|MASK_CLE);
-	switch (cmd) {
-	case NAND_CTL_SETCLE:
-		IO_ADDR_W |= MASK_CLE;
-		break;
-	case NAND_CTL_SETALE:
-		IO_ADDR_W |= MASK_ALE;
-		break;
-	case NAND_CTL_CLRNCE:
-		at91_set_gpio_value(AT91_PIN_PD15, 1);
-		break;
-	case NAND_CTL_SETNCE:
-		at91_set_gpio_value(AT91_PIN_PD15, 0);
-		break;
+	if (ctrl & NAND_CTRL_CHANGE) {
+		ulong IO_ADDR_W = (ulong) this->IO_ADDR_W;
+		IO_ADDR_W &= ~(MASK_ALE | MASK_CLE);
+
+		if (ctrl & NAND_CLE)
+			IO_ADDR_W |= MASK_CLE;
+		if (ctrl & NAND_ALE)
+			IO_ADDR_W |= MASK_ALE;
+
+		at91_set_gpio_value(AT91_PIN_PD15, !(ctrl & NAND_NCE));
+		this->IO_ADDR_W = (void *) IO_ADDR_W;
 	}
-	this->IO_ADDR_W = (void *) IO_ADDR_W;
+
+	if (cmd != NAND_CMD_NONE)
+		writeb(cmd, this->IO_ADDR_W);
 }
 
 int board_nand_init(struct nand_chip *nand)
 {
-	nand->eccmode = NAND_ECC_SOFT;
+	nand->ecc.mode = NAND_ECC_SOFT;
 #ifdef CFG_NAND_DBW_16
 	nand->options = NAND_BUSWIDTH_16;
 #endif
-	nand->hwcontrol = at91cap9adk_nand_hwcontrol;
+	nand->cmd_ctrl = at91cap9adk_nand_hwcontrol;
 	nand->chip_delay = 20;
 
 	return 0;

board/atmel/at91sam9260ek/at91sam9260ek.c

@@ -30,9 +30,11 @@
 #include <asm/arch/at91_rstc.h>
 #include <asm/arch/gpio.h>
 #include <asm/arch/io.h>
+#include <asm/arch/hardware.h>
 #if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB)
 #include <net.h>
 #endif
+#include <netdev.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -248,3 +250,12 @@ void reset_phy(void)
 #endif
 }
 #endif
+
+int board_eth_init(bd_t *bis)
+{
+	int rc = 0;
+#ifdef CONFIG_MACB
+	rc = macb_eth_initialize(0, (void *)AT91_BASE_EMAC, 0x00);
+#endif
+	return rc;
+}

board/atmel/at91sam9260ek/nand.c

@@ -37,27 +37,26 @@
 #define	MASK_ALE	(1 << 21)	/* our ALE is AD21 */
 #define	MASK_CLE	(1 << 22)	/* our CLE is AD22 */
 
-static void at91sam9260ek_nand_hwcontrol(struct mtd_info *mtd, int cmd)
+static void at91sam9260ek_nand_hwcontrol(struct mtd_info *mtd,
+					 int cmd, unsigned int ctrl)
 {
 	struct nand_chip *this = mtd->priv;
-	ulong IO_ADDR_W = (ulong) this->IO_ADDR_W;
 
-	IO_ADDR_W &= ~(MASK_ALE|MASK_CLE);
-	switch (cmd) {
-	case NAND_CTL_SETCLE:
-		IO_ADDR_W |= MASK_CLE;
-		break;
-	case NAND_CTL_SETALE:
-		IO_ADDR_W |= MASK_ALE;
-		break;
-	case NAND_CTL_CLRNCE:
-		at91_set_gpio_value(AT91_PIN_PC14, 1);
-		break;
-	case NAND_CTL_SETNCE:
-		at91_set_gpio_value(AT91_PIN_PC14, 0);
-		break;
+	if (ctrl & NAND_CTRL_CHANGE) {
+		ulong IO_ADDR_W = (ulong) this->IO_ADDR_W;
+		IO_ADDR_W &= ~(MASK_ALE | MASK_CLE);
+
+		if (ctrl & NAND_CLE)
+			IO_ADDR_W |= MASK_CLE;
+		if (ctrl & NAND_ALE)
+			IO_ADDR_W |= MASK_ALE;
+
+		at91_set_gpio_value(AT91_PIN_PC14, !(ctrl & NAND_NCE));
+		this->IO_ADDR_W = (void *) IO_ADDR_W;
 	}
-	this->IO_ADDR_W = (void *) IO_ADDR_W;
+
+	if (cmd != NAND_CMD_NONE)
+		writeb(cmd, this->IO_ADDR_W);
 }
 
 static int at91sam9260ek_nand_ready(struct mtd_info *mtd)
@@ -67,11 +66,11 @@ static int at91sam9260ek_nand_ready(struct mtd_info *mtd)
 
 int board_nand_init(struct nand_chip *nand)
 {
-	nand->eccmode = NAND_ECC_SOFT;
+	nand->ecc.mode = NAND_ECC_SOFT;
 #ifdef CFG_NAND_DBW_16
 	nand->options = NAND_BUSWIDTH_16;
 #endif
-	nand->hwcontrol = at91sam9260ek_nand_hwcontrol;
+	nand->cmd_ctrl = at91sam9260ek_nand_hwcontrol;
 	nand->dev_ready = at91sam9260ek_nand_ready;
 	nand->chip_delay = 20;
 

board/atmel/at91sam9261ek/nand.c

@@ -37,27 +37,26 @@
 #define	MASK_ALE	(1 << 22)	/* our ALE is AD22 */
 #define	MASK_CLE	(1 << 21)	/* our CLE is AD21 */
 
-static void at91sam9261ek_nand_hwcontrol(struct mtd_info *mtd, int cmd)
+static void at91sam9261ek_nand_hwcontrol(struct mtd_info *mtd,
+					 int cmd, unsigned int ctrl)
 {
 	struct nand_chip *this = mtd->priv;
-	ulong IO_ADDR_W = (ulong) this->IO_ADDR_W;
 
-	IO_ADDR_W &= ~(MASK_ALE|MASK_CLE);
-	switch (cmd) {
-	case NAND_CTL_SETCLE:
-		IO_ADDR_W |= MASK_CLE;
-		break;
-	case NAND_CTL_SETALE:
-		IO_ADDR_W |= MASK_ALE;
-		break;
-	case NAND_CTL_CLRNCE:
-		at91_set_gpio_value(AT91_PIN_PC14, 1);
-		break;
-	case NAND_CTL_SETNCE:
-		at91_set_gpio_value(AT91_PIN_PC14, 0);
-		break;
+	if (ctrl & NAND_CTRL_CHANGE) {
+		ulong IO_ADDR_W = (ulong) this->IO_ADDR_W;
+		IO_ADDR_W &= ~(MASK_ALE | MASK_CLE);
+
+		if (ctrl & NAND_CLE)
+			IO_ADDR_W |= MASK_CLE;
+		if (ctrl & NAND_ALE)
+			IO_ADDR_W |= MASK_ALE;
+
+		at91_set_gpio_value(AT91_PIN_PC14, !(ctrl & NAND_NCE));
+		this->IO_ADDR_W = (void *) IO_ADDR_W;
 	}
-	this->IO_ADDR_W = (void *) IO_ADDR_W;
+
+	if (cmd != NAND_CMD_NONE)
+		writeb(cmd, this->IO_ADDR_W);
 }
 
 static int at91sam9261ek_nand_ready(struct mtd_info *mtd)
@@ -67,11 +66,11 @@ static int at91sam9261ek_nand_ready(struct mtd_info *mtd)
 
 int board_nand_init(struct nand_chip *nand)
 {
-	nand->eccmode = NAND_ECC_SOFT;
+	nand->ecc.mode = NAND_ECC_SOFT;
 #ifdef CFG_NAND_DBW_16
 	nand->options = NAND_BUSWIDTH_16;
 #endif
-	nand->hwcontrol = at91sam9261ek_nand_hwcontrol;
+	nand->cmd_ctrl = at91sam9261ek_nand_hwcontrol;
 	nand->dev_ready = at91sam9261ek_nand_ready;
 	nand->chip_delay = 20;
 

board/atmel/at91sam9263ek/at91sam9263ek.c

@@ -31,11 +31,13 @@
 #include <asm/arch/at91_rstc.h>
 #include <asm/arch/gpio.h>
 #include <asm/arch/io.h>
+#include <asm/arch/hardware.h>
 #include <lcd.h>
 #include <atmel_lcdc.h>
 #if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB)
 #include <net.h>
 #endif
+#include <netdev.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -308,3 +310,12 @@ void reset_phy(void)
 #endif
 }
 #endif
+
+int board_eth_init(bd_t *bis)
+{
+	int rc = 0;
+#ifdef CONFIG_MACB
+	rc = macb_eth_initialize(0, (void *)AT91_BASE_EMAC, 0x00);
+#endif
+	return rc;
+}

board/atmel/at91sam9263ek/nand.c

@@ -37,27 +37,26 @@
 #define	MASK_ALE	(1 << 21)	/* our ALE is AD21 */
 #define	MASK_CLE	(1 << 22)	/* our CLE is AD22 */
 
-static void at91sam9263ek_nand_hwcontrol(struct mtd_info *mtd, int cmd)
+static void at91sam9263ek_nand_hwcontrol(struct mtd_info *mtd,
+					 int cmd, unsigned int ctrl)
 {
 	struct nand_chip *this = mtd->priv;
-	ulong IO_ADDR_W = (ulong) this->IO_ADDR_W;
 
-	IO_ADDR_W &= ~(MASK_ALE|MASK_CLE);
-	switch (cmd) {
-	case NAND_CTL_SETCLE:
-		IO_ADDR_W |= MASK_CLE;
-		break;
-	case NAND_CTL_SETALE:
-		IO_ADDR_W |= MASK_ALE;
-		break;
-	case NAND_CTL_CLRNCE:
-		at91_set_gpio_value(AT91_PIN_PD15, 1);
-		break;
-	case NAND_CTL_SETNCE:
-		at91_set_gpio_value(AT91_PIN_PD15, 0);
-		break;
+	if (ctrl & NAND_CTRL_CHANGE) {
+		ulong IO_ADDR_W = (ulong) this->IO_ADDR_W;
+		IO_ADDR_W &= ~(MASK_ALE | MASK_CLE);
+
+		if (ctrl & NAND_CLE)
+			IO_ADDR_W |= MASK_CLE;
+		if (ctrl & NAND_ALE)
+			IO_ADDR_W |= MASK_ALE;
+
+		at91_set_gpio_value(AT91_PIN_PD15, !(ctrl & NAND_NCE));
+		this->IO_ADDR_W = (void *) IO_ADDR_W;
 	}
-	this->IO_ADDR_W = (void *) IO_ADDR_W;
+
+	if (cmd != NAND_CMD_NONE)
+		writeb(cmd, this->IO_ADDR_W);
 }
 
 static int at91sam9263ek_nand_ready(struct mtd_info *mtd)
@@ -67,11 +66,11 @@ static int at91sam9263ek_nand_ready(struct mtd_info *mtd)
 
 int board_nand_init(struct nand_chip *nand)
 {
-	nand->eccmode = NAND_ECC_SOFT;
+	nand->ecc.mode = NAND_ECC_SOFT;
 #ifdef CFG_NAND_DBW_16
 	nand->options = NAND_BUSWIDTH_16;
 #endif
-	nand->hwcontrol = at91sam9263ek_nand_hwcontrol;
+	nand->cmd_ctrl = at91sam9263ek_nand_hwcontrol;
 	nand->dev_ready = at91sam9263ek_nand_ready;
 	nand->chip_delay = 20;
 

board/atmel/at91sam9rlek/nand.c

@@ -37,27 +37,26 @@
 #define	MASK_ALE	(1 << 21)	/* our ALE is AD21 */
 #define	MASK_CLE	(1 << 22)	/* our CLE is AD22 */
 
-static void at91sam9rlek_nand_hwcontrol(struct mtd_info *mtd, int cmd)
+static void at91sam9rlek_nand_hwcontrol(struct mtd_info *mtd,
+					int cmd, unsigned int ctrl)
 {
 	struct nand_chip *this = mtd->priv;
-	ulong IO_ADDR_W = (ulong) this->IO_ADDR_W;
 
-	IO_ADDR_W &= ~(MASK_ALE|MASK_CLE);
-	switch (cmd) {
-	case NAND_CTL_SETCLE:
-		IO_ADDR_W |= MASK_CLE;
-		break;
-	case NAND_CTL_SETALE:
-		IO_ADDR_W |= MASK_ALE;
-		break;
-	case NAND_CTL_CLRNCE:
-		at91_set_gpio_value(AT91_PIN_PB6, 1);
-		break;
-	case NAND_CTL_SETNCE:
-		at91_set_gpio_value(AT91_PIN_PB6, 0);
-		break;
+	if (ctrl & NAND_CTRL_CHANGE) {
+		ulong IO_ADDR_W = (ulong) this->IO_ADDR_W;
+		IO_ADDR_W &= ~(MASK_ALE | MASK_CLE);
+
+		if (ctrl & NAND_CLE)
+			IO_ADDR_W |= MASK_CLE;
+		if (ctrl & NAND_ALE)
+			IO_ADDR_W |= MASK_ALE;
+
+		at91_set_gpio_value(AT91_PIN_PB6, !(ctrl & NAND_NCE));
+		this->IO_ADDR_W = (void *) IO_ADDR_W;
 	}
-	this->IO_ADDR_W = (void *) IO_ADDR_W;
+
+	if (cmd != NAND_CMD_NONE)
+		writeb(cmd, this->IO_ADDR_W);
 }
 
 static int at91sam9rlek_nand_ready(struct mtd_info *mtd)
@@ -67,11 +66,11 @@ static int at91sam9rlek_nand_ready(struct mtd_info *mtd)
 
 int board_nand_init(struct nand_chip *nand)
 {
-	nand->eccmode = NAND_ECC_SOFT;
+	nand->ecc.mode = NAND_ECC_SOFT;
 #ifdef CFG_NAND_DBW_16
 	nand->options = NAND_BUSWIDTH_16;
 #endif
-	nand->hwcontrol = at91sam9rlek_nand_hwcontrol;
+	nand->cmd_ctrl = at91sam9rlek_nand_hwcontrol;
 	nand->dev_ready = at91sam9rlek_nand_ready;
 	nand->chip_delay = 20;
 

board/atmel/atngw100/Makefile

@@ -22,7 +22,7 @@ include $(TOPDIR)/config.mk
 
 LIB	:= $(obj)lib$(BOARD).a
 
-COBJS	:= $(BOARD).o eth.o
+COBJS	:= $(BOARD).o
 
 SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
 OBJS	:= $(addprefix $(obj),$(SOBJS) $(COBJS))

board/atmel/atngw100/atngw100.c

@@ -26,6 +26,7 @@
 #include <asm/arch/clk.h>
 #include <asm/arch/gpio.h>
 #include <asm/arch/hmatrix.h>
+#include <netdev.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -93,6 +94,15 @@ void board_init_info(void)
 	gd->bd->bi_phy_id[1] = 0x03;
 }
 
+#ifdef CONFIG_CMD_NET
+int board_eth_init(bd_t *bi)
+{
+	macb_eth_initialize(0, (void *)MACB0_BASE, bi->bi_phy_id[0]);
+	macb_eth_initialize(1, (void *)MACB1_BASE, bi->bi_phy_id[1]);
+	return 0;
+}
+#endif
+
 /* SPI chip select control */
 #ifdef CONFIG_ATMEL_SPI
 #include <spi.h>

board/atmel/atstk1000/Makefile

@@ -26,7 +26,7 @@ include $(TOPDIR)/config.mk
 
 LIB	:= $(obj)lib$(BOARD).a
 
-COBJS	:= $(BOARD).o flash.o eth.o
+COBJS	:= $(BOARD).o flash.o
 
 SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
 OBJS	:= $(addprefix $(obj),$(SOBJS) $(COBJS))

board/atmel/atstk1000/atstk1000.c

@@ -26,6 +26,7 @@
 #include <asm/arch/clk.h>
 #include <asm/arch/gpio.h>
 #include <asm/arch/hmatrix.h>
+#include <netdev.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -115,3 +116,12 @@ void board_init_info(void)
 	gd->bd->bi_phy_id[0] = 0x10;
 	gd->bd->bi_phy_id[1] = 0x11;
 }
+
+#ifdef CONFIG_CMD_NET
+int board_eth_init(bd_t *bi)
+{
+	macb_eth_initialize(0, (void *)MACB0_BASE, bi->bi_phy_id[0]);
+	macb_eth_initialize(1, (void *)MACB1_BASE, bi->bi_phy_id[1]);
+	return 0;
+}
+#endif

board/atum8548/Makefile

@@ -29,10 +29,13 @@ endif
 
 LIB	= $(obj)lib$(BOARD).a
 
-COBJS	:= $(BOARD).o law.o tlb.o
+COBJS-y	+= $(BOARD).o
+COBJS-y	+= law.o
+COBJS-y	+= tlb.o
+COBJS-$(CONFIG_FSL_DDR2) += ddr.o
 
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
+SRCS	:= $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS-y))
 SOBJS	:= $(addprefix $(obj),$(SOBJS))
 
 $(LIB):	$(obj).depend $(OBJS) $(SOBJS)

board/atum8548/atum8548.c

@@ -29,7 +29,9 @@
 #include <asm/processor.h>
 #include <asm/immap_85xx.h>
 #include <asm/immap_fsl_pci.h>
+#include <asm/fsl_ddr_sdram.h>
 #include <asm/io.h>
+#include <asm/mmu.h>
 #include <spd_sdram.h>
 #include <miiphy.h>
 #include <libfdt.h>
@@ -106,8 +108,10 @@ initdram(int board_type)
 	puts("Initializing\n");
 
 #if defined(CONFIG_SPD_EEPROM)
-	puts("spd_sdram\n");
-	dram_size = spd_sdram ();
+	puts("fsl_ddr_sdram\n");
+	dram_size = fsl_ddr_sdram();
+	dram_size = setup_ddr_tlbs(dram_size / 0x100000);
+	dram_size *= 0x100000;
 #else
 	puts("fixed_sdram\n");
 	dram_size = fixed_sdram ();

board/atum8548/ddr.c

@@ -0,0 +1,80 @@
+/*
+ * Copyright 2008 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * Version 2 as published by the Free Software Foundation.
+ */
+
+#include <common.h>
+#include <i2c.h>
+
+#include <asm/fsl_ddr_sdram.h>
+
+static void
+get_spd(ddr2_spd_eeprom_t *spd, unsigned char i2c_address)
+{
+	i2c_read(i2c_address, 0, 1, (uchar *)spd, sizeof(ddr2_spd_eeprom_t));
+}
+
+unsigned int fsl_ddr_get_mem_data_rate(void)
+{
+	return get_ddr_freq(0);
+}
+
+void fsl_ddr_get_spd(ddr2_spd_eeprom_t *ctrl_dimms_spd,
+			unsigned int ctrl_num)
+{
+	unsigned int i;
+
+	if (ctrl_num) {
+		printf("%s unexpected ctrl_num = %u\n", __FUNCTION__, ctrl_num);
+		return;
+	}
+
+	for (i = 0; i < CONFIG_DIMM_SLOTS_PER_CTLR; i++) {
+		get_spd(&(ctrl_dimms_spd[i]), SPD_EEPROM_ADDRESS);
+	}
+}
+
+void fsl_ddr_board_options(memctl_options_t *popts, unsigned int ctrl_num)
+{
+	/*
+	 * Factors to consider for clock adjust:
+	 *	- number of chips on bus
+	 *	- position of slot
+	 *	- DDR1 vs. DDR2?
+	 *	- ???
+	 *
+	 * This needs to be determined on a board-by-board basis.
+	 *	0110	3/4 cycle late
+	 *	0111	7/8 cycle late
+	 */
+	popts->clk_adjust = 7;
+
+	/*
+	 * Factors to consider for CPO:
+	 *	- frequency
+	 *	- ddr1 vs. ddr2
+	 */
+	popts->cpo_override = 10;
+
+	/*
+	 * Factors to consider for write data delay:
+	 *	- number of DIMMs
+	 *
+	 * 1 = 1/4 clock delay
+	 * 2 = 1/2 clock delay
+	 * 3 = 3/4 clock delay
+	 * 4 = 1   clock delay
+	 * 5 = 5/4 clock delay
+	 * 6 = 3/2 clock delay
+	 */
+	popts->write_data_delay = 3;
+
+	/*
+	 * Factors to consider for half-strength driver enable:
+	 *	- number of DIMMs installed
+	 */
+	popts->half_strength_driver_enable = 0;
+}

board/avnet/v5fx30teval/Makefile

@@ -0,0 +1,27 @@
+#
+# (C) Copyright 2008
+# Ricardo Ribalda,Universidad Autonoma de Madrid, ricardo.ribalda@uam.es
+# This work has been supported by: Qtechnology http://qtec.com/
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+COBJS	+= $(BOARD).o
+
+include $(SRCTREE)/board/xilinx/ppc440-generic/Makefile

board/avnet/v5fx30teval/config.mk

@@ -0,0 +1,26 @@
+#
+# (C) Copyright 2008
+# Ricardo Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@uam.es
+# Work supported by Qtechnology http://www.qtec.com
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+#
+
+sinclude $(SRCTREE)/board/xilinx/ppc440-generic/config.mk

board/avnet/v5fx30teval/v5fx30teval.c

@@ -0,0 +1,28 @@
+/*
+ * (C) Copyright 2008
+ * Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@uam.es
+ * This work has been supported by: QTechnology  http://qtec.com/
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+*/
+
+#include <config.h>
+#include <common.h>
+#include <asm/processor.h>
+
+
+int checkboard(void)
+{
+	puts("Avnet Virtex 5 FX30 Evaluation Board\n");
+	return 0;
+}

board/avnet/v5fx30teval/xparameters.h

@@ -0,0 +1,33 @@
+/*
+ * (C) Copyright 2008
+ * Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@uam.es
+ * This work has been supported by: QTechnology  http://qtec.com/
+ * based on xparameters.h by Xilinx
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+*/
+
+#ifndef XPARAMETER_H
+#define XPARAMETER_H
+
+#define XPAR_DDR2_SDRAM_MEM_BASEADDR	0x00000000
+#define XPAR_INTC_0_BASEADDR		0x81800000
+#define XPAR_UARTLITE_0_BASEADDR	0x84000000
+#define XPAR_FLASH_MEM0_BASEADDR	0xFF000000
+#define XPAR_PLB_CLOCK_FREQ_HZ		100000000
+#define XPAR_CORE_CLOCK_FREQ_HZ		400000000
+#define XPAR_INTC_MAX_NUM_INTR_INPUTS	13
+#define XPAR_UARTLITE_0_BAUDRATE	9600
+
+#endif

board/bc3450/bc3450.c

@@ -33,6 +33,7 @@
 #include <common.h>
 #include <mpc5xxx.h>
 #include <pci.h>
+#include <netdev.h>
 
 #ifdef CONFIG_VIDEO_SM501
 #include <sm501.h>
@@ -669,3 +670,9 @@ int board_get_height (void)
 }
 
 #endif /* CONFIG_VIDEO_SM501 */
+
+int board_eth_init(bd_t *bis)
+{
+	cpu_eth_init(bis); /* Built in FEC comes first */
+	return pci_eth_init(bis);
+}

board/bf537-stamp/bf537-stamp.c

@@ -32,6 +32,7 @@
 #include <asm/io.h>
 #include <net.h>
 #include <asm/mach-common/bits/bootrom.h>
+#include <netdev.h>
 
 /**
  * is_valid_ether_addr - Determine if the given Ethernet address is valid
@@ -154,6 +155,14 @@ int misc_init_r(void)
 }
 #endif				/* CONFIG_MISC_INIT_R */
 
+#if defined(CONFIG_BFIN_MAC)
+
+int board_eth_init(bd_t *bis)
+{
+	return bfin_EMAC_initialize(bis);
+}
+#endif
+
 #ifdef CONFIG_POST
 /* Using sw10-PF5 as the hotkey */
 int post_hotkeys_pressed(void)

board/bf537-stamp/nand.c

@@ -37,34 +37,29 @@
 /*
  * hardware specific access to control-lines
  */
-static void bfin_hwcontrol(struct mtd_info *mtd, int cmd)
+static void bfin_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl)
 {
 	register struct nand_chip *this = mtd->priv;
+	u32 IO_ADDR_W = (u32) this->IO_ADDR_W;
 
-	switch (cmd) {
-
-	case NAND_CTL_SETCLE:
-		this->IO_ADDR_W = CFG_NAND_BASE + BFIN_NAND_CLE;
-		break;
-	case NAND_CTL_CLRCLE:
-		this->IO_ADDR_W = CFG_NAND_BASE;
-		break;
-
-	case NAND_CTL_SETALE:
-		this->IO_ADDR_W = CFG_NAND_BASE + BFIN_NAND_ALE;
-		break;
-	case NAND_CTL_CLRALE:
-		this->IO_ADDR_W = CFG_NAND_BASE;
-		break;
-	case NAND_CTL_SETNCE:
-	case NAND_CTL_CLRNCE:
-		break;
+	if (ctrl & NAND_CTRL_CHANGE) {
+		if( ctrl & NAND_CLE )
+			IO_ADDR_W = CFG_NAND_BASE + BFIN_NAND_CLE;
+		else
+			IO_ADDR_W = CFG_NAND_BASE;
+		if( ctrl & NAND_ALE )
+			IO_ADDR_W = CFG_NAND_BASE + BFIN_NAND_ALE;
+		else
+			IO_ADDR_W = CFG_NAND_BASE;
+		this->IO_ADDR_W = (void __iomem *) IO_ADDR_W;
 	}
-
 	this->IO_ADDR_R = this->IO_ADDR_W;
 
 	/* Drain the writebuffer */
 	SSYNC();
+
+	if (cmd != NAND_CMD_NONE)
+		writeb(cmd, this->IO_ADDR_W);
 }
 
 int bfin_device_ready(struct mtd_info *mtd)
@@ -79,11 +74,11 @@ int bfin_device_ready(struct mtd_info *mtd)
  * argument are board-specific (per include/linux/mtd/nand.h):
  * - IO_ADDR_R?: address to read the 8 I/O lines of the flash device
  * - IO_ADDR_W?: address to write the 8 I/O lines of the flash device
- * - hwcontrol: hardwarespecific function for accesing control-lines
+ * - cmd_ctrl: hardwarespecific function for accesing control-lines
  * - dev_ready: hardwarespecific function for  accesing device ready/busy line
  * - enable_hwecc?: function to enable (reset)  hardware ecc generator. Must
  *   only be provided if a hardware ECC is available
- * - eccmode: mode of ecc, see defines
+ * - ecc.mode: mode of ecc, see defines
  * - chip_delay: chip dependent delay for transfering data from array to
  *   read regs (tR)
  * - options: various chip options. They can partly be set to inform
@@ -98,8 +93,8 @@ void board_nand_init(struct nand_chip *nand)
 	*PORT(CONFIG_NAND_GPIO_PORT, IO_DIR) &= ~BFIN_NAND_READY;
 	*PORT(CONFIG_NAND_GPIO_PORT, IO_INEN) |= BFIN_NAND_READY;
 
-	nand->hwcontrol = bfin_hwcontrol;
-	nand->eccmode = NAND_ECC_SOFT;
+	nand->cmd_ctrl = bfin_hwcontrol;
+	nand->ecc.mode = NAND_ECC_SOFT;
 	nand->dev_ready = bfin_device_ready;
 	nand->chip_delay = 30;
 }

board/bmw/m48t59y.c

@@ -299,8 +299,7 @@ rtc_get( struct rtc_time *tmp )
 	return 0;
 }
 
-void
-rtc_set( struct rtc_time *tmp )
+int rtc_set( struct rtc_time *tmp )
 {
 	m48_tod_set(tmp->tm_year,		/* 1980-2079 */
 		    tmp->tm_mon,		/* 01-12 */
@@ -315,6 +314,7 @@ rtc_set( struct rtc_time *tmp )
 		tmp->tm_hour, tmp->tm_min, tmp->tm_sec);
 #endif
 
+	return 0;
 }
 
 void

board/cpc45/cpc45.c

@@ -27,6 +27,7 @@
 #include <asm/io.h>
 #include <pci.h>
 #include <i2c.h>
+#include <netdev.h>
 
 int sysControlDisplay(int digit, uchar ascii_code);
 extern void Plx9030Init(void);
@@ -273,3 +274,8 @@ void ide_led (uchar led, uchar status)
 	writeb(val, BCSR_BASE + 0x04);
 }
 # endif
+
+int board_eth_init(bd_t *bis)
+{
+	return pci_eth_init(bis);
+}

board/cpu86/cpu86.c

@@ -313,7 +313,6 @@ phys_size_t initdram (int board_type)
 }
 
 #if defined(CONFIG_CMD_DOC)
-extern void doc_probe (ulong physadr);
 void doc_init (void)
 {
 	doc_probe (CFG_DOC_BASE);

board/cpu87/cpu87.c

@@ -26,6 +26,7 @@
 #include <mpc8260.h>
 #include "cpu87.h"
 #include <pci.h>
+#include <netdev.h>
 
 /*
  * I/O Port configuration table
@@ -322,7 +323,6 @@ phys_size_t initdram (int board_type)
 }
 
 #if defined(CONFIG_CMD_DOC)
-extern void doc_probe (ulong physadr);
 void doc_init (void)
 {
 	doc_probe (CFG_DOC_BASE);
@@ -339,3 +339,8 @@ void pci_init_board(void)
 	pci_mpc8250_init(&hose);
 }
 #endif
+
+int board_eth_init(bd_t *bis)
+{
+	return pci_eth_init(bis);
+}

board/cray/L1/L1.c

@@ -181,9 +181,9 @@ int rtc_get (struct rtc_time *tmp)
 {
 	return 0;
 }
-void rtc_set (struct rtc_time *tmp)
+int rtc_set (struct rtc_time *tmp)
 {
-	return;
+	return 0;
 }
 void rtc_reset (void)
 {

board/cu824/cu824.c

@@ -28,6 +28,7 @@
 #include <mpc824x.h>
 #include <asm/processor.h>
 #include <pci.h>
+#include <netdev.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -91,3 +92,8 @@ void pci_init_board(void)
 {
 	pci_mpc824x_init(&hose);
 }
+
+int board_eth_init(bd_t *bis)
+{
+	return pci_eth_init(bis);
+}

board/dave/PPChameleonEVB/nand.c

@@ -21,7 +21,7 @@
  */
 
 #include <common.h>
-
+#include <asm/io.h>
 
 #if defined(CONFIG_CMD_NAND)
 
@@ -31,31 +31,28 @@
  * hardware specific access to control-lines
  * function borrowed from Linux 2.6 (drivers/mtd/nand/ppchameleonevb.c)
  */
-static void ppchameleonevb_hwcontrol(struct mtd_info *mtdinfo, int cmd)
+static void ppchameleonevb_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl)
 {
-	struct nand_chip *this = mtdinfo->priv;
+	struct nand_chip *this = mtd->priv;
 	ulong base = (ulong) this->IO_ADDR_W;
 
-	switch(cmd) {
-	case NAND_CTL_SETCLE:
-		MACRO_NAND_CTL_SETCLE((unsigned long)base);
-		break;
-	case NAND_CTL_CLRCLE:
-		MACRO_NAND_CTL_CLRCLE((unsigned long)base);
-		break;
-	case NAND_CTL_SETALE:
-		MACRO_NAND_CTL_SETALE((unsigned long)base);
-		break;
-	case NAND_CTL_CLRALE:
-		MACRO_NAND_CTL_CLRALE((unsigned long)base);
-		break;
-	case NAND_CTL_SETNCE:
-		MACRO_NAND_ENABLE_CE((unsigned long)base);
-		break;
-	case NAND_CTL_CLRNCE:
-		MACRO_NAND_DISABLE_CE((unsigned long)base);
-		break;
+	if (ctrl & NAND_CTRL_CHANGE) {
+		if ( ctrl & NAND_CLE )
+			MACRO_NAND_CTL_SETCLE((unsigned long)base);
+		else
+			MACRO_NAND_CTL_CLRCLE((unsigned long)base);
+		if ( ctrl & NAND_ALE )
+			MACRO_NAND_CTL_CLRCLE((unsigned long)base);
+		else
+			MACRO_NAND_CTL_CLRALE((unsigned long)base);
+		if ( ctrl & NAND_NCE )
+			MACRO_NAND_ENABLE_CE((unsigned long)base);
+		else
+			MACRO_NAND_DISABLE_CE((unsigned long)base);
 	}
+
+	if (cmd != NAND_CMD_NONE)
+		writeb(cmd, this->IO_ADDR_W);
 }
 
 
@@ -92,11 +89,11 @@ static int ppchameleonevb_device_ready(struct mtd_info *mtdinfo)
  * argument are board-specific (per include/linux/mtd/nand.h):
  * - IO_ADDR_R?: address to read the 8 I/O lines of the flash device
  * - IO_ADDR_W?: address to write the 8 I/O lines of the flash device
- * - hwcontrol: hardwarespecific function for accesing control-lines
+ * - cmd_ctrl: hardwarespecific function for accesing control-lines
  * - dev_ready: hardwarespecific function for  accesing device ready/busy line
  * - enable_hwecc?: function to enable (reset)  hardware ecc generator. Must
  *   only be provided if a hardware ECC is available
- * - eccmode: mode of ecc, see defines
+ * - ecc.mode: mode of ecc, see defines
  * - chip_delay: chip dependent delay for transfering data from array to
  *   read regs (tR)
  * - options: various chip options. They can partly be set to inform
@@ -108,9 +105,9 @@ static int ppchameleonevb_device_ready(struct mtd_info *mtdinfo)
 int board_nand_init(struct nand_chip *nand)
 {
 
-	nand->hwcontrol = ppchameleonevb_hwcontrol;
+	nand->cmd_ctrl = ppchameleonevb_hwcontrol;
 	nand->dev_ready = ppchameleonevb_device_ready;
-	nand->eccmode = NAND_ECC_SOFT;
+	nand->ecc.mode = NAND_ECC_SOFT;
 	nand->chip_delay = NAND_BIG_DELAY_US;
 	nand->options = NAND_SAMSUNG_LP_OPTIONS;
 	return 0;

board/davinci/common/Makefile

@@ -0,0 +1,53 @@
+#
+# (C) Copyright 2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+ifneq ($(OBJTREE),$(SRCTREE))
+$(shell mkdir -p $(obj)board/$(VENDOR)/common)
+endif
+
+LIB	= $(obj)lib$(VENDOR).a
+
+COBJS	:= psc.o misc.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+# This is for $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################

board/davinci/common/misc.c

@@ -0,0 +1,126 @@
+/*
+ * Miscelaneous DaVinci functions.
+ *
+ * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
+ * Copyright (C) 2008 Lyrtech <www.lyrtech.com>
+ * Copyright (C) 2004 Texas Instruments.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#include <common.h>
+#include <i2c.h>
+#include <asm/arch/hardware.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int dram_init(void)
+{
+	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+
+	return(0);
+}
+
+static int dv_get_pllm_output(uint32_t pllm)
+{
+	return (pllm + 1) * (CFG_HZ_CLOCK / 1000000);
+}
+
+void dv_display_clk_infos(void)
+{
+	printf("ARM Clock: %dMHz\n", dv_get_pllm_output(REG(PLL1_PLLM)) / 2);
+	printf("DDR Clock: %dMHz\n", dv_get_pllm_output(REG(PLL2_PLLM)) /
+	       ((REG(PLL2_DIV2) & 0x1f) + 1) / 2);
+}
+
+/* Read ethernet MAC address from EEPROM for DVEVM compatible boards.
+ * Returns 1 if found, 0 otherwise.
+ */
+int dvevm_read_mac_address(uint8_t *buf)
+{
+#ifdef CFG_I2C_EEPROM_ADDR
+	/* Read MAC address. */
+	if (i2c_read(CFG_I2C_EEPROM_ADDR, 0x7F00, CFG_I2C_EEPROM_ADDR_LEN,
+		     (uint8_t *) &buf[0], 6))
+		goto i2cerr;
+
+	/* Check that MAC address is not null. */
+	if (memcmp(buf, "\0\0\0\0\0\0", 6) == 0)
+		goto err;
+
+	return 1; /* Found */
+
+i2cerr:
+	printf("Read from EEPROM @ 0x%02x failed\n", CFG_I2C_EEPROM_ADDR);
+err:
+#endif /* CFG_I2C_EEPROM_ADDR */
+
+	return 0;
+}
+
+/* If there is a MAC address in the environment, and if it is not identical to
+ * the MAC address in the ROM, then a warning is printed and the MAC address
+ * from the environment is used.
+ *
+ * If there is no MAC address in the environment, then it will be initialized
+ * (silently) from the value in the ROM.
+ */
+void dv_configure_mac_address(uint8_t *rom_enetaddr)
+{
+	int i;
+	u_int8_t env_enetaddr[6];
+	char *tmp = getenv("ethaddr");
+	char *end;
+
+	/* Read Ethernet MAC address from the U-Boot environment.
+	 * If it is not defined, env_enetaddr[] will be cleared. */
+	for (i = 0; i < 6; i++) {
+		env_enetaddr[i] = tmp ? simple_strtoul(tmp, &end, 16) : 0;
+		if (tmp)
+			tmp = (*end) ? end+1 : end;
+	}
+
+	/* Check if ROM and U-Boot environment MAC addresses match. */
+	if (memcmp(env_enetaddr, "\0\0\0\0\0\0", 6) != 0 &&
+	    memcmp(env_enetaddr, rom_enetaddr, 6) != 0) {
+		printf("Warning: MAC addresses don't match:\n");
+		printf("  ROM MAC address: %02X:%02X:%02X:%02X:%02X:%02X\n",
+		       rom_enetaddr[0], rom_enetaddr[1],
+		       rom_enetaddr[2], rom_enetaddr[3],
+		       rom_enetaddr[4], rom_enetaddr[5]);
+		printf("  \"ethaddr\" value: %02X:%02X:%02X:%02X:%02X:%02X\n",
+		       env_enetaddr[0], env_enetaddr[1],
+		       env_enetaddr[2], env_enetaddr[3],
+		       env_enetaddr[4], env_enetaddr[5]) ;
+		debug("### Using MAC address from environment\n");
+	}
+	if (!tmp) {
+		char ethaddr[20];
+
+		/* There is no MAC address in the environment, so we initialize
+		 * it from the value in the ROM. */
+		sprintf(ethaddr, "%02X:%02X:%02X:%02X:%02X:%02X",
+			rom_enetaddr[0], rom_enetaddr[1],
+			rom_enetaddr[2], rom_enetaddr[3],
+			rom_enetaddr[4], rom_enetaddr[5]) ;
+		debug("### Setting environment from ROM MAC address = \"%s\"\n",
+		      ethaddr);
+		setenv("ethaddr", ethaddr);
+	}
+}

board/davinci/common/misc.h

@@ -0,0 +1,32 @@
+/*
+ * Copyright (C) 2008 Lyrtech <www.lyrtech.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#ifndef __MISC_H
+#define __MISC_H
+
+extern void timer_init(void);
+extern int eth_hw_init(void);
+
+void dv_display_clk_infos(void);
+int dvevm_read_mac_address(uint8_t *buf);
+void dv_configure_mac_address(uint8_t *rom_enetaddr);
+
+#endif /* __MISC_H */

board/davinci/common/psc.c

@@ -0,0 +1,117 @@
+/*
+ * Power and Sleep Controller (PSC) functions.
+ *
+ * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
+ * Copyright (C) 2008 Lyrtech <www.lyrtech.com>
+ * Copyright (C) 2004 Texas Instruments.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#include <common.h>
+#include <asm/arch/hardware.h>
+
+/*
+ * The DM6446 includes two separate power domains: "Always On" and "DSP". The
+ * "Always On" power domain is always on when the chip is on. The "Always On"
+ * domain is powered by the VDD pins of the DM6446. The majority of the
+ * DM6446's modules lie within the "Always On" power domain. A separate
+ * domain called the "DSP" domain houses the C64x+ and VICP. The "DSP" domain
+ * is not always on. The "DSP" power domain is powered by the CVDDDSP pins of
+ * the DM6446.
+ */
+
+/* Works on Always On power domain only (no PD argument) */
+void lpsc_on(unsigned int id)
+{
+	dv_reg_p mdstat, mdctl;
+
+	if (id >= DAVINCI_LPSC_GEM)
+		return;			/* Don't work on DSP Power Domain */
+
+	mdstat = REG_P(PSC_MDSTAT_BASE + (id * 4));
+	mdctl = REG_P(PSC_MDCTL_BASE + (id * 4));
+
+	while (REG(PSC_PTSTAT) & 0x01);
+
+	if ((*mdstat & 0x1f) == 0x03)
+		return;			/* Already on and enabled */
+
+	*mdctl |= 0x03;
+
+	/* Special treatment for some modules as for sprue14 p.7.4.2 */
+	switch (id) {
+	case DAVINCI_LPSC_VPSSSLV:
+	case DAVINCI_LPSC_EMAC:
+	case DAVINCI_LPSC_EMAC_WRAPPER:
+	case DAVINCI_LPSC_MDIO:
+	case DAVINCI_LPSC_USB:
+	case DAVINCI_LPSC_ATA:
+	case DAVINCI_LPSC_VLYNQ:
+	case DAVINCI_LPSC_UHPI:
+	case DAVINCI_LPSC_DDR_EMIF:
+	case DAVINCI_LPSC_AEMIF:
+	case DAVINCI_LPSC_MMC_SD:
+	case DAVINCI_LPSC_MEMSTICK:
+	case DAVINCI_LPSC_McBSP:
+	case DAVINCI_LPSC_GPIO:
+		*mdctl |= 0x200;
+		break;
+	}
+
+	REG(PSC_PTCMD) = 0x01;
+
+	while (REG(PSC_PTSTAT) & 0x03);
+	while ((*mdstat & 0x1f) != 0x03);	/* Probably an overkill... */
+}
+
+/* If DSPLINK is used, we don't want U-Boot to power on the DSP. */
+#if !defined(CFG_USE_DSPLINK)
+void dsp_on(void)
+{
+	int i;
+
+	if (REG(PSC_PDSTAT1) & 0x1f)
+		return;			/* Already on */
+
+	REG(PSC_GBLCTL) |= 0x01;
+	REG(PSC_PDCTL1) |= 0x01;
+	REG(PSC_PDCTL1) &= ~0x100;
+	REG(PSC_MDCTL_BASE + (DAVINCI_LPSC_GEM * 4)) |= 0x03;
+	REG(PSC_MDCTL_BASE + (DAVINCI_LPSC_GEM * 4)) &= 0xfffffeff;
+	REG(PSC_MDCTL_BASE + (DAVINCI_LPSC_IMCOP * 4)) |= 0x03;
+	REG(PSC_MDCTL_BASE + (DAVINCI_LPSC_IMCOP * 4)) &= 0xfffffeff;
+	REG(PSC_PTCMD) = 0x02;
+
+	for (i = 0; i < 100; i++) {
+		if (REG(PSC_EPCPR) & 0x02)
+			break;
+	}
+
+	REG(PSC_CHP_SHRTSW) = 0x01;
+	REG(PSC_PDCTL1) |= 0x100;
+	REG(PSC_EPCCR) = 0x02;
+
+	for (i = 0; i < 100; i++) {
+		if (!(REG(PSC_PTSTAT) & 0x02))
+			break;
+	}
+
+	REG(PSC_GBLCTL) &= ~0x1f;
+}
+#endif /* CFG_USE_DSPLINK */

board/davinci/common/psc.h

@@ -0,0 +1,28 @@
+/*
+ * Copyright (C) 2008 Lyrtech <www.lyrtech.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#ifndef __PSC_H
+#define __PSC_H
+
+void lpsc_on(unsigned int id);
+void dsp_on(void);
+
+#endif /* __PSC_H */

board/davinci/dv-evm/dv_board.c

@@ -1,202 +0,0 @@
-/*
- * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
- *
- * Parts are shamelessly stolen from various TI sources, original copyright
- * follows:
- * -----------------------------------------------------------------
- *
- * Copyright (C) 2004 Texas Instruments.
- *
- * ----------------------------------------------------------------------------
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License
- *  along with this program; if not, write to the Free Software
- *  Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- * ----------------------------------------------------------------------------
- */
-
-#include <common.h>
-#include <i2c.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/emac_defs.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-extern void	timer_init(void);
-extern int	eth_hw_init(void);
-
-
-/* Works on Always On power domain only (no PD argument) */
-void lpsc_on(unsigned int id)
-{
-	dv_reg_p	mdstat, mdctl;
-
-	if (id >= DAVINCI_LPSC_GEM)
-		return;			/* Don't work on DSP Power Domain */
-
-	mdstat = REG_P(PSC_MDSTAT_BASE + (id * 4));
-	mdctl = REG_P(PSC_MDCTL_BASE + (id * 4));
-
-	while (REG(PSC_PTSTAT) & 0x01) {;}
-
-	if ((*mdstat & 0x1f) == 0x03)
-		return;			/* Already on and enabled */
-
-	*mdctl |= 0x03;
-
-	/* Special treatment for some modules as for sprue14 p.7.4.2 */
-	if (	(id == DAVINCI_LPSC_VPSSSLV) ||
-		(id == DAVINCI_LPSC_EMAC) ||
-		(id == DAVINCI_LPSC_EMAC_WRAPPER) ||
-		(id == DAVINCI_LPSC_MDIO) ||
-		(id == DAVINCI_LPSC_USB) ||
-		(id == DAVINCI_LPSC_ATA) ||
-		(id == DAVINCI_LPSC_VLYNQ) ||
-		(id == DAVINCI_LPSC_UHPI) ||
-		(id == DAVINCI_LPSC_DDR_EMIF) ||
-		(id == DAVINCI_LPSC_AEMIF) ||
-		(id == DAVINCI_LPSC_MMC_SD) ||
-		(id == DAVINCI_LPSC_MEMSTICK) ||
-		(id == DAVINCI_LPSC_McBSP) ||
-		(id == DAVINCI_LPSC_GPIO)
-	   )
-		*mdctl |= 0x200;
-
-	REG(PSC_PTCMD) = 0x01;
-
-	while (REG(PSC_PTSTAT) & 0x03) {;}
-	while ((*mdstat & 0x1f) != 0x03) {;}	/* Probably an overkill... */
-}
-
-void dsp_on(void)
-{
-	int	i;
-
-	if (REG(PSC_PDSTAT1) & 0x1f)
-		return;			/* Already on */
-
-	REG(PSC_GBLCTL) |= 0x01;
-	REG(PSC_PDCTL1) |= 0x01;
-	REG(PSC_PDCTL1) &= ~0x100;
-	REG(PSC_MDCTL_BASE + (DAVINCI_LPSC_GEM * 4)) |= 0x03;
-	REG(PSC_MDCTL_BASE + (DAVINCI_LPSC_GEM * 4)) &= 0xfffffeff;
-	REG(PSC_MDCTL_BASE + (DAVINCI_LPSC_IMCOP * 4)) |= 0x03;
-	REG(PSC_MDCTL_BASE + (DAVINCI_LPSC_IMCOP * 4)) &= 0xfffffeff;
-	REG(PSC_PTCMD) = 0x02;
-
-	for (i = 0; i < 100; i++) {
-		if (REG(PSC_EPCPR) & 0x02)
-			break;
-	}
-
-	REG(PSC_CHP_SHRTSW) = 0x01;
-	REG(PSC_PDCTL1) |= 0x100;
-	REG(PSC_EPCCR) = 0x02;
-
-	for (i = 0; i < 100; i++) {
-		if (!(REG(PSC_PTSTAT) & 0x02))
-			break;
-	}
-
-	REG(PSC_GBLCTL) &= ~0x1f;
-}
-
-
-int board_init(void)
-{
-	/* arch number of the board */
-	gd->bd->bi_arch_number = MACH_TYPE_DAVINCI_EVM;
-
-	/* address of boot parameters */
-	gd->bd->bi_boot_params = LINUX_BOOT_PARAM_ADDR;
-
-	/* Workaround for TMS320DM6446 errata 1.3.22 */
-	REG(PSC_SILVER_BULLET) = 0;
-
-	/* Power on required peripherals */
-	lpsc_on(DAVINCI_LPSC_EMAC);
-	lpsc_on(DAVINCI_LPSC_EMAC_WRAPPER);
-	lpsc_on(DAVINCI_LPSC_MDIO);
-	lpsc_on(DAVINCI_LPSC_I2C);
-	lpsc_on(DAVINCI_LPSC_UART0);
-	lpsc_on(DAVINCI_LPSC_TIMER1);
-	lpsc_on(DAVINCI_LPSC_GPIO);
-
-	/* Powerup the DSP */
-	dsp_on();
-
-	/* Bringup UART0 out of reset */
-	REG(UART0_PWREMU_MGMT) = 0x0000e003;
-
-	/* Enable GIO3.3V cells used for EMAC */
-	REG(VDD3P3V_PWDN) = 0;
-
-	/* Enable UART0 MUX lines */
-	REG(PINMUX1) |= 1;
-
-	/* Enable EMAC and AEMIF pins */
-	REG(PINMUX0) = 0x80000c1f;
-
-	/* Enable I2C pin Mux */
-	REG(PINMUX1) |= (1 << 7);
-
-	/* Set the Bus Priority Register to appropriate value */
-	REG(VBPR) = 0x20;
-
-	timer_init();
-
-	return(0);
-}
-
-int misc_init_r (void)
-{
-	u_int8_t	tmp[20], buf[10];
-	int		i = 0;
-	int		clk = 0;
-
-	clk = ((REG(PLL2_PLLM) + 1) * 27) / ((REG(PLL2_DIV2) & 0x1f) + 1);
-
-	printf ("ARM Clock : %dMHz\n", ((REG(PLL1_PLLM) + 1) * 27 ) / 2);
-	printf ("DDR Clock : %dMHz\n", (clk / 2));
-
-	/* Set Ethernet MAC address from EEPROM */
-	if (i2c_read(CFG_I2C_EEPROM_ADDR, 0x7f00, CFG_I2C_EEPROM_ADDR_LEN, buf, 6)) {
-		printf("\nEEPROM @ 0x%02x read FAILED!!!\n", CFG_I2C_EEPROM_ADDR);
-	} else {
-		tmp[0] = 0xff;
-		for (i = 0; i < 6; i++)
-			tmp[0] &= buf[i];
-
-		if ((tmp[0] != 0xff) && (getenv("ethaddr") == NULL)) {
-			sprintf((char *)&tmp[0], "%02x:%02x:%02x:%02x:%02x:%02x",
-				buf[0], buf[1], buf[2], buf[3], buf[4], buf[5]);
-			setenv("ethaddr", (char *)&tmp[0]);
-		}
-	}
-
-	if (!eth_hw_init())
-		printf("ethernet init failed!\n");
-
-	i2c_read (0x39, 0x00, 1, (u_int8_t *)&i, 1);
-
-	setenv ("videostd", ((i  & 0x80) ? "pal" : "ntsc"));
-
-	return(0);
-}
-
-int dram_init(void)
-{
-	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
-	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
-
-	return(0);
-}

board/davinci/dvevm/Makefile

@@ -27,7 +27,7 @@ include $(TOPDIR)/config.mk
 
 LIB	= $(obj)lib$(BOARD).a
 
-COBJS	:= dv_board.o
+COBJS	:= $(BOARD).o
 SOBJS	:= board_init.o
 
 SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)

board/davinci/dvevm/dvevm.c

@@ -0,0 +1,103 @@
+/*
+ * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
+ *
+ * Parts are shamelessly stolen from various TI sources, original copyright
+ * follows:
+ * -----------------------------------------------------------------
+ *
+ * Copyright (C) 2004 Texas Instruments.
+ *
+ * ----------------------------------------------------------------------------
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License
+ *  along with this program; if not, write to the Free Software
+ *  Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ * ----------------------------------------------------------------------------
+ */
+
+#include <common.h>
+#include <i2c.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/emac_defs.h>
+#include "../common/psc.h"
+#include "../common/misc.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_init(void)
+{
+	/* arch number of the board */
+	gd->bd->bi_arch_number = MACH_TYPE_DAVINCI_EVM;
+
+	/* address of boot parameters */
+	gd->bd->bi_boot_params = LINUX_BOOT_PARAM_ADDR;
+
+	/* Workaround for TMS320DM6446 errata 1.3.22 */
+	REG(PSC_SILVER_BULLET) = 0;
+
+	/* Power on required peripherals */
+	lpsc_on(DAVINCI_LPSC_EMAC);
+	lpsc_on(DAVINCI_LPSC_EMAC_WRAPPER);
+	lpsc_on(DAVINCI_LPSC_MDIO);
+	lpsc_on(DAVINCI_LPSC_I2C);
+	lpsc_on(DAVINCI_LPSC_UART0);
+	lpsc_on(DAVINCI_LPSC_TIMER1);
+	lpsc_on(DAVINCI_LPSC_GPIO);
+
+#if !defined(CFG_USE_DSPLINK)
+	/* Powerup the DSP */
+	dsp_on();
+#endif /* CFG_USE_DSPLINK */
+
+	/* Bringup UART0 out of reset */
+	REG(UART0_PWREMU_MGMT) = 0x0000e003;
+
+	/* Enable GIO3.3V cells used for EMAC */
+	REG(VDD3P3V_PWDN) = 0;
+
+	/* Enable UART0 MUX lines */
+	REG(PINMUX1) |= 1;
+
+	/* Enable EMAC and AEMIF pins */
+	REG(PINMUX0) = 0x80000c1f;
+
+	/* Enable I2C pin Mux */
+	REG(PINMUX1) |= (1 << 7);
+
+	/* Set the Bus Priority Register to appropriate value */
+	REG(VBPR) = 0x20;
+
+	timer_init();
+
+	return(0);
+}
+
+int misc_init_r(void)
+{
+	uint8_t video_mode;
+	uint8_t eeprom_enetaddr[6];
+
+	dv_display_clk_infos();
+
+	/* Read Ethernet MAC address from EEPROM if available. */
+	if (dvevm_read_mac_address(eeprom_enetaddr))
+		dv_configure_mac_address(eeprom_enetaddr);
+
+	if (!eth_hw_init())
+		printf("ethernet init failed!\n");
+
+	i2c_read(0x39, 0x00, 1, &video_mode, 1);
+
+	setenv("videostd", ((video_mode & 0x80) ? "pal" : "ntsc"));
+
+	return(0);
+}

board/davinci/schmoogie/Makefile

@@ -27,7 +27,7 @@ include $(TOPDIR)/config.mk
 
 LIB	= $(obj)lib$(BOARD).a
 
-COBJS	:= dv_board.o
+COBJS	:= $(BOARD).o
 SOBJS	:= board_init.o
 
 SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)

board/davinci/schmoogie/schmoogie.c

@@ -28,89 +28,11 @@
 #include <i2c.h>
 #include <asm/arch/hardware.h>
 #include <asm/arch/emac_defs.h>
+#include "../common/psc.h"
+#include "../common/misc.h"
 
 DECLARE_GLOBAL_DATA_PTR;
 
-extern void	timer_init(void);
-extern int	eth_hw_init(void);
-
-
-/* Works on Always On power domain only (no PD argument) */
-void lpsc_on(unsigned int id)
-{
-	dv_reg_p	mdstat, mdctl;
-
-	if (id >= DAVINCI_LPSC_GEM)
-		return;			/* Don't work on DSP Power Domain */
-
-	mdstat = REG_P(PSC_MDSTAT_BASE + (id * 4));
-	mdctl = REG_P(PSC_MDCTL_BASE + (id * 4));
-
-	while (REG(PSC_PTSTAT) & 0x01) {;}
-
-	if ((*mdstat & 0x1f) == 0x03)
-		return;			/* Already on and enabled */
-
-	*mdctl |= 0x03;
-
-	/* Special treatment for some modules as for sprue14 p.7.4.2 */
-	if (	(id == DAVINCI_LPSC_VPSSSLV) ||
-		(id == DAVINCI_LPSC_EMAC) ||
-		(id == DAVINCI_LPSC_EMAC_WRAPPER) ||
-		(id == DAVINCI_LPSC_MDIO) ||
-		(id == DAVINCI_LPSC_USB) ||
-		(id == DAVINCI_LPSC_ATA) ||
-		(id == DAVINCI_LPSC_VLYNQ) ||
-		(id == DAVINCI_LPSC_UHPI) ||
-		(id == DAVINCI_LPSC_DDR_EMIF) ||
-		(id == DAVINCI_LPSC_AEMIF) ||
-		(id == DAVINCI_LPSC_MMC_SD) ||
-		(id == DAVINCI_LPSC_MEMSTICK) ||
-		(id == DAVINCI_LPSC_McBSP) ||
-		(id == DAVINCI_LPSC_GPIO)
-	   )
-		*mdctl |= 0x200;
-
-	REG(PSC_PTCMD) = 0x01;
-
-	while (REG(PSC_PTSTAT) & 0x03) {;}
-	while ((*mdstat & 0x1f) != 0x03) {;}	/* Probably an overkill... */
-}
-
-void dsp_on(void)
-{
-	int	i;
-
-	if (REG(PSC_PDSTAT1) & 0x1f)
-		return;			/* Already on */
-
-	REG(PSC_GBLCTL) |= 0x01;
-	REG(PSC_PDCTL1) |= 0x01;
-	REG(PSC_PDCTL1) &= ~0x100;
-	REG(PSC_MDCTL_BASE + (DAVINCI_LPSC_GEM * 4)) |= 0x03;
-	REG(PSC_MDCTL_BASE + (DAVINCI_LPSC_GEM * 4)) &= 0xfffffeff;
-	REG(PSC_MDCTL_BASE + (DAVINCI_LPSC_IMCOP * 4)) |= 0x03;
-	REG(PSC_MDCTL_BASE + (DAVINCI_LPSC_IMCOP * 4)) &= 0xfffffeff;
-	REG(PSC_PTCMD) = 0x02;
-
-	for (i = 0; i < 100; i++) {
-		if (REG(PSC_EPCPR) & 0x02)
-			break;
-	}
-
-	REG(PSC_CHP_SHRTSW) = 0x01;
-	REG(PSC_PDCTL1) |= 0x100;
-	REG(PSC_EPCCR) = 0x02;
-
-	for (i = 0; i < 100; i++) {
-		if (!(REG(PSC_PTSTAT) & 0x02))
-			break;
-	}
-
-	REG(PSC_GBLCTL) &= ~0x1f;
-}
-
-
 int board_init(void)
 {
 	/* arch number of the board */
@@ -131,8 +53,10 @@ int board_init(void)
 	lpsc_on(DAVINCI_LPSC_TIMER1);
 	lpsc_on(DAVINCI_LPSC_GPIO);
 
+#if !defined(CFG_USE_DSPLINK)
 	/* Powerup the DSP */
 	dsp_on();
+#endif /* CFG_USE_DSPLINK */
 
 	/* Bringup UART0 out of reset */
 	REG(UART0_PWREMU_MGMT) = 0x0000e003;
@@ -157,11 +81,10 @@ int board_init(void)
 	return(0);
 }
 
-int misc_init_r (void)
+int misc_init_r(void)
 {
 	u_int8_t	tmp[20], buf[10];
 	int		i = 0;
-	int		clk = 0;
 
 	/* Set serial number from UID chip */
 	u_int8_t	crc_tbl[256] = {
@@ -199,17 +122,15 @@ int misc_init_r (void)
 			0xb6, 0xe8, 0x0a, 0x54, 0xd7, 0x89, 0x6b, 0x35
 		};
 
-	clk = ((REG(PLL2_PLLM) + 1) * 27) / ((REG(PLL2_DIV2) & 0x1f) + 1);
-
-	printf ("ARM Clock : %dMHz\n", ((REG(PLL1_PLLM) + 1) * 27 ) / 2);
-	printf ("DDR Clock : %dMHz\n", (clk / 2));
+	dv_display_clk_infos();
 
 	/* Set serial number from UID chip */
 	if (i2c_read(CFG_UID_ADDR, 0, 1, buf, 8)) {
 		printf("\nUID @ 0x%02x read FAILED!!!\n", CFG_UID_ADDR);
 		forceenv("serial#", "FAILED");
 	} else {
-		if (buf[0] != 0x70) {	/* Device Family Code */
+		if (buf[0] != 0x70) {
+			/* Device Family Code */
 			printf("\nUID @ 0x%02x read FAILED!!!\n", CFG_UID_ADDR);
 			forceenv("serial#", "FAILED");
 		}
@@ -234,11 +155,3 @@ int misc_init_r (void)
 
 	return(0);
 }
-
-int dram_init(void)
-{
-	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
-	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
-
-	return(0);
-}

board/davinci/sffsdr/sffsdr.c

@@ -31,6 +31,8 @@
 #include <i2c.h>
 #include <asm/arch/hardware.h>
 #include <asm/arch/emac_defs.h>
+#include "../common/psc.h"
+#include "../common/misc.h"
 
 #define DAVINCI_A3CR     (0x01E00014)	/* EMIF-A CS3 config register. */
 #define DAVINCI_A3CR_VAL (0x3FFFFFFD)	/* EMIF-A CS3 value for FPGA. */
@@ -41,89 +43,6 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-extern void timer_init(void);
-extern int eth_hw_init(void);
-
-
-/* Works on Always On power domain only (no PD argument) */
-void lpsc_on(unsigned int id)
-{
-	dv_reg_p mdstat, mdctl;
-
-	if (id >= DAVINCI_LPSC_GEM)
-		return;			/* Don't work on DSP Power Domain */
-
-	mdstat = REG_P(PSC_MDSTAT_BASE + (id * 4));
-	mdctl = REG_P(PSC_MDCTL_BASE + (id * 4));
-
-	while (REG(PSC_PTSTAT) & 0x01);
-
-	if ((*mdstat & 0x1f) == 0x03)
-		return;			/* Already on and enabled */
-
-	*mdctl |= 0x03;
-
-	/* Special treatment for some modules as for sprue14 p.7.4.2 */
-	switch (id) {
-	case DAVINCI_LPSC_VPSSSLV:
-	case DAVINCI_LPSC_EMAC:
-	case DAVINCI_LPSC_EMAC_WRAPPER:
-	case DAVINCI_LPSC_MDIO:
-	case DAVINCI_LPSC_USB:
-	case DAVINCI_LPSC_ATA:
-	case DAVINCI_LPSC_VLYNQ:
-	case DAVINCI_LPSC_UHPI:
-	case DAVINCI_LPSC_DDR_EMIF:
-	case DAVINCI_LPSC_AEMIF:
-	case DAVINCI_LPSC_MMC_SD:
-	case DAVINCI_LPSC_MEMSTICK:
-	case DAVINCI_LPSC_McBSP:
-	case DAVINCI_LPSC_GPIO:
-		*mdctl |= 0x200;
-		break;
-	}
-
-	REG(PSC_PTCMD) = 0x01;
-
-	while (REG(PSC_PTSTAT) & 0x03);
-	while ((*mdstat & 0x1f) != 0x03);	/* Probably an overkill... */
-}
-
-#if !defined(CFG_USE_DSPLINK)
-void dsp_on(void)
-{
-	int i;
-
-	if (REG(PSC_PDSTAT1) & 0x1f)
-		return;			/* Already on */
-
-	REG(PSC_GBLCTL) |= 0x01;
-	REG(PSC_PDCTL1) |= 0x01;
-	REG(PSC_PDCTL1) &= ~0x100;
-	REG(PSC_MDCTL_BASE + (DAVINCI_LPSC_GEM * 4)) |= 0x03;
-	REG(PSC_MDCTL_BASE + (DAVINCI_LPSC_GEM * 4)) &= 0xfffffeff;
-	REG(PSC_MDCTL_BASE + (DAVINCI_LPSC_IMCOP * 4)) |= 0x03;
-	REG(PSC_MDCTL_BASE + (DAVINCI_LPSC_IMCOP * 4)) &= 0xfffffeff;
-	REG(PSC_PTCMD) = 0x02;
-
-	for (i = 0; i < 100; i++) {
-		if (REG(PSC_EPCPR) & 0x02)
-			break;
-	}
-
-	REG(PSC_CHP_SHRTSW) = 0x01;
-	REG(PSC_PDCTL1) |= 0x100;
-	REG(PSC_EPCCR) = 0x02;
-
-	for (i = 0; i < 100; i++) {
-		if (!(REG(PSC_PTSTAT) & 0x02))
-			break;
-	}
-
-	REG(PSC_GBLCTL) &= ~0x1f;
-}
-#endif /* CFG_USE_DSPLINK */
-
 int board_init(void)
 {
 	/* arch number of the board */
@@ -172,8 +91,10 @@ int board_init(void)
 	return(0);
 }
 
-/* Read ethernet MAC address from Integrity data structure inside EEPROM. */
-int read_mac_address(uint8_t *buf)
+/* Read ethernet MAC address from Integrity data structure inside EEPROM.
+ * Returns 1 if found, 0 otherwise.
+ */
+static int sffsdr_read_mac_address(uint8_t *buf)
 {
 	u_int32_t value, mac[2], address;
 
@@ -182,7 +103,7 @@ int read_mac_address(uint8_t *buf)
 		     CFG_I2C_EEPROM_ADDR_LEN, (uint8_t *) &value, 4))
 		goto err;
 	if (value != INTEGRITY_CHECKWORD_VALUE)
-		return 1;
+		return 0;
 
 	/* Read SYSCFG structure offset. */
 	if (i2c_read(CFG_I2C_EEPROM_ADDR, INTEGRITY_SYSCFG_OFFSET,
@@ -216,30 +137,23 @@ int read_mac_address(uint8_t *buf)
 	buf[4] = mac[1] >> 24;
 	buf[5] = mac[1] >> 16;
 
-	return 0;
+	return 1; /* Found */
 
 err:
 	printf("Read from EEPROM @ 0x%02x failed\n", CFG_I2C_EEPROM_ADDR);
-	return 1;
+	return 0;
 }
 
 /* Platform dependent initialisation. */
 int misc_init_r(void)
 {
-	int i;
-	u_int8_t i2cbuf;
-	u_int8_t env_enetaddr[6], eeprom_enetaddr[6];
-	char *tmp = getenv("ethaddr");
-	char *end;
-	int clk;
+	uint8_t i2cbuf;
+	uint8_t eeprom_enetaddr[6];
 
 	/* EMIF-A CS3 configuration for FPGA. */
 	REG(DAVINCI_A3CR) = DAVINCI_A3CR_VAL;
 
-	clk = ((REG(PLL2_PLLM) + 1) * 27) / ((REG(PLL2_DIV2) & 0x1f) + 1);
-
-	printf("ARM Clock: %dMHz\n", ((REG(PLL1_PLLM) + 1) * 27) / 2);
-	printf("DDR Clock: %dMHz\n", (clk / 2));
+	dv_display_clk_infos();
 
 	/* Configure I2C switch (PCA9543) to enable channel 0. */
 	i2cbuf = CFG_I2C_PCA9543_ENABLE_CH0;
@@ -249,43 +163,9 @@ int misc_init_r(void)
 		return 1;
 	}
 
-	/* Read Ethernet MAC address from the U-Boot environment. */
-	for (i = 0; i < 6; i++) {
-		env_enetaddr[i] = tmp ? simple_strtoul(tmp, &end, 16) : 0;
-		if (tmp)
-			tmp = (*end) ? end+1 : end;
-	}
-
-	/* Read Ethernet MAC address from EEPROM. */
-	if (read_mac_address(eeprom_enetaddr) == 0) {
-		if (memcmp(env_enetaddr, "\0\0\0\0\0\0", 6) != 0 &&
-		    memcmp(env_enetaddr, eeprom_enetaddr, 6) != 0) {
-			printf("\nWarning: MAC addresses don't match:\n");
-			printf("\tHW MAC address:  "
-			       "%02X:%02X:%02X:%02X:%02X:%02X\n",
-			       eeprom_enetaddr[0], eeprom_enetaddr[1],
-			       eeprom_enetaddr[2], eeprom_enetaddr[3],
-			       eeprom_enetaddr[4], eeprom_enetaddr[5]);
-			printf("\t\"ethaddr\" value: "
-			       "%02X:%02X:%02X:%02X:%02X:%02X\n",
-			       env_enetaddr[0], env_enetaddr[1],
-			       env_enetaddr[2], env_enetaddr[3],
-			       env_enetaddr[4], env_enetaddr[5]) ;
-			debug("### Set MAC addr from environment\n");
-			memcpy(eeprom_enetaddr, env_enetaddr, 6);
-		}
-		if (!tmp) {
-			char ethaddr[20];
-
-			sprintf(ethaddr, "%02X:%02X:%02X:%02X:%02X:%02X",
-				eeprom_enetaddr[0], eeprom_enetaddr[1],
-				eeprom_enetaddr[2], eeprom_enetaddr[3],
-				eeprom_enetaddr[4], eeprom_enetaddr[5]) ;
-			debug("### Set environment from HW MAC addr = \"%s\"\n",
-			      ethaddr);
-			setenv("ethaddr", ethaddr);
-		}
-	}
+	/* Read Ethernet MAC address from EEPROM if available. */
+	if (sffsdr_read_mac_address(eeprom_enetaddr))
+		dv_configure_mac_address(eeprom_enetaddr);
 
 	if (!eth_hw_init())
 		printf("Ethernet init failed\n");
@@ -296,11 +176,3 @@ int misc_init_r(void)
 
 	return(0);
 }
-
-int dram_init(void)
-{
-	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
-	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
-
-	return(0);
-}

board/davinci/sonata/Makefile

@@ -27,7 +27,7 @@ include $(TOPDIR)/config.mk
 
 LIB	= $(obj)lib$(BOARD).a
 
-COBJS	:= dv_board.o
+COBJS	:= $(BOARD).o
 SOBJS	:= board_init.o
 
 SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)

board/davinci/sonata/dv_board.c

@@ -1,199 +0,0 @@
-/*
- * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
- *
- * Parts are shamelessly stolen from various TI sources, original copyright
- * follows:
- * -----------------------------------------------------------------
- *
- * Copyright (C) 2004 Texas Instruments.
- *
- * ----------------------------------------------------------------------------
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License
- *  along with this program; if not, write to the Free Software
- *  Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- * ----------------------------------------------------------------------------
- */
-
-#include <common.h>
-#include <i2c.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/emac_defs.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-extern void	timer_init(void);
-extern int	eth_hw_init(void);
-
-
-/* Works on Always On power domain only (no PD argument) */
-void lpsc_on(unsigned int id)
-{
-	dv_reg_p	mdstat, mdctl;
-
-	if (id >= DAVINCI_LPSC_GEM)
-		return;			/* Don't work on DSP Power Domain */
-
-	mdstat = REG_P(PSC_MDSTAT_BASE + (id * 4));
-	mdctl = REG_P(PSC_MDCTL_BASE + (id * 4));
-
-	while (REG(PSC_PTSTAT) & 0x01) {;}
-
-	if ((*mdstat & 0x1f) == 0x03)
-		return;			/* Already on and enabled */
-
-	*mdctl |= 0x03;
-
-	/* Special treatment for some modules as for sprue14 p.7.4.2 */
-	if (	(id == DAVINCI_LPSC_VPSSSLV) ||
-		(id == DAVINCI_LPSC_EMAC) ||
-		(id == DAVINCI_LPSC_EMAC_WRAPPER) ||
-		(id == DAVINCI_LPSC_MDIO) ||
-		(id == DAVINCI_LPSC_USB) ||
-		(id == DAVINCI_LPSC_ATA) ||
-		(id == DAVINCI_LPSC_VLYNQ) ||
-		(id == DAVINCI_LPSC_UHPI) ||
-		(id == DAVINCI_LPSC_DDR_EMIF) ||
-		(id == DAVINCI_LPSC_AEMIF) ||
-		(id == DAVINCI_LPSC_MMC_SD) ||
-		(id == DAVINCI_LPSC_MEMSTICK) ||
-		(id == DAVINCI_LPSC_McBSP) ||
-		(id == DAVINCI_LPSC_GPIO)
-	   )
-		*mdctl |= 0x200;
-
-	REG(PSC_PTCMD) = 0x01;
-
-	while (REG(PSC_PTSTAT) & 0x03) {;}
-	while ((*mdstat & 0x1f) != 0x03) {;}	/* Probably an overkill... */
-}
-
-void dsp_on(void)
-{
-	int	i;
-
-	if (REG(PSC_PDSTAT1) & 0x1f)
-		return;			/* Already on */
-
-	REG(PSC_GBLCTL) |= 0x01;
-	REG(PSC_PDCTL1) |= 0x01;
-	REG(PSC_PDCTL1) &= ~0x100;
-	REG(PSC_MDCTL_BASE + (DAVINCI_LPSC_GEM * 4)) |= 0x03;
-	REG(PSC_MDCTL_BASE + (DAVINCI_LPSC_GEM * 4)) &= 0xfffffeff;
-	REG(PSC_MDCTL_BASE + (DAVINCI_LPSC_IMCOP * 4)) |= 0x03;
-	REG(PSC_MDCTL_BASE + (DAVINCI_LPSC_IMCOP * 4)) &= 0xfffffeff;
-	REG(PSC_PTCMD) = 0x02;
-
-	for (i = 0; i < 100; i++) {
-		if (REG(PSC_EPCPR) & 0x02)
-			break;
-	}
-
-	REG(PSC_CHP_SHRTSW) = 0x01;
-	REG(PSC_PDCTL1) |= 0x100;
-	REG(PSC_EPCCR) = 0x02;
-
-	for (i = 0; i < 100; i++) {
-		if (!(REG(PSC_PTSTAT) & 0x02))
-			break;
-	}
-
-	REG(PSC_GBLCTL) &= ~0x1f;
-}
-
-
-int board_init(void)
-{
-	/* arch number of the board */
-	gd->bd->bi_arch_number = MACH_TYPE_SONATA;
-
-	/* address of boot parameters */
-	gd->bd->bi_boot_params = LINUX_BOOT_PARAM_ADDR;
-
-	/* Workaround for TMS320DM6446 errata 1.3.22 */
-	REG(PSC_SILVER_BULLET) = 0;
-
-	/* Power on required peripherals */
-	lpsc_on(DAVINCI_LPSC_EMAC);
-	lpsc_on(DAVINCI_LPSC_EMAC_WRAPPER);
-	lpsc_on(DAVINCI_LPSC_MDIO);
-	lpsc_on(DAVINCI_LPSC_I2C);
-	lpsc_on(DAVINCI_LPSC_UART0);
-	lpsc_on(DAVINCI_LPSC_TIMER1);
-	lpsc_on(DAVINCI_LPSC_GPIO);
-
-	/* Powerup the DSP */
-	dsp_on();
-
-	/* Bringup UART0 out of reset */
-	REG(UART0_PWREMU_MGMT) = 0x0000e003;
-
-	/* Enable GIO3.3V cells used for EMAC */
-	REG(VDD3P3V_PWDN) = 0;
-
-	/* Enable UART0 MUX lines */
-	REG(PINMUX1) |= 1;
-
-	/* Enable EMAC and AEMIF pins */
-	REG(PINMUX0) = 0x80000c1f;
-
-	/* Enable I2C pin Mux */
-	REG(PINMUX1) |= (1 << 7);
-
-	/* Set the Bus Priority Register to appropriate value */
-	REG(VBPR) = 0x20;
-
-	timer_init();
-
-	return(0);
-}
-
-int misc_init_r (void)
-{
-	u_int8_t	tmp[20], buf[10];
-	int		i = 0;
-	int		clk = 0;
-
-
-	clk = ((REG(PLL2_PLLM) + 1) * 27) / ((REG(PLL2_DIV2) & 0x1f) + 1);
-
-	printf ("ARM Clock : %dMHz\n", ((REG(PLL1_PLLM) + 1) * 27 ) / 2);
-	printf ("DDR Clock : %dMHz\n", (clk / 2));
-
-	/* Set Ethernet MAC address from EEPROM */
-	if (i2c_read(CFG_I2C_EEPROM_ADDR, 0x7f00, CFG_I2C_EEPROM_ADDR_LEN, buf, 6)) {
-		printf("\nEEPROM @ 0x%02x read FAILED!!!\n", CFG_I2C_EEPROM_ADDR);
-	} else {
-		tmp[0] = 0xff;
-		for (i = 0; i < 6; i++)
-			tmp[0] &= buf[i];
-
-		if ((tmp[0] != 0xff) && (getenv("ethaddr") == NULL)) {
-			sprintf((char *)&tmp[0], "%02x:%02x:%02x:%02x:%02x:%02x",
-				buf[0], buf[1], buf[2], buf[3], buf[4], buf[5]);
-			setenv("ethaddr", (char *)&tmp[0]);
-		}
-	}
-
-	if (!eth_hw_init())
-		printf("ethernet init failed!\n");
-
-	return(0);
-}
-
-int dram_init(void)
-{
-	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
-	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
-
-	return(0);
-}

board/davinci/sonata/sonata.c

@@ -0,0 +1,97 @@
+/*
+ * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
+ *
+ * Parts are shamelessly stolen from various TI sources, original copyright
+ * follows:
+ * -----------------------------------------------------------------
+ *
+ * Copyright (C) 2004 Texas Instruments.
+ *
+ * ----------------------------------------------------------------------------
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License
+ *  along with this program; if not, write to the Free Software
+ *  Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ * ----------------------------------------------------------------------------
+ */
+
+#include <common.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/emac_defs.h>
+#include "../common/psc.h"
+#include "../common/misc.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_init(void)
+{
+	/* arch number of the board */
+	gd->bd->bi_arch_number = MACH_TYPE_SONATA;
+
+	/* address of boot parameters */
+	gd->bd->bi_boot_params = LINUX_BOOT_PARAM_ADDR;
+
+	/* Workaround for TMS320DM6446 errata 1.3.22 */
+	REG(PSC_SILVER_BULLET) = 0;
+
+	/* Power on required peripherals */
+	lpsc_on(DAVINCI_LPSC_EMAC);
+	lpsc_on(DAVINCI_LPSC_EMAC_WRAPPER);
+	lpsc_on(DAVINCI_LPSC_MDIO);
+	lpsc_on(DAVINCI_LPSC_I2C);
+	lpsc_on(DAVINCI_LPSC_UART0);
+	lpsc_on(DAVINCI_LPSC_TIMER1);
+	lpsc_on(DAVINCI_LPSC_GPIO);
+
+#if !defined(CFG_USE_DSPLINK)
+	/* Powerup the DSP */
+	dsp_on();
+#endif /* CFG_USE_DSPLINK */
+
+	/* Bringup UART0 out of reset */
+	REG(UART0_PWREMU_MGMT) = 0x0000e003;
+
+	/* Enable GIO3.3V cells used for EMAC */
+	REG(VDD3P3V_PWDN) = 0;
+
+	/* Enable UART0 MUX lines */
+	REG(PINMUX1) |= 1;
+
+	/* Enable EMAC and AEMIF pins */
+	REG(PINMUX0) = 0x80000c1f;
+
+	/* Enable I2C pin Mux */
+	REG(PINMUX1) |= (1 << 7);
+
+	/* Set the Bus Priority Register to appropriate value */
+	REG(VBPR) = 0x20;
+
+	timer_init();
+
+	return(0);
+}
+
+int misc_init_r(void)
+{
+	uint8_t eeprom_enetaddr[6];
+
+	dv_display_clk_infos();
+
+	/* Read Ethernet MAC address from EEPROM if available. */
+	if (dvevm_read_mac_address(eeprom_enetaddr))
+		dv_configure_mac_address(eeprom_enetaddr);
+
+	if (!eth_hw_init())
+		printf("ethernet init failed!\n");
+
+	return(0);
+}

board/delta/nand.c

@@ -23,7 +23,7 @@
 #include <common.h>
 
 #if defined(CONFIG_CMD_NAND)
-#if !defined(CFG_NAND_LEGACY)
+#if !defined(CONFIG_NAND_LEGACY)
 
 #include <nand.h>
 #include <asm/arch/pxa-regs.h>
@@ -69,7 +69,7 @@ static struct nand_oobinfo delta_oob = {
 /*
  * not required for Monahans DFC
  */
-static void dfc_hwcontrol(struct mtd_info *mtdinfo, int cmd)
+static void dfc_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl)
 {
 	return;
 }
@@ -110,30 +110,6 @@ static void dfc_write_buf(struct mtd_info *mtd, const u_char *buf, int len)
 }
 
 
-/*
- * These functions are quite problematic for the DFC. Luckily they are
- * not used in the current nand code, except for nand_command, which
- * we've defined our own anyway. The problem is, that we always need
- * to write 4 bytes to the DFC Data Buffer, but in these functions we
- * don't know if to buffer the bytes/half words until we've gathered 4
- * bytes or if to send them straight away.
- *
- * Solution: Don't use these with Mona's DFC and complain loudly.
- */
-static void dfc_write_word(struct mtd_info *mtd, u16 word)
-{
-	printf("dfc_write_word: WARNING, this function does not work with the Monahans DFC!\n");
-}
-static void dfc_write_byte(struct mtd_info *mtd, u_char byte)
-{
-	printf("dfc_write_byte: WARNING, this function does not work with the Monahans DFC!\n");
-}
-
-/* The original:
- * static void dfc_read_buf(struct mtd_info *mtd, const u_char *buf, int len)
- *
- * Shouldn't this be "u_char * const buf" ?
- */
 static void dfc_read_buf(struct mtd_info *mtd, u_char* const buf, int len)
 {
 	int i=0, j;
@@ -168,7 +144,7 @@ static void dfc_read_buf(struct mtd_info *mtd, u_char* const buf, int len)
  */
 static u16 dfc_read_word(struct mtd_info *mtd)
 {
-	printf("dfc_write_byte: UNIMPLEMENTED.\n");
+	printf("dfc_read_word: UNIMPLEMENTED.\n");
 	return 0;
 }
 
@@ -289,9 +265,10 @@ static void dfc_new_cmd(void)
 
 /* this function is called after Programm and Erase Operations to
  * check for success or failure */
-static int dfc_wait(struct mtd_info *mtd, struct nand_chip *this, int state)
+static int dfc_wait(struct mtd_info *mtd, struct nand_chip *this)
 {
 	unsigned long ndsr=0, event=0;
+	int state = this->state;
 
 	if(state == FL_WRITING) {
 		event = NDSR_CS0_CMDD | NDSR_CS0_BBD;
@@ -439,7 +416,7 @@ static void dfc_gpio_init(void)
  * - dev_ready: hardwarespecific function for  accesing device ready/busy line
  * - enable_hwecc?: function to enable (reset)  hardware ecc generator. Must
  *   only be provided if a hardware ECC is available
- * - eccmode: mode of ecc, see defines
+ * - ecc.mode: mode of ecc, see defines
  * - chip_delay: chip dependent delay for transfering data from array to
  *   read regs (tR)
  * - options: various chip options. They can partly be set to inform
@@ -561,20 +538,18 @@ int board_nand_init(struct nand_chip *nand)
 	/*	wait(10); */
 
 
-	nand->hwcontrol = dfc_hwcontrol;
+	nand->cmd_ctrl = dfc_hwcontrol;
 /*	nand->dev_ready = dfc_device_ready; */
-	nand->eccmode = NAND_ECC_SOFT;
+	nand->ecc.mode = NAND_ECC_SOFT;
 	nand->options = NAND_BUSWIDTH_16;
 	nand->waitfunc = dfc_wait;
 	nand->read_byte = dfc_read_byte;
-	nand->write_byte = dfc_write_byte;
 	nand->read_word = dfc_read_word;
-	nand->write_word = dfc_write_word;
 	nand->read_buf = dfc_read_buf;
 	nand->write_buf = dfc_write_buf;
 
 	nand->cmdfunc = dfc_cmdfunc;
-	nand->autooob = &delta_oob;
+/*	nand->autooob = &delta_oob; */
 	nand->badblock_pattern = &delta_bbt_descr;
 	return 0;
 }

board/eXalion/eXalion.c

@@ -30,6 +30,7 @@
 #include <asm/io.h>
 #include <pci.h>
 #include <ide.h>
+#include <netdev.h>
 #include "piix_pci.h"
 #include "eXalion.h"
 
@@ -290,3 +291,8 @@ void pci_init_board (void)
 {
 	pci_mpc824x_init (&hose);
 }
+
+int board_eth_init(bd_t *bis)
+{
+	return pci_eth_init(bis);
+}

board/earthlcd/favr-32-ezkit/Makefile

@@ -0,0 +1,42 @@
+#
+# (C) Copyright 2001-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# Copyright (C) 2008 Atmel Corporation
+#
+# See file CREDITS for list of people who contributed to this project.
+#
+# This program is free software; you can redistribute it and/or modify it under
+# the terms of the GNU General Public License as published by the Free Software
+# Foundation; either version 2 of the License, or (at your option) any later
+# version.
+#
+# This program is distributed in the hope that it will be useful, but WITHOUT
+# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
+# FOR A PARTICULAR PURPOSE.  See the GNU General Public License for more
+# details.
+#
+# You should have received a copy of the GNU General Public License along with
+# this program; if not, write to the Free Software Foundation, Inc., 59 Temple
+# Place, Suite 330, Boston, MA 02111-1307 USA
+
+include $(TOPDIR)/config.mk
+
+LIB	:= $(obj)lib$(BOARD).a
+
+COBJS	:= $(BOARD).o flash.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(SOBJS) $(COBJS))
+
+$(LIB): $(obj).depend $(OBJS)
+	$(AR) $(ARFLAGS) $@ $(OBJS)
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################

board/earthlcd/favr-32-ezkit/config.mk

@@ -0,0 +1,4 @@
+PLATFORM_RELFLAGS	+= -ffunction-sections -fdata-sections
+PLATFORM_LDFLAGS	+= --gc-sections
+TEXT_BASE		= 0x00000000
+LDSCRIPT		= $(obj)board/earthlcd/favr-32-ezkit/u-boot.lds

board/earthlcd/favr-32-ezkit/favr-32-ezkit.c

@@ -0,0 +1,95 @@
+/*
+ * Copyright (C) 2008 Atmel Corporation
+ *
+ * See file CREDITS for list of people who contributed to this project.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the Free
+ * Software Foundation; either version 2 of the License, or (at your option)
+ * any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program; if not, write to the Free Software Foundation, Inc., 59 Temple
+ * Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+#include <common.h>
+#include <netdev.h>
+
+#include <asm/io.h>
+#include <asm/sdram.h>
+#include <asm/arch/clk.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/hmatrix.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static const struct sdram_config sdram_config = {
+	/* MT48LC4M32B2P-6 (16 MB) */
+	.data_bits	= SDRAM_DATA_32BIT,
+	.row_bits	= 12,
+	.col_bits	= 8,
+	.bank_bits	= 2,
+	.cas		= 3,
+	.twr		= 2,
+	.trc		= 7,
+	.trp		= 2,
+	.trcd		= 2,
+	.tras		= 5,
+	.txsr		= 5,
+	/* 15.6 us */
+	.refresh_period	= (156 * (SDRAMC_BUS_HZ / 1000)) / 10000,
+};
+
+int board_early_init_f(void)
+{
+	/* Enable SDRAM in the EBI mux */
+	hmatrix_slave_write(EBI, SFR, HMATRIX_BIT(EBI_SDRAM_ENABLE));
+
+	gpio_enable_ebi();
+	gpio_enable_usart3();
+#if defined(CONFIG_MACB)
+	gpio_enable_macb0();
+#endif
+#if defined(CONFIG_MMC)
+	gpio_enable_mmci();
+#endif
+
+	return 0;
+}
+
+phys_size_t initdram(int board_type)
+{
+	unsigned long expected_size;
+	unsigned long actual_size;
+	void *sdram_base;
+
+	sdram_base = map_physmem(EBI_SDRAM_BASE, EBI_SDRAM_SIZE, MAP_NOCACHE);
+
+	expected_size = sdram_init(sdram_base, &sdram_config);
+	actual_size = get_ram_size(sdram_base, expected_size);
+
+	unmap_physmem(sdram_base, EBI_SDRAM_SIZE);
+
+	if (expected_size != actual_size)
+		printf("Warning: Only %lu of %lu MiB SDRAM is working\n",
+				actual_size >> 20, expected_size >> 20);
+
+	return actual_size;
+}
+
+void board_init_info(void)
+{
+	gd->bd->bi_phy_id[0] = 0x01;
+}
+
+#if defined(CONFIG_MACB) && defined(CONFIG_CMD_NET)
+int board_eth_init(bd_t *bi)
+{
+	return macb_eth_initialize(0, (void *)MACB0_BASE, bi->bi_phy_id[0]);
+}
+#endif

board/earthlcd/favr-32-ezkit/flash.c

@@ -0,0 +1,230 @@
+/*
+ * Copyright (C) 2008 Atmel Corporation
+ *
+ * See file CREDITS for list of people who contributed to this project.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the Free
+ * Software Foundation; either version 2 of the License, or (at your option)
+ * any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program; if not, write to the Free Software Foundation, Inc., 59 Temple
+ * Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+#include <common.h>
+
+#ifdef CONFIG_FAVR32_EZKIT_EXT_FLASH
+#include <asm/cacheflush.h>
+#include <asm/io.h>
+#include <asm/sections.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+flash_info_t flash_info[1];
+
+static void flash_identify(uint16_t *flash, flash_info_t *info)
+{
+	unsigned long flags;
+
+	flags = disable_interrupts();
+
+	dcache_flush_unlocked();
+
+	writew(0xaa, flash + 0x555);
+	writew(0x55, flash + 0xaaa);
+	writew(0x90, flash + 0x555);
+	info->flash_id = readl(flash);
+	writew(0xff, flash);
+
+	readw(flash);
+
+	if (flags)
+		enable_interrupts();
+}
+
+unsigned long flash_init(void)
+{
+	unsigned long addr;
+	unsigned int i;
+
+	flash_info[0].size = CFG_FLASH_SIZE;
+	flash_info[0].sector_count = 135;
+
+	flash_identify(uncached((void *)CFG_FLASH_BASE), &flash_info[0]);
+
+	for (i = 0, addr = 0; i < 8; i++, addr += 0x2000)
+		flash_info[0].start[i] = addr;
+	for (; i < flash_info[0].sector_count; i++, addr += 0x10000)
+		flash_info[0].start[i] = addr;
+
+	return CFG_FLASH_SIZE;
+}
+
+void flash_print_info(flash_info_t *info)
+{
+	printf("Flash: Vendor ID: 0x%02lx, Product ID: 0x%02lx\n",
+	       info->flash_id >> 16, info->flash_id & 0xffff);
+	printf("Size: %ld MB in %d sectors\n",
+	       info->size >> 10, info->sector_count);
+}
+
+int flash_erase(flash_info_t *info, int s_first, int s_last)
+{
+	unsigned long flags;
+	unsigned long start_time;
+	uint16_t *fb, *sb;
+	unsigned int i;
+	int ret;
+	uint16_t status;
+
+	if ((s_first < 0) || (s_first > s_last)
+	    || (s_last >= info->sector_count)) {
+		puts("Error: first and/or last sector out of range\n");
+		return ERR_INVAL;
+	}
+
+	for (i = s_first; i < s_last; i++)
+		if (info->protect[i]) {
+			printf("Error: sector %d is protected\n", i);
+			return ERR_PROTECTED;
+		}
+
+	fb = (uint16_t *)uncached(info->start[0]);
+
+	dcache_flush_unlocked();
+
+	for (i = s_first; (i <= s_last) && !ctrlc(); i++) {
+		printf("Erasing sector %3d...", i);
+
+		sb = (uint16_t *)uncached(info->start[i]);
+
+		flags = disable_interrupts();
+
+		start_time = get_timer(0);
+
+		/* Unlock sector */
+		writew(0xaa, fb + 0x555);
+		writew(0x70, sb);
+
+		/* Erase sector */
+		writew(0xaa, fb + 0x555);
+		writew(0x55, fb + 0xaaa);
+		writew(0x80, fb + 0x555);
+		writew(0xaa, fb + 0x555);
+		writew(0x55, fb + 0xaaa);
+		writew(0x30, sb);
+
+		/* Wait for completion */
+		ret = ERR_OK;
+		do {
+			/* TODO: Timeout */
+			status = readw(sb);
+		} while ((status != 0xffff) && !(status & 0x28));
+
+		writew(0xf0, fb);
+
+		/*
+		 * Make sure the command actually makes it to the bus
+		 * before we re-enable interrupts.
+		 */
+		readw(fb);
+
+		if (flags)
+			enable_interrupts();
+
+		if (status != 0xffff) {
+			printf("Flash erase error at address 0x%p: 0x%02x\n",
+			       sb, status);
+			ret = ERR_PROG_ERROR;
+			break;
+		}
+	}
+
+	if (ctrlc())
+		printf("User interrupt!\n");
+
+	return ERR_OK;
+}
+
+int write_buff(flash_info_t *info, uchar *src,
+			   ulong addr, ulong count)
+{
+	unsigned long flags;
+	uint16_t *base, *p, *s, *end;
+	uint16_t word, status, status1;
+	int ret = ERR_OK;
+
+	if (addr < info->start[0]
+	    || (addr + count) > (info->start[0] + info->size)
+	    || (addr + count) < addr) {
+		puts("Error: invalid address range\n");
+		return ERR_INVAL;
+	}
+
+	if (addr & 1 || count & 1 || (unsigned int)src & 1) {
+		puts("Error: misaligned source, destination or count\n");
+		return ERR_ALIGN;
+	}
+
+	base = (uint16_t *)uncached(info->start[0]);
+	end = (uint16_t *)uncached(addr + count);
+
+	flags = disable_interrupts();
+
+	dcache_flush_unlocked();
+	sync_write_buffer();
+
+	for (p = (uint16_t *)uncached(addr), s = (uint16_t *)src;
+	     p < end && !ctrlc(); p++, s++) {
+		word = *s;
+
+		writew(0xaa, base + 0x555);
+		writew(0x55, base + 0xaaa);
+		writew(0xa0, base + 0x555);
+		writew(word, p);
+
+		sync_write_buffer();
+
+		/* Wait for completion */
+		status1 = readw(p);
+		do {
+			/* TODO: Timeout */
+			status = status1;
+			status1 = readw(p);
+		} while (((status ^ status1) & 0x40)	/* toggled */
+			 && !(status1 & 0x28));		/* error bits */
+
+		/*
+		 * We'll need to check once again for toggle bit
+		 * because the toggle bit may stop toggling as I/O5
+		 * changes to "1" (ref at49bv642.pdf p9)
+		 */
+		status1 = readw(p);
+		status = readw(p);
+		if ((status ^ status1) & 0x40) {
+			printf("Flash write error at address 0x%p: "
+			       "0x%02x != 0x%02x\n",
+			       p, status,word);
+			ret = ERR_PROG_ERROR;
+			writew(0xf0, base);
+			readw(base);
+			break;
+		}
+
+		writew(0xf0, base);
+		readw(base);
+	}
+
+	if (flags)
+		enable_interrupts();
+
+	return ret;
+}
+
+#endif /* CONFIG_FAVR32_EZKIT_EXT_FLASH */

board/earthlcd/favr-32-ezkit/u-boot.lds

@@ -0,0 +1,71 @@
+/* -*- Fundamental -*-
+ *
+ * Copyright (C) 2008 Atmel Corporation
+ *
+ * See file CREDITS for list of people who contributed to this project.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the Free
+ * Software Foundation; either version 2 of the License, or (at your option)
+ * any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program; if not, write to the Free Software Foundation, Inc., 59 Temple
+ * Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+OUTPUT_FORMAT("elf32-avr32", "elf32-avr32", "elf32-avr32")
+OUTPUT_ARCH(avr32)
+ENTRY(_start)
+
+SECTIONS
+{
+	. = 0;
+	_text = .;
+	.text : {
+		*(.exception.text)
+		*(.text)
+		*(.text.*)
+	}
+	_etext = .;
+
+	.rodata : {
+		*(.rodata)
+		*(.rodata.*)
+	}
+
+	. = ALIGN(8);
+	_data = .;
+	.data : {
+		*(.data)
+		*(.data.*)
+	}
+
+	. = ALIGN(4);
+	__u_boot_cmd_start = .;
+	.u_boot_cmd : {
+		KEEP(*(.u_boot_cmd))
+	}
+	__u_boot_cmd_end = .;
+
+	. = ALIGN(4);
+	_got = .;
+	.got : {
+		*(.got)
+	}
+	_egot = .;
+
+	. = ALIGN(8);
+	_edata = .;
+
+	.bss (NOLOAD) : {
+		*(.bss)
+		*(.bss.*)
+	}
+	. = ALIGN(8);
+	_end = .;
+}

board/eltec/bab7xx/bab7xx.c

@@ -30,6 +30,7 @@
 #include <74xx_7xx.h>
 #include <ns87308.h>
 #include <video_fb.h>
+#include <netdev.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -244,3 +245,8 @@ void video_get_info_str (int line_number, char *info)
 #endif
 
 /*---------------------------------------------------------------------------*/
+
+int board_eth_init(bd_t *bis)
+{
+	return pci_eth_init(bis);
+}

board/eltec/elppc/elppc.c

@@ -25,6 +25,7 @@
 #include <command.h>
 #include <mpc106.h>
 #include <video_fb.h>
+#include <netdev.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -172,3 +173,8 @@ void video_get_info_str (int line_number, char *info)
 	return;
 }
 #endif
+
+int board_eth_init(bd_t *bis)
+{
+	return pci_eth_init(bis);
+}

board/esd/adciop/adciop.c

@@ -22,6 +22,7 @@
  */
 
 #include <common.h>
+#include <netdev.h>
 #include "adciop.h"
 
 /* ------------------------------------------------------------------------- */
@@ -95,3 +96,8 @@ int testdram (void)
 }
 
 /* ------------------------------------------------------------------------- */
+
+int board_eth_init(bd_t *bis)
+{
+	return pci_eth_init(bis);
+}

board/esd/apc405/apc405.c

@@ -423,16 +423,6 @@ int checkboard (void)
 	return 0;
 }
 
-phys_size_t initdram (int board_type)
-{
-	unsigned long val;
-
-	mtdcr(memcfga, mem_mb0cf);
-	val = mfdcr(memcfgd);
-
-	return (4*1024*1024 << ((val & 0x000e0000) >> 17));
-}
-
 #ifdef CONFIG_IDE_RESET
 void ide_set_reset(int on)
 {

board/esd/ar405/u-boot.lds

@@ -79,7 +79,6 @@ SECTIONS
     common/cmd_mem.o		(.text)
     common/cmd_nvedit.o		(.text)
     common/console.o		(.text)
-    common/lists.o		(.text)
     common/main.o		(.text)
 
 /*

board/esd/ash405/ash405.c

@@ -82,15 +82,6 @@ int board_early_init_f (void)
 	return 0;
 }
 
-
-/* ------------------------------------------------------------------------- */
-
-int misc_init_f (void)
-{
-	return 0;  /* dummy implementation */
-}
-
-
 int misc_init_r (void)
 {
 	volatile unsigned char *duart0_mcr = (unsigned char *)((ulong)DUART0_BA + 4);
@@ -205,20 +196,6 @@ int checkboard (void)
 	return 0;
 }
 
-/* ------------------------------------------------------------------------- */
-
-phys_size_t initdram (int board_type)
-{
-	unsigned long val;
-
-	mtdcr(memcfga, mem_mb0cf);
-	val = mfdcr(memcfgd);
-
-	return (4*1024*1024 << ((val & 0x000e0000) >> 17));
-}
-
-/* ------------------------------------------------------------------------- */
-
 void reset_phy(void)
 {
 #ifdef CONFIG_LXT971_NO_SLEEP

board/esd/canbt/u-boot.lds

@@ -78,7 +78,6 @@ SECTIONS
     common/cmd_mem.o		(.text)
     common/cmd_nvedit.o		(.text)
     common/console.o		(.text)
-    common/lists.o		(.text)
     common/main.o		(.text)
     net/net.o			(.text)
 

board/esd/cms700/cms700.c

@@ -77,15 +77,6 @@ int board_early_init_f (void)
 	return 0;
 }
 
-
-/* ------------------------------------------------------------------------- */
-
-int misc_init_f (void)
-{
-	return 0;  /* dummy implementation */
-}
-
-
 int misc_init_r (void)
 {
 	/* adjust flash start and offset */
@@ -141,18 +132,6 @@ int checkboard (void)
 
 /* ------------------------------------------------------------------------- */
 
-phys_size_t initdram (int board_type)
-{
-	unsigned long val;
-
-	mtdcr(memcfga, mem_mb0cf);
-	val = mfdcr(memcfgd);
-
-	return (4*1024*1024 << ((val & 0x000e0000) >> 17));
-}
-
-/* ------------------------------------------------------------------------- */
-
 #if defined(CFG_EEPROM_WREN)
 /* Input: <dev_addr>  I2C address of EEPROM device to enable.
  *         <state>     -1: deliver current state

board/esd/common/auto_update.c

@@ -27,7 +27,7 @@
 #include <command.h>
 #include <image.h>
 #include <asm/byteorder.h>
-#if defined(CFG_NAND_LEGACY)
+#if defined(CONFIG_NAND_LEGACY)
 #include <linux/mtd/nand_legacy.h>
 #endif
 #include <fat.h>
@@ -58,7 +58,7 @@ extern int flash_sect_erase(ulong, ulong);
 extern int flash_sect_protect (int, ulong, ulong);
 extern int flash_write (char *, ulong, ulong);
 
-#if defined(CONFIG_CMD_NAND) && defined(CFG_NAND_LEGACY)
+#if defined(CONFIG_CMD_NAND) && defined(CONFIG_NAND_LEGACY)
 /* references to names in cmd_nand.c */
 #define NANDRW_READ	0x01
 #define NANDRW_WRITE	0x00
@@ -158,7 +158,7 @@ int au_do_update(int i, long sz)
 	int off, rc;
 	uint nbytes;
 	int k;
-#if defined(CONFIG_CMD_NAND) && defined(CFG_NAND_LEGACY)
+#if defined(CONFIG_CMD_NAND) && defined(CONFIG_NAND_LEGACY)
 	int total;
 #endif
 
@@ -241,7 +241,7 @@ int au_do_update(int i, long sz)
 			debug ("flash_sect_erase(%lx, %lx);\n", start, end);
 			flash_sect_erase (start, end);
 		} else {
-#if defined(CONFIG_CMD_NAND) && defined(CFG_NAND_LEGACY)
+#if defined(CONFIG_CMD_NAND) && defined(CONFIG_NAND_LEGACY)
 			printf ("Updating NAND FLASH with image %s\n",
 				au_image[i].name);
 			debug ("nand_legacy_erase(%lx, %lx);\n", start, end);
@@ -273,7 +273,7 @@ int au_do_update(int i, long sz)
 			rc = flash_write ((char *)addr, start,
 					  (nbytes + 1) & ~1);
 		} else {
-#if defined(CONFIG_CMD_NAND) && defined(CFG_NAND_LEGACY)
+#if defined(CONFIG_CMD_NAND) && defined(CONFIG_NAND_LEGACY)
 			debug ("nand_legacy_rw(%p, %lx, %x)\n",
 			       addr, start, nbytes);
 			rc = nand_legacy_rw (nand_dev_desc,
@@ -298,7 +298,7 @@ int au_do_update(int i, long sz)
 			rc = crc32 (0, (uchar *)(start + off),
 				    image_get_data_size (hdr));
 		} else {
-#if defined(CONFIG_CMD_NAND) && defined(CFG_NAND_LEGACY)
+#if defined(CONFIG_CMD_NAND) && defined(CONFIG_NAND_LEGACY)
 			rc = nand_legacy_rw (nand_dev_desc,
 					     NANDRW_READ | NANDRW_JFFS2 |
 					     NANDRW_JFFS2_SKIP,

board/esd/common/esd405ep_nand.c

@@ -30,28 +30,26 @@
 /*
  * hardware specific access to control-lines
  */
-static void esd405ep_nand_hwcontrol(struct mtd_info *mtdinfo, int cmd)
+static void esd405ep_nand_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl)
 {
-	switch(cmd) {
-	case NAND_CTL_SETCLE:
-		out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) | CFG_NAND_CLE);
-		break;
-	case NAND_CTL_CLRCLE:
-		out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) & ~CFG_NAND_CLE);
-		break;
-	case NAND_CTL_SETALE:
-		out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) | CFG_NAND_ALE);
-		break;
-	case NAND_CTL_CLRALE:
-		out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) & ~CFG_NAND_ALE);
-		break;
-	case NAND_CTL_SETNCE:
-		out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) & ~CFG_NAND_CE);
-		break;
-	case NAND_CTL_CLRNCE:
-		out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) | CFG_NAND_CE);
-		break;
+	struct nand_chip *this = mtd->priv;
+	if (ctrl & NAND_CTRL_CHANGE) {
+		if ( ctrl & NAND_CLE )
+			out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) | CFG_NAND_CLE);
+		else
+			out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) & ~CFG_NAND_CLE);
+		if ( ctrl & NAND_ALE )
+			out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) | CFG_NAND_ALE);
+		else
+			out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) & ~CFG_NAND_ALE);
+		if ( ctrl & NAND_NCE )
+			out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) & ~CFG_NAND_CE);
+		else
+			out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) | CFG_NAND_CE);
 	}
+
+	if (cmd != NAND_CMD_NONE)
+		writeb(cmd, this->IO_ADDR_W);
 }
 
 
@@ -77,9 +75,9 @@ int board_nand_init(struct nand_chip *nand)
 	/*
 	 * Initialize nand_chip structure
 	 */
-	nand->hwcontrol = esd405ep_nand_hwcontrol;
+	nand->cmd_ctrl = esd405ep_nand_hwcontrol;
 	nand->dev_ready = esd405ep_nand_device_ready;
-	nand->eccmode = NAND_ECC_SOFT;
+	nand->ecc.mode = NAND_ECC_SOFT;
 	nand->chip_delay = NAND_BIG_DELAY_US;
 	nand->options = NAND_SAMSUNG_LP_OPTIONS;
 	return 0;

board/esd/cpci2dp/cpci2dp.c

@@ -67,13 +67,6 @@ int board_early_init_f (void)
 	return 0;
 }
 
-
-int misc_init_f (void)
-{
-	return 0;  /* dummy implementation */
-}
-
-
 int misc_init_r (void)
 {
 	unsigned long cntrl0Reg;
@@ -115,20 +108,6 @@ int checkboard (void)
 	return 0;
 }
 
-/* ------------------------------------------------------------------------- */
-
-phys_size_t initdram (int board_type)
-{
-	unsigned long val;
-
-	mtdcr(memcfga, mem_mb0cf);
-	val = mfdcr(memcfgd);
-
-	return (4*1024*1024 << ((val & 0x000e0000) >> 17));
-}
-
-/* ------------------------------------------------------------------------- */
-
 #if defined(CFG_EEPROM_WREN)
 /* Input: <dev_addr>  I2C address of EEPROM device to enable.
  *	   <state>     -1: deliver current state

board/esd/cpci405/config.mk

@@ -21,20 +21,8 @@
 # MA 02111-1307 USA
 #
 
-#
-# esd CPCI405 boards
-#
+sinclude $(OBJTREE)/board/$(BOARDDIR)/config.tmp
 
-ifeq ($(BOARD_REVISION),CPCI4052)
-TEXT_BASE = 0xFFFC0000
-else
-ifeq ($(BOARD_REVISION),CPCI405DT)
-TEXT_BASE = 0xFFFC0000
-else
-ifeq ($(BOARD_REVISION),CPCI405AB)
-TEXT_BASE = 0xFFFC0000
-else
+ifndef TEXT_BASE
 TEXT_BASE = 0xFFFD0000
 endif
-endif
-endif

board/esd/cpci405/cpci405.c

@@ -255,11 +255,6 @@ int cpci405_version(void)
 	}
 }
 
-int misc_init_f (void)
-{
-	return 0;  /* dummy implementation */
-}
-
 int misc_init_r (void)
 {
 	unsigned long cntrl0Reg;
@@ -493,18 +488,6 @@ int checkboard (void)
 	return 0;
 }
 
-/* ------------------------------------------------------------------------- */
-
-phys_size_t initdram (int board_type)
-{
-	unsigned long val;
-
-	mtdcr(memcfga, mem_mb0cf);
-	val = mfdcr(memcfgd);
-
-	return (4*1024*1024 << ((val & 0x000e0000) >> 17));
-}
-
 void reset_phy(void)
 {
 #ifdef CONFIG_LXT971_NO_SLEEP
@@ -516,8 +499,6 @@ void reset_phy(void)
 #endif
 }
 
-/* ------------------------------------------------------------------------- */
-
 #ifdef CONFIG_CPCI405_VER2
 #ifdef CONFIG_IDE_RESET