Prepare v2020.01-stm32mp-r1

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Change-Id: I01762962eaa565268c262247ee70e852d499fbe3
Reviewed-on: https://gerrit.st.com/c/mpu/oe/st/u-boot/+/163194
Reviewed-by: CITOOLS <smet-aci-reviews@lists.codex.cro.st.com>

.azure-pipelines.yml

@@ -1,37 +1,42 @@
 variables:
-  windows_vm: windows-2019
-  ubuntu_vm: ubuntu-22.04
-  macos_vm: macOS-12
-  ci_runner_image: trini/u-boot-gitlab-ci-runner:jammy-20220801-09Aug2022
+  windows_vm: vs2015-win2012r2
+  ubuntu_vm: ubuntu-18.04
+  ci_runner_image: trini/u-boot-gitlab-ci-runner:bionic-20191010-20Oct2019
   # Add '-u 0' options for Azure pipelines, otherwise we get "permission
   # denied" error when it tries to "useradd -m -u 1001 vsts_azpcontainer",
   # since our $(ci_runner_image) user is not root.
   container_option: -u 0
   work_dir: /u
 
-stages:
-- stage: testsuites
-  jobs:
+jobs:
   - job: tools_only_windows
     displayName: 'Ensure host tools build for Windows'
     pool:
       vmImage: $(windows_vm)
+    strategy:
+      matrix:
+        i686:
+          MSYS_DIR: msys32
+          BASE_REPO: msys2-ci-base-i686
+        x86_64:
+          MSYS_DIR: msys64
+          BASE_REPO: msys2-ci-base
     steps:
-      - powershell: |
-          (New-Object Net.WebClient).DownloadFile("https://github.com/msys2/msys2-installer/releases/download/2021-06-04/msys2-base-x86_64-20210604.sfx.exe", "sfx.exe")
+      - script: |
+          git clone https://github.com/msys2/$(BASE_REPO).git %CD:~0,2%\$(MSYS_DIR)
         displayName: 'Install MSYS2'
       - script: |
-          sfx.exe -y -o%CD:~0,2%\
-          %CD:~0,2%\msys64\usr\bin\bash -lc " "
-          %CD:~0,2%\msys64\usr\bin\bash -lc "pacman --noconfirm -Syuu"
-          %CD:~0,2%\msys64\usr\bin\bash -lc "pacman --noconfirm -Syuu"
+          set PATH=%CD:~0,2%\$(MSYS_DIR)\usr\bin;C:\Windows\system32;C:\Windows;C:\Windows\System32\Wbem
+          %CD:~0,2%\$(MSYS_DIR)\usr\bin\pacman --noconfirm -Syyuu
         displayName: 'Update MSYS2'
       - script: |
-          %CD:~0,2%\msys64\usr\bin\bash -lc "pacman --noconfirm --needed -Sy make gcc bison flex diffutils openssl-devel libgnutls-devel libutil-linux-devel"
+          set PATH=%CD:~0,2%\$(MSYS_DIR)\usr\bin;C:\Windows\system32;C:\Windows;C:\Windows\System32\Wbem
+          %CD:~0,2%\$(MSYS_DIR)\usr\bin\pacman --noconfirm --needed -S make gcc bison diffutils openssl-devel
         displayName: 'Install Toolchain'
       - script: |
+          set PATH=C:\Windows\system32;C:\Windows;C:\Windows\System32\Wbem
           echo make tools-only_defconfig tools-only NO_SDL=1 > build-tools.sh
-          %CD:~0,2%\msys64\usr\bin\bash -lc "bash build-tools.sh"
+          %CD:~0,2%\$(MSYS_DIR)\usr\bin\bash -lc "bash build-tools.sh"
         displayName: 'Build Host Tools'
         env:
           # Tell MSYS2 we need a POSIX emulation layer
@@ -39,52 +44,6 @@ stages:
           # Tell MSYS2 not to ‘cd’ our startup directory to HOME
           CHERE_INVOKING: yes
 
-  - job: tools_only_macOS
-    displayName: 'Ensure host tools build for macOS X'
-    pool:
-      vmImage: $(macos_vm)
-    steps:
-      - script: brew install make ossp-uuid
-        displayName: Brew install dependencies
-      - script: |
-          gmake tools-only_config tools-only NO_SDL=1 \
-            HOSTCFLAGS="-I/usr/local/opt/openssl@1.1/include" \
-            HOSTLDFLAGS="-L/usr/local/opt/openssl@1.1/lib" \
-            -j$(sysctl -n hw.logicalcpu)
-        displayName: 'Perform tools-only build'
-
-  - job: check_for_migrated_symbols_in_board_header
-    displayName: 'Check for migrated symbols in board header'
-    pool:
-      vmImage: $(ubuntu_vm)
-    container:
-      image: $(ci_runner_image)
-      options: $(container_option)
-    steps:
-      - script: |
-          KSYMLST=`mktemp`
-          KUSEDLST=`mktemp`
-          RET=0
-          cat `find . -name "Kconfig*"` | \
-             sed -n -e 's/^\s*config *\([A-Za-z0-9_]*\).*$/CONFIG_\1/p' \
-             -e 's/^\s*menuconfig *\([A-Za-z0-9_]*\).*$/CONFIG_\1/p' \
-             | sort -u > $KSYMLST
-          for CFG in `find include/configs -name "*.h"`; do
-             (grep '#define[[:blank:]]CONFIG_' $CFG | \
-                sed -n 's/#define.\(CONFIG_[A-Za-z0-9_]*\).*/\1/p' ; \
-                grep '#undef[[:blank:]]CONFIG_' $CFG | \
-                sed -n 's/#undef.\(CONFIG_[A-Za-z0-9_]*\).*/\1/p') | \
-                sort -u > ${KUSEDLST} || true
-             NUM=`comm -123 --total --output-delimiter=, ${KSYMLST} ${KUSEDLST} | \
-                cut -d , -f 3`
-             if [[ $NUM -ne 0 ]]; then
-                echo "Unmigrated symbols found in $CFG:"
-                comm -12 ${KSYMLST} ${KUSEDLST}
-                RET=1
-             fi
-          done
-          exit $RET
-
   - job: cppcheck
     displayName: 'Static code analysis with cppcheck'
     pool:
@@ -93,21 +52,7 @@ stages:
       image: $(ci_runner_image)
       options: $(container_option)
     steps:
-      - script: cppcheck -j$(nproc) --force --quiet --inline-suppr .
-
-  - job: htmldocs
-    displayName: 'Build HTML documentation'
-    pool:
-      vmImage: $(ubuntu_vm)
-    container:
-      image: $(ci_runner_image)
-      options: $(container_option)
-    steps:
-      - script: |
-          virtualenv -p /usr/bin/python3 /tmp/venvhtml
-          . /tmp/venvhtml/bin/activate
-          pip install -r doc/sphinx/requirements.txt
-          make htmldocs
+      - script: cppcheck --force --quiet --inline-suppr .
 
   - job: todo
     displayName: 'Search for TODO within source tree'
@@ -140,7 +85,7 @@ stages:
       options: $(container_option)
     steps:
       - script: |
-          ./tools/buildman/buildman -R
+          if [ `./tools/genboardscfg.py -f 2>&1 | wc -l` -ne 0 ]; then exit 1; fi
 
   - job: tools_only
     displayName: 'Ensure host tools build'
@@ -165,73 +110,36 @@ stages:
           make tools-only_config envtools -j$(nproc)
 
   - job: utils
-    displayName: 'Run binman, buildman, dtoc, Kconfig and patman testsuites'
+    displayName: 'Run binman, buildman, dtoc and patman testsuites'
     pool:
       vmImage: $(ubuntu_vm)
     steps:
       - script: |
-          cat << "EOF" > build.sh
-          cd $(work_dir)
+          cat << EOF > build.sh
+          set -ex
+          cd ${WORK_DIR}
+          EOF
+          cat << "EOF" >> build.sh
           git config --global user.name "Azure Pipelines"
           git config --global user.email bmeng.cn@gmail.com
-          git config --global --add safe.directory $(work_dir)
           export USER=azure
-          virtualenv -p /usr/bin/python3 /tmp/venv
+          virtualenv /tmp/venv
           . /tmp/venv/bin/activate
-          pip install -r test/py/requirements.txt
-          export UBOOT_TRAVIS_BUILD_DIR=/tmp/sandbox_spl
+          pip install pyelftools
+          export UBOOT_TRAVIS_BUILD_DIR=/tmp/.bm-work/sandbox_spl
           export PYTHONPATH=${UBOOT_TRAVIS_BUILD_DIR}/scripts/dtc/pylibfdt
           export PATH=${UBOOT_TRAVIS_BUILD_DIR}/scripts/dtc:${PATH}
-          ./tools/buildman/buildman -T0 -o ${UBOOT_TRAVIS_BUILD_DIR} -w --board sandbox_spl
-          set -ex
+          ./tools/buildman/buildman -o /tmp -P sandbox_spl
           ./tools/binman/binman --toolpath ${UBOOT_TRAVIS_BUILD_DIR}/tools test
           ./tools/buildman/buildman -t
           ./tools/dtoc/dtoc -t
-          ./tools/patman/patman test
-          make O=${UBOOT_TRAVIS_BUILD_DIR} testconfig
+          ./tools/patman/patman --test
           EOF
           cat build.sh
           # We cannot use "container" like other jobs above, as buildman
           # seems to hang forever with pre-configured "container" environment
           docker run -v $PWD:$(work_dir) $(ci_runner_image) /bin/bash $(work_dir)/build.sh
 
-  - job: nokia_rx51_test
-    displayName: 'Run tests for Nokia RX-51 (aka N900)'
-    pool:
-      vmImage: $(ubuntu_vm)
-    container:
-      image: $(ci_runner_image)
-      options: $(container_option)
-    steps:
-      - script: |
-          export PATH=/opt/gcc-11.1.0-nolibc/arm-linux-gnueabi/bin:$PATH
-          test/nokia_rx51_test.sh
-
-  - job: pylint
-    displayName: Check for any pylint regressions
-    pool:
-      vmImage: $(ubuntu_vm)
-    container:
-      image: $(ci_runner_image)
-      options: $(container_option)
-    steps:
-      - script: |
-          git config --global --add safe.directory $(work_dir)
-          export USER=azure
-          pip install -r test/py/requirements.txt
-          pip install asteval pylint==2.12.2 pyopenssl
-          export PATH=${PATH}:~/.local/bin
-          echo "[MASTER]" >> .pylintrc
-          echo "load-plugins=pylint.extensions.docparams" >> .pylintrc
-          export UBOOT_TRAVIS_BUILD_DIR=/tmp/sandbox_spl
-          ./tools/buildman/buildman -T0 -o ${UBOOT_TRAVIS_BUILD_DIR} -w --board sandbox_spl
-          set -ex
-          pylint --version
-          export PYTHONPATH=${UBOOT_TRAVIS_BUILD_DIR}/scripts/dtc/pylibfdt
-          make pylint_err
-
-- stage: test_py
-  jobs:
   - job: test_py
     displayName: 'test.py'
     pool:
@@ -240,110 +148,90 @@ stages:
       matrix:
         sandbox:
           TEST_PY_BD: "sandbox"
+          BUILDMAN: "^sandbox$"
         sandbox_clang:
           TEST_PY_BD: "sandbox"
-          OVERRIDE: "-O clang-13"
+          BUILDMAN: "^sandbox$"
+          OVERRIDE: "-O clang-7"
         sandbox_spl:
           TEST_PY_BD: "sandbox_spl"
-          TEST_PY_TEST_SPEC: "test_ofplatdata or test_handoff or test_spl"
-        sandbox_vpl:
-          TEST_PY_BD: "sandbox_vpl"
-          TEST_PY_TEST_SPEC: "test_vpl_help or test_spl"
-        sandbox_noinst:
-          TEST_PY_BD: "sandbox_noinst"
-          TEST_PY_TEST_SPEC: "test_ofplatdata or test_handoff or test_spl"
+          TEST_PY_TEST_SPEC: "test_ofplatdata"
+          BUILDMAN: "^sandbox_spl$"
         sandbox_flattree:
           TEST_PY_BD: "sandbox_flattree"
-        coreboot:
-          TEST_PY_BD: "coreboot"
-          TEST_PY_ID: "--id qemu"
-          TEST_PY_TEST_SPEC: "not sleep"
+          BUILDMAN: "^sandbox_flattree$"
         evb_ast2500:
           TEST_PY_BD: "evb-ast2500"
           TEST_PY_ID: "--id qemu"
-        evb_ast2600:
-          TEST_PY_BD: "evb-ast2600"
+          BUILDMAN: "^evb-ast2500$"
+        vexpress_ca15_tc2:
+          TEST_PY_BD: "vexpress_ca15_tc2"
           TEST_PY_ID: "--id qemu"
+          BUILDMAN: "^vexpress_ca15_tc2$"
         vexpress_ca9x4:
           TEST_PY_BD: "vexpress_ca9x4"
           TEST_PY_ID: "--id qemu"
+          BUILDMAN: "^vexpress_ca9x4$"
         integratorcp_cm926ejs:
           TEST_PY_BD: "integratorcp_cm926ejs"
           TEST_PY_ID: "--id qemu"
           TEST_PY_TEST_SPEC: "not sleep"
+          BUILDMAN: "^integratorcp_cm926ejs$"
         qemu_arm:
           TEST_PY_BD: "qemu_arm"
           TEST_PY_TEST_SPEC: "not sleep"
+          BUILDMAN: "^qemu_arm$"
         qemu_arm64:
           TEST_PY_BD: "qemu_arm64"
           TEST_PY_TEST_SPEC: "not sleep"
-        qemu_malta:
-          TEST_PY_BD: "malta"
-          TEST_PY_ID: "--id qemu"
-          TEST_PY_TEST_SPEC: "not sleep and not efi"
-        qemu_maltael:
-          TEST_PY_BD: "maltael"
-          TEST_PY_ID: "--id qemu"
-          TEST_PY_TEST_SPEC: "not sleep and not efi"
-        qemu_malta64:
-          TEST_PY_BD: "malta64"
-          TEST_PY_ID: "--id qemu"
-          TEST_PY_TEST_SPEC: "not sleep and not efi"
-        qemu_malta64el:
-          TEST_PY_BD: "malta64el"
-          TEST_PY_ID: "--id qemu"
-          TEST_PY_TEST_SPEC: "not sleep and not efi"
+          BUILDMAN: "^qemu_arm64$"
+        qemu_mips:
+          TEST_PY_BD: "qemu_mips"
+          TEST_PY_TEST_SPEC: "not sleep"
+          BUILDMAN: "^qemu_mips$"
+        qemu_mipsel:
+          TEST_PY_BD: "qemu_mipsel"
+          TEST_PY_TEST_SPEC: "not sleep"
+          BUILDMAN: "^qemu_mipsel$"
+        qemu_mips64:
+          TEST_PY_BD: "qemu_mips64"
+          TEST_PY_TEST_SPEC: "not sleep"
+          BUILDMAN: "^qemu_mips64$"
+        qemu_mips64el:
+          TEST_PY_BD: "qemu_mips64el"
+          TEST_PY_TEST_SPEC: "not sleep"
+          BUILDMAN: "^qemu_mips64el$"
         qemu_ppce500:
           TEST_PY_BD: "qemu-ppce500"
           TEST_PY_TEST_SPEC: "not sleep"
-        qemu_riscv32:
-          TEST_PY_BD: "qemu-riscv32"
-          TEST_PY_TEST_SPEC: "not sleep"
+          BUILDMAN: "^qemu-ppce500$"
         qemu_riscv64:
           TEST_PY_BD: "qemu-riscv64"
           TEST_PY_TEST_SPEC: "not sleep"
-        qemu_riscv32_spl:
-          TEST_PY_BD: "qemu-riscv32_spl"
-          TEST_PY_TEST_SPEC: "not sleep"
-        qemu_riscv64_spl:
-          TEST_PY_BD: "qemu-riscv64_spl"
-          TEST_PY_TEST_SPEC: "not sleep"
+          BUILDMAN: "^qemu-riscv64$"
         qemu_x86:
           TEST_PY_BD: "qemu-x86"
           TEST_PY_TEST_SPEC: "not sleep"
+          BUILDMAN: "^qemu-x86$"
         qemu_x86_64:
           TEST_PY_BD: "qemu-x86_64"
           TEST_PY_TEST_SPEC: "not sleep"
-        r2dplus_i82557c:
-          TEST_PY_BD: "r2dplus"
-          TEST_PY_ID: "--id i82557c_qemu"
-        r2dplus_pcnet:
-          TEST_PY_BD: "r2dplus"
-          TEST_PY_ID: "--id pcnet_qemu"
-        r2dplus_rtl8139:
-          TEST_PY_BD: "r2dplus"
-          TEST_PY_ID: "--id rtl8139_qemu"
-        r2dplus_tulip:
-          TEST_PY_BD: "r2dplus"
-          TEST_PY_ID: "--id tulip_qemu"
-        sifive_unleashed_sdcard:
-          TEST_PY_BD: "sifive_unleashed"
-          TEST_PY_ID: "--id sdcard_qemu"
-        sifive_unleashed_spi-nor:
-          TEST_PY_BD: "sifive_unleashed"
-          TEST_PY_ID: "--id spi-nor_qemu"
-        xilinx_zynq_virt:
-          TEST_PY_BD: "xilinx_zynq_virt"
+          BUILDMAN: "^qemu-x86_64$"
+        zynq_zc702:
+          TEST_PY_BD: "zynq_zc702"
           TEST_PY_ID: "--id qemu"
           TEST_PY_TEST_SPEC: "not sleep"
+          BUILDMAN: "^zynq_zc702$"
         xilinx_versal_virt:
           TEST_PY_BD: "xilinx_versal_virt"
           TEST_PY_ID: "--id qemu"
           TEST_PY_TEST_SPEC: "not sleep"
+          BUILDMAN: "^xilinx_versal_virt$"
         xtfpga:
           TEST_PY_BD: "xtfpga"
           TEST_PY_ID: "--id qemu"
           TEST_PY_TEST_SPEC: "not sleep"
+          BUILDMAN: "^xtfpga$"
     steps:
       - script: |
           cat << EOF > test.sh
@@ -353,99 +241,68 @@ stages:
           export TEST_PY_BD="${TEST_PY_BD}"
           export TEST_PY_ID="${TEST_PY_ID}"
           export TEST_PY_TEST_SPEC="${TEST_PY_TEST_SPEC}"
+          export BUILDMAN="${BUILDMAN}"
           export OVERRIDE="${OVERRIDE}"
           EOF
           cat << "EOF" >> test.sh
           # the below corresponds to .gitlab-ci.yml "before_script"
           cd ${WORK_DIR}
-          git clone --depth=1 https://source.denx.de/u-boot/u-boot-test-hooks /tmp/uboot-test-hooks
+          git clone --depth=1 git://github.com/swarren/uboot-test-hooks.git /tmp/uboot-test-hooks
           ln -s travis-ci /tmp/uboot-test-hooks/bin/`hostname`
           ln -s travis-ci /tmp/uboot-test-hooks/py/`hostname`
           grub-mkimage --prefix=\"\" -o ~/grub_x86.efi -O i386-efi normal  echo lsefimmap lsefi lsefisystab efinet tftp minicmd
           grub-mkimage --prefix=\"\" -o ~/grub_x64.efi -O x86_64-efi normal  echo lsefimmap lsefi lsefisystab efinet tftp minicmd
-          if [[ "${TEST_PY_BD}" == "qemu-riscv32_spl" ]]; then
-              wget -O - https://github.com/riscv/opensbi/releases/download/v0.9/opensbi-0.9-rv-bin.tar.xz | tar -C /tmp -xJ;
-              export OPENSBI=/tmp/opensbi-0.9-rv-bin/share/opensbi/ilp32/generic/firmware/fw_dynamic.bin;
-          fi
-          if [[ "${TEST_PY_BD}" == "qemu-riscv64_spl" ]] || [[ "${TEST_PY_BD}" == "sifive_unleashed" ]]; then
-              wget -O - https://github.com/riscv/opensbi/releases/download/v0.9/opensbi-0.9-rv-bin.tar.xz | tar -C /tmp -xJ;
-              export OPENSBI=/tmp/opensbi-0.9-rv-bin/share/opensbi/lp64/generic/firmware/fw_dynamic.bin;
-          fi
+          mkdir ~/grub2-arm
+          cd ~/grub2-arm; wget -O - http://download.opensuse.org/ports/armv7hl/distribution/leap/42.2/repo/oss/suse/armv7hl/grub2-arm-efi-2.02~beta2-87.1.armv7hl.rpm | rpm2cpio | cpio -di
+          mkdir ~/grub2-arm64
+          cd ~/grub2-arm64; wget -O - http://download.opensuse.org/ports/aarch64/distribution/leap/42.2/repo/oss/suse/aarch64/grub2-arm64-efi-2.02~beta2-87.1.aarch64.rpm | rpm2cpio | cpio -di
           # the below corresponds to .gitlab-ci.yml "script"
           cd ${WORK_DIR}
-          export UBOOT_TRAVIS_BUILD_DIR=/tmp/${TEST_PY_BD};
-          tools/buildman/buildman -o ${UBOOT_TRAVIS_BUILD_DIR} -w -E -W -e --board ${TEST_PY_BD} ${OVERRIDE}
-          cp ~/grub_x86.efi ${UBOOT_TRAVIS_BUILD_DIR}/
-          cp ~/grub_x64.efi ${UBOOT_TRAVIS_BUILD_DIR}/
-          cp /opt/grub/grubriscv64.efi ${UBOOT_TRAVIS_BUILD_DIR}/grub_riscv64.efi
-          cp /opt/grub/grubaa64.efi ${UBOOT_TRAVIS_BUILD_DIR}/grub_arm64.efi
-          cp /opt/grub/grubarm.efi ${UBOOT_TRAVIS_BUILD_DIR}/grub_arm.efi
-          # create sdcard / spi-nor images for sifive unleashed using genimage
-          if [[ "${TEST_PY_BD}" == "sifive_unleashed" ]]; then
-              mkdir -p root;
-              cp ${UBOOT_TRAVIS_BUILD_DIR}/spl/u-boot-spl.bin .;
-              cp ${UBOOT_TRAVIS_BUILD_DIR}/u-boot.itb .;
-              rm -rf tmp;
-              genimage --inputpath . --config board/sifive/unleashed/genimage_sdcard.cfg;
-              cp images/sdcard.img ${UBOOT_TRAVIS_BUILD_DIR}/;
-              rm -rf tmp;
-              genimage --inputpath . --config board/sifive/unleashed/genimage_spi-nor.cfg;
-              cp images/spi-nor.img ${UBOOT_TRAVIS_BUILD_DIR}/;
-          fi
-          if [[ "${TEST_PY_BD}" == "coreboot" ]]; then
-              wget -O - "https://drive.google.com/uc?id=1x6nrtWIyIRPLS2cQBwYTnT2TbOI8UjmM&export=download" |xz -dc >${UBOOT_TRAVIS_BUILD_DIR}/coreboot.rom;
-              wget -O - "https://drive.google.com/uc?id=149Cz-5SZXHNKpi9xg6R_5XITWohu348y&export=download" >cbfstool;
-              chmod a+x cbfstool;
-              ./cbfstool ${UBOOT_TRAVIS_BUILD_DIR}/coreboot.rom add-flat-binary -f ${UBOOT_TRAVIS_BUILD_DIR}/u-boot.bin -n fallback/payload -c LZMA -l 0x1110000 -e 0x1110000;
+          if [[ "${BUILDMAN}" != "" ]]; then
+              ret=0;
+              tools/buildman/buildman -o /tmp -P -E ${BUILDMAN} ${OVERRIDE} || ret=$?;
+              if [[ $ret -ne 0 && $ret -ne 129 ]]; then
+                  tools/buildman/buildman -o /tmp -sdeP ${BUILDMAN};
+                  exit $ret;
+              fi;
           fi
           virtualenv -p /usr/bin/python3 /tmp/venv
           . /tmp/venv/bin/activate
           pip install -r test/py/requirements.txt
+          export UBOOT_TRAVIS_BUILD_DIR=/tmp/.bm-work/${TEST_PY_BD};
           export PATH=/opt/qemu/bin:/tmp/uboot-test-hooks/bin:${PATH};
           export PYTHONPATH=/tmp/uboot-test-hooks/py/travis-ci;
-          # "${var:+"-k $var"}" expands to "" if $var is empty, "-k $var" if not
-          ./test/py/test.py -ra --bd ${TEST_PY_BD} ${TEST_PY_ID} ${TEST_PY_TEST_SPEC:+"-k ${TEST_PY_TEST_SPEC}"} --build-dir "$UBOOT_TRAVIS_BUILD_DIR";
+          if [[ "${TEST_PY_BD}" != "" ]]; then
+              ./test/py/test.py --bd ${TEST_PY_BD} ${TEST_PY_ID} -k "${TEST_PY_TEST_SPEC:-not a_test_which_does_not_exist}" --build-dir "$UBOOT_TRAVIS_BUILD_DIR";
+              ret=$?;
+              if [[ $ret -ne 0 ]]; then
+                  exit $ret;
+              fi;
+          fi
           # the below corresponds to .gitlab-ci.yml "after_script"
-          rm -rf /tmp/uboot-test-hooks /tmp/venv
+          rm -rf ~/grub2* /tmp/uboot-test-hooks /tmp/venv
           EOF
           cat test.sh
           # make current directory writeable to uboot user inside the container
           # as sandbox testing need create files like spi flash images, etc.
           # (TODO: clean up this in the future)
           chmod 777 .
-          # Filesystem tests need extra docker args to run
-          set --
-          if [[ "${TEST_PY_BD}" == "sandbox" ]]; then
-              # mount -o loop needs the loop devices
-              if modprobe loop; then
-                  for d in $(find /dev -maxdepth 1 -name 'loop*'); do
-                      set -- "$@" --device $d:$d
-                  done
-              fi
-              # Needed for mount syscall (for guestmount as well)
-              set -- "$@" --cap-add SYS_ADMIN
-              # Default apparmor profile denies mounts
-              set -- "$@" --security-opt apparmor=unconfined
-          fi
-          # Some tests using libguestfs-tools need the fuse device to run
-          docker run "$@" --device /dev/fuse:/dev/fuse -v $PWD:$(work_dir) $(ci_runner_image) /bin/bash $(work_dir)/test.sh
+          docker run -v $PWD:$(work_dir) $(ci_runner_image) /bin/bash $(work_dir)/test.sh
 
-- stage: world_build
-  jobs:
   - job: build_the_world
     displayName: 'Build the World'
     pool:
       vmImage: $(ubuntu_vm)
     strategy:
       # Use almost the same target division in .travis.yml, only merged
-      # 3 small build jobs (arc/microblaze/xtensa) into one.
+      # 4 small build jobs (arc/microblaze/nds32/xtensa) into one.
       matrix:
-        arc_microblaze_xtensa:
-          BUILDMAN: "arc microblaze xtensa"
+        arc_microblaze_nds32_xtensa:
+          BUILDMAN: "arc microblaze nds32 xtensa"
         arm11_arm7_arm920t_arm946es:
           BUILDMAN: "arm11 arm7 arm920t arm946es"
         arm926ejs:
-          BUILDMAN: "arm926ejs -x freescale,siemens,at91,kirkwood,omap"
+          BUILDMAN: "arm926ejs -x freescale,siemens,at91,kirkwood,spear,omap"
         at91_non_armv7:
           BUILDMAN: "at91 -x armv7"
         at91_non_arm926ejs:
@@ -472,18 +329,12 @@ stages:
           BUILDMAN: "mx6 -x boundary,engicam,freescale,technexion,toradex"
         imx:
           BUILDMAN: "mx -x mx6,freescale,technexion,toradex"
-        imx8:
-          BUILDMAN: "imx8"
         keystone2_keystone3:
           BUILDMAN: "k2 k3"
-        sandbox_asan:
-          BUILDMAN: "sandbox"
-          OVERRIDE: "-a ASAN"
-        sandbox_clang_asan:
-          BUILDMAN: "sandbox"
-          OVERRIDE: "-O clang-13 -a ASAN"
         samsung_socfpga:
           BUILDMAN: "samsung socfpga"
+        spear:
+          BUILDMAN: "spear"
         sun4i:
           BUILDMAN: "sun4i"
         sun5i:
@@ -501,7 +352,7 @@ stages:
         sun50i:
           BUILDMAN: "sun50i"
         arm_catch_all:
-          BUILDMAN: "arm -x arm11,arm7,arm9,aarch64,at91,bcm,freescale,kirkwood,mvebu,renesas,siemens,tegra,uniphier,mx,samsung,sunxi,am33xx,omap,rk,toradex,socfpga,k2,k3,zynq"
+          BUILDMAN: "arm -x arm11,arm7,arm9,aarch64,at91,bcm,freescale,kirkwood,mvebu,siemens,tegra,uniphier,mx,samsung,sunxi,am33xx,omap,rockchip,toradex,socfpga,k2,k3,zynq"
         sandbox_x86:
           BUILDMAN: "sandbox x86"
         technexion:
@@ -514,8 +365,20 @@ stages:
           BUILDMAN: "m68k"
         mips:
           BUILDMAN: "mips"
-        powerpc:
-          BUILDMAN: "powerpc"
+        non_fsl_ppc:
+          BUILDMAN: "powerpc -x freescale"
+        mpc85xx_freescale:
+          BUILDMAN: "mpc85xx&freescale -x t208xrdb -x t4qds -x t102* -x p1_p2_rdb_pc -x p1010rdb -x corenet_ds -x b4860qds -x bsc91*"
+        t208xrdb_corenet_ds:
+          BUILDMAN: "t208xrdb corenet_ds"
+        fsl_ppc:
+          BUILDMAN: "t4qds b4860qds mpc83xx&freescale mpc86xx&freescale"
+        t102x:
+          BUILDMAN: "t102*"
+        p1_p2_rdb_pc:
+          BUILDMAN: "p1_p2_rdb_pc"
+        p1010rdb_bsc91:
+          BUILDMAN: "p1010rdb bsc91"
         siemens:
           BUILDMAN: "siemens"
         tegra:
@@ -527,11 +390,11 @@ stages:
         uniphier:
           BUILDMAN: "uniphier"
         aarch64_catch_all:
-          BUILDMAN: "aarch64 -x bcm,imx8,k3,tegra,ls1,ls2,lx216,mvebu,uniphier,renesas,sunxi,samsung,socfpga,rk,versal,zynq"
+          BUILDMAN: "aarch64 -x bcm,k3,tegra,ls1,ls2,mvebu,uniphier,sunxi,samsung,rockchip,versal,zynq"
         rockchip:
-          BUILDMAN: "rk"
-        renesas:
-          BUILDMAN: "renesas"
+          BUILDMAN: "rockchip"
+        sh:
+          BUILDMAN: "sh -x arm"
         zynq:
           BUILDMAN: "zynq&armv7"
         zynqmp_versal:
@@ -549,9 +412,9 @@ stages:
           cat << "EOF" >> build.sh
           if [[ "${BUILDMAN}" != "" ]]; then
               ret=0;
-              tools/buildman/buildman -o /tmp -P -E -W ${BUILDMAN} ${OVERRIDE} || ret=$?;
-              if [[ $ret -ne 0 ]]; then
-                  tools/buildman/buildman -o /tmp -seP ${BUILDMAN};
+              tools/buildman/buildman -o /tmp -P -E ${BUILDMAN} ${OVERRIDE} || ret=$?;
+              if [[ $ret -ne 0 && $ret -ne 129 ]]; then
+                  tools/buildman/buildman -o /tmp -sdeP ${BUILDMAN};
                   exit $ret;
               fi;
           fi

.checkpatch.conf

@@ -26,11 +26,5 @@
 # addresses are __aligned(2)".
 --ignore PREFER_ETHER_ADDR_COPY
 
-# ENOSYS is a conventionally used error, even though U-Boot lacks system calls.
---ignore ENOSYS
-
 # A bit shorter of a description is OK with us.
 --min-conf-desc-length=2
-
-# Extra checks for U-Boot
---u-boot

.get_maintainer.conf

@@ -1 +0,0 @@
---find-maintainer-files --maintainer-path=.

.gitattributes

@@ -3,4 +3,3 @@
 # Denote all files that are truly binary and should not be modified
 *.bmp binary
 *.ttf binary
-*.gz binary

.github/pull_request_template.md

@@ -1,6 +1,3 @@
 Please do not submit a Pull Request via github.  Our project makes use of
 mailing lists for patch submission and review.  For more details please
-see https://u-boot.readthedocs.io/en/latest/develop/sending_patches.html
-
-The only exception to this is in order to trigger a CI loop on Azure prior
-to posting of patches.
+see https://www.denx.de/wiki/U-Boot/Patches

.gitignore

@@ -10,7 +10,6 @@
 *.asn1.[ch]
 *.bin
 *.cfgout
-*.cover
 *.dtb
 *.dtbo
 *.dtb.S
@@ -23,7 +22,6 @@
 *.lex.c
 *.lst
 *.mod.c
-*.mbx
 *.o
 *.o.*
 *.order
@@ -95,12 +93,5 @@ GTAGS
 *~
 \#*#
 
-# Python cache
-__pycache__
-
-# Python code coverage output (python3-coverage html)
-/htmlcov/
-
-# pylint files
-/pylint.cur
-/pylint.out/
+/oe-*
+bitbake-cookerdaemon.log

.gitlab-ci.yml

@@ -1,8 +1,8 @@
 # SPDX-License-Identifier: GPL-2.0+
 
-# Grab our configured image.  The source for this is found
-# in the u-boot tree at tools/docker/Dockerfile
-image: trini/u-boot-gitlab-ci-runner:jammy-20220801-09Aug2022
+# Grab our configured image.  The source for this is found at:
+# https://gitlab.denx.de/u-boot/gitlab-ci-runner
+image: trini/u-boot-gitlab-ci-runner:bionic-20191010-20Oct2019
 
 # We run some tests in different order, to catch some failures quicker.
 stages:
@@ -11,149 +11,111 @@ stages:
   - world build
 
 .buildman_and_testpy_template: &buildman_and_testpy_dfn
+  tags: [ 'all' ]
   stage: test.py
   before_script:
     # Clone uboot-test-hooks
-    - git clone --depth=1 https://source.denx.de/u-boot/u-boot-test-hooks /tmp/uboot-test-hooks
+    - git clone --depth=1 git://github.com/swarren/uboot-test-hooks.git /tmp/uboot-test-hooks
     - ln -s travis-ci /tmp/uboot-test-hooks/bin/`hostname`
     - ln -s travis-ci /tmp/uboot-test-hooks/py/`hostname`
     - grub-mkimage --prefix="" -o ~/grub_x86.efi -O i386-efi normal  echo lsefimmap lsefi lsefisystab efinet tftp minicmd
     - grub-mkimage --prefix="" -o ~/grub_x64.efi -O x86_64-efi normal  echo lsefimmap lsefi lsefisystab efinet tftp minicmd
-    - if [[ "${TEST_PY_BD}" == "qemu-riscv32_spl" ]]; then
-        wget -O - https://github.com/riscv/opensbi/releases/download/v0.9/opensbi-0.9-rv-bin.tar.xz | tar -C /tmp -xJ;
-        export OPENSBI=/tmp/opensbi-0.9-rv-bin/share/opensbi/ilp32/generic/firmware/fw_dynamic.bin;
-      fi
-    - if [[ "${TEST_PY_BD}" == "qemu-riscv64_spl" ]] || [[ "${TEST_PY_BD}" == "sifive_unleashed" ]]; then
-        wget -O - https://github.com/riscv/opensbi/releases/download/v0.9/opensbi-0.9-rv-bin.tar.xz | tar -C /tmp -xJ;
-        export OPENSBI=/tmp/opensbi-0.9-rv-bin/share/opensbi/lp64/generic/firmware/fw_dynamic.bin;
-      fi
+    - mkdir ~/grub2-arm
+    - ( cd ~/grub2-arm; wget -O - http://download.opensuse.org/ports/armv7hl/distribution/leap/42.2/repo/oss/suse/armv7hl/grub2-arm-efi-2.02~beta2-87.1.armv7hl.rpm | rpm2cpio | cpio -di )
+    - mkdir ~/grub2-arm64
+    - ( cd ~/grub2-arm64; wget -O - http://download.opensuse.org/ports/aarch64/distribution/leap/42.2/repo/oss/suse/aarch64/grub2-arm64-efi-2.02~beta2-87.1.aarch64.rpm | rpm2cpio | cpio -di )
 
   after_script:
-    - rm -rf /tmp/uboot-test-hooks /tmp/venv
+    - rm -rf ~/grub2* /tmp/uboot-test-hooks /tmp/venv
   script:
-    # If we've been asked to use clang only do one configuration.
-    - export UBOOT_TRAVIS_BUILD_DIR=/tmp/${TEST_PY_BD}
-    - tools/buildman/buildman -o ${UBOOT_TRAVIS_BUILD_DIR} -w -E -W -e
-        --board ${TEST_PY_BD} ${OVERRIDE}
-    - cp ~/grub_x86.efi $UBOOT_TRAVIS_BUILD_DIR/
-    - cp ~/grub_x64.efi $UBOOT_TRAVIS_BUILD_DIR/
-    - cp /opt/grub/grubriscv64.efi $UBOOT_TRAVIS_BUILD_DIR/grub_riscv64.efi
-    - cp /opt/grub/grubaa64.efi $UBOOT_TRAVIS_BUILD_DIR/grub_arm64.efi
-    - cp /opt/grub/grubarm.efi $UBOOT_TRAVIS_BUILD_DIR/grub_arm.efi
-    # create sdcard / spi-nor images for sifive unleashed using genimage
-    - if [[ "${TEST_PY_BD}" == "sifive_unleashed" ]]; then
-        mkdir -p root;
-        cp ${UBOOT_TRAVIS_BUILD_DIR}/spl/u-boot-spl.bin .;
-        cp ${UBOOT_TRAVIS_BUILD_DIR}/u-boot.itb .;
-        rm -rf tmp;
-        genimage --inputpath . --config board/sifive/unleashed/genimage_sdcard.cfg;
-        cp images/sdcard.img ${UBOOT_TRAVIS_BUILD_DIR}/;
-        rm -rf tmp;
-        genimage --inputpath . --config board/sifive/unleashed/genimage_spi-nor.cfg;
-        cp images/spi-nor.img ${UBOOT_TRAVIS_BUILD_DIR}/;
-      fi
-    - if [[ "${TEST_PY_BD}" == "coreboot" ]]; then
-        wget -O -
-          "https://drive.google.com/uc?id=1x6nrtWIyIRPLS2cQBwYTnT2TbOI8UjmM&export=download" |
-          xz -dc >${UBOOT_TRAVIS_BUILD_DIR}/coreboot.rom;
-        wget -O -
-          "https://drive.google.com/uc?id=149Cz-5SZXHNKpi9xg6R_5XITWohu348y&export=download" >
-          cbfstool;
-        chmod a+x cbfstool;
-        ./cbfstool ${UBOOT_TRAVIS_BUILD_DIR}/coreboot.rom add-flat-binary -f ${UBOOT_TRAVIS_BUILD_DIR}/u-boot.bin -n fallback/payload -c LZMA -l 0x1110000 -e 0x1110000;
+    # From buildman, exit code 129 means warnings only.  If we've been asked to
+    # use clang only do one configuration.
+    - if [[ "${BUILDMAN}" != "" ]]; then
+        ret=0;
+        tools/buildman/buildman -o /tmp -P -E ${BUILDMAN} ${OVERRIDE}|| ret=$?;
+        if [[ $ret -ne 0 && $ret -ne 129 ]]; then
+          tools/buildman/buildman -o /tmp -sdeP ${BUILDMAN};
+          exit $ret;
+        fi;
       fi
+    # "not a_test_which_does_not_exist" is a dummy -k parameter which will
+    # never prevent any test from running. That way, we can always pass
+    # "-k something" even when $TEST_PY_TEST_SPEC doesnt need a custom
+    # value.
     - virtualenv -p /usr/bin/python3 /tmp/venv
     - . /tmp/venv/bin/activate
     - pip install -r test/py/requirements.txt
-    # "${var:+"-k $var"}" expands to "" if $var is empty, "-k $var" if not
-    - export PATH=/opt/qemu/bin:/tmp/uboot-test-hooks/bin:${PATH};
+    - export UBOOT_TRAVIS_BUILD_DIR=/tmp/.bm-work/${TEST_PY_BD};
+      export PATH=/opt/qemu/bin:/tmp/uboot-test-hooks/bin:${PATH};
       export PYTHONPATH=/tmp/uboot-test-hooks/py/travis-ci;
-      ./test/py/test.py -ra --bd ${TEST_PY_BD} ${TEST_PY_ID}
-        ${TEST_PY_TEST_SPEC:+"-k ${TEST_PY_TEST_SPEC}"}
-        --build-dir "$UBOOT_TRAVIS_BUILD_DIR"
-    # It seems that the files in /tmp go away, so copy out what we need
-    - if [[ "${TEST_PY_BD}" == "coreboot" ]]; then
-        cp -v /tmp/coreboot/*.{html,css} .;
-      fi
+      if [[ "${TEST_PY_BD}" != "" ]]; then
+        ./test/py/test.py --bd ${TEST_PY_BD} ${TEST_PY_ID}
+          -k "${TEST_PY_TEST_SPEC:-not a_test_which_does_not_exist}"
+          --build-dir "$UBOOT_TRAVIS_BUILD_DIR";
+        ret=$?;
+        if [[ $ret -ne 0 ]]; then
+          exit $ret;
+        fi;
+      fi;
 
 build all 32bit ARM platforms:
+  tags: [ 'all' ]
   stage: world build
   script:
     - ret=0;
-      ./tools/buildman/buildman -o /tmp -P -E -W arm -x aarch64 || ret=$?;
-      if [[ $ret -ne 0 ]]; then
-        ./tools/buildman/buildman -o /tmp -seP;
+      ./tools/buildman/buildman -o /tmp -P -E arm -x aarch64 || ret=$?;
+      if [[ $ret -ne 0 && $ret -ne 129 ]]; then
+        ./tools/buildman/buildman -o /tmp -sdeP;
         exit $ret;
       fi;
 
 build all 64bit ARM platforms:
+  tags: [ 'all' ]
   stage: world build
   script:
-    - virtualenv -p /usr/bin/python3 /tmp/venv
+    - virtualenv /tmp/venv
     - . /tmp/venv/bin/activate
     - pip install pyelftools
     - ret=0;
-      ./tools/buildman/buildman -o /tmp -P -E -W aarch64 || ret=$?;
-      if [[ $ret -ne 0 ]]; then
-        ./tools/buildman/buildman -o /tmp -seP;
+      ./tools/buildman/buildman -o /tmp -P -E aarch64 || ret=$?;
+      if [[ $ret -ne 0 && $ret -ne 129 ]]; then
+        ./tools/buildman/buildman -o /tmp -sdeP;
         exit $ret;
       fi;
 
 build all PowerPC platforms:
+  tags: [ 'all' ]
   stage: world build
   script:
     - ret=0;
-      ./tools/buildman/buildman -o /tmp -P -E -W powerpc || ret=$?;
-      if [[ $ret -ne 0 ]]; then
-        ./tools/buildman/buildman -o /tmp -seP;
+      ./tools/buildman/buildman -o /tmp -P -E powerpc || ret=$?;
+      if [[ $ret -ne 0 && $ret -ne 129 ]]; then
+        ./tools/buildman/buildman -o /tmp -sdeP;
         exit $ret;
       fi;
 
 build all other platforms:
+  tags: [ 'all' ]
   stage: world build
   script:
     - ret=0;
-      ./tools/buildman/buildman -o /tmp -P -E -W -x arm,powerpc || ret=$?;
-      if [[ $ret -ne 0 ]]; then
-        ./tools/buildman/buildman -o /tmp -seP;
+      ./tools/buildman/buildman -o /tmp -P -E -x arm,powerpc || ret=$?;
+      if [[ $ret -ne 0 && $ret -ne 129 ]]; then
+        ./tools/buildman/buildman -o /tmp -sdeP;
         exit $ret;
       fi;
 
-check for migrated symbols in board header:
-  stage: testsuites
-  script:
-    - KSYMLST=`mktemp`;
-      KUSEDLST=`mktemp`;
-      RET=0;
-      cat `find . -name "Kconfig*"` |
-         sed -n -e 's/^\s*config *\([A-Za-z0-9_]*\).*$/CONFIG_\1/p'
-         -e 's/^\s*menuconfig *\([A-Za-z0-9_]*\).*$/CONFIG_\1/p'
-         | sort -u > $KSYMLST;
-      for CFG in `find include/configs -name "*.h"`; do
-         (grep '#define[[:blank:]]CONFIG_' $CFG |
-            sed -n 's/#define.\(CONFIG_[A-Za-z0-9_]*\).*/\1/p' ;
-            grep '#undef[[:blank:]]CONFIG_' $CFG |
-            sed -n 's/#undef.\(CONFIG_[A-Za-z0-9_]*\).*/\1/p') |
-            sort -u > ${KUSEDLST} || true;
-         NUM=`comm -123 --total --output-delimiter=, ${KSYMLST} ${KUSEDLST} |
-            cut -d , -f 3`;
-         if [[ $NUM -ne 0 ]]; then
-            echo "Unmigrated symbols found in $CFG:";
-            comm -12 ${KSYMLST} ${KUSEDLST};
-            RET=1;
-         fi;
-      done;
-      exit $RET
-
 # QA jobs for code analytics
 # static code analysis with cppcheck (we can add --enable=all later)
 cppcheck:
+  tags: [ 'all' ]
   stage: testsuites
   script:
-    - cppcheck -j$(nproc) --force --quiet --inline-suppr .
+    - cppcheck --force --quiet --inline-suppr .
 
 # search for TODO within source tree
 grep TODO/FIXME/HACK:
+  tags: [ 'all' ]
   stage: testsuites
   script:
     - grep -r TODO .
@@ -161,294 +123,220 @@ grep TODO/FIXME/HACK:
     # search for HACK within source tree and ignore HACKKIT board
     - grep -r HACK . | grep -v HACKKIT
 
-# build HTML documentation
-htmldocs:
-  stage: testsuites
-  script:
-    - virtualenv -p /usr/bin/python3 /tmp/venvhtml
-    - . /tmp/venvhtml/bin/activate
-    - pip install -r doc/sphinx/requirements.txt
-    - make htmldocs
-
 # some statistics about the code base
 sloccount:
+  tags: [ 'all' ]
   stage: testsuites
   script:
     - sloccount .
 
 # ensure all configs have MAINTAINERS entries
 Check for configs without MAINTAINERS entry:
+  tags: [ 'all' ]
   stage: testsuites
   script:
-    - ./tools/buildman/buildman -R
+    - if [ `./tools/genboardscfg.py -f 2>&1 | wc -l` -ne 0 ]; then exit 1; fi
 
 # Ensure host tools build
 Build tools-only:
+  tags: [ 'all' ]
   stage: testsuites
   script:
     - make tools-only_config tools-only -j$(nproc)
 
 # Ensure env tools build
 Build envtools:
+  tags: [ 'all' ]
   stage: testsuites
   script:
     - make tools-only_config envtools -j$(nproc)
 
-Run binman, buildman, dtoc, Kconfig and patman testsuites:
+Run binman, buildman, dtoc and patman testsuites:
+  tags: [ 'all' ]
   stage: testsuites
   script:
     - git config --global user.name "GitLab CI Runner";
       git config --global user.email trini@konsulko.com;
-      git config --global --add safe.directory "${CI_PROJECT_DIR}";
       export USER=gitlab;
-      virtualenv -p /usr/bin/python3 /tmp/venv;
+      virtualenv /tmp/venv;
       . /tmp/venv/bin/activate;
-      pip install -r test/py/requirements.txt;
-      export UBOOT_TRAVIS_BUILD_DIR=/tmp/sandbox_spl;
+      pip install pyelftools;
+      export UBOOT_TRAVIS_BUILD_DIR=/tmp/.bm-work/sandbox_spl;
       export PYTHONPATH="${UBOOT_TRAVIS_BUILD_DIR}/scripts/dtc/pylibfdt";
       export PATH="${UBOOT_TRAVIS_BUILD_DIR}/scripts/dtc:${PATH}";
-      set +e;
-      ./tools/buildman/buildman -T0 -o ${UBOOT_TRAVIS_BUILD_DIR} -w
-        --board sandbox_spl;
-      set -e;
+      ./tools/buildman/buildman -o /tmp -P sandbox_spl;
       ./tools/binman/binman --toolpath ${UBOOT_TRAVIS_BUILD_DIR}/tools test;
       ./tools/buildman/buildman -t;
       ./tools/dtoc/dtoc -t;
-      ./tools/patman/patman test;
-      make testconfig
-
-Run tests for Nokia RX-51 (aka N900):
-  stage: testsuites
-  script:
-    - export PATH=/opt/gcc-11.1.0-nolibc/arm-linux-gnueabi/bin:$PATH;
-      test/nokia_rx51_test.sh
-
-# Check for any pylint regressions
-Run pylint:
-  stage: testsuites
-  script:
-    - git config --global --add safe.directory "${CI_PROJECT_DIR}"
-    - pip install -r test/py/requirements.txt
-    - pip install asteval pylint==2.12.2 pyopenssl
-    - export PATH=${PATH}:~/.local/bin
-    - echo "[MASTER]" >> .pylintrc
-    - echo "load-plugins=pylint.extensions.docparams" >> .pylintrc
-    - export UBOOT_TRAVIS_BUILD_DIR=/tmp/sandbox_spl
-    - set +e
-    - ./tools/buildman/buildman -T0 -o ${UBOOT_TRAVIS_BUILD_DIR} -w
-        --board sandbox_spl
-    - set -e
-    - pylint --version
-    - export PYTHONPATH="${UBOOT_TRAVIS_BUILD_DIR}/scripts/dtc/pylibfdt"
-    - make pylint_err
+      ./tools/patman/patman --test
 
 # Test sandbox with test.py
 sandbox test.py:
+  tags: [ 'all' ]
   variables:
     TEST_PY_BD: "sandbox"
+    BUILDMAN: "^sandbox$"
   <<: *buildman_and_testpy_dfn
 
 sandbox with clang test.py:
+  tags: [ 'all' ]
   variables:
     TEST_PY_BD: "sandbox"
-    OVERRIDE: "-O clang-13"
+    BUILDMAN: "^sandbox$"
+    OVERRIDE: "-O clang-7"
   <<: *buildman_and_testpy_dfn
 
 sandbox_spl test.py:
+  tags: [ 'all' ]
   variables:
     TEST_PY_BD: "sandbox_spl"
-    TEST_PY_TEST_SPEC: "test_ofplatdata or test_handoff or test_spl"
-  <<: *buildman_and_testpy_dfn
-
-sandbox_noinst_test.py:
-  variables:
-    TEST_PY_BD: "sandbox_noinst"
-    TEST_PY_TEST_SPEC: "test_ofplatdata or test_handoff or test_spl"
-  <<: *buildman_and_testpy_dfn
-
-sandbox_vpl test.py:
-  variables:
-    TEST_PY_BD: "sandbox_vpl"
-    TEST_PY_TEST_SPEC: "test_vpl_help or test_spl"
+    BUILDMAN: "^sandbox_spl$"
+    TEST_PY_TEST_SPEC: "test_ofplatdata"
   <<: *buildman_and_testpy_dfn
 
 evb-ast2500 test.py:
+  tags: [ 'all' ]
   variables:
     TEST_PY_BD: "evb-ast2500"
     TEST_PY_ID: "--id qemu"
-  <<: *buildman_and_testpy_dfn
-
-evb-ast2600 test.py:
-  variables:
-    TEST_PY_BD: "evb-ast2600"
-    TEST_PY_ID: "--id qemu"
+    BUILDMAN: "^evb-ast2500$"
   <<: *buildman_and_testpy_dfn
 
 sandbox_flattree test.py:
+  tags: [ 'all' ]
   variables:
     TEST_PY_BD: "sandbox_flattree"
+    BUILDMAN: "^sandbox_flattree$"
+  <<: *buildman_and_testpy_dfn
+
+vexpress_ca15_tc2 test.py:
+  tags: [ 'all' ]
+  variables:
+    TEST_PY_BD: "vexpress_ca15_tc2"
+    TEST_PY_ID: "--id qemu"
+    BUILDMAN: "^vexpress_ca15_tc2$"
   <<: *buildman_and_testpy_dfn
 
 vexpress_ca9x4 test.py:
+  tags: [ 'all' ]
   variables:
     TEST_PY_BD: "vexpress_ca9x4"
     TEST_PY_ID: "--id qemu"
+    BUILDMAN: "^vexpress_ca9x4$"
   <<: *buildman_and_testpy_dfn
 
 integratorcp_cm926ejs test.py:
+  tags: [ 'all' ]
   variables:
     TEST_PY_BD: "integratorcp_cm926ejs"
     TEST_PY_TEST_SPEC: "not sleep"
     TEST_PY_ID: "--id qemu"
+    BUILDMAN: "^integratorcp_cm926ejs$"
   <<: *buildman_and_testpy_dfn
 
 qemu_arm test.py:
+  tags: [ 'all' ]
   variables:
     TEST_PY_BD: "qemu_arm"
     TEST_PY_TEST_SPEC: "not sleep"
+    BUILDMAN: "^qemu_arm$"
   <<: *buildman_and_testpy_dfn
 
 qemu_arm64 test.py:
+  tags: [ 'all' ]
   variables:
     TEST_PY_BD: "qemu_arm64"
     TEST_PY_TEST_SPEC: "not sleep"
+    BUILDMAN: "^qemu_arm64$"
   <<: *buildman_and_testpy_dfn
 
-qemu_malta test.py:
+qemu_mips test.py:
+  tags: [ 'all' ]
   variables:
-    TEST_PY_BD: "malta"
-    TEST_PY_TEST_SPEC: "not sleep and not efi"
-    TEST_PY_ID: "--id qemu"
+    TEST_PY_BD: "qemu_mips"
+    TEST_PY_TEST_SPEC: "not sleep"
+    BUILDMAN: "^qemu_mips$"
   <<: *buildman_and_testpy_dfn
 
-qemu_maltael test.py:
+qemu_mipsel test.py:
+  tags: [ 'all' ]
   variables:
-    TEST_PY_BD: "maltael"
-    TEST_PY_TEST_SPEC: "not sleep and not efi"
-    TEST_PY_ID: "--id qemu"
+    TEST_PY_BD: "qemu_mipsel"
+    TEST_PY_TEST_SPEC: "not sleep"
+    BUILDMAN: "^qemu_mipsel$"
   <<: *buildman_and_testpy_dfn
 
-qemu_malta64 test.py:
+qemu_mips64 test.py:
+  tags: [ 'all' ]
   variables:
-    TEST_PY_BD: "malta64"
-    TEST_PY_TEST_SPEC: "not sleep and not efi"
-    TEST_PY_ID: "--id qemu"
+    TEST_PY_BD: "qemu_mips64"
+    TEST_PY_TEST_SPEC: "not sleep"
+    BUILDMAN: "^qemu_mips64$"
   <<: *buildman_and_testpy_dfn
 
-qemu_malta64el test.py:
+qemu_mips64el test.py:
+  tags: [ 'all' ]
   variables:
-    TEST_PY_BD: "malta64el"
-    TEST_PY_TEST_SPEC: "not sleep and not efi"
-    TEST_PY_ID: "--id qemu"
+    TEST_PY_BD: "qemu_mips64el"
+    TEST_PY_TEST_SPEC: "not sleep"
+    BUILDMAN: "^qemu_mips64el$"
   <<: *buildman_and_testpy_dfn
 
 qemu-ppce500 test.py:
+  tags: [ 'all' ]
   variables:
     TEST_PY_BD: "qemu-ppce500"
     TEST_PY_TEST_SPEC: "not sleep"
-  <<: *buildman_and_testpy_dfn
-
-qemu-riscv32 test.py:
-  variables:
-    TEST_PY_BD: "qemu-riscv32"
-    TEST_PY_TEST_SPEC: "not sleep"
+    BUILDMAN: "^qemu-ppce500$"
   <<: *buildman_and_testpy_dfn
 
 qemu-riscv64 test.py:
+  tags: [ 'all' ]
   variables:
     TEST_PY_BD: "qemu-riscv64"
     TEST_PY_TEST_SPEC: "not sleep"
-  <<: *buildman_and_testpy_dfn
-
-qemu-riscv32_spl test.py:
-  variables:
-    TEST_PY_BD: "qemu-riscv32_spl"
-    TEST_PY_TEST_SPEC: "not sleep"
-  <<: *buildman_and_testpy_dfn
-
-qemu-riscv64_spl test.py:
-  variables:
-    TEST_PY_BD: "qemu-riscv64_spl"
-    TEST_PY_TEST_SPEC: "not sleep"
+    BUILDMAN: "^qemu-riscv64$"
   <<: *buildman_and_testpy_dfn
 
 qemu-x86 test.py:
+  tags: [ 'all' ]
   variables:
     TEST_PY_BD: "qemu-x86"
     TEST_PY_TEST_SPEC: "not sleep"
+    BUILDMAN: "^qemu-x86$"
   <<: *buildman_and_testpy_dfn
 
 qemu-x86_64 test.py:
+  tags: [ 'all' ]
   variables:
     TEST_PY_BD: "qemu-x86_64"
     TEST_PY_TEST_SPEC: "not sleep"
+    BUILDMAN: "^qemu-x86_64$"
   <<: *buildman_and_testpy_dfn
 
-r2dplus_i82557c test.py:
+zynq_zc702 test.py:
+  tags: [ 'all' ]
   variables:
-    TEST_PY_BD: "r2dplus"
-    TEST_PY_ID: "--id i82557c_qemu"
-  <<: *buildman_and_testpy_dfn
-
-r2dplus_pcnet test.py:
-  variables:
-    TEST_PY_BD: "r2dplus"
-    TEST_PY_ID: "--id pcnet_qemu"
-  <<: *buildman_and_testpy_dfn
-
-r2dplus_rtl8139 test.py:
-  variables:
-    TEST_PY_BD: "r2dplus"
-    TEST_PY_ID: "--id rtl8139_qemu"
-  <<: *buildman_and_testpy_dfn
-
-r2dplus_tulip test.py:
-  variables:
-    TEST_PY_BD: "r2dplus"
-    TEST_PY_ID: "--id tulip_qemu"
-  <<: *buildman_and_testpy_dfn
-
-sifive_unleashed_sdcard test.py:
-  variables:
-    TEST_PY_BD: "sifive_unleashed"
-    TEST_PY_ID: "--id sdcard_qemu"
-  <<: *buildman_and_testpy_dfn
-
-sifive_unleashed_spi-nor test.py:
-  variables:
-    TEST_PY_BD: "sifive_unleashed"
-    TEST_PY_ID: "--id spi-nor_qemu"
-  <<: *buildman_and_testpy_dfn
-
-xilinx_zynq_virt test.py:
-  variables:
-    TEST_PY_BD: "xilinx_zynq_virt"
+    TEST_PY_BD: "zynq_zc702"
     TEST_PY_TEST_SPEC: "not sleep"
     TEST_PY_ID: "--id qemu"
+    BUILDMAN: "^zynq_zc702$"
   <<: *buildman_and_testpy_dfn
 
 xilinx_versal_virt test.py:
+  tags: [ 'all' ]
   variables:
     TEST_PY_BD: "xilinx_versal_virt"
     TEST_PY_TEST_SPEC: "not sleep"
     TEST_PY_ID: "--id qemu"
+    BUILDMAN: "^xilinx_versal_virt$"
   <<: *buildman_and_testpy_dfn
 
 xtfpga test.py:
+  tags: [ 'all' ]
   variables:
     TEST_PY_BD: "xtfpga"
     TEST_PY_TEST_SPEC: "not sleep"
     TEST_PY_ID: "--id qemu"
-  <<: *buildman_and_testpy_dfn
-
-coreboot test.py:
-  variables:
-    TEST_PY_BD: "coreboot"
-    TEST_PY_TEST_SPEC: "not sleep"
-    TEST_PY_ID: "--id qemu"
-  artifacts:
-    paths:
-      - "*.html"
-      - "*.css"
-    expire_in: 1 week
+    BUILDMAN: "^xtfpga$"
   <<: *buildman_and_testpy_dfn

.mailmap

@@ -20,60 +20,28 @@ Allen Martin <amartin@nvidia.com>
 Andreas Bießmann <andreas.devel@googlemail.com>
 Andreas Bießmann <andreas@biessmann.org>
 Aneesh V <aneesh@ti.com>
-Anup Patel <anup@brainfault.org> <anup.patel@wdc.com>
-Atish Patra <atishp@atishpatra.org> <atish.patra@wdc.com>
-Bin Meng <bmeng.cn@gmail.com> <bin.meng@windriver.com>
 Boris Brezillon <bbrezillon@kernel.org> <boris.brezillon@bootlin.com>
 Boris Brezillon <bbrezillon@kernel.org> <boris.brezillon@free-electrons.com>
 Dirk Behme <dirk.behme@googlemail.com>
 Fabio Estevam <fabio.estevam@nxp.com>
-Heinrich Schuchardt <xypron.glpk@gmx.de> <heinrich.schuchardt@canonical.com>
-Heinrich Schuchardt <xypron.glpk@gmx.de> xypron.glpk@gmx.de <xypron.glpk@gmx.de>
 Jagan Teki <402jagan@gmail.com>
 Jagan Teki <jaganna@gmail.com>
 Jagan Teki <jaganna@xilinx.com>
 Jagan Teki <jagannadh.teki@gmail.com>
 Jagan Teki <jagannadha.sutradharudu-teki@xilinx.com>
-Jernej Skrabec <jernej.skrabec@gmail.com> <jernej.skrabec@siol.net>
 Igor Opaniuk <igor.opaniuk@gmail.com> <igor.opaniuk@linaro.org>
-Igor Opaniuk <igor.opaniuk@gmail.com> <igor.opaniuk@toradex.com>
-Marek Behún <kabel@kernel.org> <marek.behun@nic.cz>
-Marek Behún <kabel@kernel.org> Marek Behun <marek.behun@nic.cz>
-Marek Vasut <marex@denx.de> <marek.vasut+renesas@gmail.com>
-Marek Vasut <marex@denx.de> <marek.vasut@gmail.com>
-Marek Vasut <marex@denx.de> <marex at denx.de>
 Markus Klotzbuecher <mk@denx.de>
-Masahiro Yamada <yamada.masahiro@socionext.com> <yamada.m@jp.panasonic.com>
-Masahiro Yamada <yamada.masahiro@socionext.com> <masahiroy@kernel.org>
-Michal Simek <michal.simek@amd.com> <michal.simek@xilinx.com>
-Michal Simek <michal.simek@xilinx.com> <monstr@monstr.eu>
-Michal Simek <michal.simek@xilinx.com> <Monstr@seznam.cz>
-Michal Simek <michal.simek@xilinx.com> <root@monstr.eu>
-Neil Armstrong <neil.armstrong@linaro.org> <narmstrong@baylibre.com>
-Nicolas Saenz Julienne <nsaenz@kernel.org> <nsaenzjulienne@suse.de>
-Patrice Chotard <patrice.chotard@foss.st.com> <patrice.chotard@st.com>
-Patrick Delaunay <patrick.delaunay@foss.st.com> <patrick.delaunay@st.com>
 Paul Burton <paul.burton@mips.com> <paul.burton@imgtec.com>
 Prabhakar Kushwaha <prabhakar@freescale.com>
 Rajeshwari Shinde <rajeshwari.s@samsung.com>
 Ricardo Ribalda <ricardo@ribalda.com> <ricardo.ribalda@uam.es>
 Ricardo Ribalda <ricardo@ribalda.com> <ricardo.ribalda@gmail.com>
-Ruchika Gupta <ruchika.gupta@nxp.com> <ruchika.gupta@freescale.com>
 Sandeep Paulraj <s-paulraj@ti.com>
 Shaohui Xie <Shaohui.Xie@freescale.com>
-Stefan Roese <sr@denx.de> <stroese>
+Stefan Roese <stroese>
 Stefano Babic <sbabic@denx.de>
-Tom Rini <trini@konsulko.com> <trini@ti.com>
 TsiChung Liew <Tsi-Chung.Liew@freescale.com>
-Wolfgang Denk <wd@denx.de> <wdenk>
-Wolfgang Denk <wd@denx.de> <wd@pollux.denx.de>
-Wolfgang Denk <wd@denx.de> <wd@pollux.(none)>
-Wolfgang Denk <wd@denx.de> <wd@fifi.denx.de>
-Wolfgang Denk <wd@denx.de> <wd@nyx.denx.de>
-Wolfgang Denk <wd@denx.de> <wd@atlas.denx.de>
-Wolfgang Denk <wd@denx.de> <wd@castor.denx.de>
-Wolfgang Denk <wd@denx.de> <wd@xpert.denx.de>
-Wolfgang Denk <wd@denx.de> <wd@nyx.(none)>
+Wolfgang Denk <wdenk>
 York Sun <yorksun@freescale.com>
 York Sun <york.sun@nxp.com>
 Łukasz Majewski <l.majewski@samsung.com>

.readthedocs.yml

@@ -1,24 +0,0 @@
-# .readthedocs.yml
-# Read the Docs configuration file
-# See https://docs.readthedocs.io/en/stable/config-file/v2.html for details
-
-# Required
-version: 2
-
-build:
-  os: "ubuntu-20.04"
-  apt_packages:
-    - python3-six
-  tools:
-    python: "3.9"
-
-# Build documentation in the docs/ directory with Sphinx
-sphinx:
-  configuration: doc/conf.py
-
-# Optionally build your docs in additional formats such as PDF and ePub
-formats: []
-
-python:
-  install:
-    - requirements: doc/sphinx/requirements.txt

.travis.yml

@@ -0,0 +1,528 @@
+# SPDX-License-Identifier: GPL-2.0+
+# Copyright Roger Meier <r.meier@siemens.com>
+
+# build U-Boot on Travis CI - https://travis-ci.org/
+
+sudo: required
+dist: bionic
+
+language: c
+
+addons:
+  apt:
+    sources:
+    - ubuntu-toolchain-r-test
+    - llvm-toolchain-bionic-7
+    packages:
+    - cppcheck
+    - sloccount
+    - sparse
+    - bc
+    - build-essential
+    - libsdl1.2-dev
+    - python
+    - python-pyelftools
+    - python3-virtualenv
+    - python3-pip
+    - swig
+    - libpython-dev
+    - iasl
+    - grub-efi-ia32-bin
+    - grub-efi-amd64-bin
+    - rpm2cpio
+    - wget
+    - device-tree-compiler
+    - lzop
+    - liblz4-tool
+    - lzma-alone
+    - libisl15
+    - clang-7
+    - srecord
+
+install:
+ # Clone uboot-test-hooks
+ - git clone --depth=1 git://github.com/swarren/uboot-test-hooks.git /tmp/uboot-test-hooks
+ - ln -s travis-ci /tmp/uboot-test-hooks/bin/`hostname`
+ - ln -s travis-ci /tmp/uboot-test-hooks/py/`hostname`
+ # prepare buildman environment
+ - echo -e "[toolchain]\nroot = /usr" > ~/.buildman
+ - echo -e "arc = /tmp/arc_gnu_2018.09_prebuilt_uclibc_le_archs_linux_install" >> ~/.buildman
+ - echo -e "\n[toolchain-alias]\nsh = sh2" >> ~/.buildman
+ - echo -e "x86 = i386" >> ~/.buildman;
+ - echo -e "riscv = riscv64" >> ~/.buildman;
+ - cat ~/.buildman
+ - grub-mkimage --prefix="" -o ~/grub_x86.efi -O i386-efi normal  echo lsefimmap lsefi lsefisystab efinet tftp minicmd
+ - grub-mkimage --prefix="" -o ~/grub_x64.efi -O x86_64-efi normal  echo lsefimmap lsefi lsefisystab efinet tftp minicmd
+ - mkdir ~/grub2-arm
+ - ( cd ~/grub2-arm; wget -O - http://download.opensuse.org/ports/armv7hl/distribution/leap/42.2/repo/oss/suse/armv7hl/grub2-arm-efi-2.02~beta2-87.1.armv7hl.rpm | rpm2cpio | cpio -di )
+ - mkdir ~/grub2-arm64
+ - ( cd ~/grub2-arm64; wget -O - http://download.opensuse.org/ports/aarch64/distribution/leap/42.2/repo/oss/suse/aarch64/grub2-arm64-efi-2.02~beta2-87.1.aarch64.rpm | rpm2cpio | cpio -di )
+ - wget http://mirrors.kernel.org/ubuntu/pool/main/m/mpfr4/libmpfr4_3.1.4-1_amd64.deb && sudo dpkg -i libmpfr4_3.1.4-1_amd64.deb && rm libmpfr4_3.1.4-1_amd64.deb
+
+env:
+  global:
+    - PATH=/tmp/qemu-install/bin:/tmp/uboot-test-hooks/bin:/usr/bin:/bin:/usr/local/bin
+    - PYTHONPATH=/tmp/uboot-test-hooks/py/travis-ci
+    - BUILD_DIR=build
+    - HOSTCC="cc"
+    - HOSTCXX="c++"
+    - QEMU_VERSION="v3.1.0"
+
+before_script:
+  # install toolchains based on TOOLCHAIN} variable
+  - if [[ "${TOOLCHAIN}" == *m68k* ]]; then ./tools/buildman/buildman --fetch-arch m68k ; fi
+  - if [[ "${TOOLCHAIN}" == *microblaze* ]]; then ./tools/buildman/buildman --fetch-arch microblaze ; fi
+  - if [[ "${TOOLCHAIN}" == *mips* ]]; then ./tools/buildman/buildman --fetch-arch mips ; fi
+  - if [[ "${TOOLCHAIN}" == *sh* ]]; then ./tools/buildman/buildman --fetch-arch sh2 ; fi
+  - if [[ "${TOOLCHAIN}" == *i386* ]]; then
+      ./tools/buildman/buildman --fetch-arch i386;
+    fi
+  - if [[ "${TOOLCHAIN}" == arc ]]; then
+       wget https://github.com/foss-for-synopsys-dwc-arc-processors/toolchain/releases/download/arc-2018.09-release/arc_gnu_2018.09_prebuilt_uclibc_le_archs_linux_install.tar.gz &&
+       tar -C /tmp -xf arc_gnu_2018.09_prebuilt_uclibc_le_archs_linux_install.tar.gz;
+    fi
+  - if [[ "${TOOLCHAIN}" == "nds32" ]]; then
+       wget https://github.com/vincentzwc/prebuilt-nds32-toolchain/releases/download/20180521/nds32le-linux-glibc-v3-upstream.tar.gz &&
+       tar -C /tmp -xf nds32le-linux-glibc-v3-upstream.tar.gz &&
+       echo -e "\n[toolchain-prefix]\nnds32 = /tmp/nds32le-linux-glibc-v3-upstream/bin/nds32le-linux-" >> ~/.buildman;
+    fi
+  - if [[ "${TOOLCHAIN}" == *xtensa* ]]; then
+       wget https://github.com/foss-xtensa/toolchain/releases/download/2018.02/x86_64-2018.02-${TOOLCHAIN}.tar.gz &&
+       tar -C /tmp -xf x86_64-2018.02-${TOOLCHAIN}.tar.gz &&
+       echo -e "\n[toolchain-prefix]\nxtensa = /tmp/2018.02/${TOOLCHAIN}/bin/${TOOLCHAIN}-" >> ~/.buildman;
+    fi
+  # If TOOLCHAIN is unset, we're on some flavour of ARM.
+  - if [[ "${TOOLCHAIN}" == "" ]]; then
+       ./tools/buildman/buildman --fetch-arch arm &&
+       ./tools/buildman/buildman --fetch-arch aarch64;
+    fi
+  - if [[ "${TOOLCHAIN}" == "powerpc" ]]; then ./tools/buildman/buildman --fetch-arch powerpc; fi
+  - if [[ "${TOOLCHAIN}" == "riscv" ]]; then
+       ./tools/buildman/buildman --fetch-arch riscv64;
+    fi
+  - if [[ "${QEMU_TARGET}" != "" ]]; then
+       git clone git://git.qemu.org/qemu.git /tmp/qemu;
+       pushd /tmp/qemu;
+       git submodule update --init dtc &&
+       git checkout ${QEMU_VERSION} &&
+       ./configure --prefix=/tmp/qemu-install --target-list=${QEMU_TARGET} &&
+       make -j4 all install;
+       popd;
+    fi
+
+script:
+ # Comments must be outside the command strings below, or the Travis parser
+ # will get confused.
+ #
+ # From buildman, exit code 129 means warnings only.  If we've been asked to
+ # use clang only do one configuration.
+ - if [[ "${BUILDMAN}" != "" ]]; then
+     ret=0;
+     tools/buildman/buildman -P -E ${BUILDMAN} ${OVERRIDE}|| ret=$?;
+     if [[ $ret -ne 0 && $ret -ne 129 ]]; then
+       tools/buildman/buildman -sdeP ${BUILDMAN};
+       exit $ret;
+     fi;
+   fi
+ # "not a_test_which_does_not_exist" is a dummy -k parameter which will
+ # never prevent any test from running. That way, we can always pass
+ # "-k something" even when $TEST_PY_TEST_SPEC doesnt need a custom
+ # value.
+ - export UBOOT_TRAVIS_BUILD_DIR=`cd .. && pwd`/.bm-work/${TEST_PY_BD};
+   cp ~/grub_x86.efi $UBOOT_TRAVIS_BUILD_DIR/;
+   cp ~/grub_x64.efi $UBOOT_TRAVIS_BUILD_DIR/;
+   cp ~/grub2-arm/usr/lib/grub2/arm-efi/grub.efi $UBOOT_TRAVIS_BUILD_DIR/grub_arm.efi;
+   cp ~/grub2-arm64/usr/lib/grub2/arm64-efi/grub.efi $UBOOT_TRAVIS_BUILD_DIR/grub_arm64.efi;
+   if [[ -n "${TEST_PY_TOOLS}" ]]; then
+     PYTHONPATH="${UBOOT_TRAVIS_BUILD_DIR}/scripts/dtc/pylibfdt"
+     PATH="${UBOOT_TRAVIS_BUILD_DIR}/scripts/dtc:${PATH}"
+     ./tools/binman/binman --toolpath ${UBOOT_TRAVIS_BUILD_DIR}/tools test &&
+     ./tools/patman/patman --test &&
+     ./tools/buildman/buildman -t &&
+     PYTHONPATH="${UBOOT_TRAVIS_BUILD_DIR}/scripts/dtc/pylibfdt"
+     PATH="${UBOOT_TRAVIS_BUILD_DIR}/scripts/dtc:${PATH}"
+     ./tools/dtoc/dtoc -t;
+   fi;
+   if [[ "${TEST_PY_BD}" != "" ]]; then
+     virtualenv -p /usr/bin/python3 /tmp/venv;
+     . /tmp/venv/bin/activate;
+     pip install -r test/py/requirements.txt;
+     ./test/py/test.py --bd ${TEST_PY_BD} ${TEST_PY_ID}
+       -k "${TEST_PY_TEST_SPEC:-not a_test_which_does_not_exist}"
+       --build-dir "$UBOOT_TRAVIS_BUILD_DIR";
+     ret=$?;
+     if [[ $ret -ne 0 ]]; then
+       exit $ret;
+     fi;
+   fi
+
+matrix:
+  include:
+  # we need to build by vendor due to 50min time limit for builds
+  # each env setting here is a dedicated build
+    - name: "buildman arc"
+      env:
+        - BUILDMAN="arc"
+          TOOLCHAIN="arc"
+    - name: "buildman arm11 arm7 arm920t arm946es"
+      env:
+        - BUILDMAN="arm11 arm7 arm920t arm946es"
+    - name: "buildman arm926ejs (non-NXP,siemens,at91,kirkwood,spear)"
+      env:
+        - JOB="arm926ejs"
+          BUILDMAN="arm926ejs -x freescale,siemens,at91,kirkwood,spear,omap"
+    - name: "buildman at91 (non arm v7)"
+      env:
+        - BUILDMAN="at91 -x armv7"
+    - name: "buildman at91 (non arm926ejs)"
+      env:
+        - BUILDMAN="at91 -x arm926ejs"
+    - name: "buildman boundary engicam toradex"
+      env:
+        - BUILDMAN="boundary engicam toradex"
+    - name: "buildman ARM bcm"
+      env:
+        - BUILDMAN="bcm -x mips"
+    - name: "buildman NXP ARM32 (catch-all)"
+      env:
+        - BUILDMAN="freescale -x powerpc,m68k,aarch64,ls101,ls102,ls104,ls108,ls20,lx216"
+    - name: "buildman NXP LS101x"
+      env:
+        - BUILDMAN="freescale&ls101"
+    - name: "buildman NXP LS102x"
+      env:
+        - BUILDMAN="freescale&ls102"
+    - name: "buildman NXP LS104x"
+      env:
+        - BUILDMAN="freescale&ls104"
+    - name: "buildman NXP LS108x"
+      env:
+        - BUILDMAN="freescale&ls108"
+    - name: "buildman NXP LS20xx"
+      env:
+        - BUILDMAN="freescale&ls20"
+    - name: "buildman NXP LX216x"
+      env:
+        - BUILDMAN="freescale&lx216"
+    - name: "buildman i.MX6 tqc"
+      env:
+        - BUILDMAN="mx6&tqc"
+    - name: "buildman i.MX6 (catch-all)"
+      env:
+        - BUILDMAN="mx6 -x boundary,engicam,freescale,technexion,toradex,tqc"
+    - name: "buildman i.MX (non-i.MX6 catch-all)"
+      env:
+        - BUILDMAN="mx -x freescale,mx6,toradex,technexion"
+    - name: "buildman keystone 2/3"
+      env:
+        - BUILDMAN="k2 k3"
+    - name: "buildman samsung socfpga"
+      env:
+        - BUILDMAN="samsung socfpga"
+    - name: "buildman spear"
+      env:
+        - BUILDMAN="spear"
+    - name: "buildman sun4i"
+      env:
+        - BUILDMAN="sun4i"
+    - name: "buildman sun5i"
+      env:
+        - BUILDMAN="sun5i"
+    - name: "buildman sun6i"
+      env:
+        - BUILDMAN="sun6i"
+    - name: "buildman sun7i"
+      env:
+        - BUILDMAN="sun7i"
+    - name: "buildman 64bit sun8i"
+      env:
+        - BUILDMAN="sun8i&aarch64 -x orangepi"
+    - name: "buildman 32bit sun8i"
+      env:
+        - BUILDMAN="sun8i&armv7 -x orangepi"
+    - name: "buildman sun9i"
+      env:
+        - BUILDMAN="sun9i"
+    - name: "buildman sun50i"
+      env:
+        - BUILDMAN="sun50i -x orangepi"
+    - name: "buildman catch-all ARM"
+      env:
+        - BUILDMAN="arm -x arm11,arm7,arm9,aarch64,at91,bcm,freescale,kirkwood,mvebu,siemens,tegra,uniphier,mx,samsung,sunxi,am33xx,omap,rockchip,toradex,socfpga,k2,k3,zynq"
+    - name: "buildman sandbox x86"
+      env:
+        - BUILDMAN="sandbox x86"
+          TOOLCHAIN="i386"
+    - name: "buildman technexion"
+      env:
+        - BUILDMAN="technexion"
+    - name: "buildman kirkwood"
+      env:
+        - BUILDMAN="kirkwood"
+    - name: "buildman mvebu"
+      env:
+        - BUILDMAN="mvebu"
+    - name: "buildman m68k"
+      env:
+        - BUILDMAN="m68k"
+          TOOLCHAIN="m68k"
+    - name: "buildman microblaze"
+      env:
+        - BUILDMAN="microblaze"
+          TOOLCHAIN="microblaze"
+    - name: "buildman mips"
+      env:
+        - BUILDMAN="mips"
+          TOOLCHAIN="mips"
+    - name: "buildman non-Freescale PowerPC"
+      env:
+        - BUILDMAN="powerpc -x freescale"
+          TOOLCHAIN="powerpc"
+    - name: "buildman mpc85xx&freescale (excluding many)"
+      env:
+        - BUILDMAN="mpc85xx&freescale -x t208xrdb -x t4qds -x t102* -x p1_p2_rdb_pc -x p1010rdb -x corenet_ds -x b4860qds -x bsc91*"
+          TOOLCHAIN="powerpc"
+    - name: "buildman t208xrdb corenet_ds"
+      env:
+        - BUILDMAN="t208xrdb corenet_ds"
+          TOOLCHAIN="powerpc"
+    - name: "buildman Freescale PowerPC"
+      env:
+        - BUILDMAN="t4qds b4860qds mpc83xx&freescale mpc86xx&freescale"
+          TOOLCHAIN="powerpc"
+    - name: "buildman t102*"
+      env:
+        - BUILDMAN="t102*"
+          TOOLCHAIN="powerpc"
+    - name: "buildman p1_p2_rdb_pc"
+      env:
+        - BUILDMAN="p1_p2_rdb_pc"
+          TOOLCHAIN="powerpc"
+    - name: "buildman p1010rdb bsc91"
+      env:
+        - BUILDMAN="p1010rdb bsc91"
+          TOOLCHAIN="powerpc"
+    - name: "buildman siemens"
+      env:
+        - BUILDMAN="siemens"
+    - name: "buildman tegra"
+      env:
+        - BUILDMAN="tegra -x toradex"
+    - name: "buildman am33xx (no siemens)"
+      env:
+        - BUILDMAN="am33xx -x siemens"
+    - name: "buildman omap"
+      env:
+        - BUILDMAN="omap"
+    - name: "buildman orangepi"
+      env:
+        - BUILDMAN="orangepi"
+    - name: "buildman uniphier"
+      env:
+        - BUILDMAN="uniphier"
+    - name: "buildman catch-all AArch64"
+      env:
+        - BUILDMAN="aarch64 -x bcm,k3,tegra,ls1,ls2,mvebu,uniphier,sunxi,samsung,rockchip,versal,zynq"
+    - name: "buildman rockchip"
+      env:
+        - BUILDMAN="rockchip -x orangepi"
+    - name: "buildman sh"
+      env:
+        - BUILDMAN="sh -x arm"
+          TOOLCHAIN="sh"
+    - name: "buildman Zynq* (ARMv7)"
+      env:
+        - BUILDMAN="zynq&armv7"
+    - name: "buildman ZynqMP and Versal"
+      env:
+        - BUILDMAN="versal|zynqmp&aarch64"
+    - name: "buildman xtensa"
+      env:
+        - BUILDMAN="xtensa"
+          TOOLCHAIN="xtensa-dc233c-elf"
+    - name: "buildman riscv"
+      env:
+        - BUILDMAN="riscv"
+          TOOLCHAIN="riscv"
+    - name: "buildman nds32"
+      env:
+        - BUILDMAN="nds32"
+          TOOLCHAIN="nds32"
+
+    # QA jobs for code analytics
+    # static code analysis with cppcheck (we can add --enable=all later)
+    - name: "cppcheck"
+      script:
+        - cppcheck --force --quiet --inline-suppr .
+    # search for TODO within source tree
+    - name: "grep TODO"
+      script:
+        - grep -r TODO .
+    # search for FIXME within source tree
+    - name: "grep FIXME HACK"
+      script:
+        - grep -r FIXME .
+    # search for HACK within source tree and ignore HACKKIT board
+      script:
+        - grep -r HACK . | grep -v HACKKIT
+    # some statistics about the code base
+    - name: "sloccount"
+      script:
+        - sloccount .
+    # ensure all configs have MAINTAINERS entries
+    - name: "Check for configs without MAINTAINERS entry"
+      script:
+        - if [ `./tools/genboardscfg.py -f 2>&1 | wc -l` -ne 0 ]; then exit 1; fi
+    # Ensure host tools build
+    - name: "Build tools-only"
+      script:
+        - make tools-only_config tools-only -j$(nproc)
+    # Ensure env tools build
+    - name: "Build envtools"
+      script:
+        - make tools-only_config envtools -j$(nproc)
+
+    # test/py
+    - name: "test/py sandbox"
+      env:
+        - TEST_PY_BD="sandbox"
+          BUILDMAN="^sandbox$"
+          TOOLCHAIN="i386"
+    - name: "test/py sandbox with clang"
+      env:
+        - TEST_PY_BD="sandbox"
+          BUILDMAN="^sandbox$"
+          OVERRIDE="-O clang-7"
+    - name: "test/py sandbox_spl"
+      env:
+        - TEST_PY_BD="sandbox_spl"
+          TEST_PY_TEST_SPEC="test_ofplatdata"
+          BUILDMAN="^sandbox$"
+          TOOLCHAIN="i386"
+          TEST_PY_TOOLS="yes"
+    - name: "test/py sandbox_flattree"
+      env:
+        - TEST_PY_BD="sandbox_flattree"
+          BUILDMAN="^sandbox_flattree$"
+          TOOLCHAIN="i386"
+    - name: "test/py evb-ast2500"
+      env:
+        - TEST_PY_BD="evb-ast2500"
+          TEST_PY_ID="--id qemu"
+          QEMU_TARGET="arm-softmmu"
+          QEMU_VERSION="506179e42112be77bfd071f050b15762d3b2cd43"
+          BUILDMAN="^evb-ast2500$"
+    - name: "test/py vexpress_ca15_tc2"
+      env:
+        - TEST_PY_BD="vexpress_ca15_tc2"
+          TEST_PY_ID="--id qemu"
+          QEMU_TARGET="arm-softmmu"
+          QEMU_VERSION="v3.0.0"
+          BUILDMAN="^vexpress_ca15_tc2$"
+    - name: "test/py vexpress_ca9x4"
+      env:
+        - TEST_PY_BD="vexpress_ca9x4"
+          TEST_PY_ID="--id qemu"
+          QEMU_TARGET="arm-softmmu"
+          BUILDMAN="^vexpress_ca9x4$"
+    - name: "test/py integratorcp_cm926ejs"
+      env:
+        - TEST_PY_BD="integratorcp_cm926ejs"
+          TEST_PY_TEST_SPEC="not sleep"
+          TEST_PY_ID="--id qemu"
+          QEMU_TARGET="arm-softmmu"
+          BUILDMAN="^integratorcp_cm926ejs$"
+    - name: "test/py qemu_arm"
+      env:
+        - TEST_PY_BD="qemu_arm"
+          TEST_PY_TEST_SPEC="not sleep"
+          QEMU_TARGET="arm-softmmu"
+          BUILDMAN="^qemu_arm$"
+    - name: "test/py qemu_arm64"
+      env:
+        - TEST_PY_BD="qemu_arm64"
+          TEST_PY_TEST_SPEC="not sleep"
+          QEMU_TARGET="aarch64-softmmu"
+          BUILDMAN="^qemu_arm64$"
+    - name: "test/py qemu_mips"
+      env:
+        - TEST_PY_BD="qemu_mips"
+          TEST_PY_TEST_SPEC="not sleep"
+          QEMU_TARGET="mips-softmmu"
+          BUILDMAN="^qemu_mips$"
+          TOOLCHAIN="mips"
+    - name: "test/py qemu_mipsel"
+      env:
+        - TEST_PY_BD="qemu_mipsel"
+          TEST_PY_TEST_SPEC="not sleep"
+          QEMU_TARGET="mipsel-softmmu"
+          BUILDMAN="^qemu_mipsel$"
+          TOOLCHAIN="mips"
+    - name: "test/py qemu_mips64"
+      env:
+        - TEST_PY_BD="qemu_mips64"
+          TEST_PY_TEST_SPEC="not sleep"
+          QEMU_TARGET="mips64-softmmu"
+          BUILDMAN="^qemu_mips64$"
+          TOOLCHAIN="mips"
+    - name: "test/py qemu_mips64el"
+      env:
+        - TEST_PY_BD="qemu_mips64el"
+          TEST_PY_TEST_SPEC="not sleep"
+          QEMU_TARGET="mips64el-softmmu"
+          BUILDMAN="^qemu_mips64el$"
+          TOOLCHAIN="mips"
+    - name: "test/py qemu-ppce500"
+      env:
+        - TEST_PY_BD="qemu-ppce500"
+          TEST_PY_TEST_SPEC="not sleep"
+          QEMU_TARGET="ppc-softmmu"
+          BUILDMAN="^qemu-ppce500$"
+          TOOLCHAIN="powerpc"
+    - name: "test/py qemu-riscv64"
+      env:
+        - TEST_PY_BD="qemu-riscv64"
+          TEST_PY_TEST_SPEC="not sleep"
+          QEMU_TARGET="riscv64-softmmu"
+          BUILDMAN="^qemu-riscv64$"
+          TOOLCHAIN="riscv"
+    - name: "test/py qemu-x86"
+      env:
+        - TEST_PY_BD="qemu-x86"
+          TEST_PY_TEST_SPEC="not sleep"
+          QEMU_TARGET="i386-softmmu"
+          BUILDMAN="^qemu-x86$"
+          TOOLCHAIN="i386"
+          BUILD_ROM="yes"
+    - name: "test/py qemu-x86_64"
+      env:
+        - TEST_PY_BD="qemu-x86_64"
+          TEST_PY_TEST_SPEC="not sleep"
+          QEMU_TARGET="x86_64-softmmu"
+          BUILDMAN="^qemu-x86_64$"
+          TOOLCHAIN="i386"
+          BUILD_ROM="yes"
+    - name: "test/py zynq_zc702"
+      env:
+        - TEST_PY_BD="zynq_zc702"
+          TEST_PY_TEST_SPEC="not sleep"
+          QEMU_TARGET="arm-softmmu"
+          TEST_PY_ID="--id qemu"
+          BUILDMAN="^zynq_zc702$"
+    - name: "test/py xilinx_versal_virt"
+      env:
+        - TEST_PY_BD="xilinx_versal_virt"
+          TEST_PY_TEST_SPEC="not sleep"
+          QEMU_TARGET="aarch64-softmmu"
+          TEST_PY_ID="--id qemu"
+          BUILDMAN="^xilinx_versal_virt$"
+    - name: "test/py xtfpga"
+      env:
+        - TEST_PY_BD="xtfpga"
+          TEST_PY_TEST_SPEC="not sleep"
+          QEMU_TARGET="xtensa-softmmu"
+          TEST_PY_ID="--id qemu"
+          BUILDMAN="^xtfpga$"
+          TOOLCHAIN="xtensa-dc233c-elf"
+
+# TODO make it perfect ;-r

Kbuild

@@ -1,22 +1,54 @@
-# SPDX-License-Identifier: GPL-2.0
 #
 # Kbuild for top-level directory of U-Boot
+# This file takes care of the following:
+# 1) Generate generic-asm-offsets.h
+# 2) Generate asm-offsets.h
+
+# Default sed regexp - multiline due to syntax constraints
+define sed-y
+	"s:[[:space:]]*\.ascii[[:space:]]*\"\(.*\)\":\1:; \
+	/^->/{s:->#\(.*\):/* \1 */:; \
+	s:^->\([^ ]*\) [\$$#]*\([-0-9]*\) \(.*\):#define \1 \2 /* \3 */:; \
+	s:^->\([^ ]*\) [\$$#]*\([^ ]*\) \(.*\):#define \1 \2 /* \3 */:; \
+	s:->::; p;}"
+endef
+
+# Use filechk to avoid rebuilds when a header changes, but the resulting file
+# does not
+define filechk_offsets
+	(set -e; \
+	 echo "#ifndef $2"; \
+	 echo "#define $2"; \
+	 echo "/*"; \
+	 echo " * DO NOT MODIFY."; \
+	 echo " *"; \
+	 echo " * This file was generated by Kbuild"; \
+	 echo " */"; \
+	 echo ""; \
+	 sed -ne $(sed-y); \
+	 echo ""; \
+	 echo "#endif" )
+endef
 
 #####
-# Generate generic-asm-offsets.h
+# 1) Generate generic-asm-offsets.h
 
 generic-offsets-file := include/generated/generic-asm-offsets.h
 
 always  := $(generic-offsets-file)
 targets := lib/asm-offsets.s
 
-CFLAGS_REMOVE_asm-offsets.o := $(LTO_CFLAGS)
+# We use internal kbuild rules to avoid the "is up to date" message from make
+lib/asm-offsets.s: lib/asm-offsets.c FORCE
+	$(Q)mkdir -p $(dir $@)
+	$(call if_changed_dep,cc_s_c)
 
-$(obj)/$(generic-offsets-file): $(obj)/lib/asm-offsets.s FORCE
+$(obj)/$(generic-offsets-file): lib/asm-offsets.s FORCE
 	$(call filechk,offsets,__GENERIC_ASM_OFFSETS_H__)
 
 #####
-# Generate asm-offsets.h
+# 2) Generate asm-offsets.h
+#
 
 ifneq ($(wildcard $(srctree)/arch/$(ARCH)/lib/asm-offsets.c),)
 offsets-file := include/generated/asm-offsets.h
@@ -27,5 +59,10 @@ targets += arch/$(ARCH)/lib/asm-offsets.s
 
 CFLAGS_asm-offsets.o := -DDO_DEPS_ONLY
 
-$(obj)/$(offsets-file): $(obj)/arch/$(ARCH)/lib/asm-offsets.s FORCE
+# We use internal kbuild rules to avoid the "is up to date" message from make
+arch/$(ARCH)/lib/asm-offsets.s: arch/$(ARCH)/lib/asm-offsets.c FORCE
+	$(Q)mkdir -p $(dir $@)
+	$(call if_changed_dep,cc_s_c)
+
+$(obj)/$(offsets-file): arch/$(ARCH)/lib/asm-offsets.s FORCE
 	$(call filechk,offsets,__ASM_OFFSETS_H__)

Kconfig

@@ -3,11 +3,11 @@
 # see the file Documentation/kbuild/kconfig-language.txt in the
 # Linux kernel source tree.
 #
-mainmenu "U-Boot $(UBOOTVERSION) Configuration"
+mainmenu "U-Boot $UBOOTVERSION Configuration"
 
-comment "Compiler: $(CC_VERSION_TEXT)"
-
-source "scripts/Kconfig.include"
+config UBOOTVERSION
+	string
+	option env="UBOOTVERSION"
 
 # Allow defaults in arch-specific code to override any given here
 source "arch/Kconfig"
@@ -57,96 +57,15 @@ config LOCALVERSION_AUTO
 
 	  which is done within the script "scripts/setlocalversion".)
 
-config CC_IS_GCC
-	def_bool $(success,$(CC) --version | head -n 1 | grep -q gcc)
-
-config GCC_VERSION
-	int
-	default $(shell,$(srctree)/scripts/gcc-version.sh -p $(CC) | sed 's/^0*//') if CC_IS_GCC
-	default 0
-
-config CC_IS_CLANG
-	def_bool $(success,$(CC) --version | head -n 1 | grep -q clang)
-
-config CLANG_VERSION
-	int
-	default $(shell,$(srctree)/scripts/clang-version.sh $(CC))
-
-choice
-	prompt "Optimization level"
-	default CC_OPTIMIZE_FOR_SIZE
-
 config CC_OPTIMIZE_FOR_SIZE
 	bool "Optimize for size"
+	default y
 	help
-	  Enabling this option will pass "-Os" to gcc, resulting in a smaller
-	  U-Boot image.
+	  Enabling this option will pass "-Os" instead of "-O2" to gcc
+	  resulting in a smaller U-Boot image.
 
 	  This option is enabled by default for U-Boot.
 
-config CC_OPTIMIZE_FOR_SPEED
-	bool "Optimize for speed"
-	help
-	  Enabling this option will pass "-O2" to gcc, resulting in a faster
-	  U-Boot image.
-
-config CC_OPTIMIZE_FOR_DEBUG
-	bool "Optimize for debugging"
-	help
-	  Enabling this option will pass "-Og" to gcc, enabling optimizations
-	  which don't interfere with debugging.
-
-endchoice
-
-config OPTIMIZE_INLINING
-	bool "Allow compiler to uninline functions marked 'inline' in full U-Boot"
-	help
-	  This option determines if U-Boot forces gcc to inline the functions
-	  developers have marked 'inline'. Doing so takes away freedom from gcc to
-	  do what it thinks is best, which is desirable in some cases for size
-	  reasons.
-
-config SPL_OPTIMIZE_INLINING
-	bool "Allow compiler to uninline functions marked 'inline' in SPL"
-	depends on SPL
-	help
-	  This option determines if U-Boot forces gcc to inline the functions
-	  developers have marked 'inline'. Doing so takes away freedom from gcc to
-	  do what it thinks is best, which is desirable in some cases for size
-	  reasons.
-
-config ARCH_SUPPORTS_LTO
-	bool
-
-config LTO
-	bool "Enable Link Time Optimizations"
-	depends on ARCH_SUPPORTS_LTO
-	help
-	  This option enables Link Time Optimization (LTO), a mechanism which
-	  allows the compiler to optimize between different compilation units.
-
-	  This can optimize away dead code paths, resulting in smaller binary
-	  size (if CC_OPTIMIZE_FOR_SIZE is enabled).
-
-	  This option is not available for every architecture and may
-	  introduce bugs.
-
-	  Currently, when compiling with GCC, due to a weird bug regarding
-	  jobserver, the final linking will not respect make's --jobs argument.
-	  Instead all available processors will be used (as reported by the
-	  nproc command).
-
-	  If unsure, say n.
-
-config TPL_OPTIMIZE_INLINING
-	bool "Allow compiler to uninline functions marked 'inline' in TPL"
-	depends on TPL
-	help
-	  This option determines if U-Boot forces gcc to inline the functions
-	  developers have marked 'inline'. Doing so takes away freedom from gcc to
-	  do what it thinks is best, which is desirable in some cases for size
-	  reasons.
-
 config CC_COVERAGE
 	bool "Enable code coverage analysis"
 	depends on SANDBOX
@@ -154,43 +73,6 @@ config CC_COVERAGE
 	  Enabling this option will pass "--coverage" to gcc to compile
 	  and link code instrumented for coverage analysis.
 
-config ASAN
-	bool "Enable AddressSanitizer"
-	depends on SANDBOX
-	help
-	  Enables AddressSanitizer to discover out-of-bounds accesses,
-	  use-after-free, double-free and memory leaks.
-
-config FUZZ
-	bool "Enable fuzzing"
-	depends on CC_IS_CLANG
-	depends on DM_FUZZING_ENGINE
-	select ASAN
-	help
-	  Enables the fuzzing infrastructure to generate fuzzing data and run
-          fuzz tests.
-
-config CC_HAS_ASM_INLINE
-	def_bool $(success,echo 'void foo(void) { asm inline (""); }' | $(CC) -x c - -c -o /dev/null)
-
-config XEN
-	bool "Select U-Boot be run as a bootloader for XEN Virtual Machine"
-	help
-	  Enabling this option will make U-Boot be run as a bootloader
-	  for XEN [1] Virtual Machine.
-
-	  Xen is a virtual machine monitor (VMM) or a type-1 hypervisor with support
-	  for para-virtualization. Xen can organize the safe execution of several
-	  virtual machines on the same physical system with performance close to
-	  native. It is used as the basis for a number of different commercial and
-	  open source applications, such as: server virtualization, Infrastructure
-	  as a Service (IaaS), desktop virtualization, security applications,
-	  embedded and hardware appliances.
-	  Xen has a special VM called Domain-0 that runs the Dom0 kernel and allows
-	  Xen to use the device drivers for the Domain-0 kernel by default.
-
-	  [1] - https://xenproject.org/
-
 config DISTRO_DEFAULTS
 	bool "Select defaults suitable for booting general purpose Linux distributions"
 	select AUTO_COMPLETE
@@ -233,7 +115,6 @@ config ENV_VARS_UBOOT_CONFIG
 
 config NR_DRAM_BANKS
 	int "Number of DRAM banks"
-	default 1 if ARCH_SUNXI || ARCH_OWL
 	default 4
 	help
 	  This defines the number of DRAM banks.
@@ -244,38 +125,12 @@ config SYS_BOOT_GET_CMDLINE
 	  Enables allocating and saving kernel cmdline in space between
 	  "bootm_low" and "bootm_low" + BOOTMAPSZ.
 
-config SYS_BARGSIZE
-	int "Size of kernel command line buffer in bytes"
-	depends on SYS_BOOT_GET_CMDLINE
-	default 512
-	help
-	  Buffer size for Boot Arguments which are passed to the application
-	  (usually a Linux kernel) when it is booted
-
 config SYS_BOOT_GET_KBD
 	bool "Enable kernel board information setup"
 	help
 	  Enables allocating and saving a kernel copy of the bd_info in
 	  space between "bootm_low" and "bootm_low" + BOOTMAPSZ.
 
-config HAS_CUSTOM_SYS_INIT_SP_ADDR
-	bool "Use a custom location for the initial stack pointer address"
-	depends on ARC || (ARM && !INIT_SP_RELATIVE) || MIPS || PPC || RISCV
-	default y if TFABOOT
-	help
-	  Typically, we use an initial stack pointer address that is calculated
-	  by taking the statically defined CONFIG_SYS_INIT_RAM_ADDR, adding the
-	  statically defined CONFIG_SYS_INIT_RAM_SIZE and then subtracting the
-	  build-time constant of GENERATED_GBL_DATA_SIZE.  On MIPS a different
-	  but statica calculation is performed.  However, some platforms will
-	  take a different approach.  Say Y here to define the address statically
-	  instead.
-
-config CUSTOM_SYS_INIT_SP_ADDR
-	hex "Static location for the initial stack pointer"
-	depends on HAS_CUSTOM_SYS_INIT_SP_ADDR
-	default SYS_TEXT_BASE if TFABOOT
-
 config SYS_MALLOC_F
 	bool "Enable malloc() pool before relocation"
 	default y if DM
@@ -289,18 +144,11 @@ config SYS_MALLOC_F
 config SYS_MALLOC_F_LEN
 	hex "Size of malloc() pool before relocation"
 	depends on SYS_MALLOC_F
-	default 0x400 if M68K || PPC || ROCKCHIP_PX30 || ROCKCHIP_RK3036 || \
-			 ROCKCHIP_RK3308 || ROCKCHIP_RV1108
-	default 0x600 if ARCH_ZYNQMP_R5 || ARCH_ZYNQMP
-	default 0x800 if ARCH_ZYNQ || ROCKCHIP_RK3128 || ROCKCHIP_RK3188 || \
-			 ROCKCHIP_RK322X || X86
-	default 0x1000 if ARCH_MESON || ARCH_BMIPS || ARCH_MTMIPS
-	default 0x1800 if ARCH_TEGRA
-	default 0x4000 if SANDBOX || RISCV || ARCH_APPLE || ROCKCHIP_RK3368 || \
-			  ROCKCHIP_RK3399
-	default 0x8000 if RCAR_GEN3
-	default 0x10000 if ARCH_IMX8 || ARCH_IMX8M
-	default 0x2000
+	default 0x1000 if AM33XX
+	default 0x2800 if SANDBOX
+	default 0x2000 if (ARCH_IMX8 || ARCH_IMX8M || ARCH_MX7 || \
+			   ARCH_MX7ULP || ARCH_MX6 || ARCH_MX5)
+	default 0x400
 	help
 	  Before relocation, memory is very limited on many platforms. Still,
 	  we can provide a small malloc() pool if needed. Driver model in
@@ -309,61 +157,26 @@ config SYS_MALLOC_F_LEN
 
 config SYS_MALLOC_LEN
 	hex "Define memory for Dynamic allocation"
-	default 0x4000000 if SANDBOX
-	default 0x2000000 if ARCH_ROCKCHIP || ARCH_OMAP2PLUS || ARCH_MESON
-	default 0x200000 if ARCH_BMIPS || X86
-	default 0x120000 if MACH_SUNIV
-	default 0x220000 if MACH_SUN8I_V3S
-	default 0x4020000 if ARCH_SUNXI
-	default 0x400000
+	depends on ARCH_ZYNQ || ARCH_VERSAL || ARCH_STM32MP || ARCH_ROCKCHIP
+	default 0x2000000 if ARCH_ROCKCHIP
 	help
 	  This defines memory to be allocated for Dynamic allocation
 	  TODO: Use for other architectures
 
 config SPL_SYS_MALLOC_F_LEN
-	hex "Size of malloc() pool in SPL"
+	hex "Size of malloc() pool in SPL before relocation"
 	depends on SYS_MALLOC_F && SPL
-	default 0 if !SPL_FRAMEWORK
 	default 0x2800 if RCAR_GEN3
-	default 0x2000 if IMX8MQ
 	default SYS_MALLOC_F_LEN
 	help
-	  In SPL memory is very limited on many platforms. Still,
+	  Before relocation, memory is very limited on many platforms. Still,
 	  we can provide a small malloc() pool if needed. Driver model in
 	  particular needs this to operate, so that it can allocate the
 	  initial serial device and any others that are needed.
 
-	  It is possible to enable CONFIG_SYS_SPL_MALLOC_START to start a new
-	  malloc() region in SDRAM once it is inited.
-
 config TPL_SYS_MALLOC_F_LEN
-	hex "Size of malloc() pool in TPL"
+	hex "Size of malloc() pool in TPL before relocation"
 	depends on SYS_MALLOC_F && TPL
-	default SPL_SYS_MALLOC_F_LEN
-	help
-	  In TPL memory is very limited on many platforms. Still,
-	  we can provide a small malloc() pool if needed. Driver model in
-	  particular needs this to operate, so that it can allocate the
-	  initial serial device and any others that are needed.
-
-config VALGRIND
-	bool "Inform valgrind about memory allocations"
-	depends on !RISCV
-	help
-	  Valgrind is an instrumentation framework for building dynamic analysis
-	  tools. In particular, it may be used to detect memory management bugs
-	  in U-Boot. It relies on knowing when heap blocks are allocated in
-	  order to give accurate results. This happens automatically for
-	  standard allocator functions provided by the host OS. However, this
-	  doesn't automatically happen for U-Boot's malloc implementation.
-
-	  Enable this option to annotate U-Boot's malloc implementation so that
-	  it can be handled accurately by Valgrind. If you aren't planning on
-	  using valgrind to debug U-Boot, say 'n'.
-
-config VPL_SYS_MALLOC_F_LEN
-	hex "Size of malloc() pool in VPL before relocation"
-	depends on SYS_MALLOC_F && VPL
 	default SYS_MALLOC_F_LEN
 	help
 	  Before relocation, memory is very limited on many platforms. Still,
@@ -397,19 +210,6 @@ if EXPERT
 	  When disabling this, please check if malloc calls, maybe
 	  should be replaced by calloc - if one expects zeroed memory.
 
-config SYS_MALLOC_DEFAULT_TO_INIT
-	bool "Default malloc to init while reserving the memory for it"
-	help
-	  It may happen that one needs to move the dynamic allocation
-	  from one to another memory range, eg. when moving the malloc
-	  from the limited static to a potentially large dynamic (DDR)
-	  memory.
-
-	  If so then on top of setting the updated memory aside one
-	  needs to bring the malloc init.
-
-	  If such a scenario is sought choose yes.
-
 config TOOLS_DEBUG
 	bool "Enable debug information for tools"
 	help
@@ -427,12 +227,14 @@ config PHYS_64BIT
 	  This can be used not only for 64bit SoCs, but also for
 	  large physical address extension on 32bit SoCs.
 
-config HAS_ROM
-	bool
-	select BINMAN
+config BUILD_ROM
+	bool "Build U-Boot as BIOS replacement"
+	depends on X86
 	help
-	  Enables building of a u-boot.rom target. This collects U-Boot and
-	  any necessary binary blobs.
+	  This option allows to build a ROM version of U-Boot.
+	  The build process generally requires several binary blobs
+	  which are not shipped in the U-Boot source tree.
+	  Please, see doc/README.x86 for details.
 
 config SPL_IMAGE
 	string "SPL image used in the combined SPL+U-Boot image"
@@ -445,22 +247,15 @@ config SPL_IMAGE
 	  used to generate a combined image with SPL and main U-Boot
 	  proper as one single image.
 
-config REMAKE_ELF
-	bool "Recreate an ELF image from raw U-Boot binary"
-	help
-	  Enable this to recreate an ELF image (u-boot.elf) from the raw
-	  U-Boot binary (u-boot.bin), which may already have been statically
-	  relocated and may already have a device-tree appended to it.
-
 config BUILD_TARGET
 	string "Build target special images"
 	default "u-boot-with-spl.sfp" if TARGET_SOCFPGA_ARRIA10
 	default "u-boot-with-spl.sfp" if TARGET_SOCFPGA_GEN5
 	default "u-boot-spl.kwb" if ARCH_MVEBU && SPL
 	default "u-boot-elf.srec" if RCAR_GEN3
-	default "u-boot.itb" if !BINMAN && SPL_LOAD_FIT && (ARCH_ROCKCHIP || \
-				ARCH_SUNXI || RISCV || ARCH_ZYNQMP)
-	default "u-boot.kwb" if ARCH_KIRKWOOD
+	default "u-boot.itb" if SPL_LOAD_FIT && (ARCH_ROCKCHIP || \
+				ARCH_SUNXI || RISCV)
+	default "u-boot.kwb" if KIRKWOOD
 	default "u-boot-with-spl.bin" if ARCH_AT91 && SPL_NAND_SUPPORT
 	default "u-boot-with-spl.imx" if ARCH_MX6 && SPL
 	help
@@ -470,23 +265,6 @@ config BUILD_TARGET
 	  special image will be automatically built upon calling
 	  make / buildman.
 
-config HAS_BOARD_SIZE_LIMIT
-	bool "Define a maximum size for the U-Boot image"
-	default y if RCAR_GEN3
-	help
-	  In some cases, we need to enforce a hard limit on how big the U-Boot
-	  image itself can be.
-
-config BOARD_SIZE_LIMIT
-	int "Maximum size of the U-Boot image in bytes"
-	default 1048576 if RCAR_GEN3
-	depends on HAS_BOARD_SIZE_LIMIT
-	help
-	  Maximum size of the U-Boot image. When defined, the build system
-	  checks that the actual size does not exceed it.  This does not
-	  include SPL nor TPL, on platforms that use that functionality, they
-	  have a separate option to restict size.
-
 config SYS_CUSTOM_LDSCRIPT
 	bool "Use a custom location for the U-Boot linker script"
 	help
@@ -504,21 +282,6 @@ config SYS_LDSCRIPT
 	  Path within the source tree to the linker script to use for the
 	  main U-Boot binary.
 
-config SYS_LOAD_ADDR
-	hex "Address in memory to use by default"
-	default 0x01000000 if ARCH_SOCFPGA
-	default 0x02000000 if PPC || X86
-	default 0x81000000 if MACH_SUNIV
-	default 0x22000000 if MACH_SUN9I
-	default 0x42000000 if ARCH_SUNXI
-	default 0x82000000 if ARCH_KEYSTONE || ARCH_OMAP2PLUS || ARCH_K3
-	default 0x82000000 if ARCH_MX6 && (MX6SL || MX6SLL  || MX6SX || MX6UL || MX6ULL)
-	default 0x12000000 if ARCH_MX6 && !(MX6SL || MX6SLL  || MX6SX || MX6UL || MX6ULL)
-	default 0x80800000 if ARCH_MX7
-	default 0x90000000 if FSL_LSCH2 || FSL_LSCH3
-	help
-	  Address in memory to use as the default safe load address.
-
 config ERR_PTR_OFFSET
 	hex
 	default 0x0
@@ -533,75 +296,285 @@ config ERR_PTR_OFFSET
 	  pointer values - up to 'MAX_ERRNO' bytes below this value must be
 	  unused/invalid addresses.
 
-config PLATFORM_ELFENTRY
-	string
-	default "__start" if MIPS
-	default "_start"
-
-config STACK_SIZE
-	hex "Define max stack size that can be used by U-Boot"
-	default 0x4000000 if ARCH_VERSAL || ARCH_ZYNQMP
-	default 0x200000 if MICROBLAZE
-	default 0x1000000
-	help
-	  Define Max stack size that can be used by U-Boot. This value is used
-	  by the UEFI sub-system. On some boards initrd_high is calculated as
-	  base stack pointer minus this stack size.
-
-config SYS_MEM_TOP_HIDE
-	hex "Exclude some memory from U-Boot / OS information"
-	default 0x0
-	help
-	  If set, this specified memory area will get subtracted from the top
-	  (end) of RAM and won't get "touched" at all by U-Boot. By fixing up
-	  gd->ram_size the OS / next stage should gets passed the now
-	  "corrected" memory size and won't touch it either.
-	  WARNING: Please make sure that this value is a multiple of the OS
-	  page size.
-
-config SYS_HAS_SRAM
-	bool
-	default y if TARGET_PIC32MZDASK
-	default y if TARGET_DEVKIT8000
-	default y if TARGET_TRICORDER
-	help
-	  Enable this to allow support for the on board SRAM.
-	  SRAM base address is controlled by CONFIG_SYS_SRAM_BASE.
-	  SRAM size is controlled by CONFIG_SYS_SRAM_SIZE.
-
-config SYS_SRAM_BASE
-	hex
-	default 0x80000000 if TARGET_PIC32MZDASK
-	default 0x40200000 if TARGET_DEVKIT8000
-	default 0x40200000 if TARGET_TRICORDER
-	default 0x0
-
-config SYS_SRAM_SIZE
-	hex
-	default 0x00080000 if TARGET_PIC32MZDASK
-	default 0x10000 if TARGET_DEVKIT8000
-	default 0x10000 if TARGET_TRICORDER
-	default 0x0
-
-config MP
-	bool "Support for multiprocessor"
-	help
-	  This provides an option to bringup different processors
-	  in multiprocessor cases.
-
-config EXAMPLES
-	bool "Compile API examples"
-	depends on !SANDBOX
-	default y if ARCH_QEMU
-	help
-	  U-Boot provides an API for standalone applications. Examples are
-	  provided in directory examples/.
-
 endmenu		# General setup
 
-source "api/Kconfig"
+menu "Boot images"
 
-source "boot/Kconfig"
+config ANDROID_BOOT_IMAGE
+	bool "Enable support for Android Boot Images"
+	default y if FASTBOOT
+	help
+	  This enables support for booting images which use the Android
+	  image format header.
+
+config FIT
+	bool "Support Flattened Image Tree"
+	select MD5
+	select SHA1
+	help
+	  This option allows you to boot the new uImage structure,
+	  Flattened Image Tree.  FIT is formally a FDT, which can include
+	  images of various types (kernel, FDT blob, ramdisk, etc.)
+	  in a single blob.  To boot this new uImage structure,
+	  pass the address of the blob to the "bootm" command.
+	  FIT is very flexible, supporting compression, multiple images,
+	  multiple configurations, verification through hashing and also
+	  verified boot (secure boot using RSA).
+
+if FIT
+
+config FIT_EXTERNAL_OFFSET
+	hex "FIT external data offset"
+	default 0x0
+	help
+	  This specifies a data offset in fit image.
+	  The offset is from data payload offset to the beginning of
+	  fit image header. When specifies a offset, specific data
+	  could be put in the hole between data payload and fit image
+	  header, such as CSF data on i.MX platform.
+
+config FIT_ENABLE_SHA256_SUPPORT
+	bool "Support SHA256 checksum of FIT image contents"
+	default y
+	select SHA256
+	help
+	  Enable this to support SHA256 checksum of FIT image contents. A
+	  SHA256 checksum is a 256-bit (32-byte) hash value used to check that
+	  the image contents have not been corrupted. SHA256 is recommended
+	  for use in secure applications since (as at 2016) there is no known
+	  feasible attack that could produce a 'collision' with differing
+	  input data. Use this for the highest security. Note that only the
+	  SHA256 variant is supported: SHA512 and others are not currently
+	  supported in U-Boot.
+
+config FIT_SIGNATURE
+	bool "Enable signature verification of FIT uImages"
+	depends on DM
+	select HASH
+	select RSA
+	help
+	  This option enables signature verification of FIT uImages,
+	  using a hash signed and verified using RSA. If
+	  CONFIG_SHA_PROG_HW_ACCEL is defined, i.e support for progressive
+	  hashing is available using hardware, then the RSA library will use
+	  it. See doc/uImage.FIT/signature.txt for more details.
+
+	  WARNING: When relying on signed FIT images with a required signature
+	  check the legacy image format is disabled by default, so that
+	  unsigned images cannot be loaded. If a board needs the legacy image
+	  format support in this case, enable it using
+	  CONFIG_LEGACY_IMAGE_FORMAT.
+
+config FIT_SIGNATURE_MAX_SIZE
+	hex "Max size of signed FIT structures"
+	depends on FIT_SIGNATURE
+	default 0x10000000
+	help
+	  This option sets a max size in bytes for verified FIT uImages.
+	  A sane value of 256MB protects corrupted DTB structures from overlapping
+	  device memory. Assure this size does not extend past expected storage
+	  space.
+
+config FIT_ENABLE_RSASSA_PSS_SUPPORT
+	bool "Support rsassa-pss signature scheme of FIT image contents"
+	depends on FIT_SIGNATURE
+	default n
+	help
+	  Enable this to support the pss padding algorithm as described
+	  in the rfc8017 (https://tools.ietf.org/html/rfc8017).
+
+config FIT_VERBOSE
+	bool "Show verbose messages when FIT images fail"
+	help
+	  Generally a system will have valid FIT images so debug messages
+	  are a waste of code space. If you are debugging your images then
+	  you can enable this option to get more verbose information about
+	  failures.
+
+config FIT_BEST_MATCH
+	bool "Select the best match for the kernel device tree"
+	help
+	  When no configuration is explicitly selected, default to the
+	  one whose fdt's compatibility field best matches that of
+	  U-Boot itself. A match is considered "best" if it matches the
+	  most specific compatibility entry of U-Boot's fdt's root node.
+	  The order of entries in the configuration's fdt is ignored.
+
+config FIT_IMAGE_POST_PROCESS
+	bool "Enable post-processing of FIT artifacts after loading by U-Boot"
+	depends on TI_SECURE_DEVICE
+	help
+	  Allows doing any sort of manipulation to blobs after they got extracted
+	  from FIT images like stripping off headers or modifying the size of the
+	  blob, verification, authentication, decryption etc. in a platform or
+	  board specific way. In order to use this feature a platform or board-
+	  specific implementation of board_fit_image_post_process() must be
+	  provided. Also, anything done during this post-processing step would
+	  need to be comprehended in how the images were prepared before being
+	  injected into the FIT creation (i.e. the blobs would have been pre-
+	  processed before being added to the FIT image).
+
+if SPL
+
+config SPL_FIT
+	bool "Support Flattened Image Tree within SPL"
+	depends on SPL
+	select SPL_OF_LIBFDT
+
+config SPL_FIT_PRINT
+	bool "Support FIT printing within SPL"
+	depends on SPL_FIT
+	help
+	  Support printing the content of the fitImage in a verbose manner in SPL.
+
+config SPL_FIT_SIGNATURE
+	bool "Enable signature verification of FIT firmware within SPL"
+	depends on SPL_DM
+	select SPL_FIT
+	select SPL_RSA
+
+config SPL_LOAD_FIT
+	bool "Enable SPL loading U-Boot as a FIT (basic fitImage features)"
+	select SPL_FIT
+	help
+	  Normally with the SPL framework a legacy image is generated as part
+	  of the build. This contains U-Boot along with information as to
+	  where it should be loaded. This option instead enables generation
+	  of a FIT (Flat Image Tree) which provides more flexibility. In
+	  particular it can handle selecting from multiple device tree
+	  and passing the correct one to U-Boot.
+
+config SPL_LOAD_FIT_FULL
+	bool "Enable SPL loading U-Boot as a FIT (full fitImage features)"
+	select SPL_FIT
+	help
+	  Normally with the SPL framework a legacy image is generated as part
+	  of the build. This contains U-Boot along with information as to
+	  where it should be loaded. This option instead enables generation
+	  of a FIT (Flat Image Tree) which provides more flexibility. In
+	  particular it can handle selecting from multiple device tree
+	  and passing the correct one to U-Boot.
+
+config SPL_FIT_IMAGE_POST_PROCESS
+	bool "Enable post-processing of FIT artifacts after loading by the SPL"
+	depends on SPL_LOAD_FIT
+	help
+	  Allows doing any sort of manipulation to blobs after they got extracted
+	  from the U-Boot FIT image like stripping off headers or modifying the
+	  size of the blob, verification, authentication, decryption etc. in a
+	  platform or board specific way. In order to use this feature a platform
+	  or board-specific implementation of board_fit_image_post_process() must
+	  be provided. Also, anything done during this post-processing step would
+	  need to be comprehended in how the images were prepared before being
+	  injected into the FIT creation (i.e. the blobs would have been pre-
+	  processed before being added to the FIT image).
+
+config SPL_FIT_SOURCE
+	string ".its source file for U-Boot FIT image"
+	depends on SPL_FIT
+	help
+	  Specifies a (platform specific) FIT source file to generate the
+	  U-Boot FIT image. This could specify further image to load and/or
+	  execute.
+
+config SPL_FIT_GENERATOR
+	string ".its file generator script for U-Boot FIT image"
+	depends on SPL_FIT
+	default "board/sunxi/mksunxi_fit_atf.sh" if SPL_LOAD_FIT && ARCH_SUNXI
+	default "arch/arm/mach-rockchip/make_fit_atf.py" if SPL_LOAD_FIT && ARCH_ROCKCHIP
+	default "arch/riscv/lib/mkimage_fit_opensbi.sh" if SPL_LOAD_FIT && RISCV
+	help
+	  Specifies a (platform specific) script file to generate the FIT
+	  source file used to build the U-Boot FIT image file. This gets
+	  passed a list of supported device tree file stub names to
+	  include in the generated image.
+
+endif # SPL
+
+endif # FIT
+
+config LEGACY_IMAGE_FORMAT
+	bool "Enable support for the legacy image format"
+	default y if !FIT_SIGNATURE
+	help
+	  This option enables the legacy image format. It is enabled by
+	  default for backward compatibility, unless FIT_SIGNATURE is
+	  set where it is disabled so that unsigned images cannot be
+	  loaded. If a board needs the legacy image format support in this
+	  case, enable it here.
+
+config OF_BOARD_SETUP
+	bool "Set up board-specific details in device tree before boot"
+	depends on OF_LIBFDT
+	help
+	  This causes U-Boot to call ft_board_setup() before booting into
+	  the Operating System. This function can set up various
+	  board-specific information in the device tree for use by the OS.
+	  The device tree is then passed to the OS.
+
+config OF_SYSTEM_SETUP
+	bool "Set up system-specific details in device tree before boot"
+	depends on OF_LIBFDT
+	help
+	  This causes U-Boot to call ft_system_setup() before booting into
+	  the Operating System. This function can set up various
+	  system-specific information in the device tree for use by the OS.
+	  The device tree is then passed to the OS.
+
+config OF_STDOUT_VIA_ALIAS
+	bool "Update the device-tree stdout alias from U-Boot"
+	depends on OF_LIBFDT
+	help
+	  This uses U-Boot's serial alias from the aliases node to update
+	  the device tree passed to the OS. The "linux,stdout-path" property
+	  in the chosen node is set to point to the correct serial node.
+	  This option currently references CONFIG_CONS_INDEX, which is
+	  incorrect when used with device tree as this option does not
+	  exist / should not be used.
+
+config SYS_EXTRA_OPTIONS
+	string "Extra Options (DEPRECATED)"
+	help
+	  The old configuration infrastructure (= mkconfig + boards.cfg)
+	  provided the extra options field. If you have something like
+	  "HAS_BAR,BAZ=64", the optional options
+	    #define CONFIG_HAS
+	    #define CONFIG_BAZ	64
+	  will be defined in include/config.h.
+	  This option was prepared for the smooth migration from the old
+	  configuration to Kconfig. Since this option will be removed sometime,
+	  new boards should not use this option.
+
+config SYS_TEXT_BASE
+	depends on !NIOS2 && !XTENSA
+	depends on !EFI_APP
+	default 0x80800000 if ARCH_OMAP2PLUS || ARCH_K3
+	default 0x4a000000 if ARCH_SUNXI && !MACH_SUN9I && !MACH_SUN8I_V3S
+	default 0x2a000000 if ARCH_SUNXI && MACH_SUN9I
+	default 0x42e00000 if ARCH_SUNXI && MACH_SUN8I_V3S
+	hex "Text Base"
+	help
+	  The address in memory that U-Boot will be running from, initially.
+
+
+
+config SYS_CLK_FREQ
+	depends on ARC || ARCH_SUNXI || MPC83xx
+	int "CPU clock frequency"
+	help
+	  TODO: Move CONFIG_SYS_CLK_FREQ for all the architecture
+
+config ARCH_FIXUP_FDT_MEMORY
+	bool "Enable arch_fixup_memory_banks() call"
+	default y
+	help
+	  Enable FDT memory map syncup before OS boot. This feature can be
+	  used for booting OS with different memory setup where the part of
+	  the memory location should be used for different purpose.
+
+endmenu		# Boot images
+
+source "api/Kconfig"
 
 source "common/Kconfig"
 
@@ -622,5 +595,3 @@ source "fs/Kconfig"
 source "lib/Kconfig"
 
 source "test/Kconfig"
-
-source "tools/Kconfig"

Licenses/README

@@ -139,7 +139,6 @@ License identifier syntax
 
 Full name					SPDX Identifier	OSI Approved	File name		URI
 =======================================================================================================================================
-bzip2 and libbzip2 License v1.0.6		bzip2-1.0.6			bzip2-1.0.6.txt		https://spdx.org/licenses/bzip2-1.0.6.html
 GNU General Public License v2.0 only		GPL-2.0		Y		gpl-2.0.txt		http://www.gnu.org/licenses/gpl-2.0.txt
 GNU General Public License v2.0 or later	GPL-2.0+	Y		gpl-2.0.txt		http://www.gnu.org/licenses/gpl-2.0.txt
 GNU Library General Public License v2 or later	LGPL-2.0+	Y		lgpl-2.0.txt		http://www.gnu.org/licenses/old-licenses/lgpl-2.0.txt
@@ -150,6 +149,5 @@ BSD 3-clause "New" or "Revised" License		BSD-3-Clause	Y		bsd-3-clause.txt	http:/
 IBM PIBS (PowerPC Initialization and		IBM-pibs			ibm-pibs.txt
 	Boot Software) license
 ISC License					ISC		Y		isc.txt			https://spdx.org/licenses/ISC
-MIT License					MIT		Y		mit.txt			https://spdx.org/licenses/MIT.html
 SIL OPEN FONT LICENSE (OFL-1.1)			OFL-1.1		Y		OFL.txt			https://spdx.org/licenses/OFL-1.1.html
 X11 License					X11				x11.txt			https://spdx.org/licenses/X11.html

Licenses/bzip2-1.0.6.txt

@@ -1,30 +0,0 @@
-Redistribution and use in source and binary forms, with or without
-modification, are permitted provided that the following conditions
-are met:
-
-1. Redistributions of source code must retain the above copyright
-   notice, this list of conditions and the following disclaimer.
-
-2. The origin of this software must not be misrepresented; you must 
-   not claim that you wrote the original software.  If you use this 
-   software in a product, an acknowledgment in the product 
-   documentation would be appreciated but is not required.
-
-3. Altered source versions must be plainly marked as such, and must
-   not be misrepresented as being the original software.
-
-4. The name of the author may not be used to endorse or promote 
-   products derived from this software without specific prior written 
-   permission.
-
-THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS
-OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
-DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
-GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
-WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
-NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Licenses/lgpl-2.0.txt

@@ -133,7 +133,7 @@ such a program is covered only if its contents constitute a work based
 on the Library (independent of the use of the Library in a tool for
 writing it).  Whether that is true depends on what the Library does
 and what the program that uses the Library does.
-
+  
   1. You may copy and distribute verbatim copies of the Library's
 complete source code as you receive it, in any medium, provided that
 you conspicuously and appropriately publish on each copy an

Licenses/mit.txt

@@ -1,20 +0,0 @@
-MIT License
-Copyright (c) 2020 EPAM Systems Inc.
-
-Permission is hereby granted, free of charge, to any person obtaining a copy
-of this software and associated documentation files (the "Software"), to deal
-in the Software without restriction, including without limitation the rights
-to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-copies of the Software, and to permit persons to whom the Software is
-furnished to do so, subject to the following conditions:
-
-The above copyright notice and this permission notice shall be included in all
-copies or substantial portions of the Software.
-
-THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-SOFTWARE.

SECURITY.md

@@ -1,8 +0,0 @@
-# Report potential product security vulnerabilities
-ST places a high priority on security, and our Product Security Incident Response Team (PSIRT) is committed to rapidly addressing potential security vulnerabilities affecting our products. PSIRT's long history and vast experience in security allows ST to perform clear analyses and provide appropriate guidance on mitigations  and solutions when applicable.
-If you wish to report potential security vulnerabilities regarding our products, **please do not report them through public GitHub issues.** Instead, we encourage you to report them to our ST PSIRT following the process described at: **https://www.st.com/content/st_com/en/security/report-vulnerabilities.html**
-
-### IMPORTANT - READ CAREFULLY:
-STMicroelectronics International N.V., on behalf of itself, its affiliates and  subsidiaries, (collectively “ST”) takes all potential security vulnerability reports or other related communications (“Report(s)”)  seriously. In order to review Your Report (the terms “You” and “Yours”  include your employer, and all affiliates, subsidiaries and related  persons or entities) and take actions as deemed appropriate, ST requires that we have the rights and Your permission to do so.
-As such, by submitting Your Report to ST, You agree that You have the right to do so, and You grant to ST the rights to use the Report for purposes related to security vulnerability analysis, testing, correction, patching, reporting and any other related purpose or function.
-By submitting Your Report, You agree that ST’s [Privacy Policy](https://www.st.com/content/st_com/en/common/privacy-portal.html) applies to all related communications.

api/Kconfig

@@ -2,6 +2,7 @@ menu "API"
 
 config API
 	bool "Enable U-Boot API"
+	default n
 	help
 	  This option enables the U-Boot API. See api/README for more information.
 

api/api.c

@@ -11,7 +11,6 @@
 #include <env.h>
 #include <malloc.h>
 #include <env_internal.h>
-#include <linux/delay.h>
 #include <linux/types.h>
 #include <api_public.h>
 #include <u-boot/crc.h>
@@ -57,7 +56,7 @@ static int API_getc(va_list ap)
 	if ((c = (int *)va_arg(ap, uintptr_t)) == NULL)
 		return API_EINVAL;
 
-	*c = getchar();
+	*c = getc();
 	return 0;
 }
 
@@ -642,7 +641,7 @@ int syscall(int call, int *retval, ...)
 	return 1;
 }
 
-int api_init(void)
+void api_init(void)
 {
 	struct api_signature *sig;
 
@@ -679,7 +678,7 @@ int api_init(void)
 	sig = malloc(sizeof(struct api_signature));
 	if (sig == NULL) {
 		printf("API: could not allocate memory for the signature!\n");
-		return -ENOMEM;
+		return;
 	}
 
 	env_set_hex("api_address", (unsigned long)sig);
@@ -691,8 +690,6 @@ int api_init(void)
 	sig->checksum = crc32(0, (unsigned char *)sig,
 			      sizeof(struct api_signature));
 	debugf("syscall entry: 0x%lX\n", (unsigned long)sig->syscall);
-
-	return 0;
 }
 
 void platform_set_mr(struct sys_info *si, unsigned long start, unsigned long size,

api/api_display.c

@@ -6,7 +6,6 @@
 #include <common.h>
 #include <api_public.h>
 #include <lcd.h>
-#include <log.h>
 #include <video_font.h> /* Get font width and height */
 
 /* lcd.h needs BMP_LOGO_HEIGHT to calculate CONSOLE_ROWS */

api/api_platform-mips.c

@@ -24,7 +24,8 @@ DECLARE_GLOBAL_DATA_PTR;
 int platform_sys_info(struct sys_info *si)
 {
 
-	platform_set_mr(si, gd->ram_base, gd->ram_size, MR_ATTR_DRAM);
+	platform_set_mr(si, gd->bd->bi_memstart,
+			gd->bd->bi_memsize, MR_ATTR_DRAM);
 
 	return 1;
 }

api/api_platform-powerpc.c

@@ -42,7 +42,7 @@ int platform_sys_info(struct sys_info *si)
 	si->bar = 0;
 #endif
 
-	platform_set_mr(si, gd->ram_base, gd->ram_size, MR_ATTR_DRAM);
+	platform_set_mr(si, gd->bd->bi_memstart, gd->bd->bi_memsize, MR_ATTR_DRAM);
 	platform_set_mr(si, gd->bd->bi_flashstart, gd->bd->bi_flashsize, MR_ATTR_FLASH);
 	platform_set_mr(si, gd->bd->bi_sramstart, gd->bd->bi_sramsize, MR_ATTR_SRAM);
 

api/api_private.h

@@ -8,7 +8,7 @@
 #ifndef _API_PRIVATE_H_
 #define _API_PRIVATE_H_
 
-int	api_init(void);
+void	api_init(void);
 void	platform_set_mr(struct sys_info *, unsigned long, unsigned long, int);
 int	platform_sys_info(struct sys_info *);
 

api/api_storage.c

@@ -8,8 +8,6 @@
 #include <config.h>
 #include <common.h>
 #include <api_public.h>
-#include <part.h>
-#include <scsi.h>
 
 #if defined(CONFIG_CMD_USB) && defined(CONFIG_USB_STORAGE)
 #include <usb.h>
@@ -72,7 +70,7 @@ void dev_stor_init(void)
 	specs[ENUM_SATA].name = "sata";
 #endif
 #if defined(CONFIG_SCSI)
-	specs[ENUM_SCSI].max_dev = SCSI_MAX_DEVICE;
+	specs[ENUM_SCSI].max_dev = CONFIG_SYS_SCSI_MAX_DEVICE;
 	specs[ENUM_SCSI].enum_started = 0;
 	specs[ENUM_SCSI].enum_ended = 0;
 	specs[ENUM_SCSI].type = DEV_TYP_STOR | DT_STOR_SCSI;

arch/Kconfig

@@ -1,99 +1,54 @@
-config ARCH_MAP_SYSMEM
-	depends on SANDBOX
-	def_bool y
-
 config CREATE_ARCH_SYMLINK
 	bool
 
 config HAVE_ARCH_IOREMAP
 	bool
 
-config SYS_CACHE_SHIFT_4
-	bool
-
-config SYS_CACHE_SHIFT_5
-	bool
-
-config SYS_CACHE_SHIFT_6
-	bool
-
-config SYS_CACHE_SHIFT_7
-	bool
-
-config SYS_CACHELINE_SIZE
-	int
-	default 128 if SYS_CACHE_SHIFT_7
-	default 64 if SYS_CACHE_SHIFT_6
-	default 32 if SYS_CACHE_SHIFT_5
-	default 16 if SYS_CACHE_SHIFT_4
-	# Fall-back for MIPS
-	default 32 if MIPS
-
-config LINKER_LIST_ALIGN
-	int
-	default 32 if SANDBOX
-	default 8 if ARM64 || X86
-	default 4
-	help
-	  Force the each linker list to be aligned to this boundary. This
-	  is required if ll_entry_get() is used, since otherwise the linker
-	  may add padding into the table, thus breaking it.
-	  See linker_lists.rst for full details.
-
 choice
 	prompt "Architecture select"
 	default SANDBOX
 
 config ARC
 	bool "ARC architecture"
+	select ARCH_EARLY_INIT_R
 	select ARC_TIMER
 	select CLK
-	select DM
 	select HAVE_PRIVATE_LIBGCC
 	select SUPPORT_OF_CONTROL
-	select SYS_CACHE_SHIFT_7
 	select TIMER
-	select SYS_BIG_ENDIAN if CPU_BIG_ENDIAN
-	select SYS_LITTLE_ENDIAN if !CPU_BIG_ENDIAN
 
 config ARM
 	bool "ARM architecture"
-	select ARCH_SUPPORTS_LTO
 	select CREATE_ARCH_SYMLINK
 	select HAVE_PRIVATE_LIBGCC if !ARM64
-	select SUPPORT_ACPI
 	select SUPPORT_OF_CONTROL
 
 config M68K
 	bool "M68000 architecture"
 	select HAVE_PRIVATE_LIBGCC
-	select NEEDS_MANUAL_RELOC
 	select SYS_BOOT_GET_CMDLINE
 	select SYS_BOOT_GET_KBD
-	select SYS_CACHE_SHIFT_4
 	select SUPPORT_OF_CONTROL
 
 config MICROBLAZE
 	bool "MicroBlaze architecture"
 	select SUPPORT_OF_CONTROL
-	imply CMD_TIMER
-	imply SPL_REGMAP if SPL
-	imply SPL_TIMER if SPL
-	imply TIMER
-	imply XILINX_TIMER
+	imply CMD_IRQ
 
 config MIPS
 	bool "MIPS architecture"
 	select HAVE_ARCH_IOREMAP
 	select HAVE_PRIVATE_LIBGCC
 	select SUPPORT_OF_CONTROL
-	select SPL_SEPARATE_BSS if SPL
+
+config NDS32
+	bool "NDS32 architecture"
+	select SUPPORT_OF_CONTROL
 
 config NIOS2
 	bool "Nios II architecture"
 	select CPU
 	select DM
-	imply DM_EVENT
 	select OF_CONTROL
 	select SUPPORT_OF_CONTROL
 	imply CMD_DM
@@ -111,10 +66,8 @@ config RISCV
 	select SUPPORT_OF_CONTROL
 	select OF_CONTROL
 	select DM
-	select SPL_SEPARATE_BSS if SPL
 	imply DM_SERIAL
 	imply DM_ETH
-	imply DM_EVENT
 	imply DM_MMC
 	imply DM_SPI
 	imply DM_SPI_FLASH
@@ -127,17 +80,13 @@ config RISCV
 	imply SPL_OF_CONTROL
 	imply SPL_LIBCOMMON_SUPPORT
 	imply SPL_LIBGENERIC_SUPPORT
-	imply SPL_SERIAL
+	imply SPL_SERIAL_SUPPORT
 	imply SPL_TIMER
 
 config SANDBOX
 	bool "Sandbox"
-	select ARCH_SUPPORTS_LTO
 	select BOARD_LATE_INIT
-	select BZIP2
-	select CMD_POWEROFF
 	select DM
-	select DM_FUZZING_ENGINE
 	select DM_GPIO
 	select DM_I2C
 	select DM_KEYBOARD
@@ -145,23 +94,15 @@ config SANDBOX
 	select DM_SERIAL
 	select DM_SPI
 	select DM_SPI_FLASH
-	select GZIP_COMPRESSED
 	select HAVE_BLOCK_DEVICE
 	select LZO
-	select OF_BOARD_SETUP
 	select PCI_ENDPOINT
 	select SPI
 	select SUPPORT_OF_CONTROL
-	select SYSRESET_CMD_POWEROFF
-	select SYS_CACHE_SHIFT_4
-	select IRQ
-	select SUPPORT_EXTENSION_SCAN
-	select SUPPORT_ACPI
+	select SYSRESET_CMD_POWEROFF if CMD_POWEROFF
 	imply BITREVERSE
 	select BLOBLIST
-	imply LTO
 	imply CMD_DM
-	imply CMD_EXCEPTION
 	imply CMD_GETTIME
 	imply CMD_HASH
 	imply CMD_IO
@@ -173,16 +114,13 @@ config SANDBOX
 	imply CRC32_VERIFY
 	imply FAT_WRITE
 	imply FIRMWARE
-	imply FUZZING_ENGINE_SANDBOX
 	imply HASH_VERIFY
 	imply LZMA
+	imply SCSI
 	imply TEE
 	imply AVB_VERIFY
 	imply LIBAVB
 	imply CMD_AVB
-	imply PARTITION_TYPE_GUID
-	imply SCP03
-	imply CMD_SCP03
 	imply UDP_FUNCTION_FASTBOOT
 	imply VIRTIO_MMIO
 	imply VIRTIO_PCI
@@ -195,19 +133,6 @@ config SANDBOX
 	imply PHYLIB
 	imply DM_MDIO
 	imply DM_MDIO_MUX
-	imply ACPI_PMC
-	imply ACPI_PMC_SANDBOX
-	imply CMD_PMC
-	imply CMD_CLONE
-	imply SILENT_CONSOLE
-	imply BOOTARGS_SUBST
-	imply PHY_FIXED
-	imply DM_DSA
-	imply CMD_EXTENSION
-	imply KEYBOARD
-	imply PHYSMEM
-	imply GENERATE_ACPI_TABLE
-	imply BINMAN
 
 config SH
 	bool "SuperH architecture"
@@ -220,18 +145,15 @@ config X86
 	select SUPPORT_TPL
 	select CREATE_ARCH_SYMLINK
 	select DM
+	select DM_PCI
 	select HAVE_ARCH_IOMAP
 	select HAVE_PRIVATE_LIBGCC
 	select OF_CONTROL
 	select PCI
-	select SUPPORT_ACPI
 	select SUPPORT_OF_CONTROL
-	select SYS_CACHE_SHIFT_6
 	select TIMER
 	select USE_PRIVATE_LIBGCC
 	select X86_TSC_TIMER
-	select IRQ
-	imply HAS_ROM if X86_RESET_VECTOR
 	imply BLK
 	imply CMD_DM
 	imply CMD_FPGA_LOADMK
@@ -243,7 +165,6 @@ config X86
 	imply CMD_SF_TEST
 	imply CMD_ZBOOT
 	imply DM_ETH
-	imply DM_EVENT
 	imply DM_GPIO
 	imply DM_KEYBOARD
 	imply DM_MMC
@@ -261,36 +182,32 @@ config X86
 	imply USB_ETHER_SMSC95XX
 	imply USB_HOST_ETHER
 	imply PCH
-	imply PHYSMEM
 	imply RTC_MC146818
-	imply ACPIGEN if !QEMU && !EFI_APP
-	imply SYSINFO if GENERATE_SMBIOS_TABLE
-	imply SYSINFO_SMBIOS if GENERATE_SMBIOS_TABLE
-	imply TIMESTAMP
 
 	# Thing to enable for when SPL/TPL are enabled: SPL
 	imply SPL_DM
 	imply SPL_OF_LIBFDT
-	imply SPL_DRIVERS_MISC
-	imply SPL_GPIO
-	imply SPL_PINCTRL
+	imply SPL_DRIVERS_MISC_SUPPORT
+	imply SPL_GPIO_SUPPORT
 	imply SPL_LIBCOMMON_SUPPORT
 	imply SPL_LIBGENERIC_SUPPORT
-	imply SPL_SERIAL
+	imply SPL_SERIAL_SUPPORT
 	imply SPL_SPI_FLASH_SUPPORT
-	imply SPL_SPI
+	imply SPL_SPI_SUPPORT
 	imply SPL_OF_CONTROL
 	imply SPL_TIMER
 	imply SPL_REGMAP
 	imply SPL_SYSCON
 	# TPL
 	imply TPL_DM
-	imply TPL_DRIVERS_MISC
-	imply TPL_GPIO
-	imply TPL_PINCTRL
+	imply TPL_OF_LIBFDT
+	imply TPL_DRIVERS_MISC_SUPPORT
+	imply TPL_GPIO_SUPPORT
 	imply TPL_LIBCOMMON_SUPPORT
 	imply TPL_LIBGENERIC_SUPPORT
-	imply TPL_SERIAL
+	imply TPL_SERIAL_SUPPORT
+	imply TPL_SPI_FLASH_SUPPORT
+	imply TPL_SPI_SUPPORT
 	imply TPL_OF_CONTROL
 	imply TPL_TIMER
 	imply TPL_REGMAP
@@ -368,83 +285,12 @@ config SYS_DISABLE_DCACHE_OPS
 	 Note that, its up to the individual architectures to implement
 	 this functionality.
 
-config SYS_IMMR
-	hex "Address for the Internal Memory-Mapped Registers (IMMR) window"
-	depends on PPC || FSL_LSCH2 || FSL_LSCH3 || ARCH_LS1021A
-	default 0xFF000000 if MPC8xx
-	default 0xF0000000 if ARCH_MPC8313
-	default 0xE0000000 if MPC83xx && !ARCH_MPC8313
-	default 0x01000000 if ARCH_LS1021A || FSL_LSCH2 || FSL_LSCH3
-	default 0xFFE00000 if ARCH_P1010 || ARCH_P1011 || ARCH_P1020 || \
-			      ARCH_P1021 || ARCH_P1024 || ARCH_P1025 || \
-			      ARCH_P2020
-	default SYS_CCSRBAR_DEFAULT
-	help
-	  Address for the Internal Memory-Mapped Registers (IMMR) window used
-	  to configure the features of many Freescale / NXP SoCs.
-
-config SKIP_LOWLEVEL_INIT
-	bool "Skip the calls to certain low level initialization functions"
-	depends on ARM || MIPS || RISCV
-	help
-	  If enabled, then certain low level initializations (like setting up
-	  the memory controller) are omitted and/or U-Boot does not relocate
-	  itself into RAM.
-	  Normally this variable MUST NOT be defined. The only exception is
-	  when U-Boot is loaded (to RAM) by some other boot loader or by a
-	  debugger which performs these initializations itself.
-
-config SPL_SKIP_LOWLEVEL_INIT
-	bool "Skip the calls to certain low level initialization functions"
-	depends on SPL && (ARM || MIPS || RISCV)
-	help
-	  If enabled, then certain low level initializations (like setting up
-	  the memory controller) are omitted and/or U-Boot does not relocate
-	  itself into RAM.
-	  Normally this variable MUST NOT be defined. The only exception is
-	  when U-Boot is loaded (to RAM) by some other boot loader or by a
-	  debugger which performs these initializations itself.
-
-config TPL_SKIP_LOWLEVEL_INIT
-	bool "Skip the calls to certain low level initialization functions"
-	depends on SPL && ARM
-	help
-	  If enabled, then certain low level initializations (like setting up
-	  the memory controller) are omitted and/or U-Boot does not relocate
-	  itself into RAM.
-	  Normally this variable MUST NOT be defined. The only exception is
-	  when U-Boot is loaded (to RAM) by some other boot loader or by a
-	  debugger which performs these initializations itself.
-
-config SKIP_LOWLEVEL_INIT_ONLY
-	bool "Skip the call to lowlevel_init during early boot ONLY"
-	depends on ARM
-	help
-	  This allows just the call to lowlevel_init() to be skipped. The
-	  normal CP15 init (such as enabling the instruction cache) is still
-	  performed.
-
-config SPL_SKIP_LOWLEVEL_INIT_ONLY
-	bool "Skip the call to lowlevel_init during early boot ONLY"
-	depends on SPL && ARM
-	help
-	  This allows just the call to lowlevel_init() to be skipped. The
-	  normal CP15 init (such as enabling the instruction cache) is still
-	  performed.
-
-config TPL_SKIP_LOWLEVEL_INIT_ONLY
-	bool "Skip the call to lowlevel_init during early boot ONLY"
-	depends on TPL && ARM
-	help
-	  This allows just the call to lowlevel_init() to be skipped. The
-	  normal CP15 init (such as enabling the instruction cache) is still
-	  performed.
-
 source "arch/arc/Kconfig"
 source "arch/arm/Kconfig"
 source "arch/m68k/Kconfig"
 source "arch/microblaze/Kconfig"
 source "arch/mips/Kconfig"
+source "arch/nds32/Kconfig"
 source "arch/nios2/Kconfig"
 source "arch/powerpc/Kconfig"
 source "arch/sandbox/Kconfig"
@@ -452,33 +298,3 @@ source "arch/sh/Kconfig"
 source "arch/x86/Kconfig"
 source "arch/xtensa/Kconfig"
 source "arch/riscv/Kconfig"
-
-if ARM || M68K || PPC
-
-source "arch/Kconfig.nxp"
-
-endif
-
-source "board/keymile/Kconfig"
-
-if MIPS || MICROBLAZE
-
-choice
-	prompt "Endianness selection"
-	help
-	  Some MIPS boards can be configured for either little or big endian
-	  byte order. These modes require different U-Boot images. In general there
-	  is one preferred byteorder for a particular system but some systems are
-	  just as commonly used in the one or the other endianness.
-
-config SYS_BIG_ENDIAN
-	bool "Big endian"
-	depends on (SUPPORTS_BIG_ENDIAN && MIPS) || MICROBLAZE
-
-config SYS_LITTLE_ENDIAN
-	bool "Little endian"
-	depends on (SUPPORTS_LITTLE_ENDIAN && MIPS) || MICROBLAZE
-
-endchoice
-
-endif

arch/Kconfig.nxp

@@ -1,253 +0,0 @@
-config NXP_ESBC
-	bool "NXP ESBC (secure boot) functionality"
-	help
-	  Enable Freescale Secure Boot feature. Normally selected by defconfig.
-	  If unsure, do not change.
-
-menu "Chain of trust / secure boot options"
-	depends on !FIT_SIGNATURE && NXP_ESBC
-
-config CHAIN_OF_TRUST
-	select FSL_CAAM
-	select ARCH_MISC_INIT
-	select FSL_SEC_MON
-	select SPL_BOARD_INIT if (ARM && SPL)
-	select SPL_HASH if (ARM && SPL)
-	select SHA_HW_ACCEL
-	select SHA_PROG_HW_ACCEL
-	select ENV_IS_NOWHERE
-	select SYS_CPC_REINIT_F if MPC85xx && !SYS_RAMBOOT
-	select CMD_EXT4 if ARM
-	select CMD_EXT4_WRITE if ARM
-	imply CMD_BLOB
-	imply CMD_HASH if ARM
-	def_bool y
-
-config CMD_ESBC_VALIDATE
-	bool "Enable the 'esbc_validate' and 'esbc_halt' commands"
-	default y
-	help
-	  This option enables two commands used for secure booting:
-
-	    esbc_validate - validate signature using RSA verification
-	    esbc_halt - put the core in spin loop (Secure Boot Only)
-
-config ESBC_HDR_LS
-	bool
-
-config ESBC_ADDR_64BIT
-	def_bool y
-	depends on ESBC_HDR_LS && FSL_LAYERSCAPE
-	help
-	  For Layerscape based platforms, ESBC image Address in Header is 64bit.
-
-config SYS_FSL_SFP_BE
-	def_bool y
-	depends on PPC || FSL_LSCH2 || ARCH_LS1021A
-
-config SYS_FSL_SFP_LE
-	def_bool y
-	depends on !SYS_FSL_SFP_BE
-
-choice
-	prompt "SFP IP revision"
-	default SYS_FSL_SFP_VER_3_0 if PPC
-	default SYS_FSL_SFP_VER_3_4
-
-config SYS_FSL_SFP_VER_3_0
-	bool "SFP version 3.0"
-
-config SYS_FSL_SFP_VER_3_2
-	bool "SFP version 3.2"
-
-config SYS_FSL_SFP_VER_3_4
-	bool "SFP version 3.4"
-
-endchoice
-
-config SPL_UBOOT_KEY_HASH
-	string "Non-SRK key hash for U-Boot public/private key pair"
-	depends on SPL
-	default ""
-	help
-	  Set the key hash for U-Boot here if public/private key pair used to
-	  sign U-boot are different from the SRK hash put in the fuse.  Example
-	  of a key hash is
-	  41066b564c6ffcef40ccbc1e0a5d0d519604000c785d97bbefd25e4d288d1c8b.
-	  Otherwise leave this empty.
-
-if PPC
-
-config BOOTSCRIPT_COPY_RAM
-	bool "Secure boot copies boot script to RAM"
-	help
-	  On systems that support chain of trust booting, a number of addresses
-	  are required to set variables that are used in the copying and then
-	  verification of different parts of the system.  If enabled, the subsequent
-	  options are for what location to use in each step.
-
-config BS_ADDR_DEVICE
-	hex "Address in RAM for bs_device"
-	depends on BOOTSCRIPT_COPY_RAM
-
-config BS_SIZE
-	hex "The size of bs_size which is the amount read from bs_device"
-	depends on BOOTSCRIPT_COPY_RAM
-
-config BS_ADDR_RAM
-	hex "Address in RAM for bs_ram"
-	depends on BOOTSCRIPT_COPY_RAM
-
-config BS_HDR_ADDR_DEVICE
-	hex "Address in RAM for bs_hdr_device"
-	depends on BOOTSCRIPT_COPY_RAM
-
-config BS_HDR_SIZE
-	hex "The size of bs_hdr_size which is the amount read from bs_hdr_device"
-	depends on BOOTSCRIPT_COPY_RAM
-
-config BS_HDR_ADDR_RAM
-	hex "Address in RAM for bs_hdr_ram"
-	depends on BOOTSCRIPT_COPY_RAM
-
-config BOOTSCRIPT_HDR_ADDR
-	hex "CONFIG_BOOTSCRIPT_HDR_ADDR"
-	default BS_ADDR_RAM if BOOTSCRIPT_COPY_RAM
-
-endif
-
-config SYS_FSL_SRK_LE
-	def_bool y
-	depends on ARM
-
-config KEY_REVOCATION
-	def_bool y
-
-endmenu
-
-comment "Other functionality shared between NXP SoCs"
-
-config DEEP_SLEEP
-	bool "Enable SoC deep sleep feature"
-	depends on ARCH_T1024 || ARCH_T1040 || ARCH_T1042 || ARCH_LS1021A
-	default y
-	help
-	  Indicates this SoC supports deep sleep feature. If deep sleep is
-	  supported, core will start to execute uboot when wakes up.
-
-config LAYERSCAPE_NS_ACCESS
-	bool "Layerscape non-secure access support"
-	depends on ARCH_LS1021A || FSL_LSCH2
-
-config PCIE1
-	bool "PCIe controller #1"
-	depends on LAYERSCAPE_NS_ACCESS || PPC
-
-config PCIE2
-	bool "PCIe controller #2"
-	depends on LAYERSCAPE_NS_ACCESS || PPC
-
-config PCIE3
-	bool "PCIe controller #3"
-	depends on LAYERSCAPE_NS_ACCESS || PPC
-
-config PCIE4
-	bool "PCIe controller #4"
-	depends on LAYERSCAPE_NS_ACCESS || PPC
-
-config FSL_USE_PCA9547_MUX
-	bool "Enable PCA9547 I2C Mux on Freescale boards"
-	depends on PPC || ARCH_LS1021A || FSL_LSCH2 || FSL_LSCH3
-	help
-	 This option enables the PCA9547 I2C mux on Freescale boards.
-
-config VID
-	bool "Enable Freescale VID"
-	depends on (PPC || ARCH_LS1021A || FSL_LSCH2 || FSL_LSCH3) && (I2C || DM_I2C)
-	help
-	 This option enables setting core voltage based on individual
-	 values saved in SoC fuses.
-
-config SPL_VID
-	bool "Enable Freescale VID in SPL"
-	depends on (PPC || ARCH_LS1021A || FSL_LSCH2 || FSL_LSCH3) && (SPL_I2C || DM_SPL_I2C)
-	help
-	 This option enables setting core voltage based on individual
-	 values saved in SoC fuses, in SPL.
-
-if VID || SPL_VID
-
-config VID_FLS_ENV
-	string "Environment variable for overriding VDD"
-	help
-	  This option allows for specifying the environment variable
-	  to check to override VDD information.
-
-config VOL_MONITOR_INA220
-	bool "Enable the INA220 voltage monitor read"
-	help
-	  This option enables INA220 voltage monitor read
-	  functionality. It is used by the common VID driver.
-
-config VOL_MONITOR_IR36021_READ
-	bool "Enable the IR36021 voltage monitor read"
-	help
-	 This option enables IR36021 voltage monitor read
-	 functionality. It is used by the common VID driver.
-
-config VOL_MONITOR_IR36021_SET
-	bool "Enable the IR36021 voltage monitor set"
-	help
-	 This option enables IR36021 voltage monitor set
-	 functionality. It is used by the common VID driver.
-
-config VOL_MONITOR_LTC3882_READ
-	bool "Enable the LTC3882 voltage monitor read"
-	help
-	 This option enables LTC3882 voltage monitor read
-	 functionality. It is used by the common VID driver.
-
-config VOL_MONITOR_LTC3882_SET
-	bool "Enable the LTC3882 voltage monitor set"
-	help
-	 This option enables LTC3882 voltage monitor set
-	 functionality. It is used by the common VID driver.
-
-config VOL_MONITOR_ISL68233_READ
-	bool "Enable the ISL68233 voltage monitor read"
-	help
-	 This option enables ISL68233 voltage monitor read
-	 functionality. It is used by the common VID driver.
-
-config VOL_MONITOR_ISL68233_SET
-	bool "Enable the ISL68233 voltage monitor set"
-	help
-	 This option enables ISL68233 voltage monitor set
-	 functionality. It is used by the common VID driver.
-
-endif
-
-config SYS_FSL_NUM_CC_PLLS
-	int "Number of clock control PLLs"
-	depends on MPC85xx || FSL_LSCH2 || FSL_LSCH3 || ARCH_LS1021A || ARCH_LS1028A
-	default 2 if ARCH_LS1021A || ARCH_LS1028A || FSL_LSCH2
-	default 6 if FSL_LSCH3 || MPC85xx
-
-config SYS_FSL_ESDHC_BE
-	bool
-
-config SYS_FSL_IFC_BE
-	bool
-
-config FSL_QIXIS
-	bool "Enable QIXIS support"
-	depends on PPC || ARCH_LS1021A || FSL_LSCH2 || FSL_LSCH3
-
-config QIXIS_I2C_ACCESS
-	bool "Access to QIXIS is over i2c"
-	depends on FSL_QIXIS
-	default y
-
-config HAS_FSL_DR_USB
-	def_bool y
-	depends on USB_EHCI_HCD && PPC

arch/arc/Kconfig

@@ -104,11 +104,13 @@ endchoice
 
 config CPU_BIG_ENDIAN
 	bool "Enable Big Endian Mode"
+	default n
 	help
 	  Build kernel for Big Endian Mode of ARC CPU
 
 config SYS_ICACHE_OFF
 	bool "Do not enable icache"
+	default n
 	help
 	  Do not enable instruction cache in U-Boot.
 
@@ -121,6 +123,7 @@ config SPL_SYS_ICACHE_OFF
 
 config SYS_DCACHE_OFF
 	bool "Do not enable dcache"
+	default n
 	help
 	  Do not enable data cache in U-Boot.
 
@@ -133,12 +136,14 @@ config SPL_SYS_DCACHE_OFF
 
 menuconfig ARC_DBG
 	bool "ARC debugging"
+	default n
 
 if ARC_DBG
 
 config ARC_DBG_IOC_ENABLE
 	bool "Enable IO coherency unit"
 	depends on CPU_ARCHS38
+	default n
 	help
 	  Enable IO coherency unit to debug problems with caches and
 	  DMA peripherals.
@@ -155,20 +160,22 @@ config TARGET_TB100
 	bool "Support tb100"
 
 config TARGET_NSIM
-	bool "Support ARC simulation & prototyping platforms"
+	bool "Support standalone nSIM & Free nSIM"
 
 config TARGET_AXS101
 	bool "Support Synopsys Designware SDP board AXS101"
+	select BOUNCE_BUFFER if CMD_NAND
 
 config TARGET_AXS103
 	bool "Support Synopsys Designware SDP board AXS103"
+	select BOUNCE_BUFFER if CMD_NAND
 
 config TARGET_EMSDP
 	bool "Synopsys EM Software Development Platform"
 	select CPU_ARCEM6
 
 config TARGET_HSDK
-	bool "Support Synopsys HSDK or HSDK-4xD board"
+	bool "Support Synpsys HS DevelopmentKit board"
 
 config TARGET_IOT_DEVKIT
 	bool "Synopsys Brite IoT Development kit"
@@ -177,10 +184,10 @@ config TARGET_IOT_DEVKIT
 endchoice
 
 source "board/abilis/tb100/Kconfig"
+source "board/synopsys/Kconfig"
 source "board/synopsys/axs10x/Kconfig"
 source "board/synopsys/emsdp/Kconfig"
 source "board/synopsys/hsdk/Kconfig"
 source "board/synopsys/iot_devkit/Kconfig"
-source "board/synopsys/nsim/Kconfig"
 
 endmenu

arch/arc/config.mk

@@ -2,13 +2,19 @@
 #
 # Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved.
 
+ifndef CONFIG_CPU_BIG_ENDIAN
+CONFIG_SYS_LITTLE_ENDIAN = 1
+else
+CONFIG_SYS_BIG_ENDIAN = 1
+endif
+
 ifdef CONFIG_SYS_LITTLE_ENDIAN
-KBUILD_LDFLAGS += -EL
+PLATFORM_LDFLAGS += -EL
 PLATFORM_CPPFLAGS += -mlittle-endian
 endif
 
 ifdef CONFIG_SYS_BIG_ENDIAN
-KBUILD_LDFLAGS += -EB
+PLATFORM_LDFLAGS += -EB
 PLATFORM_CPPFLAGS += -mbig-endian
 endif
 
@@ -16,6 +22,26 @@ ifdef CONFIG_ARC_MMU_VER
 CONFIG_MMU = 1
 endif
 
+ifdef CONFIG_CPU_ARC750D
+PLATFORM_CPPFLAGS += -mcpu=arc700
+endif
+
+ifdef CONFIG_CPU_ARC770D
+PLATFORM_CPPFLAGS += -mcpu=arc700 -mlock -mswape
+endif
+
+ifdef CONFIG_CPU_ARCEM6
+PLATFORM_CPPFLAGS += -mcpu=arcem
+endif
+
+ifdef CONFIG_CPU_ARCHS34
+PLATFORM_CPPFLAGS += -mcpu=archs
+endif
+
+ifdef CONFIG_CPU_ARCHS38
+PLATFORM_CPPFLAGS += -mcpu=archs
+endif
+
 PLATFORM_CPPFLAGS += -ffixed-r25 -D__ARC__ -gdwarf-2 -mno-sdata
 PLATFORM_RELFLAGS += -ffunction-sections -fdata-sections -fno-common
 

arch/arc/cpu/u-boot.lds

@@ -39,8 +39,8 @@ SECTIONS
 	}
 
 	. = ALIGN(4);
-	__u_boot_list : {
-		KEEP(*(SORT(__u_boot_list*)));
+	.u_boot_list : {
+		KEEP(*(SORT(.u_boot_list*)));
 	}
 
 	. = ALIGN(4);

arch/arc/dts/Makefile

@@ -5,11 +5,9 @@ dtb-$(CONFIG_TARGET_AXS103) +=  axs103.dtb
 dtb-$(CONFIG_TARGET_NSIM) +=  nsim.dtb
 dtb-$(CONFIG_TARGET_TB100) +=  abilis_tb100.dtb
 dtb-$(CONFIG_TARGET_EMSDP) +=  emsdp.dtb
-dtb-$(CONFIG_TARGET_HSDK) +=  hsdk.dtb hsdk-4xd.dtb
+dtb-$(CONFIG_TARGET_HSDK) +=  hsdk.dtb
 dtb-$(CONFIG_TARGET_IOT_DEVKIT) +=  iot_devkit.dtb
 
-include $(srctree)/scripts/Makefile.dts
-
 targets += $(dtb-y)
 
 DTC_FLAGS += -R 4 -p 0x1000

arch/arc/dts/axs10x_mb.dtsi

@@ -62,12 +62,12 @@
 			max-speed = <100>;
 		};
 
-		ehci@40000 {
+		ehci@0x40000 {
 			compatible = "generic-ehci";
 			reg = < 0x40000 0x100 >;
 		};
 
-		ohci@60000 {
+		ohci@0x60000 {
 			compatible = "generic-ohci";
 			reg = < 0x60000 0x100 >;
 		};
@@ -90,15 +90,14 @@
 		};
 
 		spi0: spi@0 {
-			compatible = "snps,axs10x-spi", "snps,dw-apb-ssi";
+			compatible = "snps,dw-apb-ssi";
 			reg = <0x0 0x100>;
 			#address-cells = <1>;
 			#size-cells = <0>;
 			spi-max-frequency = <4000000>;
 			clocks = <&apbclk>;
 			clock-names = "spi_clk";
-			num-cs = <1>;
-			cs-gpios = <&cs_gpio 0>;
+			cs-gpio = <&cs_gpio 0>;
 			spi_flash@0 {
 				compatible = "jedec,spi-nor";
 				reg = <0>;

arch/arc/dts/hsdk-4xd.dts

@@ -1,12 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2020 Synopsys, Inc. All rights reserved.
- * Author: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
- */
-/dts-v1/;
-
-#include "hsdk-common.dtsi"
-
-/ {
-	model = "snps,hsdk-4xd";
-};

arch/arc/dts/hsdk-common.dtsi

@@ -1,160 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2017-2020 Synopsys, Inc. All rights reserved.
- * Author: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
- */
-/dts-v1/;
-
-#include "skeleton.dtsi"
-#include "dt-bindings/clock/snps,hsdk-cgu.h"
-#include "dt-bindings/reset/snps,hsdk-reset.h"
-
-/ {
-	#address-cells = <1>;
-	#size-cells = <1>;
-
-	aliases {
-		console = &uart0;
-		spi0 = &spi0;
-	};
-
-	cpu_card {
-		core_clk: core_clk {
-			#clock-cells = <0>;
-			compatible = "fixed-clock";
-			clock-frequency = <500000000>;
-			u-boot,dm-pre-reloc;
-		};
-	};
-
-	clk-fmeas {
-		clocks = <&cgu_clk CLK_ARC_PLL>, <&cgu_clk CLK_SYS_PLL>,
-			 <&cgu_clk CLK_TUN_PLL>, <&cgu_clk CLK_DDR_PLL>,
-			 <&cgu_clk CLK_ARC>, <&cgu_clk CLK_HDMI_PLL>,
-			 <&cgu_clk CLK_TUN_TUN>, <&cgu_clk CLK_HDMI>,
-			 <&cgu_clk CLK_SYS_APB>, <&cgu_clk CLK_SYS_AXI>,
-			 <&cgu_clk CLK_SYS_ETH>, <&cgu_clk CLK_SYS_USB>,
-			 <&cgu_clk CLK_SYS_SDIO>, <&cgu_clk CLK_SYS_HDMI>,
-			 <&cgu_clk CLK_SYS_GFX_CORE>, <&cgu_clk CLK_SYS_GFX_DMA>,
-			 <&cgu_clk CLK_SYS_GFX_CFG>, <&cgu_clk CLK_SYS_DMAC_CORE>,
-			 <&cgu_clk CLK_SYS_DMAC_CFG>, <&cgu_clk CLK_SYS_SDIO_REF>,
-			 <&cgu_clk CLK_SYS_SPI_REF>, <&cgu_clk CLK_SYS_I2C_REF>,
-			 <&cgu_clk CLK_SYS_UART_REF>, <&cgu_clk CLK_SYS_EBI_REF>,
-			 <&cgu_clk CLK_TUN_ROM>, <&cgu_clk CLK_TUN_PWM>,
-			 <&cgu_clk CLK_TUN_TIMER>;
-		clock-names = "cpu-pll", "sys-pll",
-			      "tun-pll", "ddr-clk",
-			      "cpu-clk", "hdmi-pll",
-			      "tun-clk", "hdmi-clk",
-			      "apb-clk", "axi-clk",
-			      "eth-clk", "usb-clk",
-			      "sdio-clk", "hdmi-sys-clk",
-			      "gfx-core-clk", "gfx-dma-clk",
-			      "gfx-cfg-clk", "dmac-core-clk",
-			      "dmac-cfg-clk", "sdio-ref-clk",
-			      "spi-clk", "i2c-clk",
-			      "uart-clk", "ebi-clk",
-			      "rom-clk", "pwm-clk",
-			      "timer-clk";
-	};
-
-	cgu_clk: cgu-clk@f0000000 {
-		compatible = "snps,hsdk-cgu-clock";
-		reg = <0xf0000000 0x10>, <0xf00014B8 0x4>;
-		#clock-cells = <1>;
-	};
-
-	cgu_rst: reset-controller@f00008a0 {
-		compatible = "snps,hsdk-reset";
-		#reset-cells = <1>;
-		reg = <0xf00008a0 0x4>, <0xf0000ff0 0x4>;
-	};
-
-	uart0: serial0@f0005000 {
-		compatible = "snps,dw-apb-uart";
-		reg = <0xf0005000 0x1000>;
-		reg-shift = <2>;
-		reg-io-width = <4>;
-	};
-
-	ethernet@f0008000 {
-		#interrupt-cells = <1>;
-		compatible = "snps,arc-dwmac-3.70a";
-		reg = <0xf0008000 0x2000>;
-		phy-mode = "gmii";
-	};
-
-	ehci@f0040000 {
-		compatible = "generic-ehci";
-		reg = <0xf0040000 0x100>;
-
-		/*
-		 * OHCI and EHCI have reset line shared so we don't add
-		 * reset property to OHCI node as it is probed later and
-		 * it will reset sucessfuly probed and configured EHCI HW.
-		 */
-		resets = <&cgu_rst HSDK_USB_RESET>;
-	};
-
-	ohci@f0060000 {
-		compatible = "generic-ohci";
-		reg = <0xf0060000 0x100>;
-	};
-
-	mmcclk_ciu: mmcclk-ciu {
-		compatible = "fixed-clock";
-		/*
-		 * DW sdio controller has external ciu clock divider
-		 * controlled via register in SDIO IP. Due to its
-		 * unexpected default value (it should divide by 1
-		 * but it divides by 8) SDIO IP uses wrong clock and
-		 * works unstable (see STAR 9001204800)
-		 * We switched to the minimum possible value of the
-		 * divisor (div-by-2) in HSDK platform code.
-		 * So default mmcclk ciu clock is 50000000 Hz.
-		 */
-		clock-frequency = <50000000>;
-		#clock-cells = <0>;
-	};
-
-	mmc: mmc0@f000a000 {
-		compatible = "snps,dw-mshc";
-		reg = <0xf000a000 0x400>;
-		bus-width = <4>;
-		fifo-depth = <256>;
-		clocks = <&cgu_clk CLK_SYS_SDIO>, <&mmcclk_ciu>;
-		clock-names = "biu", "ciu";
-		max-frequency = <25000000>;
-	};
-
-	spi0: spi@f0020000 {
-		compatible = "snps,hsdk-spi", "snps,dw-apb-ssi";
-		reg = <0xf0020000 0x1000>;
-		#address-cells = <1>;
-		#size-cells = <0>;
-		spi-max-frequency = <4000000>;
-		clocks = <&cgu_clk CLK_SYS_SPI_REF>;
-		clock-names = "spi_clk";
-		num-cs = <1>;
-		cs-gpios = <&cs_gpio 0>;
-		spi_flash@0 {
-			compatible = "jedec,spi-nor";
-			reg = <0>;
-			spi-max-frequency = <4000000>;
-		};
-	};
-
-	cs_gpio: gpio@f00014b0 {
-		compatible = "snps,creg-gpio";
-		reg = <0xf00014b0 0x4>;
-		gpio-controller;
-		#gpio-cells = <1>;
-		gpio-bank-name = "hsdk-spi-cs";
-		gpio-count = <1>;
-		gpio-first-shift = <0>;
-		gpio-bit-per-line = <2>;
-		gpio-activate-val = <2>;
-		gpio-deactivate-val = <3>;
-		gpio-default-val = <1>;
-	};
-};

arch/arc/dts/hsdk.dts

@@ -1,12 +1,144 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
- * Copyright (C) 2017-2020 Synopsys, Inc. All rights reserved.
- * Author: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
+ * Copyright (C) 2017 Synopsys, Inc. All rights reserved.
  */
 /dts-v1/;
 
-#include "hsdk-common.dtsi"
+#include "skeleton.dtsi"
+#include "dt-bindings/clock/snps,hsdk-cgu.h"
 
 / {
 	model = "snps,hsdk";
+
+	#address-cells = <1>;
+	#size-cells = <1>;
+
+	aliases {
+		console = &uart0;
+		spi0 = &spi0;
+	};
+
+	cpu_card {
+		core_clk: core_clk {
+			#clock-cells = <0>;
+			compatible = "fixed-clock";
+			clock-frequency = <500000000>;
+			u-boot,dm-pre-reloc;
+		};
+	};
+
+	clk-fmeas {
+		clocks = <&cgu_clk CLK_ARC_PLL>, <&cgu_clk CLK_SYS_PLL>,
+			 <&cgu_clk CLK_TUN_PLL>, <&cgu_clk CLK_DDR_PLL>,
+			 <&cgu_clk CLK_ARC>, <&cgu_clk CLK_HDMI_PLL>,
+			 <&cgu_clk CLK_TUN_TUN>, <&cgu_clk CLK_HDMI>,
+			 <&cgu_clk CLK_SYS_APB>, <&cgu_clk CLK_SYS_AXI>,
+			 <&cgu_clk CLK_SYS_ETH>, <&cgu_clk CLK_SYS_USB>,
+			 <&cgu_clk CLK_SYS_SDIO>, <&cgu_clk CLK_SYS_HDMI>,
+			 <&cgu_clk CLK_SYS_GFX_CORE>, <&cgu_clk CLK_SYS_GFX_DMA>,
+			 <&cgu_clk CLK_SYS_GFX_CFG>, <&cgu_clk CLK_SYS_DMAC_CORE>,
+			 <&cgu_clk CLK_SYS_DMAC_CFG>, <&cgu_clk CLK_SYS_SDIO_REF>,
+			 <&cgu_clk CLK_SYS_SPI_REF>, <&cgu_clk CLK_SYS_I2C_REF>,
+			 <&cgu_clk CLK_SYS_UART_REF>, <&cgu_clk CLK_SYS_EBI_REF>,
+			 <&cgu_clk CLK_TUN_ROM>, <&cgu_clk CLK_TUN_PWM>;
+		clock-names = "cpu-pll", "sys-pll",
+			      "tun-pll", "ddr-clk",
+			      "cpu-clk", "hdmi-pll",
+			      "tun-clk", "hdmi-clk",
+			      "apb-clk", "axi-clk",
+			      "eth-clk", "usb-clk",
+			      "sdio-clk", "hdmi-sys-clk",
+			      "gfx-core-clk", "gfx-dma-clk",
+			      "gfx-cfg-clk", "dmac-core-clk",
+			      "dmac-cfg-clk", "sdio-ref-clk",
+			      "spi-clk", "i2c-clk",
+			      "uart-clk", "ebi-clk",
+			      "rom-clk", "pwm-clk";
+	};
+
+	cgu_clk: cgu-clk@f0000000 {
+		compatible = "snps,hsdk-cgu-clock";
+		reg = <0xf0000000 0x10>, <0xf00014B8 0x4>;
+		#clock-cells = <1>;
+	};
+
+	uart0: serial0@f0005000 {
+		compatible = "snps,dw-apb-uart";
+		reg = <0xf0005000 0x1000>;
+		reg-shift = <2>;
+		reg-io-width = <4>;
+	};
+
+	ethernet@f0008000 {
+		#interrupt-cells = <1>;
+		compatible = "snps,arc-dwmac-3.70a";
+		reg = <0xf0008000 0x2000>;
+		phy-mode = "gmii";
+	};
+
+	ehci@0xf0040000 {
+		compatible = "generic-ehci";
+		reg = <0xf0040000 0x100>;
+	};
+
+	ohci@0xf0060000 {
+		compatible = "generic-ohci";
+		reg = <0xf0060000 0x100>;
+	};
+
+	mmcclk_ciu: mmcclk-ciu {
+		compatible = "fixed-clock";
+		/*
+		 * DW sdio controller has external ciu clock divider
+		 * controlled via register in SDIO IP. Due to its
+		 * unexpected default value (it should divide by 1
+		 * but it divides by 8) SDIO IP uses wrong clock and
+		 * works unstable (see STAR 9001204800)
+		 * We switched to the minimum possible value of the
+		 * divisor (div-by-2) in HSDK platform code.
+		 * So default mmcclk ciu clock is 50000000 Hz.
+		 */
+		clock-frequency = <50000000>;
+		#clock-cells = <0>;
+	};
+
+	mmc: mmc0@f000a000 {
+		compatible = "snps,dw-mshc";
+		reg = <0xf000a000 0x400>;
+		bus-width = <4>;
+		fifo-depth = <256>;
+		clocks = <&cgu_clk CLK_SYS_SDIO>, <&mmcclk_ciu>;
+		clock-names = "biu", "ciu";
+		max-frequency = <25000000>;
+	};
+
+	spi0: spi@f0020000 {
+		compatible = "snps,dw-apb-ssi";
+		reg = <0xf0020000 0x1000>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		spi-max-frequency = <4000000>;
+		clocks = <&cgu_clk CLK_SYS_SPI_REF>;
+		clock-names = "spi_clk";
+		cs-gpio = <&cs_gpio 0>;
+		spi_flash@0 {
+			compatible = "jedec,spi-nor";
+			reg = <0>;
+			spi-max-frequency = <4000000>;
+		};
+	};
+
+	cs_gpio: gpio@f00014b0 {
+		compatible = "snps,creg-gpio";
+		reg = <0xf00014b0 0x4>;
+		gpio-controller;
+		#gpio-cells = <1>;
+		gpio-bank-name = "hsdk-spi-cs";
+		gpio-count = <1>;
+		gpio-first-shift = <0>;
+		gpio-bit-per-line = <2>;
+		gpio-activate-val = <2>;
+		gpio-deactivate-val = <3>;
+		gpio-default-val = <1>;
+	};
 };

arch/arc/dts/iot_devkit.dts

@@ -39,7 +39,7 @@
 	};
 
 	usbphy: phy {
-		compatible = "usb-nop-xceiv";
+		compatible = "nop-phy";
 		#phy-cells = <0>;
 	};
 

arch/arc/dts/nsim.dts

@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
- * Copyright (C) 2015-2016, 2020 Synopsys, Inc. (www.synopsys.com)
+ * Copyright (C) 2015-2016 Synopsys, Inc. (www.synopsys.com)
  */
 /dts-v1/;
 
@@ -10,7 +10,7 @@
 	model = "snps,nsim";
 
 	aliases {
-		console = &uart0;
+		console = &arcuart0;
 	};
 
 	cpu_card {
@@ -22,36 +22,10 @@
 		};
 	};
 
-	uart0: serial@f0000000 {
-		compatible = "snps,dw-apb-uart";
-		reg = <0xf0000000 0x1000>;
-		reg-shift = <2>;
-		reg-io-width = <4>;
+	arcuart0: serial@0xc0fc1000 {
+		compatible = "snps,arc-uart";
+		reg = <0xc0fc1000 0x100>;
 		clock-frequency = <70000000>;
 	};
 
-	virtio0: virtio@f0100000 {
-		compatible = "virtio,mmio";
-		reg = <0xf0100000 0x2000>;
-	};
-
-	virtio1: virtio@f0102000 {
-		compatible = "virtio,mmio";
-		reg = <0xf0102000 0x2000>;
-	};
-
-	virtio2: virtio@f0104000 {
-		compatible = "virtio,mmio";
-		reg = <0xf0104000 0x2000>;
-	};
-
-	virtio3: virtio@f0106000 {
-		compatible = "virtio,mmio";
-		reg = <0xf0106000 0x2000>;
-	};
-
-	virtio4: virtio@f0108000 {
-		compatible = "virtio,mmio";
-		reg = <0xf0108000 0x2000>;
-	};
 };

arch/arc/include/asm/arcregs.h

@@ -51,9 +51,6 @@
 #define ARC_AUX_DCCM_BASE	0x18	/* DCCM Base Addr ARCv2 */
 #define ARC_AUX_ICCM_BASE	0x208	/* ICCM Base Addr ARCv2 */
 
-/* CSM auxiliary registers */
-#define ARC_AUX_CSM_ENABLE	0x9A0
-
 /* Timer related auxiliary registers */
 #define ARC_AUX_TIMER0_CNT	0x21	/* Timer 0 count */
 #define ARC_AUX_TIMER0_CTRL	0x22	/* Timer 0 control */
@@ -103,14 +100,11 @@
 
 /* DSP-extensions related auxiliary registers */
 #define ARC_AUX_DSP_BUILD	0x7A
-#define ARC_AUX_DSP_CTRL	0x59F
 
 /* ARC Subsystems related auxiliary registers */
 #define ARC_AUX_SUBSYS_BUILD	0xF0
 
 #ifndef __ASSEMBLY__
-#include <linux/bitops.h>
-
 /* Accessors for auxiliary registers */
 #define read_aux_reg(reg)	__builtin_arc_lr(reg)
 

arch/arc/include/asm/cache.h

@@ -16,6 +16,9 @@
  */
 #define ARCH_DMA_MINALIGN	128
 
+/* CONFIG_SYS_CACHELINE_SIZE is used a lot in drivers */
+#define CONFIG_SYS_CACHELINE_SIZE	ARCH_DMA_MINALIGN
+
 #if defined(ARC_MMU_ABSENT)
 #define CONFIG_ARC_MMU_VER 0
 #elif defined(CONFIG_ARC_MMU_V2)
@@ -37,13 +40,6 @@ static const inline int is_ioc_enabled(void)
 	return IS_ENABLED(CONFIG_ARC_DBG_IOC_ENABLE);
 }
 
-/*
- * We export SLC control functions to use them in platform configuration code.
- * They maust not be used in any generic code!
- */
-void slc_enable(void);
-void slc_disable(void);
-
 #endif /* __ASSEMBLY__ */
 
 #endif /* __ASM_ARC_CACHE_H */

arch/arc/include/asm/config.h

@@ -6,4 +6,8 @@
 #ifndef __ASM_ARC_CONFIG_H_
 #define __ASM_ARC_CONFIG_H_
 
+#define CONFIG_SYS_BOOT_RAMDISK_HIGH
+
+#define CONFIG_LMB
+
 #endif /*__ASM_ARC_CONFIG_H_ */

arch/arc/include/asm/dma-mapping.h

@@ -1 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */

arch/arc/include/asm/global_data.h

@@ -6,6 +6,8 @@
 #ifndef	__ASM_ARC_GLOBAL_DATA_H
 #define __ASM_ARC_GLOBAL_DATA_H
 
+#include <config.h>
+
 #ifndef __ASSEMBLY__
 /* Architecture-specific global data */
 struct arch_global_data {

arch/arc/include/asm/io.h

@@ -1,6 +1,6 @@
 /* SPDX-License-Identifier: GPL-2.0+ */
 /*
- * Copyright (C) 2013-2014, 2020 Synopsys, Inc. All rights reserved.
+ * Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved.
  */
 
 #ifndef __ASM_ARC_IO_H
@@ -9,12 +9,6 @@
 #include <linux/types.h>
 #include <asm/byteorder.h>
 
-/*
- * Compiler barrier. It prevents compiler from reordering instructions before
- * and after it. It doesn't prevent HW (CPU) from any reordering though.
- */
-#define __comp_b()		asm volatile("" : : : "memory")
-
 #ifdef __ARCHS__
 
 /*
@@ -51,8 +45,8 @@
 #define __iormb()		rmb()
 #define __iowmb()		wmb()
 #else
-#define __iormb()		__comp_b()
-#define __iowmb()		__comp_b()
+#define __iormb()		asm volatile("" : : : "memory")
+#define __iowmb()		asm volatile("" : : : "memory")
 #endif
 
 static inline void sync(void)
@@ -60,117 +54,134 @@ static inline void sync(void)
 	/* Not yet implemented */
 }
 
-/*
- * We must use 'volatile' in C-version read/write IO accessors implementation
- * to avoid merging several reads (writes) into one read (write), or optimizing
- * them out by compiler.
- * We must use compiler barriers before and after operation (read or write) so
- * it won't be reordered by compiler.
- */
-#define __arch_getb(a)		({ u8  __v; __comp_b(); __v = *(volatile u8  *)(a); __comp_b(); __v; })
-#define __arch_getw(a)		({ u16 __v; __comp_b(); __v = *(volatile u16 *)(a); __comp_b(); __v; })
-#define __arch_getl(a)		({ u32 __v; __comp_b(); __v = *(volatile u32 *)(a); __comp_b(); __v; })
-#define __arch_getq(a)		({ u64 __v; __comp_b(); __v = *(volatile u64 *)(a); __comp_b(); __v; })
-
-#define __arch_putb(v, a)	({ __comp_b(); *(volatile u8  *)(a) = (v); __comp_b(); })
-#define __arch_putw(v, a)	({ __comp_b(); *(volatile u16 *)(a) = (v); __comp_b(); })
-#define __arch_putl(v, a)	({ __comp_b(); *(volatile u32 *)(a) = (v); __comp_b(); })
-#define __arch_putq(v, a)	({ __comp_b(); *(volatile u64 *)(a) = (v); __comp_b(); })
-
-
-/*
- * We add memory barriers for __raw_readX / __raw_writeX accessors same way as
- * it is done for readX and writeX accessors as lots of U-boot driver uses
- * __raw_readX / __raw_writeX instead of proper accessor with barrier.
- */
-#define __raw_writeb(v, c)	({ __iowmb(); __arch_putb(v, c); })
-#define __raw_writew(v, c)	({ __iowmb(); __arch_putw(v, c); })
-#define __raw_writel(v, c)	({ __iowmb(); __arch_putl(v, c); })
-#define __raw_writeq(v, c)	({ __iowmb(); __arch_putq(v, c); })
-
-#define __raw_readb(c)		({ u8  __v = __arch_getb(c); __iormb(); __v; })
-#define __raw_readw(c)		({ u16 __v = __arch_getw(c); __iormb(); __v; })
-#define __raw_readl(c)		({ u32 __v = __arch_getl(c); __iormb(); __v; })
-#define __raw_readq(c)		({ u64 __v = __arch_getq(c); __iormb(); __v; })
-
-
-static inline void __raw_writesb(unsigned long addr, const void *data,
-				 int bytelen)
+static inline u8 __raw_readb(const volatile void __iomem *addr)
 {
-	u8 *buf = (uint8_t *)data;
+	u8 b;
 
-	__iowmb();
-
-	while (bytelen--)
-		__arch_putb(*buf++, addr);
+	__asm__ __volatile__("ldb%U1	%0, %1\n"
+			     : "=r" (b)
+			     : "m" (*(volatile u8 __force *)addr)
+			     : "memory");
+	return b;
 }
 
-static inline void __raw_writesw(unsigned long addr, const void *data,
-				 int wordlen)
+static inline u16 __raw_readw(const volatile void __iomem *addr)
 {
-	u16 *buf = (uint16_t *)data;
+	u16 s;
 
-	__iowmb();
-
-	while (wordlen--)
-		__arch_putw(*buf++, addr);
+	__asm__ __volatile__("ldw%U1	%0, %1\n"
+			     : "=r" (s)
+			     : "m" (*(volatile u16 __force *)addr)
+			     : "memory");
+	return s;
 }
 
-static inline void __raw_writesl(unsigned long addr, const void *data,
-				 int longlen)
+static inline u32 __raw_readl(const volatile void __iomem *addr)
 {
-	u32 *buf = (uint32_t *)data;
+	u32 w;
 
-	__iowmb();
-
-	while (longlen--)
-		__arch_putl(*buf++, addr);
+	__asm__ __volatile__("ld%U1	%0, %1\n"
+			     : "=r" (w)
+			     : "m" (*(volatile u32 __force *)addr)
+			     : "memory");
+	return w;
 }
 
-static inline void __raw_readsb(unsigned long addr, void *data, int bytelen)
+static inline void __raw_writeb(u8 b, volatile void __iomem *addr)
 {
-	u8 *buf = (uint8_t *)data;
-
-	while (bytelen--)
-		*buf++ = __arch_getb(addr);
-
-	__iormb();
+	__asm__ __volatile__("stb%U1	%0, %1\n"
+			     :
+			     : "r" (b), "m" (*(volatile u8 __force *)addr)
+			     : "memory");
 }
 
-static inline void __raw_readsw(unsigned long addr, void *data, int wordlen)
+static inline void __raw_writew(u16 s, volatile void __iomem *addr)
 {
-	u16 *buf = (uint16_t *)data;
-
-	while (wordlen--)
-		*buf++ = __arch_getw(addr);
-
-	__iormb();
+	__asm__ __volatile__("stw%U1	%0, %1\n"
+			     :
+			     : "r" (s), "m" (*(volatile u16 __force *)addr)
+			     : "memory");
 }
 
-static inline void __raw_readsl(unsigned long addr, void *data, int longlen)
+static inline void __raw_writel(u32 w, volatile void __iomem *addr)
 {
-	u32 *buf = (uint32_t *)data;
-
-	while (longlen--)
-		*buf++ = __arch_getl(addr);
-
-	__iormb();
+	__asm__ __volatile__("st%U1	%0, %1\n"
+			     :
+			     : "r" (w), "m" (*(volatile u32 __force *)addr)
+			     : "memory");
 }
 
-/*
- * Relaxed I/O memory access primitives. These follow the Device memory
- * ordering rules but do not guarantee any ordering relative to Normal memory
- * accesses.
- */
-#define readb_relaxed(c)	({ u8  __r = __arch_getb(c); __r; })
-#define readw_relaxed(c)	({ u16 __r = le16_to_cpu((__force __le16)__arch_getw(c)); __r; })
-#define readl_relaxed(c)	({ u32 __r = le32_to_cpu((__force __le32)__arch_getl(c)); __r; })
-#define readq_relaxed(c)	({ u64 __r = le64_to_cpu((__force __le64)__arch_getq(c)); __r; })
+static inline int __raw_readsb(unsigned int addr, void *data, int bytelen)
+{
+	__asm__ __volatile__ ("1:ld.di	r8, [r0]\n"
+			      "sub.f	r2, r2, 1\n"
+			      "bnz.d	1b\n"
+			      "stb.ab	r8, [r1, 1]\n"
+			      :
+			      : "r" (addr), "r" (data), "r" (bytelen)
+			      : "r8");
+	return bytelen;
+}
 
-#define writeb_relaxed(v, c)	((void)__arch_putb((v), (c)))
-#define writew_relaxed(v, c)	((void)__arch_putw((__force u16)cpu_to_le16(v), (c)))
-#define writel_relaxed(v, c)	((void)__arch_putl((__force u32)cpu_to_le32(v), (c)))
-#define writeq_relaxed(v, c)	((void)__arch_putq((__force u64)cpu_to_le64(v), (c)))
+static inline int __raw_readsw(unsigned int addr, void *data, int wordlen)
+{
+	__asm__ __volatile__ ("1:ld.di	r8, [r0]\n"
+			      "sub.f	r2, r2, 1\n"
+			      "bnz.d	1b\n"
+			      "stw.ab	r8, [r1, 2]\n"
+			      :
+			      : "r" (addr), "r" (data), "r" (wordlen)
+			      : "r8");
+	return wordlen;
+}
+
+static inline int __raw_readsl(unsigned int addr, void *data, int longlen)
+{
+	__asm__ __volatile__ ("1:ld.di	r8, [r0]\n"
+			      "sub.f	r2, r2, 1\n"
+			      "bnz.d	1b\n"
+			      "st.ab	r8, [r1, 4]\n"
+			      :
+			      : "r" (addr), "r" (data), "r" (longlen)
+			      : "r8");
+	return longlen;
+}
+
+static inline int __raw_writesb(unsigned int addr, void *data, int bytelen)
+{
+	__asm__ __volatile__ ("1:ldb.ab	r8, [r1, 1]\n"
+			      "sub.f	r2, r2, 1\n"
+			      "bnz.d	1b\n"
+			      "st.di	r8, [r0, 0]\n"
+			      :
+			      : "r" (addr), "r" (data), "r" (bytelen)
+			      : "r8");
+	return bytelen;
+}
+
+static inline int __raw_writesw(unsigned int addr, void *data, int wordlen)
+{
+	__asm__ __volatile__ ("1:ldw.ab	r8, [r1, 2]\n"
+			      "sub.f	r2, r2, 1\n"
+			      "bnz.d	1b\n"
+			      "st.ab.di	r8, [r0, 0]\n"
+			      :
+			      : "r" (addr), "r" (data), "r" (wordlen)
+			      : "r8");
+	return wordlen;
+}
+
+static inline int __raw_writesl(unsigned int addr, void *data, int longlen)
+{
+	__asm__ __volatile__ ("1:ld.ab	r8, [r1, 4]\n"
+			      "sub.f	r2, r2, 1\n"
+			      "bnz.d	1b\n"
+			      "st.ab.di	r8, [r0, 0]\n"
+			      :
+			      : "r" (addr), "r" (data), "r" (longlen)
+			      : "r8");
+	return longlen;
+}
 
 /*
  * MMIO can also get buffered/optimized in micro-arch, so barriers needed
@@ -184,15 +195,32 @@ static inline void __raw_readsl(unsigned long addr, void *data, int longlen)
  *
  * http://lkml.kernel.org/r/20150622133656.GG1583@arm.com
  */
-#define readb(c)	({ u8  __v = readb_relaxed(c); __iormb(); __v; })
-#define readw(c)	({ u16 __v = readw_relaxed(c); __iormb(); __v; })
-#define readl(c)	({ u32 __v = readl_relaxed(c); __iormb(); __v; })
-#define readq(c)	({ u64 __v = readq_relaxed(c); __iormb(); __v; })
+#define readb(c)		({ u8  __v = readb_relaxed(c); __iormb(); __v; })
+#define readw(c)		({ u16 __v = readw_relaxed(c); __iormb(); __v; })
+#define readl(c)		({ u32 __v = readl_relaxed(c); __iormb(); __v; })
 
-#define writeb(v, c)	({ __iowmb(); writeb_relaxed(v, c); })
-#define writew(v, c)	({ __iowmb(); writew_relaxed(v, c); })
-#define writel(v, c)	({ __iowmb(); writel_relaxed(v, c); })
-#define writeq(v, c)	({ __iowmb(); writeq_relaxed(v, c); })
+#define writeb(v,c)		({ __iowmb(); writeb_relaxed(v,c); })
+#define writew(v,c)		({ __iowmb(); writew_relaxed(v,c); })
+#define writel(v,c)		({ __iowmb(); writel_relaxed(v,c); })
+
+/*
+ * Relaxed API for drivers which can handle barrier ordering themselves
+ *
+ * Also these are defined to perform little endian accesses.
+ * To provide the typical device register semantics of fixed endian,
+ * swap the byte order for Big Endian
+ *
+ * http://lkml.kernel.org/r/201603100845.30602.arnd@arndb.de
+ */
+#define readb_relaxed(c)	__raw_readb(c)
+#define readw_relaxed(c) ({ u16 __r = le16_to_cpu((__force __le16) \
+					__raw_readw(c)); __r; })
+#define readl_relaxed(c) ({ u32 __r = le32_to_cpu((__force __le32) \
+					__raw_readl(c)); __r; })
+
+#define writeb_relaxed(v,c)	__raw_writeb(v,c)
+#define writew_relaxed(v,c)	__raw_writew((__force u16) cpu_to_le16(v),c)
+#define writel_relaxed(v,c)	__raw_writel((__force u32) cpu_to_le32(v),c)
 
 #define out_arch(type, endian, a, v)	__raw_write##type(cpu_to_##endian(v), a)
 #define in_arch(type, endian, a)	endian##_to_cpu(__raw_read##type(a))

arch/arc/lib/bootm.c

@@ -3,17 +3,41 @@
  * Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved.
  */
 
-#include <common.h>
-#include <bootstage.h>
-#include <env.h>
-#include <image.h>
 #include <irq_func.h>
-#include <log.h>
 #include <asm/cache.h>
-#include <asm/global_data.h>
+#include <common.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
+static ulong get_sp(void)
+{
+	ulong ret;
+
+	asm("mov %0, sp" : "=r"(ret) : );
+	return ret;
+}
+
+void arch_lmb_reserve(struct lmb *lmb)
+{
+	ulong sp;
+
+	/*
+	 * Booting a (Linux) kernel image
+	 *
+	 * Allocate space for command line and board info - the
+	 * address should be as high as possible within the reach of
+	 * the kernel (see CONFIG_SYS_BOOTMAPSZ settings), but in unused
+	 * memory, which means far enough below the current stack
+	 * pointer.
+	 */
+	sp = get_sp();
+	debug("## Current stack ends at 0x%08lx ", sp);
+
+	/* adjust sp by 4K to be safe */
+	sp -= 4096;
+	lmb_reserve(lmb, sp, (CONFIG_SYS_SDRAM_BASE + gd->ram_size - sp));
+}
+
 static int cleanup_before_linux(void)
 {
 	disable_interrupts();
@@ -29,11 +53,9 @@ static int boot_prep_linux(bootm_headers_t *images)
 {
 	int ret;
 
-	if (CONFIG_IS_ENABLED(LMB)) {
-		ret = image_setup_linux(images);
-		if (ret)
-			return ret;
-	}
+	ret = image_setup_linux(images);
+	if (ret)
+		return ret;
 
 	return board_prep_linux(images);
 }
@@ -65,7 +87,7 @@ static void boot_jump_linux(bootm_headers_t *images, int flag)
 	       "(fake run for tracing)" : "");
 	bootstage_mark_name(BOOTSTAGE_ID_BOOTM_HANDOFF, "start_kernel");
 
-	if (CONFIG_IS_ENABLED(OF_LIBFDT) && images->ft_len) {
+	if (IMAGE_ENABLE_OF_LIBFDT && images->ft_len) {
 		r0 = 2;
 		r2 = (unsigned int)images->ft_addr;
 	} else {

arch/arc/lib/cache.c

@@ -6,12 +6,9 @@
 #include <config.h>
 #include <common.h>
 #include <cpu_func.h>
-#include <asm/global_data.h>
-#include <linux/bitops.h>
 #include <linux/compiler.h>
 #include <linux/kernel.h>
 #include <linux/log2.h>
-#include <lmb.h>
 #include <asm/arcregs.h>
 #include <asm/arc-bcr.h>
 #include <asm/cache.h>
@@ -92,7 +89,8 @@
  *
  * [ NOTE 2 ]:
  * As of today we only support the following cache configurations on ARC.
- * Other configurations may exist in HW but we don't support it in SW.
+ * Other configurations may exist in HW (for example, since version 3.0 HS
+ * supports SL$ (L2 system level cache) disable) but we don't support it in SW.
  * Configuration 1:
  *        ______________________
  *       |                      |
@@ -122,8 +120,7 @@
  *       |                      |
  *       |   L2 (SL$)           |
  *       |______________________|
- *          always on (ARCv2, HS <  3.0)
- *          on/off    (ARCv2, HS >= 3.0)
+ *          always must be on
  *        ___|______________|____
  *       |                      |
  *       |   main memory        |
@@ -181,8 +178,6 @@ DECLARE_GLOBAL_DATA_PTR;
 
 static inlined_cachefunc void __ic_entire_invalidate(void);
 static inlined_cachefunc void __dc_entire_op(const int cacheop);
-static inlined_cachefunc void __slc_entire_op(const int op);
-static inlined_cachefunc bool ioc_enabled(void);
 
 static inline bool pae_exists(void)
 {
@@ -243,70 +238,6 @@ static inlined_cachefunc bool slc_exists(void)
 	return false;
 }
 
-enum slc_dis_status {
-	ST_SLC_MISSING = 0,
-	ST_SLC_NO_DISABLE_CTRL,
-	ST_SLC_DISABLE_CTRL
-};
-
-/*
- * ARCv1                                     -> ST_SLC_MISSING
- * ARCv2 && SLC absent                       -> ST_SLC_MISSING
- * ARCv2 && SLC exists && SLC version <= 2   -> ST_SLC_NO_DISABLE_CTRL
- * ARCv2 && SLC exists && SLC version > 2    -> ST_SLC_DISABLE_CTRL
- */
-static inlined_cachefunc enum slc_dis_status slc_disable_supported(void)
-{
-	if (is_isa_arcv2()) {
-		union bcr_generic sbcr;
-
-		sbcr.word = read_aux_reg(ARC_BCR_SLC);
-		if (sbcr.fields.ver == 0)
-			return ST_SLC_MISSING;
-		else if (sbcr.fields.ver <= 2)
-			return ST_SLC_NO_DISABLE_CTRL;
-		else
-			return ST_SLC_DISABLE_CTRL;
-	}
-
-	return ST_SLC_MISSING;
-}
-
-static inlined_cachefunc bool __slc_enabled(void)
-{
-	return !(read_aux_reg(ARC_AUX_SLC_CTRL) & SLC_CTRL_DIS);
-}
-
-static inlined_cachefunc void __slc_enable(void)
-{
-	unsigned int ctrl;
-
-	ctrl = read_aux_reg(ARC_AUX_SLC_CTRL);
-	ctrl &= ~SLC_CTRL_DIS;
-	write_aux_reg(ARC_AUX_SLC_CTRL, ctrl);
-}
-
-static inlined_cachefunc void __slc_disable(void)
-{
-	unsigned int ctrl;
-
-	ctrl = read_aux_reg(ARC_AUX_SLC_CTRL);
-	ctrl |= SLC_CTRL_DIS;
-	write_aux_reg(ARC_AUX_SLC_CTRL, ctrl);
-}
-
-static inlined_cachefunc bool slc_enabled(void)
-{
-	enum slc_dis_status slc_status = slc_disable_supported();
-
-	if (slc_status == ST_SLC_MISSING)
-		return false;
-	else if (slc_status == ST_SLC_NO_DISABLE_CTRL)
-		return true;
-	else
-		return __slc_enabled();
-}
-
 static inlined_cachefunc bool slc_data_bypass(void)
 {
 	/*
@@ -316,40 +247,7 @@ static inlined_cachefunc bool slc_data_bypass(void)
 	return !dcache_enabled();
 }
 
-void slc_enable(void)
-{
-	if (slc_disable_supported() != ST_SLC_DISABLE_CTRL)
-		return;
-
-	if (__slc_enabled())
-		return;
-
-	__slc_enable();
-}
-
-/* TODO: warn if we are not able to disable SLC */
-void slc_disable(void)
-{
-	if (slc_disable_supported() != ST_SLC_DISABLE_CTRL)
-		return;
-
-	/* we don't support SLC disabling if we use IOC */
-	if (ioc_enabled())
-		return;
-
-	if (!__slc_enabled())
-		return;
-
-	/*
-	 * We need to flush L1D$ to guarantee that we won't have any
-	 * writeback operations during SLC disabling.
-	 */
-	__dc_entire_op(OP_FLUSH);
-	__slc_entire_op(OP_FLUSH_N_INV);
-	__slc_disable();
-}
-
-static inlined_cachefunc bool ioc_exists(void)
+static inline bool ioc_exists(void)
 {
 	if (is_isa_arcv2()) {
 		union bcr_clust_cfg cbcr;
@@ -361,7 +259,7 @@ static inlined_cachefunc bool ioc_exists(void)
 	return false;
 }
 
-static inlined_cachefunc bool ioc_enabled(void)
+static inline bool ioc_enabled(void)
 {
 	/*
 	 * We check only CONFIG option instead of IOC HW state check as IOC
@@ -377,7 +275,7 @@ static inlined_cachefunc void __slc_entire_op(const int op)
 {
 	unsigned int ctrl;
 
-	if (!slc_enabled())
+	if (!slc_exists())
 		return;
 
 	ctrl = read_aux_reg(ARC_AUX_SLC_CTRL);
@@ -426,7 +324,7 @@ static void __slc_rgn_op(unsigned long paddr, unsigned long sz, const int op)
 	unsigned int ctrl;
 	unsigned long end;
 
-	if (!slc_enabled())
+	if (!slc_exists())
 		return;
 
 	/*
@@ -484,9 +382,6 @@ static void arc_ioc_setup(void)
 	if (!slc_exists())
 		panic("Try to enable IOC but SLC is not present");
 
-	if (!slc_enabled())
-		panic("Try to enable IOC but SLC is disabled");
-
 	/* Unsupported configuration. See [ NOTE 2 ] for more details. */
 	if (!dcache_enabled())
 		panic("Try to enable IOC but L1 D$ is disabled");
@@ -622,6 +517,8 @@ void invalidate_icache_all(void)
 	/*
 	 * If SL$ is bypassed for data it is used only for instructions,
 	 * so we need to invalidate it too.
+	 * TODO: HS 3.0 supports SLC disable so we need to check slc
+	 * enable/disable status here.
 	 */
 	if (is_isa_arcv2() && slc_data_bypass())
 		__slc_entire_op(OP_INV);
@@ -821,16 +718,3 @@ void sync_n_cleanup_cache_all(void)
 
 	__ic_entire_invalidate();
 }
-
-static ulong get_sp(void)
-{
-	ulong ret;
-
-	asm("mov %0, sp" : "=r"(ret) : );
-	return ret;
-}
-
-void arch_lmb_reserve(struct lmb *lmb)
-{
-	arch_lmb_reserve_generic(lmb, get_sp(), gd->ram_top, 4096);
-}

arch/arc/lib/cpu.c

@@ -4,14 +4,10 @@
  */
 
 #include <common.h>
-#include <clock_legacy.h>
-#include <init.h>
 #include <malloc.h>
 #include <vsprintf.h>
 #include <asm/arcregs.h>
 #include <asm/cache.h>
-#include <asm/global_data.h>
-#include <linux/bitops.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -19,7 +15,7 @@ int arch_cpu_init(void)
 {
 	timer_init();
 
-	gd->cpu_clk = get_board_sys_clk();
+	gd->cpu_clk = CONFIG_SYS_CLK_FREQ;
 	gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
 
 	cache_init();
@@ -27,6 +23,13 @@ int arch_cpu_init(void)
 	return 0;
 }
 
+int arch_early_init_r(void)
+{
+	gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE;
+	gd->bd->bi_memsize = CONFIG_SYS_SDRAM_SIZE;
+	return 0;
+}
+
 /* This is a dummy function on arc */
 int dram_init(void)
 {

arch/arc/lib/init_helpers.c

@@ -3,7 +3,6 @@
  * Copyright (C) 2013-2015 Synopsys, Inc. All rights reserved.
  */
 
-#include <init.h>
 #include <asm/cache.h>
 #include <common.h>
 

arch/arc/lib/libgcc2.h

@@ -35,7 +35,7 @@ typedef		 int HItype	__attribute__ ((mode (HI)));
 typedef unsigned int UHItype	__attribute__ ((mode (HI)));
 #if MIN_UNITS_PER_WORD > 1
 /* These typedefs are usually forbidden on dsp's with UNITS_PER_WORD 1.  */
-typedef		 int SItype	__attribute__ ((mode (SI)));
+typedef 	 int SItype	__attribute__ ((mode (SI)));
 typedef unsigned int USItype	__attribute__ ((mode (SI)));
 #if __SIZEOF_LONG_LONG__ > 4
 /* These typedefs are usually forbidden on archs with UNITS_PER_WORD 2.  */

arch/arc/lib/relocate.c

@@ -5,9 +5,7 @@
 
 #include <common.h>
 #include <elf.h>
-#include <log.h>
 #include <asm-generic/sections.h>
-#include <asm/global_data.h>
 
 extern ulong __image_copy_start;
 extern ulong __ivt_start;

arch/arc/lib/reset.c

@@ -5,19 +5,18 @@
 
 #include <command.h>
 #include <common.h>
-#include <cpu_func.h>
 
-__weak void reset_cpu(void)
+__weak void reset_cpu(ulong addr)
 {
 	/* Stop debug session here */
 	__builtin_arc_brk();
 }
 
-int do_reset(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
+int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
 {
 	printf("Resetting the board...\n");
 
-	reset_cpu();
+	reset_cpu(0);
 
 	return 0;
 }

arch/arc/lib/start.S

@@ -7,7 +7,6 @@
 #include <config.h>
 #include <linux/linkage.h>
 #include <asm/arcregs.h>
-#include <system-constants.h>
 
 ENTRY(_start)
 	/* Setup interrupt vector base that matches "__text_start" */
@@ -62,21 +61,6 @@ ENTRY(_start)
 1:
 #endif
 
-#ifdef CONFIG_ISA_ARCV2
-	; In case of DSP extension presence in HW some instructions
-	; (related to integer multiply, multiply-accumulate, and divide
-	; operation) executes on this DSP execution unit. So their
-	; execution will depend on dsp configuration register (DSP_CTRL)
-	; As we want these instructions to execute the same way regardless
-	; of DSP presence we need to set DSP_CTRL properly.
-	lr	r5, [ARC_AUX_DSP_BUILD]
-	bmsk	r5, r5, 7
-	breq    r5, 0, 1f
-	mov	r5, 0
-	sr	r5, [ARC_AUX_DSP_CTRL]
-1:
-#endif
-
 #ifdef __ARC_UNALIGNED__
 	/*
 	 * Enable handling of unaligned access in the CPU as by default
@@ -87,7 +71,7 @@ ENTRY(_start)
 #endif
 
 	/* Establish C runtime stack and frame */
-	mov	%sp, SYS_INIT_SP_ADDR
+	mov	%sp, CONFIG_SYS_INIT_SP_ADDR
 	mov	%fp, %sp
 
 	/* Allocate reserved area from current top of stack */

arch/arm/Makefile

@@ -1,6 +1,6 @@
 # SPDX-License-Identifier: GPL-2.0+
 
-ifeq ($(CONFIG_SPL_BUILD)$(CONFIG_ARCH_TEGRA),yy)
+ifeq ($(CONFIG_SPL_BUILD)$(CONFIG_TEGRA),yy)
 CONFIG_CPU_V7A=
 CONFIG_CPU_ARM720T=y
 endif
@@ -10,21 +10,19 @@ arch-$(CONFIG_CPU_ARM720T)	=-march=armv4
 arch-$(CONFIG_CPU_ARM920T)	=-march=armv4t
 arch-$(CONFIG_CPU_ARM926EJS)	=-march=armv5te
 arch-$(CONFIG_CPU_ARM946ES)	=-march=armv5te
+arch-$(CONFIG_CPU_SA1100)	=-march=armv4
+arch-$(CONFIG_CPU_PXA)		=
 arch-$(CONFIG_CPU_ARM1136)	=-march=armv5t
 arch-$(CONFIG_CPU_ARM1176)	=-march=armv5t
 arch-$(CONFIG_CPU_V7A)		=$(call cc-option, -march=armv7-a, \
 				 $(call cc-option, -march=armv7))
 arch-$(CONFIG_CPU_V7M)		=-march=armv7-m
 arch-$(CONFIG_CPU_V7R)		=-march=armv7-r
-ifeq ($(CONFIG_ARM64_CRC32),y)
-arch-$(CONFIG_ARM64)		=-march=armv8-a+crc
-else
 arch-$(CONFIG_ARM64)		=-march=armv8-a
-endif
 
 # On Tegra systems we must build SPL for the armv4 core on the device
 # but otherwise we can use the value in CONFIG_SYS_ARM_ARCH
-ifeq ($(CONFIG_SPL_BUILD)$(CONFIG_ARCH_TEGRA),yy)
+ifeq ($(CONFIG_SPL_BUILD)$(CONFIG_TEGRA),yy)
 arch-y += -D__LINUX_ARM_ARCH__=4
 else
 arch-y += -D__LINUX_ARM_ARCH__=$(CONFIG_SYS_ARM_ARCH)
@@ -38,6 +36,8 @@ tune-$(CONFIG_CPU_ARM720T)	=-mtune=arm7tdmi
 tune-$(CONFIG_CPU_ARM920T)	=
 tune-$(CONFIG_CPU_ARM926EJS)	=
 tune-$(CONFIG_CPU_ARM946ES)	=
+tune-$(CONFIG_CPU_SA1100)	=-mtune=strongarm1100
+tune-$(CONFIG_CPU_PXA)		=-mcpu=xscale
 tune-$(CONFIG_CPU_ARM1136)	=
 tune-$(CONFIG_CPU_ARM1176)	=
 tune-$(CONFIG_CPU_V7A)		=-mtune=generic-armv7-a
@@ -51,49 +51,40 @@ PLATFORM_CPPFLAGS += $(arch-y) $(tune-y)
 
 # Machine directory name.  This list is sorted alphanumerically
 # by CONFIG_* macro name.
-machine-$(CONFIG_ARCH_APPLE)		+= apple
 machine-$(CONFIG_ARCH_ASPEED)		+= aspeed
 machine-$(CONFIG_ARCH_AT91)		+= at91
 machine-$(CONFIG_ARCH_BCM283X)		+= bcm283x
-machine-$(CONFIG_ARCH_BCMBCA)		+= bcmbca
 machine-$(CONFIG_ARCH_BCMSTB)		+= bcmstb
 machine-$(CONFIG_ARCH_DAVINCI)		+= davinci
 machine-$(CONFIG_ARCH_EXYNOS)		+= exynos
-machine-$(CONFIG_ARCH_GXP)		+= hpe
 machine-$(CONFIG_ARCH_HIGHBANK)		+= highbank
-machine-$(CONFIG_ARCH_IPQ40XX)		+= ipq40xx
 machine-$(CONFIG_ARCH_K3)		+= k3
 machine-$(CONFIG_ARCH_KEYSTONE)		+= keystone
-machine-$(CONFIG_ARCH_KIRKWOOD)		+= kirkwood
-machine-$(CONFIG_ARCH_LPC32XX)		+= lpc32xx
+# TODO: rename CONFIG_KIRKWOOD -> CONFIG_ARCH_KIRKWOOD
+machine-$(CONFIG_KIRKWOOD)		+= kirkwood
 machine-$(CONFIG_ARCH_MEDIATEK)		+= mediatek
 machine-$(CONFIG_ARCH_MESON)		+= meson
 machine-$(CONFIG_ARCH_MVEBU)		+= mvebu
-machine-$(CONFIG_ARCH_NEXELL)		+= nexell
-machine-$(CONFIG_ARCH_NPCM)             += npcm
+# TODO: rename CONFIG_TEGRA -> CONFIG_ARCH_TEGRA
+# TODO: rename CONFIG_ORION5X -> CONFIG_ARCH_ORION5X
+machine-$(CONFIG_ORION5X)		+= orion5x
 machine-$(CONFIG_ARCH_OMAP2PLUS)	+= omap2
-machine-$(CONFIG_ARCH_ORION5X)		+= orion5x
 machine-$(CONFIG_ARCH_OWL)		+= owl
-machine-$(CONFIG_ARCH_RMOBILE)		+= rmobile
-machine-$(CONFIG_ARCH_ROCKCHIP)		+= rockchip
 machine-$(CONFIG_ARCH_S5PC1XX)		+= s5pc1xx
+machine-$(CONFIG_ARCH_SUNXI)		+= sunxi
 machine-$(CONFIG_ARCH_SNAPDRAGON)	+= snapdragon
 machine-$(CONFIG_ARCH_SOCFPGA)		+= socfpga
-machine-$(CONFIG_ARCH_STM32)		+= stm32
+machine-$(CONFIG_ARCH_RMOBILE)		+= rmobile
+machine-$(CONFIG_ARCH_ROCKCHIP)		+= rockchip
+machine-$(CONFIG_STM32)			+= stm32
 machine-$(CONFIG_ARCH_STM32MP)		+= stm32mp
-machine-$(CONFIG_ARCH_SUNXI)		+= sunxi
-machine-$(CONFIG_ARCH_TEGRA)		+= tegra
-machine-$(CONFIG_ARCH_U8500)		+= u8500
-machine-$(CONFIG_ARCH_OCTEONTX)		+= octeontx
-machine-$(CONFIG_ARCH_OCTEONTX2)	+= octeontx2
+machine-$(CONFIG_TEGRA)			+= tegra
 machine-$(CONFIG_ARCH_UNIPHIER)		+= uniphier
-machine-$(CONFIG_ARCH_VERSAL)		+= versal
 machine-$(CONFIG_ARCH_ZYNQ)		+= zynq
 machine-$(CONFIG_ARCH_ZYNQMP)		+= zynqmp
+machine-$(CONFIG_ARCH_VERSAL)		+= versal
 machine-$(CONFIG_ARCH_ZYNQMP_R5)	+= zynqmp-r5
 
-machine-$(CONFIG_MACH_IMX)		+= imx
-
 machdirs := $(patsubst %,arch/arm/mach-%/,$(machine-y))
 
 PLATFORM_CPPFLAGS += $(patsubst %,-I$(srctree)/%include,$(machdirs))
@@ -103,8 +94,8 @@ libs-y += $(machdirs)
 head-y := arch/arm/cpu/$(CPU)/start.o
 
 ifeq ($(CONFIG_SPL_BUILD),y)
-ifeq ($(CONFIG_SYS_SOC)$(CONFIG_SPL_FRAMEWORK),"mxs")
-head-y := arch/arm/cpu/arm926ejs/mxs/start.o
+ifneq ($(CONFIG_SPL_START_S_PATH),)
+head-y := $(CONFIG_SPL_START_S_PATH:"%"=%)/start.o
 endif
 endif
 
@@ -112,6 +103,16 @@ libs-y += arch/arm/cpu/$(CPU)/
 libs-y += arch/arm/cpu/
 libs-y += arch/arm/lib/
 
+ifeq ($(CONFIG_SPL_BUILD),y)
+ifneq (,$(CONFIG_MX23)$(CONFIG_MX28)$(CONFIG_MX35)$(filter $(SOC), mx25 mx5 mx6 mx7 mx35 imx8m imx8))
+libs-y += arch/arm/mach-imx/
+endif
+else
+ifneq (,$(filter $(SOC), mx25 mx27 mx5 mx6 mx7 mx7ulp mx31 mx35 mxs imx8m imx8 vf610))
+libs-y += arch/arm/mach-imx/
+endif
+endif
+
 ifneq (,$(filter $(SOC), kirkwood))
 libs-y += arch/arm/mach-mvebu/
 endif

arch/arm/config.mk

@@ -11,21 +11,13 @@ CONFIG_STANDALONE_LOAD_ADDR = 0xc100000
 endif
 endif
 
-CFLAGS_NON_EFI := -fno-pic -ffixed-r9 -ffunction-sections -fdata-sections \
-		  -fstack-protector-strong
+CFLAGS_NON_EFI := -fno-pic -ffixed-r9 -ffunction-sections -fdata-sections
 CFLAGS_EFI := -fpic -fshort-wchar
 
-ifneq ($(CONFIG_LTO)$(CONFIG_USE_PRIVATE_LIBGCC),yy)
 LDFLAGS_FINAL += --gc-sections
-endif
-
-ifndef CONFIG_LTO
-PLATFORM_RELFLAGS += -ffunction-sections -fdata-sections
-endif
-
-PLATFORM_RELFLAGS += -fno-common -ffixed-r9
+PLATFORM_RELFLAGS += -ffunction-sections -fdata-sections \
+		     -fno-common -ffixed-r9
 PLATFORM_RELFLAGS += $(call cc-option, -msoft-float) \
-		     $(call cc-option,-mgeneral-regs-only) \
       $(call cc-option,-mshort-load-bytes,$(call cc-option,-malignment-traps,))
 
 # LLVM support
@@ -130,7 +122,7 @@ endif
 
 ifneq ($(CONFIG_SPL_BUILD),y)
 # Check that only R_ARM_RELATIVE relocations are generated.
-INPUTS-y += checkarmreloc
+ALL-y += checkarmreloc
 # The movt / movw can hardcode 16 bit parts of the addresses in the
 # instruction. Relocation is not supported for that case, so disable
 # such usage by requiring word relocations.
@@ -141,11 +133,11 @@ endif
 # limit ourselves to the sections we want in the .bin.
 ifdef CONFIG_ARM64
 OBJCOPYFLAGS += -j .text -j .secure_text -j .secure_data -j .rodata -j .data \
-		-j __u_boot_list -j .rela.dyn -j .got -j .got.plt \
+		-j .u_boot_list -j .rela.dyn -j .got -j .got.plt \
 		-j .binman_sym_table -j .text_rest
 else
 OBJCOPYFLAGS += -j .text -j .secure_text -j .secure_data -j .rodata -j .hash \
-		-j .data -j .got -j .got.plt -j __u_boot_list -j .rel.dyn \
+		-j .data -j .got -j .got.plt -j .u_boot_list -j .rel.dyn \
 		-j .binman_sym_table -j .text_rest
 endif
 
@@ -159,22 +151,20 @@ ifdef CONFIG_EFI_LOADER
 OBJCOPYFLAGS += -j .efi_runtime -j .efi_runtime_rel
 endif
 
-ifdef CONFIG_MACH_IMX
-ifneq ($(CONFIG_IMX_CONFIG),"")
+ifneq ($(CONFIG_IMX_CONFIG),)
 ifdef CONFIG_SPL
 ifndef CONFIG_SPL_BUILD
-INPUTS-y += SPL
+ALL-y += SPL
 endif
 else
 ifeq ($(CONFIG_OF_SEPARATE),y)
-INPUTS-y += u-boot-dtb.imx
+ALL-y += u-boot-dtb.imx
 else
-INPUTS-y += u-boot.imx
+ALL-y += u-boot.imx
 endif
 endif
 ifneq ($(CONFIG_VF610),)
-INPUTS-y += u-boot.vyb
-endif
+ALL-y += u-boot.vyb
 endif
 endif
 

arch/arm/cpu/arm11/cpu.c

@@ -18,7 +18,6 @@
 #include <command.h>
 #include <cpu_func.h>
 #include <irq_func.h>
-#include <asm/cache.h>
 #include <asm/system.h>
 
 static void cache_flush(void);

arch/arm/cpu/arm1136/Makefile

@@ -7,3 +7,4 @@ extra-y	= start.o
 
 obj-y += ../arm11/
 obj-$(CONFIG_MX31) += mx31/
+obj-$(CONFIG_MX35) += mx35/

arch/arm/cpu/arm1136/mx31/generic.c

@@ -6,7 +6,6 @@
 
 #include <common.h>
 #include <div64.h>
-#include <init.h>
 #include <asm/arch/imx-regs.h>
 #include <asm/arch/clock.h>
 #include <asm/io.h>

arch/arm/cpu/arm1136/mx31/timer.c

@@ -5,7 +5,6 @@
  */
 
 #include <common.h>
-#include <init.h>
 #include <asm/arch/imx-regs.h>
 #include <asm/io.h>
 

arch/arm/cpu/arm1136/mx35/Makefile

@@ -0,0 +1,11 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# (C) Copyright 2008-2009 Freescale Semiconductor, Inc.
+
+obj-y	+= generic.o
+obj-y	+= timer.o
+obj-y	+= mx35_sdram.o
+obj-y	+= relocate.o

arch/arm/cpu/arm1136/mx35/generic.c

@@ -0,0 +1,525 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2007
+ * Sascha Hauer, Pengutronix
+ *
+ * (C) Copyright 2008-2010 Freescale Semiconductor, Inc.
+ */
+
+#include <common.h>
+#include <div64.h>
+#include <asm/io.h>
+#include <linux/errno.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/crm_regs.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/sys_proto.h>
+#ifdef CONFIG_FSL_ESDHC_IMX
+#include <fsl_esdhc_imx.h>
+#endif
+#include <netdev.h>
+#include <spl.h>
+
+#define CLK_CODE(arm, ahb, sel) (((arm) << 16) + ((ahb) << 8) + (sel))
+#define CLK_CODE_ARM(c)		(((c) >> 16) & 0xFF)
+#define CLK_CODE_AHB(c)		(((c) >>  8) & 0xFF)
+#define CLK_CODE_PATH(c)	((c) & 0xFF)
+
+#define CCM_GET_DIVIDER(x, m, o) (((x) & (m)) >> (o))
+
+#ifdef CONFIG_FSL_ESDHC_IMX
+DECLARE_GLOBAL_DATA_PTR;
+#endif
+
+static int g_clk_mux_auto[8] = {
+	CLK_CODE(1, 3, 0), CLK_CODE(1, 2, 1), CLK_CODE(2, 1, 1), -1,
+	CLK_CODE(1, 6, 0), CLK_CODE(1, 4, 1), CLK_CODE(2, 2, 1), -1,
+};
+
+static int g_clk_mux_consumer[16] = {
+	CLK_CODE(1, 4, 0), CLK_CODE(1, 3, 1), CLK_CODE(1, 3, 1), -1,
+	-1, -1, CLK_CODE(4, 1, 0), CLK_CODE(1, 5, 0),
+	CLK_CODE(1, 8, 1), CLK_CODE(1, 6, 1), CLK_CODE(2, 4, 0), -1,
+	-1, -1, CLK_CODE(4, 2, 0), -1,
+};
+
+static int hsp_div_table[3][16] = {
+	{4, 3, 2, -1, -1, -1, 1, 5, 4, 3, 2, -1, -1, -1, 1, -1},
+	{-1, -1, -1, -1, -1, -1, -1, -1, 8, 6, 4, -1, -1, -1, 2, -1},
+	{3, -1, -1, -1, -1, -1, -1, -1, 3, -1, -1, -1, -1, -1, -1, -1},
+};
+
+u32 get_cpu_rev(void)
+{
+	int reg;
+	struct iim_regs *iim =
+		(struct iim_regs *)IIM_BASE_ADDR;
+	reg = readl(&iim->iim_srev);
+	if (!reg) {
+		reg = readw(ROMPATCH_REV);
+		reg <<= 4;
+	} else {
+		reg += CHIP_REV_1_0;
+	}
+
+	return 0x35000 + (reg & 0xFF);
+}
+
+static u32 get_arm_div(u32 pdr0, u32 *fi, u32 *fd)
+{
+	int *pclk_mux;
+	if (pdr0 & MXC_CCM_PDR0_AUTO_CON) {
+		pclk_mux = g_clk_mux_consumer +
+			((pdr0 & MXC_CCM_PDR0_CON_MUX_DIV_MASK) >>
+			MXC_CCM_PDR0_CON_MUX_DIV_OFFSET);
+	} else {
+		pclk_mux = g_clk_mux_auto +
+			((pdr0 & MXC_CCM_PDR0_AUTO_MUX_DIV_MASK) >>
+			MXC_CCM_PDR0_AUTO_MUX_DIV_OFFSET);
+	}
+
+	if ((*pclk_mux) == -1)
+		return -1;
+
+	if (fi && fd) {
+		if (!CLK_CODE_PATH(*pclk_mux)) {
+			*fi = *fd = 1;
+			return CLK_CODE_ARM(*pclk_mux);
+		}
+		if (pdr0 & MXC_CCM_PDR0_AUTO_CON) {
+			*fi = 3;
+			*fd = 4;
+		} else {
+			*fi = 2;
+			*fd = 3;
+		}
+	}
+	return CLK_CODE_ARM(*pclk_mux);
+}
+
+static int get_ahb_div(u32 pdr0)
+{
+	int *pclk_mux;
+
+	pclk_mux = g_clk_mux_consumer +
+		((pdr0 & MXC_CCM_PDR0_CON_MUX_DIV_MASK) >>
+		MXC_CCM_PDR0_CON_MUX_DIV_OFFSET);
+
+	if ((*pclk_mux) == -1)
+		return -1;
+
+	return CLK_CODE_AHB(*pclk_mux);
+}
+
+static u32 decode_pll(u32 reg, u32 infreq)
+{
+	u32 mfi = (reg >> 10) & 0xf;
+	s32 mfn = reg & 0x3ff;
+	u32 mfd = (reg >> 16) & 0x3ff;
+	u32 pd = (reg >> 26) & 0xf;
+
+	mfi = mfi <= 5 ? 5 : mfi;
+	mfn = mfn >= 512 ? mfn - 1024 : mfn;
+	mfd += 1;
+	pd += 1;
+
+	return lldiv(2 * (u64)infreq * (mfi * mfd + mfn),
+		mfd * pd);
+}
+
+static u32 get_mcu_main_clk(void)
+{
+	u32 arm_div = 0, fi = 0, fd = 0;
+	struct ccm_regs *ccm =
+		(struct ccm_regs *)IMX_CCM_BASE;
+	arm_div = get_arm_div(readl(&ccm->pdr0), &fi, &fd);
+	fi *= decode_pll(readl(&ccm->mpctl), MXC_HCLK);
+	return fi / (arm_div * fd);
+}
+
+static u32 get_ipg_clk(void)
+{
+	u32 freq = get_mcu_main_clk();
+	struct ccm_regs *ccm =
+		(struct ccm_regs *)IMX_CCM_BASE;
+	u32 pdr0 = readl(&ccm->pdr0);
+
+	return freq / (get_ahb_div(pdr0) * 2);
+}
+
+static u32 get_ipg_per_clk(void)
+{
+	u32 freq = get_mcu_main_clk();
+	struct ccm_regs *ccm =
+		(struct ccm_regs *)IMX_CCM_BASE;
+	u32 pdr0 = readl(&ccm->pdr0);
+	u32 pdr4 = readl(&ccm->pdr4);
+	u32 div;
+	if (pdr0 & MXC_CCM_PDR0_PER_SEL) {
+		div = CCM_GET_DIVIDER(pdr4,
+			MXC_CCM_PDR4_PER0_PODF_MASK,
+			MXC_CCM_PDR4_PER0_PODF_OFFSET) + 1;
+	} else {
+		div = CCM_GET_DIVIDER(pdr0,
+			MXC_CCM_PDR0_PER_PODF_MASK,
+			MXC_CCM_PDR0_PER_PODF_OFFSET) + 1;
+		div *= get_ahb_div(pdr0);
+	}
+	return freq / div;
+}
+
+u32 imx_get_uartclk(void)
+{
+	u32 freq;
+	struct ccm_regs *ccm =
+		(struct ccm_regs *)IMX_CCM_BASE;
+	u32 pdr4 = readl(&ccm->pdr4);
+
+	if (readl(&ccm->pdr3) & MXC_CCM_PDR3_UART_M_U)
+		freq = get_mcu_main_clk();
+	else
+		freq = decode_pll(readl(&ccm->ppctl), MXC_HCLK);
+	freq /= CCM_GET_DIVIDER(pdr4,
+			MXC_CCM_PDR4_UART_PODF_MASK,
+			MXC_CCM_PDR4_UART_PODF_OFFSET) + 1;
+	return freq;
+}
+
+unsigned int mxc_get_main_clock(enum mxc_main_clock clk)
+{
+	u32 nfc_pdf, hsp_podf;
+	u32 pll, ret_val = 0, usb_podf;
+	struct ccm_regs *ccm =
+		(struct ccm_regs *)IMX_CCM_BASE;
+
+	u32 reg = readl(&ccm->pdr0);
+	u32 reg4 = readl(&ccm->pdr4);
+
+	reg |= 0x1;
+
+	switch (clk) {
+	case CPU_CLK:
+		ret_val = get_mcu_main_clk();
+		break;
+	case AHB_CLK:
+		ret_val = get_mcu_main_clk();
+		break;
+	case HSP_CLK:
+		if (reg & CLKMODE_CONSUMER) {
+			hsp_podf = (reg >> 20) & 0x3;
+			pll = get_mcu_main_clk();
+			hsp_podf = hsp_div_table[hsp_podf][(reg>>16)&0xF];
+			if (hsp_podf > 0) {
+				ret_val = pll / hsp_podf;
+			} else {
+				puts("mismatch HSP with ARM clock setting\n");
+				ret_val = 0;
+			}
+		} else {
+			ret_val = get_mcu_main_clk();
+		}
+		break;
+	case IPG_CLK:
+		ret_val = get_ipg_clk();
+		break;
+	case IPG_PER_CLK:
+		ret_val = get_ipg_per_clk();
+		break;
+	case NFC_CLK:
+		nfc_pdf = (reg4 >> 28) & 0xF;
+		pll = get_mcu_main_clk();
+		/* AHB/nfc_pdf */
+		ret_val = pll / (nfc_pdf + 1);
+		break;
+	case USB_CLK:
+		usb_podf = (reg4 >> 22) & 0x3F;
+		if (reg4 & 0x200)
+			pll = get_mcu_main_clk();
+		else
+			pll = decode_pll(readl(&ccm->ppctl), MXC_HCLK);
+
+		ret_val = pll / (usb_podf + 1);
+		break;
+	default:
+		printf("Unknown clock: %d\n", clk);
+		break;
+	}
+
+	return ret_val;
+}
+unsigned int mxc_get_peri_clock(enum mxc_peri_clock clk)
+{
+	u32 ret_val = 0, pdf, pre_pdf, clk_sel;
+	struct ccm_regs *ccm =
+		(struct ccm_regs *)IMX_CCM_BASE;
+	u32 mpdr2 = readl(&ccm->pdr2);
+	u32 mpdr3 = readl(&ccm->pdr3);
+	u32 mpdr4 = readl(&ccm->pdr4);
+
+	switch (clk) {
+	case UART1_BAUD:
+	case UART2_BAUD:
+	case UART3_BAUD:
+		clk_sel = mpdr3 & (1 << 14);
+		pdf = (mpdr4 >> 10) & 0x3F;
+		ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) :
+			decode_pll(readl(&ccm->ppctl), MXC_HCLK)) / (pdf + 1);
+		break;
+	case SSI1_BAUD:
+		pre_pdf = (mpdr2 >> 24) & 0x7;
+		pdf = mpdr2 & 0x3F;
+		clk_sel = mpdr2 & (1 << 6);
+		ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) :
+			decode_pll(readl(&ccm->ppctl), MXC_HCLK)) /
+				((pre_pdf + 1) * (pdf + 1));
+		break;
+	case SSI2_BAUD:
+		pre_pdf = (mpdr2 >> 27) & 0x7;
+		pdf = (mpdr2 >> 8) & 0x3F;
+		clk_sel = mpdr2 & (1 << 6);
+		ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) :
+			decode_pll(readl(&ccm->ppctl), MXC_HCLK)) /
+				((pre_pdf + 1) * (pdf + 1));
+		break;
+	case CSI_BAUD:
+		clk_sel = mpdr2 & (1 << 7);
+		pdf = (mpdr2 >> 16) & 0x3F;
+		ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) :
+			decode_pll(readl(&ccm->ppctl), MXC_HCLK)) / (pdf + 1);
+		break;
+	case MSHC_CLK:
+		pre_pdf = readl(&ccm->pdr1);
+		clk_sel = (pre_pdf & 0x80);
+		pdf = (pre_pdf >> 22) & 0x3F;
+		pre_pdf = (pre_pdf >> 28) & 0x7;
+		ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) :
+			decode_pll(readl(&ccm->ppctl), MXC_HCLK)) /
+				((pre_pdf + 1) * (pdf + 1));
+		break;
+	case ESDHC1_CLK:
+		clk_sel = mpdr3 & 0x40;
+		pdf = mpdr3 & 0x3F;
+		ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) :
+			decode_pll(readl(&ccm->ppctl), MXC_HCLK)) / (pdf + 1);
+		break;
+	case ESDHC2_CLK:
+		clk_sel = mpdr3 & 0x40;
+		pdf = (mpdr3 >> 8) & 0x3F;
+		ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) :
+			decode_pll(readl(&ccm->ppctl), MXC_HCLK)) / (pdf + 1);
+		break;
+	case ESDHC3_CLK:
+		clk_sel = mpdr3 & 0x40;
+		pdf = (mpdr3 >> 16) & 0x3F;
+		ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) :
+			decode_pll(readl(&ccm->ppctl), MXC_HCLK)) / (pdf + 1);
+		break;
+	case SPDIF_CLK:
+		clk_sel = mpdr3 & 0x400000;
+		pre_pdf = (mpdr3 >> 29) & 0x7;
+		pdf = (mpdr3 >> 23) & 0x3F;
+		ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) :
+			decode_pll(readl(&ccm->ppctl), MXC_HCLK)) /
+				((pre_pdf + 1) * (pdf + 1));
+		break;
+	default:
+		printf("%s(): This clock: %d not supported yet\n",
+				__func__, clk);
+		break;
+	}
+
+	return ret_val;
+}
+
+unsigned int mxc_get_clock(enum mxc_clock clk)
+{
+	switch (clk) {
+	case MXC_ARM_CLK:
+		return get_mcu_main_clk();
+	case MXC_AHB_CLK:
+		break;
+	case MXC_IPG_CLK:
+		return get_ipg_clk();
+	case MXC_IPG_PERCLK:
+	case MXC_I2C_CLK:
+		return get_ipg_per_clk();
+	case MXC_UART_CLK:
+		return imx_get_uartclk();
+	case MXC_ESDHC1_CLK:
+		return mxc_get_peri_clock(ESDHC1_CLK);
+	case MXC_ESDHC2_CLK:
+		return mxc_get_peri_clock(ESDHC2_CLK);
+	case MXC_ESDHC3_CLK:
+		return mxc_get_peri_clock(ESDHC3_CLK);
+	case MXC_USB_CLK:
+		return mxc_get_main_clock(USB_CLK);
+	case MXC_FEC_CLK:
+		return get_ipg_clk();
+	case MXC_CSPI_CLK:
+		return get_ipg_clk();
+	}
+	return -1;
+}
+
+#ifdef CONFIG_FEC_MXC
+/*
+ * The MX35 has no fuse for MAC, return a NULL MAC
+ */
+void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
+{
+	memset(mac, 0, 6);
+}
+
+u32 imx_get_fecclk(void)
+{
+	return mxc_get_clock(MXC_IPG_CLK);
+}
+#endif
+
+int do_mx35_showclocks(cmd_tbl_t *cmdtp,
+	int flag, int argc, char * const argv[])
+{
+	u32 cpufreq = get_mcu_main_clk();
+	printf("mx35 cpu clock: %dMHz\n", cpufreq / 1000000);
+	printf("ipg clock     : %dHz\n", get_ipg_clk());
+	printf("ipg per clock : %dHz\n", get_ipg_per_clk());
+	printf("uart clock    : %dHz\n", mxc_get_clock(MXC_UART_CLK));
+
+	return 0;
+}
+
+U_BOOT_CMD(
+	clocks,	CONFIG_SYS_MAXARGS, 1, do_mx35_showclocks,
+	"display clocks",
+	""
+);
+
+#if defined(CONFIG_DISPLAY_CPUINFO)
+static char *get_reset_cause(void)
+{
+	/* read RCSR register from CCM module */
+	struct ccm_regs *ccm =
+		(struct ccm_regs *)IMX_CCM_BASE;
+
+	u32 cause = readl(&ccm->rcsr) & 0x0F;
+
+	switch (cause) {
+	case 0x0000:
+		return "POR";
+	case 0x0002:
+		return "JTAG";
+	case 0x0004:
+		return "RST";
+	case 0x0008:
+		return "WDOG";
+	default:
+		return "unknown reset";
+	}
+}
+
+int print_cpuinfo(void)
+{
+	u32 srev = get_cpu_rev();
+
+	printf("CPU:   Freescale i.MX35 rev %d.%d at %d MHz.\n",
+		(srev & 0xF0) >> 4, (srev & 0x0F),
+		get_mcu_main_clk() / 1000000);
+
+	printf("Reset cause: %s\n", get_reset_cause());
+
+	return 0;
+}
+#endif
+
+/*
+ * Initializes on-chip ethernet controllers.
+ * to override, implement board_eth_init()
+ */
+int cpu_eth_init(bd_t *bis)
+{
+	int rc = -ENODEV;
+
+#if defined(CONFIG_FEC_MXC)
+	rc = fecmxc_initialize(bis);
+#endif
+
+	return rc;
+}
+
+#ifdef CONFIG_FSL_ESDHC_IMX
+/*
+ * Initializes on-chip MMC controllers.
+ * to override, implement board_mmc_init()
+ */
+int cpu_mmc_init(bd_t *bis)
+{
+	return fsl_esdhc_mmc_init(bis);
+}
+#endif
+
+int get_clocks(void)
+{
+#ifdef CONFIG_FSL_ESDHC_IMX
+#if CONFIG_SYS_FSL_ESDHC_ADDR == MMC_SDHC2_BASE_ADDR
+	gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
+#elif CONFIG_SYS_FSL_ESDHC_ADDR == MMC_SDHC3_BASE_ADDR
+	gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
+#else
+	gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC1_CLK);
+#endif
+#endif
+	return 0;
+}
+
+#define RCSR_MEM_CTL_WEIM	0
+#define RCSR_MEM_CTL_NAND	1
+#define RCSR_MEM_CTL_ATA	2
+#define RCSR_MEM_CTL_EXPANSION	3
+#define RCSR_MEM_TYPE_NOR	0
+#define RCSR_MEM_TYPE_ONENAND	2
+#define RCSR_MEM_TYPE_SD	0
+#define RCSR_MEM_TYPE_I2C	2
+#define RCSR_MEM_TYPE_SPI	3
+
+u32 spl_boot_device(void)
+{
+	struct ccm_regs *ccm =
+		(struct ccm_regs *)IMX_CCM_BASE;
+
+	u32 rcsr = readl(&ccm->rcsr);
+	u32 mem_type, mem_ctl;
+
+	/* In external mode, no boot device is returned */
+	if ((rcsr >> 10) & 0x03)
+		return BOOT_DEVICE_NONE;
+
+	mem_ctl = (rcsr >> 25) & 0x03;
+	mem_type = (rcsr >> 23) & 0x03;
+
+	switch (mem_ctl) {
+	case RCSR_MEM_CTL_WEIM:
+		switch (mem_type) {
+		case RCSR_MEM_TYPE_NOR:
+			return BOOT_DEVICE_NOR;
+		case RCSR_MEM_TYPE_ONENAND:
+			return BOOT_DEVICE_ONENAND;
+		default:
+			return BOOT_DEVICE_NONE;
+		}
+	case RCSR_MEM_CTL_NAND:
+		return BOOT_DEVICE_NAND;
+	case RCSR_MEM_CTL_EXPANSION:
+		switch (mem_type) {
+		case RCSR_MEM_TYPE_SD:
+			return BOOT_DEVICE_MMC1;
+		case RCSR_MEM_TYPE_I2C:
+			return BOOT_DEVICE_I2C;
+		case RCSR_MEM_TYPE_SPI:
+			return BOOT_DEVICE_SPI;
+		default:
+			return BOOT_DEVICE_NONE;
+		}
+	}
+
+	return BOOT_DEVICE_NONE;
+}

arch/arm/cpu/arm1136/mx35/mx35_sdram.c

@@ -0,0 +1,120 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2012, Stefano Babic <sbabic@denx.de>
+ */
+
+#include <asm/io.h>
+#include <linux/errno.h>
+#include <asm/arch/imx-regs.h>
+#include <linux/types.h>
+#include <asm/arch/sys_proto.h>
+
+#define ESDCTL_DDR2_EMR2	0x04000000
+#define ESDCTL_DDR2_EMR3	0x06000000
+#define ESDCTL_PRECHARGE	0x00000400
+#define ESDCTL_DDR2_EN_DLL	0x02000400
+#define ESDCTL_DDR2_RESET_DLL	0x00000333
+#define ESDCTL_DDR2_MR		0x00000233
+#define ESDCTL_DDR2_OCD_DEFAULT 0x02000780
+
+enum {
+	SMODE_NORMAL =	0,
+	SMODE_PRECHARGE,
+	SMODE_AUTO_REFRESH,
+	SMODE_LOAD_REG,
+	SMODE_MANUAL_REFRESH
+};
+
+#define set_mode(x, en, m)	(x | (en << 31) | (m << 28))
+
+static inline void dram_wait(unsigned int count)
+{
+	volatile unsigned int wait = count;
+
+	while (wait--)
+		;
+
+}
+
+void mx3_setup_sdram_bank(u32 start_address, u32 ddr2_config,
+	u32 row, u32 col, u32 dsize, u32 refresh)
+{
+	struct esdc_regs *esdc = (struct esdc_regs *)ESDCTL_BASE_ADDR;
+	u32 *cfg_reg, *ctl_reg;
+	u32 val;
+	u32 ctlval;
+
+	switch (start_address) {
+	case CSD0_BASE_ADDR:
+		cfg_reg = &esdc->esdcfg0;
+		ctl_reg = &esdc->esdctl0;
+		break;
+	case CSD1_BASE_ADDR:
+		cfg_reg = &esdc->esdcfg1;
+		ctl_reg = &esdc->esdctl1;
+		break;
+	default:
+		return;
+	}
+
+	/* The MX35 supports 11 up to 14 rows */
+	if (row < 11 || row > 14 || col < 8 || col > 10)
+		return;
+	ctlval = (row - 11) << 24 | (col - 8) << 20 | (dsize << 16);
+
+	/* Initialize MISC register for DDR2 */
+	val = ESDC_MISC_RST | ESDC_MISC_MDDR_EN | ESDC_MISC_MDDR_DL_RST |
+		ESDC_MISC_DDR_EN | ESDC_MISC_DDR2_EN;
+	writel(val, &esdc->esdmisc);
+	val &= ~(ESDC_MISC_RST | ESDC_MISC_MDDR_DL_RST);
+	writel(val, &esdc->esdmisc);
+
+	/*
+	 * according to DDR2 specs, wait a while before
+	 * the PRECHARGE_ALL command
+	 */
+	dram_wait(0x20000);
+
+	/* Load DDR2 config and timing */
+	writel(ddr2_config, cfg_reg);
+
+	/* Precharge ALL */
+	writel(set_mode(ctlval, 1, SMODE_PRECHARGE),
+		ctl_reg);
+	writel(0xda, start_address + ESDCTL_PRECHARGE);
+
+	/* Load mode */
+	writel(set_mode(ctlval, 1, SMODE_LOAD_REG),
+		ctl_reg);
+	writeb(0xda, start_address + ESDCTL_DDR2_EMR2); /* EMRS2 */
+	writeb(0xda, start_address + ESDCTL_DDR2_EMR3); /* EMRS3 */
+	writeb(0xda, start_address + ESDCTL_DDR2_EN_DLL); /* Enable DLL */
+	writeb(0xda, start_address + ESDCTL_DDR2_RESET_DLL); /* Reset DLL */
+
+	/* Precharge ALL */
+	writel(set_mode(ctlval, 1, SMODE_PRECHARGE),
+		ctl_reg);
+	writel(0xda, start_address + ESDCTL_PRECHARGE);
+
+	/* Set mode auto refresh : at least two refresh are required */
+	writel(set_mode(ctlval, 1, SMODE_AUTO_REFRESH),
+		ctl_reg);
+	writel(0xda, start_address);
+	writel(0xda, start_address);
+
+	writel(set_mode(ctlval, 1, SMODE_LOAD_REG),
+		ctl_reg);
+	writeb(0xda, start_address + ESDCTL_DDR2_MR);
+	writeb(0xda, start_address + ESDCTL_DDR2_OCD_DEFAULT);
+
+	/* OCD mode exit */
+	writeb(0xda, start_address + ESDCTL_DDR2_EN_DLL); /* Enable DLL */
+
+	/* Set normal mode */
+	writel(set_mode(ctlval, 1, SMODE_NORMAL) | refresh,
+		ctl_reg);
+
+	dram_wait(0x20000);
+
+	/* Do not set delay lines, only for MDDR */
+}

arch/arm/cpu/arm1136/mx35/relocate.S

@@ -0,0 +1,22 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ *  relocate - i.MX35-specific vector relocation
+ *
+ *  Copyright (c) 2013  Albert ARIBAUD <albert.u.boot@aribaud.net>
+ */
+
+#include <linux/linkage.h>
+
+/*
+ * The i.MX35 SoC is very specific with respect to exceptions: it
+ * does not provide RAM at the high vectors address (0xFFFF0000),
+ * thus only the low address (0x00000000) is useable; but that is
+ * in ROM, so let's avoid relocating the vectors.
+ */
+	.section	.text.relocate_vectors,"ax",%progbits
+
+ENTRY(relocate_vectors)
+
+	bx	lr
+
+ENDPROC(relocate_vectors)

arch/arm/cpu/arm1136/mx35/timer.c

@@ -0,0 +1,44 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2007
+ * Sascha Hauer, Pengutronix
+ *
+ * (C) Copyright 2008-2009 Freescale Semiconductor, Inc.
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/crm_regs.h>
+
+/* General purpose timers bitfields */
+#define GPTCR_SWR       (1<<15)	/* Software reset */
+#define GPTCR_FRR       (1<<9)	/* Freerun / restart */
+#define GPTCR_CLKSOURCE_32   (4<<6)	/* Clock source */
+#define GPTCR_TEN       (1)	/* Timer enable */
+
+/*
+ * nothing really to do with interrupts, just starts up a counter.
+ * The 32KHz 32-bit timer overruns in 134217 seconds
+ */
+int timer_init(void)
+{
+	int i;
+	struct gpt_regs *gpt = (struct gpt_regs *)GPT1_BASE_ADDR;
+	struct ccm_regs *ccm = (struct ccm_regs *)CCM_BASE_ADDR;
+
+	/* setup GP Timer 1 */
+	writel(GPTCR_SWR, &gpt->ctrl);
+
+	writel(readl(&ccm->cgr1) | 3 << MXC_CCM_CGR1_GPT_OFFSET, &ccm->cgr1);
+
+	for (i = 0; i < 100; i++)
+		writel(0, &gpt->ctrl); /* We have no udelay by now */
+	writel(0, &gpt->pre); /* prescaler = 1 */
+	/* Freerun Mode, 32KHz input */
+	writel(readl(&gpt->ctrl) | GPTCR_CLKSOURCE_32 | GPTCR_FRR,
+			&gpt->ctrl);
+	writel(readl(&gpt->ctrl) | GPTCR_TEN, &gpt->ctrl);
+
+	return 0;
+}

arch/arm/cpu/arm1136/start.S

@@ -39,7 +39,7 @@ reset:
 	msr	cpsr,r0
 
 	/* the mask ROM code should have PLL and others stable */
-#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT)
+#ifndef CONFIG_SKIP_LOWLEVEL_INIT
 	bl  cpu_init_crit
 #endif
 
@@ -62,7 +62,7 @@ c_runtime_cpu_setup:
  *
  *************************************************************************
  */
-#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT)
+#ifndef CONFIG_SKIP_LOWLEVEL_INIT
 cpu_init_crit:
 	/*
 	 * flush v4 I/D caches
@@ -81,7 +81,7 @@ cpu_init_crit:
 	orr	r0, r0, #0x00001000	@ set bit 12 (I) I-Cache
 	mcr	p15, 0, r0, c1, c0, 0
 
-#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT_ONLY)
+#ifndef CONFIG_SKIP_LOWLEVEL_INIT_ONLY
 	/*
 	 * Jump to board specific initialization... The Mask ROM will have already initialized
 	 * basic memory.  Go here to bump up clock rate and handle wake up conditions.
@@ -91,4 +91,4 @@ cpu_init_crit:
 	mov	lr, ip		/* restore link */
 #endif
 	mov	pc, lr		/* back to my caller */
-#endif /* !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) */
+#endif /* CONFIG_SKIP_LOWLEVEL_INIT */

arch/arm/cpu/arm720t/interrupts.c

@@ -11,7 +11,7 @@
 
 #include <common.h>
 
-#if defined(CONFIG_ARCH_TEGRA)
+#if defined(CONFIG_TEGRA)
 static ulong timestamp;
 static ulong lastdec;
 

arch/arm/cpu/arm720t/start.S

@@ -37,8 +37,8 @@ reset:
 	 * we do sys-critical inits only at reboot,
 	 * not when booting from ram!
 	 */
-#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) && \
-		!CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT_ONLY)
+#if !defined(CONFIG_SKIP_LOWLEVEL_INIT) && \
+		!defined(CONFIG_SKIP_LOWLEVEL_INIT_ONLY)
 	bl	cpu_init_crit
 #endif
 
@@ -62,8 +62,8 @@ c_runtime_cpu_setup:
  *************************************************************************
  */
 
-#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) && \
-		!CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT_ONLY)
+#if !defined(CONFIG_SKIP_LOWLEVEL_INIT) && \
+		!defined(CONFIG_SKIP_LOWLEVEL_INIT_ONLY)
 cpu_init_crit:
 
 	mov	ip, lr
@@ -76,4 +76,4 @@ cpu_init_crit:
 	mov	lr, ip
 
 	mov	pc, lr
-#endif /* CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) */
+#endif /* CONFIG_SKIP_LOWLEVEL_INIT */

arch/arm/cpu/arm920t/Makefile

@@ -7,6 +7,7 @@ extra-y	= start.o
 
 obj-y	+= cpu.o
 
+obj-$(CONFIG_EP93XX) += ep93xx/
 obj-$(CONFIG_IMX) += imx/
 
 # some files can only build in ARM mode

arch/arm/cpu/arm920t/ep93xx/Makefile

@@ -0,0 +1,19 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Cirrus Logic EP93xx CPU-specific Makefile
+#
+# Copyright (C) 2009 Matthias Kaehlcke <matthias@kaehlcke.net>
+#
+# Copyright (C) 2004, 2005
+# Cory T. Tusar, Videon Central, Inc., <ctusar@videon-central.com>
+#
+# Copyright (C) 2006
+# Dominic Rath <Dominic.Rath@gmx.de>
+#
+# Based on an original Makefile, which is
+#
+# (C) Copyright 2000, 2001, 2002
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+
+obj-y   = cpu.o led.o speed.o timer.o
+obj-y   += lowlevel_init.o

arch/arm/cpu/arm920t/ep93xx/cpu.c

@@ -0,0 +1,36 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Cirrus Logic EP93xx CPU-specific support.
+ *
+ * Copyright (C) 2009 Matthias Kaehlcke <matthias@kaehlcke.net>
+ *
+ * Copyright (C) 2004, 2005
+ * Cory T. Tusar, Videon Central, Inc., <ctusar@videon-central.com>
+ */
+
+#include <common.h>
+#include <asm/arch/ep93xx.h>
+#include <asm/io.h>
+
+/* We reset the CPU by generating a 1-->0 transition on DeviceCfg bit 31. */
+extern void reset_cpu(ulong addr)
+{
+	struct syscon_regs *syscon = (struct syscon_regs *)SYSCON_BASE;
+	uint32_t value;
+
+	/* Unlock DeviceCfg and set SWRST */
+	writel(0xAA, &syscon->sysswlock);
+	value = readl(&syscon->devicecfg);
+	value |= SYSCON_DEVICECFG_SWRST;
+	writel(value, &syscon->devicecfg);
+
+	/* Unlock DeviceCfg and clear SWRST */
+	writel(0xAA, &syscon->sysswlock);
+	value = readl(&syscon->devicecfg);
+	value &= ~SYSCON_DEVICECFG_SWRST;
+	writel(value, &syscon->devicecfg);
+
+	/* Dying... */
+	while (1)
+		; /* noop */
+}

arch/arm/cpu/arm920t/ep93xx/led.c

@@ -0,0 +1,85 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2010, 2009 Matthias Kaehlcke <matthias@kaehlcke.net>
+ */
+
+#include <asm/io.h>
+#include <asm/arch/ep93xx.h>
+#include <config.h>
+#include <status_led.h>
+
+static uint8_t saved_state[2] = {CONFIG_LED_STATUS_OFF, CONFIG_LED_STATUS_OFF};
+static uint32_t gpio_pin[2] = {1 << CONFIG_LED_STATUS_GREEN,
+			       1 << CONFIG_LED_STATUS_RED};
+
+static inline void switch_LED_on(uint8_t led)
+{
+	register struct gpio_regs *gpio = (struct gpio_regs *)GPIO_BASE;
+
+	writel(readl(&gpio->pedr) | gpio_pin[led], &gpio->pedr);
+	saved_state[led] = CONFIG_LED_STATUS_ON;
+}
+
+static inline void switch_LED_off(uint8_t led)
+{
+	register struct gpio_regs *gpio = (struct gpio_regs *)GPIO_BASE;
+
+	writel(readl(&gpio->pedr) & ~gpio_pin[led], &gpio->pedr);
+	saved_state[led] = CONFIG_LED_STATUS_OFF;
+}
+
+void red_led_on(void)
+{
+	switch_LED_on(CONFIG_LED_STATUS_RED);
+}
+
+void red_led_off(void)
+{
+	switch_LED_off(CONFIG_LED_STATUS_RED);
+}
+
+void green_led_on(void)
+{
+	switch_LED_on(CONFIG_LED_STATUS_GREEN);
+}
+
+void green_led_off(void)
+{
+	switch_LED_off(CONFIG_LED_STATUS_GREEN);
+}
+
+void __led_init(led_id_t mask, int state)
+{
+	__led_set(mask, state);
+}
+
+void __led_toggle(led_id_t mask)
+{
+	if (CONFIG_LED_STATUS_RED == mask) {
+		if (CONFIG_LED_STATUS_ON == saved_state[CONFIG_LED_STATUS_RED])
+			red_led_off();
+		else
+			red_led_on();
+	} else if (CONFIG_LED_STATUS_GREEN == mask) {
+		if (CONFIG_LED_STATUS_ON ==
+		    saved_state[CONFIG_LED_STATUS_GREEN])
+			green_led_off();
+		else
+			green_led_on();
+	}
+}
+
+void __led_set(led_id_t mask, int state)
+{
+	if (CONFIG_LED_STATUS_RED == mask) {
+		if (CONFIG_LED_STATUS_ON == state)
+			red_led_on();
+		else
+			red_led_off();
+	} else if (CONFIG_LED_STATUS_GREEN == mask) {
+		if (CONFIG_LED_STATUS_ON == state)
+			green_led_on();
+		else
+			green_led_off();
+	}
+}

arch/arm/cpu/arm920t/ep93xx/lowlevel_init.S

@@ -0,0 +1,457 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Low-level initialization for EP93xx
+ *
+ * Copyright (C) 2009 Matthias Kaehlcke <matthias@kaehlcke.net>
+ * Copyright (C) 2013
+ * Sergey Kostanabev <sergey.kostanbaev <at> fairwaves.ru>
+ *
+ * Copyright (C) 2006 Dominic Rath <Dominic.Rath@gmx.de>
+ * Copyright (C) 2006 Cirrus Logic Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ */
+
+#include <config.h>
+#include <asm/arch-ep93xx/ep93xx.h>
+
+/*
+/* Configure the SDRAM based on the supplied settings.
+ *
+ * Input:	r0 - SDRAM DEVCFG register
+ *		r2 - configuration for SDRAM chips
+ * Output:	none
+ * Modifies:	r3, r4
+ */
+ep93xx_sdram_config:
+	/* Program the SDRAM device configuration register. */
+	ldr	r3, =SDRAM_BASE
+#ifdef CONFIG_EDB93XX_SDCS0
+	str	r0, [r3, #SDRAM_OFF_DEVCFG0]
+#endif
+#ifdef CONFIG_EDB93XX_SDCS1
+	str	r0, [r3, #SDRAM_OFF_DEVCFG1]
+#endif
+#ifdef CONFIG_EDB93XX_SDCS2
+	str	r0, [r3, #SDRAM_OFF_DEVCFG2]
+#endif
+#ifdef CONFIG_EDB93XX_SDCS3
+	str	r0, [r3, #SDRAM_OFF_DEVCFG3]
+#endif
+
+	/* Set the Initialize and MRS bits (issue continuous NOP commands
+	 * (INIT & MRS set))
+	 */
+	ldr	r4, =(EP93XX_SDRAMCTRL_GLOBALCFG_INIT | \
+			EP93XX_SDRAMCTRL_GLOBALCFG_MRS | \
+			EP93XX_SDRAMCTRL_GLOBALCFG_CKE)
+	str	r4, [r3, #SDRAM_OFF_GLCONFIG]
+
+	/* Delay for 200us. */
+	mov	r4, #0x3000
+delay1:
+	subs	r4, r4, #1
+	bne	delay1
+
+	/* Clear the MRS bit to issue a precharge all. */
+	ldr	r4, =(EP93XX_SDRAMCTRL_GLOBALCFG_INIT | \
+			EP93XX_SDRAMCTRL_GLOBALCFG_CKE)
+	str	r4, [r3, #SDRAM_OFF_GLCONFIG]
+
+	/* Temporarily set the refresh timer to 0x10. Make it really low so
+	 * that refresh cycles are generated.
+	 */
+	ldr	r4, =0x10
+	str	r4, [r3, #SDRAM_OFF_REFRSHTIMR]
+
+	/* Delay for at least 80 SDRAM clock cycles. */
+	mov	r4, #80
+delay2:
+	subs	r4, r4, #1
+	bne	delay2
+
+	/* Set the refresh timer to the fastest required for any device
+	 * that might be used. Set 9.6 ms refresh time.
+	 */
+	ldr	r4, =0x01e0
+	str	r4, [r3, #SDRAM_OFF_REFRSHTIMR]
+
+	/* Select mode register update mode. */
+	ldr	r4, =(EP93XX_SDRAMCTRL_GLOBALCFG_CKE | \
+			EP93XX_SDRAMCTRL_GLOBALCFG_MRS)
+	str	r4, [r3, #SDRAM_OFF_GLCONFIG]
+
+	/* Program the mode register on the SDRAM by performing fake read */
+	ldr	r4, [r2]
+
+	/* Select normal operating mode. */
+	ldr	r4, =EP93XX_SDRAMCTRL_GLOBALCFG_CKE
+	str	r4, [r3, #SDRAM_OFF_GLCONFIG]
+
+	/* Return to the caller. */
+	mov	pc, lr
+
+/*
+ * Test to see if the SDRAM has been configured in a usable mode.
+ *
+ * Input:	r0 - Test address of SDRAM
+ * Output:	r0 - 0 -- Test OK, -1 -- Failed
+ * Modifies:	r0-r5
+ */
+ep93xx_sdram_test:
+	/* Load the test patterns to be written to SDRAM. */
+	ldr	r1, =0xf00dface
+	ldr	r2, =0xdeadbeef
+	ldr	r3, =0x08675309
+	ldr	r4, =0xdeafc0ed
+
+	/* Store the test patterns to SDRAM. */
+	stmia	r0, {r1-r4}
+
+	/* Load the test patterns from SDRAM one at a time and compare them
+	 * to the actual pattern.
+	 */
+	ldr	r5, [r0]
+	cmp	r5, r1
+	ldreq	r5, [r0, #0x0004]
+	cmpeq	r5, r2
+	ldreq	r5, [r0, #0x0008]
+	cmpeq	r5, r3
+	ldreq	r5, [r0, #0x000c]
+	cmpeq	r5, r4
+
+	/* Return -1 if a mismatch was encountered, 0 otherwise. */
+	mvnne	r0, #0xffffffff
+	moveq	r0, #0x00000000
+
+	/* Return to the caller. */
+	mov	pc, lr
+
+/*
+ * Determine the size of the SDRAM. Use data=address for the scan.
+ *
+ * Input:	r0 - Start SDRAM address
+ * Return:	r0 - Single block size
+ *		r1 - Valid block mask
+ *		r2 - Total block count
+ * Modifies:	r0-r5
+ */
+ep93xx_sdram_size:
+	/* Store zero at offset zero. */
+	str	r0, [r0]
+
+	/* Start checking for an alias at 1MB into SDRAM. */
+	ldr	r1, =0x00100000
+
+	/* Store the offset at the current offset. */
+check_block_size:
+	str	r1, [r0, r1]
+
+	/* Read back from zero. */
+	ldr	r2, [r0]
+
+	/* Stop searching of an alias was found. */
+	cmp	r1, r2
+	beq	found_block_size
+
+	/* Advance to the next power of two boundary. */
+	mov	r1, r1, lsl #1
+
+	/* Loop back if the size has not reached 256MB. */
+	cmp	r1, #0x10000000
+	bne	check_block_size
+
+	/* A full 256MB of memory was found, so return it now. */
+	ldr	r0, =0x10000000
+	ldr	r1, =0x00000000
+	ldr	r2, =0x00000001
+	mov	pc, lr
+
+	/* An alias was found. See if the first block is 128MB in size. */
+found_block_size:
+	cmp	r1, #0x08000000
+
+	/* The first block is 128MB, so there is no further memory. Return it
+	 * now.
+	 */
+	ldreq	r0, =0x08000000
+	ldreq	r1, =0x00000000
+	ldreq	r2, =0x00000001
+	moveq	pc, lr
+
+	/* Save the block size, set the block address bits to zero, and
+	 * initialize the block count to one.
+	 */
+	mov	r3, r1
+	ldr	r4, =0x00000000
+	ldr	r5, =0x00000001
+
+	/* Look for additional blocks of memory by searching for non-aliases. */
+find_blocks:
+	/* Store zero back to address zero. It may be overwritten. */
+	str	r0, [r0]
+
+	/* Advance to the next power of two boundary. */
+	mov	r1, r1, lsl #1
+
+	/* Store the offset at the current offset. */
+	str	r1, [r0, r1]
+
+	/* Read back from zero. */
+	ldr	r2, [r0]
+
+	/* See if a non-alias was found. */
+	cmp	r1, r2
+
+	/* If a non-alias was found, then or in the block address bit and
+	 * multiply the block count by two (since there are two unique
+	 * blocks, one with this bit zero and one with it one).
+	 */
+	orrne	r4, r4, r1
+	movne	r5, r5, lsl #1
+
+	/* Continue searching if there are more address bits to check. */
+	cmp	r1, #0x08000000
+	bne	find_blocks
+
+	/* Return the block size, address mask, and count. */
+	mov	r0, r3
+	mov	r1, r4
+	mov	r2, r5
+
+	/* Return to the caller. */
+	mov	pc, lr
+
+
+.globl lowlevel_init
+lowlevel_init:
+
+	mov	r6, lr
+
+	/* Make sure caches are off and invalidated. */
+	ldr	r0, =0x00000000
+	mcr	p15, 0, r0, c1, c0, 0
+	nop
+	nop
+	nop
+	nop
+	nop
+
+	/* Turn off the green LED and turn on the red LED. If the red LED
+	 * is left on for too long, the external reset circuit described
+	 * by application note AN258 will cause the system to reset.
+	 */
+	ldr	r1, =EP93XX_LED_DATA
+	ldr	r0, [r1]
+	bic	r0, r0, #EP93XX_LED_GREEN_ON
+	orr	r0, r0, #EP93XX_LED_RED_ON
+	str	r0, [r1]
+
+	/* Undo the silly static memory controller programming performed
+	 * by the boot rom.
+	 */
+	ldr	r0, =SMC_BASE
+
+	/* Set WST1 and WST2 to 31 HCLK cycles (slowest access) */
+	ldr	r1, =0x0000fbe0
+
+	/* Reset EP93XX_OFF_SMCBCR0 */
+	ldr	r2, [r0]
+	orr	r2, r2, r1
+	str	r2, [r0]
+
+	ldr	r2, [r0, #EP93XX_OFF_SMCBCR1]
+	orr	r2, r2, r1
+	str	r2, [r0, #EP93XX_OFF_SMCBCR1]
+
+	ldr	r2, [r0, #EP93XX_OFF_SMCBCR2]
+	orr	r2, r2, r1
+	str	r2, [r0, #EP93XX_OFF_SMCBCR2]
+
+	ldr	r2, [r0, #EP93XX_OFF_SMCBCR3]
+	orr	r2, r2, r1
+	str	r2, [r0, #EP93XX_OFF_SMCBCR3]
+
+	ldr	r2, [r0, #EP93XX_OFF_SMCBCR6]
+	orr	r2, r2, r1
+	str	r2, [r0, #EP93XX_OFF_SMCBCR6]
+
+	ldr	r2, [r0, #EP93XX_OFF_SMCBCR7]
+	orr	r2, r2, r1
+	str	r2, [r0, #EP93XX_OFF_SMCBCR7]
+
+	/* Set the PLL1 and processor clock. */
+	ldr	r0, =SYSCON_BASE
+#ifdef CONFIG_EDB9301
+	/* 332MHz, giving a 166MHz processor clock. */
+	ldr	r1, = 0x02b49907
+#else
+
+#ifdef CONFIG_EDB93XX_INDUSTRIAL
+	/* 384MHz, giving a 196MHz processor clock. */
+	ldr	r1, =0x02a4bb38
+#else
+	/* 400MHz, giving a 200MHz processor clock. */
+	ldr	r1, =0x02a4e39e
+#endif
+#endif
+	str	r1, [r0, #SYSCON_OFF_CLKSET1]
+
+	nop
+	nop
+	nop
+	nop
+	nop
+
+	/* Need to make sure that SDRAM is configured correctly before
+	 * coping the code into it.
+	 */
+
+#ifdef CONFIG_EDB93XX_SDCS0
+	mov	r11, #SDRAM_DEVCFG0_BASE
+#endif
+#ifdef CONFIG_EDB93XX_SDCS1
+	mov	r11, #SDRAM_DEVCFG1_BASE
+#endif
+#ifdef CONFIG_EDB93XX_SDCS2
+	mov	r11, #SDRAM_DEVCFG2_BASE
+#endif
+#ifdef CONFIG_EDB93XX_SDCS3
+	ldr	r0, =SYSCON_BASE
+	ldr	r0, [r0, #SYSCON_OFF_SYSCFG]
+	ands	r0, r0, #SYSCON_SYSCFG_LASDO
+	moveq	r11, #SDRAM_DEVCFG3_ASD0_BASE
+	movne	r11, #SDRAM_DEVCFG3_ASD1_BASE
+#endif
+	/* See Table 13-5 in EP93xx datasheet for more info about DRAM
+	 * register mapping */
+
+	/* Try a 32-bit wide configuration of SDRAM. */
+	ldr	r0, =(EP93XX_SDRAMCTRL_DEVCFG_BANKCOUNT | \
+			EP93XX_SDRAMCTRL_DEVCFG_SROMLL | \
+			EP93XX_SDRAMCTRL_DEVCFG_CASLAT_2 | \
+			EP93XX_SDRAMCTRL_DEVCFG_RASTOCAS_2)
+
+	/* Set burst count: 4 and CAS: 2
+	 * Burst mode [A11:A10]; CAS [A16:A14]
+	 */
+	orr	r2, r11, #0x00008800
+	bl	ep93xx_sdram_config
+
+	/* Test the SDRAM. */
+	mov	r0, r11
+	bl	ep93xx_sdram_test
+	cmp	r0, #0x00000000
+	beq	ep93xx_sdram_done
+
+	/* Try a 16-bit wide configuration of SDRAM. */
+	ldr	r0, =(EP93XX_SDRAMCTRL_DEVCFG_BANKCOUNT | \
+			EP93XX_SDRAMCTRL_DEVCFG_SROMLL | \
+			EP93XX_SDRAMCTRL_DEVCFG_CASLAT_2 | \
+			EP93XX_SDRAMCTRL_DEVCFG_RASTOCAS_2 | \
+			EP93XX_SDRAMCTRL_DEVCFG_EXTBUSWIDTH)
+
+	/* Set burst count: 8, CAS: 2, sequential burst
+	 * Accoring to Table 13-3 for 16bit operations mapping must be shifted.
+	 * Burst mode [A10:A9]; CAS [A15:A13]
+	 */
+	orr	r2, r11, #0x00004600
+	bl	ep93xx_sdram_config
+
+	/* Test the SDRAM. */
+	mov	r0, r11
+	bl	ep93xx_sdram_test
+	cmp	r0, #0x00000000
+	beq	ep93xx_sdram_done
+
+	/* Turn off the red LED. */
+	ldr	r0, =EP93XX_LED_DATA
+	ldr	r1, [r0]
+	bic	r1, r1, #EP93XX_LED_RED_ON
+	str	r1, [r0]
+
+	/* There is no SDRAM so flash the green LED. */
+flash_green:
+	orr	r1, r1, #EP93XX_LED_GREEN_ON
+	str	r1, [r0]
+	ldr	r2, =0x00010000
+flash_green_delay_1:
+	subs	r2, r2, #1
+	bne	flash_green_delay_1
+	bic	r1, r1, #EP93XX_LED_GREEN_ON
+	str	r1, [r0]
+	ldr	r2, =0x00010000
+flash_green_delay_2:
+	subs	r2, r2, #1
+	bne	flash_green_delay_2
+	orr	r1, r1, #EP93XX_LED_GREEN_ON
+	str	r1, [r0]
+	ldr	r2, =0x00010000
+flash_green_delay_3:
+	subs	r2, r2, #1
+	bne	flash_green_delay_3
+	bic	r1, r1, #EP93XX_LED_GREEN_ON
+	str	r1, [r0]
+	ldr	r2, =0x00050000
+flash_green_delay_4:
+	subs	r2, r2, #1
+	bne	flash_green_delay_4
+	b	flash_green
+
+
+ep93xx_sdram_done:
+	ldr	r1, =EP93XX_LED_DATA
+	ldr	r0, [r1]
+	bic	r0, r0, #EP93XX_LED_RED_ON
+	str	r0, [r1]
+
+	/* Determine the size of the SDRAM. */
+	mov	r0, r11
+	bl	ep93xx_sdram_size
+
+	/* Save the SDRAM characteristics. */
+	mov	r8, r0
+	mov	r9, r1
+	mov	r10, r2
+
+	/* Compute total memory size into r1 */
+	mul	r1, r8, r10
+#ifdef CONFIG_EDB93XX_SDCS0
+	ldr	r2, [r0, #SDRAM_OFF_DEVCFG0]
+#endif
+#ifdef CONFIG_EDB93XX_SDCS1
+	ldr	r2, [r0, #SDRAM_OFF_DEVCFG1]
+#endif
+#ifdef CONFIG_EDB93XX_SDCS2
+	ldr	r2, [r0, #SDRAM_OFF_DEVCFG2]
+#endif
+#ifdef CONFIG_EDB93XX_SDCS3
+	ldr	r2, [r0, #SDRAM_OFF_DEVCFG3]
+#endif
+
+	/* Consider small DRAM size as:
+	 * < 32Mb for 32bit bus
+	 * < 64Mb for 16bit bus
+	 */
+	tst	r2, #EP93XX_SDRAMCTRL_DEVCFG_EXTBUSWIDTH
+	moveq	r1, r1, lsr #1
+	cmp	r1, #0x02000000
+
+#if defined(CONFIG_EDB9301)
+	/* Set refresh counter to 20ms for small DRAM size, otherwise 9.6ms */
+	movlt	r1, #0x03f0
+	movge	r1, #0x01e0
+#else
+	/* Set refresh counter to 30.7ms for small DRAM size, otherwise 15ms */
+	movlt	r1, #0x0600
+	movge	r1, #0x2f0
+#endif
+	str	r1, [r0, #SDRAM_OFF_REFRSHTIMR]
+
+	/* Save the memory configuration information. */
+	orr	r0, r11, #UBOOT_MEMORYCNF_BANK_SIZE
+	stmia	r0, {r8-r11}
+
+	mov	lr, r6
+	mov	pc, lr

arch/arm/cpu/arm920t/ep93xx/speed.c

@@ -0,0 +1,95 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Cirrus Logic EP93xx PLL support.
+ *
+ * Copyright (C) 2009 Matthias Kaehlcke <matthias@kaehlcke.net>
+ */
+
+#include <common.h>
+#include <asm/arch/ep93xx.h>
+#include <asm/io.h>
+#include <div64.h>
+
+/*
+ * CONFIG_SYS_CLK_FREQ should be defined as the input frequency of the PLL.
+ *
+ * get_FCLK(), get_HCLK(), get_PCLK() and get_UCLK() return the clock of
+ * the specified bus in HZ.
+ */
+
+/*
+ * return the PLL output frequency
+ *
+ * PLL rate = CONFIG_SYS_CLK_FREQ * (X1FBD + 1) * (X2FBD + 1)
+ * / (X2IPD + 1) / 2^PS
+ */
+static ulong get_PLLCLK(uint32_t *pllreg)
+{
+	uint8_t i;
+	const uint32_t clkset = readl(pllreg);
+	uint64_t rate = CONFIG_SYS_CLK_FREQ;
+	rate *= ((clkset >> SYSCON_CLKSET_PLL_X1FBD1_SHIFT) & 0x1f) + 1;
+	rate *= ((clkset >> SYSCON_CLKSET_PLL_X2FBD2_SHIFT) & 0x3f) + 1;
+	do_div(rate, (clkset  & 0x1f) + 1);			/* X2IPD */
+	for (i = 0; i < ((clkset >> SYSCON_CLKSET_PLL_PS_SHIFT) & 3); i++)
+		rate >>= 1;
+
+	return (ulong)rate;
+}
+
+/* return FCLK frequency */
+ulong get_FCLK(void)
+{
+	const uint8_t fclk_divisors[] = { 1, 2, 4, 8, 16, 1, 1, 1 };
+	struct syscon_regs *syscon = (struct syscon_regs *)SYSCON_BASE;
+
+	const uint32_t clkset1 = readl(&syscon->clkset1);
+	const uint8_t fclk_div =
+		fclk_divisors[(clkset1 >> SYSCON_CLKSET1_FCLK_DIV_SHIFT) & 7];
+	const ulong fclk_rate = get_PLLCLK(&syscon->clkset1) / fclk_div;
+
+	return fclk_rate;
+}
+
+/* return HCLK frequency */
+ulong get_HCLK(void)
+{
+	const uint8_t hclk_divisors[] = { 1, 2, 4, 5, 6, 8, 16, 32 };
+	struct syscon_regs *syscon = (struct syscon_regs *)SYSCON_BASE;
+
+	const uint32_t clkset1 = readl(&syscon->clkset1);
+	const uint8_t hclk_div =
+		hclk_divisors[(clkset1 >> SYSCON_CLKSET1_HCLK_DIV_SHIFT) & 7];
+	const ulong hclk_rate = get_PLLCLK(&syscon->clkset1) / hclk_div;
+
+	return hclk_rate;
+}
+
+/* return PCLK frequency */
+ulong get_PCLK(void)
+{
+	const uint8_t pclk_divisors[] = { 1, 2, 4, 8 };
+	struct syscon_regs *syscon = (struct syscon_regs *)SYSCON_BASE;
+
+	const uint32_t clkset1 = readl(&syscon->clkset1);
+	const uint8_t pclk_div =
+		pclk_divisors[(clkset1 >> SYSCON_CLKSET1_PCLK_DIV_SHIFT) & 3];
+	const ulong pclk_rate = get_HCLK() / pclk_div;
+
+	return pclk_rate;
+}
+
+/* return UCLK frequency */
+ulong get_UCLK(void)
+{
+	struct syscon_regs *syscon = (struct syscon_regs *)SYSCON_BASE;
+	ulong uclk_rate;
+
+	const uint32_t value = readl(&syscon->pwrcnt);
+	if (value & SYSCON_PWRCNT_UART_BAUD)
+		uclk_rate = CONFIG_SYS_CLK_FREQ;
+	else
+		uclk_rate = CONFIG_SYS_CLK_FREQ / 2;
+
+	return uclk_rate;
+}

arch/arm/cpu/arm920t/ep93xx/timer.c

@@ -0,0 +1,115 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Cirrus Logic EP93xx timer support.
+ *
+ * Copyright (C) 2009, 2010 Matthias Kaehlcke <matthias@kaehlcke.net>
+ *
+ * Copyright (C) 2004, 2005
+ * Cory T. Tusar, Videon Central, Inc., <ctusar@videon-central.com>
+ *
+ * Based on the original intr.c Cirrus Logic EP93xx Rev D. interrupt support,
+ * author unknown.
+ */
+
+#include <common.h>
+#include <time.h>
+#include <linux/types.h>
+#include <asm/arch/ep93xx.h>
+#include <asm/io.h>
+#include <div64.h>
+
+#define TIMER_CLKSEL	(1 << 3)
+#define TIMER_ENABLE	(1 << 7)
+
+#define TIMER_FREQ			508469		/* ticks / second */
+#define TIMER_MAX_VAL			0xFFFFFFFF
+
+static struct ep93xx_timer
+{
+	unsigned long long ticks;
+	unsigned long last_read;
+} timer;
+
+static inline unsigned long long usecs_to_ticks(unsigned long usecs)
+{
+	unsigned long long ticks = (unsigned long long)usecs * TIMER_FREQ;
+	do_div(ticks, 1000 * 1000);
+
+	return ticks;
+}
+
+static inline void read_timer(void)
+{
+	struct timer_regs *timer_regs = (struct timer_regs *)TIMER_BASE;
+	const unsigned long now = TIMER_MAX_VAL - readl(&timer_regs->timer3.value);
+
+	if (now >= timer.last_read)
+		timer.ticks += now - timer.last_read;
+	else
+		/* an overflow occurred */
+		timer.ticks += TIMER_MAX_VAL - timer.last_read + now;
+
+	timer.last_read = now;
+}
+
+/*
+ * Get the number of ticks (in CONFIG_SYS_HZ resolution)
+ */
+unsigned long long get_ticks(void)
+{
+	unsigned long long sys_ticks;
+
+	read_timer();
+
+	sys_ticks = timer.ticks * CONFIG_SYS_HZ;
+	do_div(sys_ticks, TIMER_FREQ);
+
+	return sys_ticks;
+}
+
+unsigned long get_timer(unsigned long base)
+{
+	return get_ticks() - base;
+}
+
+void __udelay(unsigned long usec)
+{
+	unsigned long long target;
+
+	read_timer();
+
+	target = timer.ticks + usecs_to_ticks(usec);
+
+	while (timer.ticks < target)
+		read_timer();
+}
+
+int timer_init(void)
+{
+	struct timer_regs *timer_regs = (struct timer_regs *)TIMER_BASE;
+
+	/* use timer 3 with 508KHz and free running, not enabled now */
+	writel(TIMER_CLKSEL, &timer_regs->timer3.control);
+
+	/* set initial timer value */
+	writel(TIMER_MAX_VAL, &timer_regs->timer3.load);
+
+	/* Enable the timer */
+	writel(TIMER_ENABLE | TIMER_CLKSEL,
+		&timer_regs->timer3.control);
+
+	/* Reset the timer */
+	read_timer();
+	timer.ticks = 0;
+
+	return 0;
+}
+
+/*
+ * This function is derived from PowerPC code (timebase clock frequency).
+ * On ARM it returns the number of timer ticks per second.
+ */
+unsigned long get_tbclk(void)
+{
+	return CONFIG_SYS_HZ;
+}

arch/arm/cpu/arm920t/imx/speed.c

@@ -7,14 +7,13 @@
 
 #include <common.h>
 #if defined (CONFIG_IMX)
-#include <clock_legacy.h>
 
 #include <asm/arch/imx-regs.h>
 
 /* ------------------------------------------------------------------------- */
 /* NOTE: This describes the proper use of this file.
  *
- * get_board_sys_clk() should be defined as the input frequency of the PLL.
+ * CONFIG_SYS_CLK_FREQ should be defined as the input frequency of the PLL.
  * SH FIXME: 16780000 in our case
  * get_FCLK(), get_HCLK(), get_PCLK() and get_UCLK() return the clock of
  * the specified bus in HZ.
@@ -46,7 +45,7 @@ ulong get_mcuPLLCLK(void)
 
 	mfi = mfi<=5 ? 5 : mfi;
 
-	return (2*(get_board_sys_clk()>>10)*( (mfi<<10) + (mfn<<10)/(mfd+1)))/(pd+1);
+	return (2*(CONFIG_SYS_CLK_FREQ>>10)*( (mfi<<10) + (mfn<<10)/(mfd+1)))/(pd+1);
 }
 
 ulong get_FCLK(void)

arch/arm/cpu/arm920t/imx/timer.c

@@ -13,12 +13,10 @@
  */
 
 #include <common.h>
-#include <cpu_func.h>
 #include <time.h>
 #if defined (CONFIG_IMX)
 
 #include <asm/arch/imx-regs.h>
-#include <linux/delay.h>
 
 int timer_init (void)
 {
@@ -49,7 +47,7 @@ ulong get_timer (ulong base)
 	return get_timer_masked() - base;
 }
 
-void __udelay(unsigned long usec)
+void __udelay (unsigned long usec)
 {
 	ulong endtime = get_timer_masked() + usec;
 	signed long diff;
@@ -73,7 +71,7 @@ unsigned long long get_ticks(void)
  * This function is derived from PowerPC code (timebase clock frequency).
  * On ARM it returns the number of timer ticks per second.
  */
-ulong get_tbclk(void)
+ulong get_tbclk (void)
 {
 	return CONFIG_SYS_HZ;
 }
@@ -81,7 +79,7 @@ ulong get_tbclk(void)
 /*
  * Reset the cpu by setting up the watchdog timer and let him time out
  */
-void reset_cpu(void)
+void reset_cpu (ulong ignored)
 {
 	/* Disable watchdog and set Time-Out field to 0 */
 	WCR = 0x00000000;

arch/arm/cpu/arm920t/start.S

@@ -35,11 +35,25 @@ reset:
 	orr	r0, r0, #0xd3
 	msr	cpsr, r0
 
+#if	defined(CONFIG_AT91RM9200DK) || defined(CONFIG_AT91RM9200EK)
+	/*
+	 * relocate exception table
+	 */
+	ldr	r0, =_start
+	ldr	r1, =0x0
+	mov	r2, #16
+copyex:
+	subs	r2, r2, #1
+	ldr	r3, [r0], #4
+	str	r3, [r1], #4
+	bne	copyex
+#endif
+
 	/*
 	 * we do sys-critical inits only at reboot,
 	 * not when booting from ram!
 	 */
-#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT)
+#ifndef CONFIG_SKIP_LOWLEVEL_INIT
 	bl	cpu_init_crit
 #endif
 
@@ -64,7 +78,7 @@ c_runtime_cpu_setup:
  */
 
 
-#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT)
+#ifndef CONFIG_SKIP_LOWLEVEL_INIT
 cpu_init_crit:
 	/*
 	 * flush v4 I/D caches
@@ -83,7 +97,7 @@ cpu_init_crit:
 	orr	r0, r0, #0x00001000	@ set bit 12 (I) I-Cache
 	mcr	p15, 0, r0, c1, c0, 0
 
-#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT_ONLY)
+#ifndef CONFIG_SKIP_LOWLEVEL_INIT_ONLY
 	/*
 	 * before relocating, we have to setup RAM timing
 	 * because memory timing is board-dependend, you will
@@ -95,4 +109,4 @@ cpu_init_crit:
 	mov	lr, ip
 #endif
 	mov	pc, lr
-#endif /* CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) */
+#endif /* CONFIG_SKIP_LOWLEVEL_INIT */

arch/arm/cpu/arm926ejs/Makefile

@@ -12,10 +12,12 @@ extra-y	:=
 endif
 endif
 
+obj-$(CONFIG_ARMADA100) += armada100/
+obj-$(if $(filter lpc32xx,$(SOC)),y) += lpc32xx/
+obj-$(CONFIG_MX25) += mx25/
 obj-$(CONFIG_MX27) += mx27/
 obj-$(if $(filter mxs,$(SOC)),y) += mxs/
 obj-$(if $(filter spear,$(SOC)),y) += spear/
-obj-$(CONFIG_ARCH_SUNXI) += sunxi/
 
 # some files can only build in ARM or THUMB2, not THUMB1
 
@@ -24,8 +26,6 @@ ifndef CONFIG_HAS_THUMB2
 
 CFLAGS_cpu.o := -marm
 CFLAGS_cache.o := -marm
-CFLAGS_REMOVE_cpu.o := $(LTO_CFLAGS)
-CFLAGS_REMOVE_cache.o := $(LTO_CFLAGS)
 
 endif
 endif

arch/arm/cpu/arm926ejs/armada100/Makefile

@@ -0,0 +1,7 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2010
+# Marvell Semiconductor <www.marvell.com>
+# Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+
+obj-y	= cpu.o timer.o dram.o

arch/arm/cpu/arm926ejs/armada100/cpu.c

@@ -0,0 +1,92 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2010
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+ * Contributor: Mahavir Jain <mjain@marvell.com>
+ */
+
+#include <common.h>
+#include <cpu_func.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/armada100.h>
+
+#define UARTCLK14745KHZ	(APBC_APBCLK | APBC_FNCLK | APBC_FNCLKSEL(1))
+#define SET_MRVL_ID	(1<<8)
+#define L2C_RAM_SEL	(1<<4)
+
+int arch_cpu_init(void)
+{
+	u32 val;
+	struct armd1cpu_registers *cpuregs =
+		(struct armd1cpu_registers *) ARMD1_CPU_BASE;
+
+	struct armd1apb1_registers *apb1clkres =
+		(struct armd1apb1_registers *) ARMD1_APBC1_BASE;
+
+	struct armd1mpmu_registers *mpmu =
+		(struct armd1mpmu_registers *) ARMD1_MPMU_BASE;
+
+	/* set SEL_MRVL_ID bit in ARMADA100_CPU_CONF register */
+	val = readl(&cpuregs->cpu_conf);
+	val = val | SET_MRVL_ID;
+	writel(val, &cpuregs->cpu_conf);
+
+	/* Enable Clocks for all hardware units */
+	writel(0xFFFFFFFF, &mpmu->acgr);
+
+	/* Turn on AIB and AIB-APB Functional clock */
+	writel(APBC_APBCLK | APBC_FNCLK, &apb1clkres->aib);
+
+	/* ensure L2 cache is not mapped as SRAM */
+	val = readl(&cpuregs->cpu_conf);
+	val = val & ~(L2C_RAM_SEL);
+	writel(val, &cpuregs->cpu_conf);
+
+	/* Enable GPIO clock */
+	writel(APBC_APBCLK, &apb1clkres->gpio);
+
+#ifdef CONFIG_I2C_MV
+	/* Enable general I2C clock */
+	writel(APBC_RST | APBC_FNCLK | APBC_APBCLK, &apb1clkres->twsi0);
+	writel(APBC_FNCLK | APBC_APBCLK, &apb1clkres->twsi0);
+
+	/* Enable power I2C clock */
+	writel(APBC_RST | APBC_FNCLK | APBC_APBCLK, &apb1clkres->twsi1);
+	writel(APBC_FNCLK | APBC_APBCLK, &apb1clkres->twsi1);
+#endif
+
+	/*
+	 * Enable Functional and APB clock at 14.7456MHz
+	 * for configured UART console
+	 */
+#if (CONFIG_SYS_NS16550_COM1 == ARMD1_UART3_BASE)
+	writel(UARTCLK14745KHZ, &apb1clkres->uart3);
+#elif (CONFIG_SYS_NS16550_COM1 == ARMD1_UART2_BASE)
+	writel(UARTCLK14745KHZ, &apb1clkres->uart2);
+#else
+	writel(UARTCLK14745KHZ, &apb1clkres->uart1);
+#endif
+	icache_enable();
+
+	return 0;
+}
+
+#if defined(CONFIG_DISPLAY_CPUINFO)
+int print_cpuinfo(void)
+{
+	u32 id;
+	struct armd1cpu_registers *cpuregs =
+		(struct armd1cpu_registers *) ARMD1_CPU_BASE;
+
+	id = readl(&cpuregs->chip_id);
+	printf("SoC:   Armada 88AP%X-%X\n", (id & 0xFFF), (id >> 0x10));
+	return 0;
+}
+#endif
+
+#ifdef CONFIG_I2C_MV
+void i2c_clk_enable(void)
+{
+}
+#endif

arch/arm/cpu/arm926ejs/armada100/dram.c

@@ -0,0 +1,115 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2010
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Prafulla Wadaskar <prafulla@marvell.com>,
+ * Contributor: Mahavir Jain <mjain@marvell.com>
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/armada100.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * ARMADA100 DRAM controller supports upto 8 banks
+ * for chip select 0 and 1
+ */
+
+/*
+ * DDR Memory Control Registers
+ * Refer Datasheet Appendix A.17
+ */
+struct armd1ddr_map_registers {
+	u32	cs;	/* Memory Address Map Register -CS */
+	u32	pad[3];
+};
+
+struct armd1ddr_registers {
+	u8	pad[0x100 - 0x000];
+	struct armd1ddr_map_registers mmap[2];
+};
+
+/*
+ * armd1_sdram_base - reads SDRAM Base Address Register
+ */
+u32 armd1_sdram_base(int chip_sel)
+{
+	struct armd1ddr_registers *ddr_regs =
+		(struct armd1ddr_registers *)ARMD1_DRAM_BASE;
+	u32 result = 0;
+	u32 CS_valid = 0x01 & readl(&ddr_regs->mmap[chip_sel].cs);
+
+	if (!CS_valid)
+		return 0;
+
+	result = readl(&ddr_regs->mmap[chip_sel].cs) & 0xFF800000;
+	return result;
+}
+
+/*
+ * armd1_sdram_size - reads SDRAM size
+ */
+u32 armd1_sdram_size(int chip_sel)
+{
+	struct armd1ddr_registers *ddr_regs =
+		(struct armd1ddr_registers *)ARMD1_DRAM_BASE;
+	u32 result = 0;
+	u32 CS_valid = 0x01 & readl(&ddr_regs->mmap[chip_sel].cs);
+
+	if (!CS_valid)
+		return 0;
+
+	result = readl(&ddr_regs->mmap[chip_sel].cs);
+	result = (result >> 16) & 0xF;
+	if (result < 0x7) {
+		printf("Unknown DRAM Size\n");
+		return -1;
+	} else {
+		return ((0x8 << (result - 0x7)) * 1024 * 1024);
+	}
+}
+
+int dram_init(void)
+{
+	int i;
+
+	gd->ram_size = 0;
+	for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
+		gd->bd->bi_dram[i].start = armd1_sdram_base(i);
+		gd->bd->bi_dram[i].size = armd1_sdram_size(i);
+		/*
+		 * It is assumed that all memory banks are consecutive
+		 * and without gaps.
+		 * If the gap is found, ram_size will be reported for
+		 * consecutive memory only
+		 */
+		if (gd->bd->bi_dram[i].start != gd->ram_size)
+			break;
+
+		gd->ram_size += gd->bd->bi_dram[i].size;
+
+	}
+
+	for (; i < CONFIG_NR_DRAM_BANKS; i++) {
+		/* If above loop terminated prematurely, we need to set
+		 * remaining banks' start address & size as 0. Otherwise other
+		 * u-boot functions and Linux kernel gets wrong values which
+		 * could result in crash */
+		gd->bd->bi_dram[i].start = 0;
+		gd->bd->bi_dram[i].size = 0;
+	}
+	return 0;
+}
+
+/*
+ * If this function is not defined here,
+ * board.c alters dram bank zero configuration defined above.
+ */
+int dram_init_banksize(void)
+{
+	dram_init();
+
+	return 0;
+}

arch/arm/cpu/arm926ejs/armada100/timer.c

@@ -0,0 +1,194 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2010
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+ * Contributor: Mahavir Jain <mjain@marvell.com>
+ */
+
+#include <common.h>
+#include <time.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/armada100.h>
+
+/*
+ * Timer registers
+ * Refer Section A.6 in Datasheet
+ */
+struct armd1tmr_registers {
+	u32 clk_ctrl;	/* Timer clk control reg */
+	u32 match[9];	/* Timer match registers */
+	u32 count[3];	/* Timer count registers */
+	u32 status[3];
+	u32 ie[3];
+	u32 preload[3];	/* Timer preload value */
+	u32 preload_ctrl[3];
+	u32 wdt_match_en;
+	u32 wdt_match_r;
+	u32 wdt_val;
+	u32 wdt_sts;
+	u32 icr[3];
+	u32 wdt_icr;
+	u32 cer;	/* Timer count enable reg */
+	u32 cmr;
+	u32 ilr[3];
+	u32 wcr;
+	u32 wfar;
+	u32 wsar;
+	u32 cvwr;
+};
+
+#define TIMER			0	/* Use TIMER 0 */
+/* Each timer has 3 match registers */
+#define MATCH_CMP(x)		((3 * TIMER) + x)
+#define TIMER_LOAD_VAL 		0xffffffff
+#define	COUNT_RD_REQ		0x1
+
+DECLARE_GLOBAL_DATA_PTR;
+/* Using gd->arch.tbu from timestamp and gd->arch.tbl for lastdec */
+
+/* For preventing risk of instability in reading counter value,
+ * first set read request to register cvwr and then read same
+ * register after it captures counter value.
+ */
+ulong read_timer(void)
+{
+	struct armd1tmr_registers *armd1timers =
+		(struct armd1tmr_registers *) ARMD1_TIMER_BASE;
+	volatile int loop=100;
+
+	writel(COUNT_RD_REQ, &armd1timers->cvwr);
+	while (loop--);
+	return(readl(&armd1timers->cvwr));
+}
+
+static ulong get_timer_masked(void)
+{
+	ulong now = read_timer();
+
+	if (now >= gd->arch.tbl) {
+		/* normal mode */
+		gd->arch.tbu += now - gd->arch.tbl;
+	} else {
+		/* we have an overflow ... */
+		gd->arch.tbu += now + TIMER_LOAD_VAL - gd->arch.tbl;
+	}
+	gd->arch.tbl = now;
+
+	return gd->arch.tbu;
+}
+
+ulong get_timer(ulong base)
+{
+	return ((get_timer_masked() / (CONFIG_SYS_HZ_CLOCK / 1000)) -
+		base);
+}
+
+void __udelay(unsigned long usec)
+{
+	ulong delayticks;
+	ulong endtime;
+
+	delayticks = (usec * (CONFIG_SYS_HZ_CLOCK / 1000000));
+	endtime = get_timer_masked() + delayticks;
+
+	while (get_timer_masked() < endtime);
+}
+
+/*
+ * init the Timer
+ */
+int timer_init(void)
+{
+	struct armd1apb1_registers *apb1clkres =
+		(struct armd1apb1_registers *) ARMD1_APBC1_BASE;
+	struct armd1tmr_registers *armd1timers =
+		(struct armd1tmr_registers *) ARMD1_TIMER_BASE;
+
+	/* Enable Timer clock at 3.25 MHZ */
+	writel(APBC_APBCLK | APBC_FNCLK | APBC_FNCLKSEL(3), &apb1clkres->timers);
+
+	/* load value into timer */
+	writel(0x0, &armd1timers->clk_ctrl);
+	/* Use Timer 0 Match Resiger 0 */
+	writel(TIMER_LOAD_VAL, &armd1timers->match[MATCH_CMP(0)]);
+	/* Preload value is 0 */
+	writel(0x0, &armd1timers->preload[TIMER]);
+	/* Enable match comparator 0 for Timer 0 */
+	writel(0x1, &armd1timers->preload_ctrl[TIMER]);
+
+	/* Enable timer 0 */
+	writel(0x1, &armd1timers->cer);
+	/* init the gd->arch.tbu and gd->arch.tbl value */
+	gd->arch.tbl = read_timer();
+	gd->arch.tbu = 0;
+
+	return 0;
+}
+
+#define MPMU_APRR_WDTR	(1<<4)
+#define TMR_WFAR	0xbaba	/* WDT Register First key */
+#define TMP_WSAR	0xeb10	/* WDT Register Second key */
+
+/*
+ * This function uses internal Watchdog Timer
+ * based reset mechanism.
+ * Steps to write watchdog registers (protected access)
+ * 1. Write key value to TMR_WFAR reg.
+ * 2. Write key value to TMP_WSAR reg.
+ * 3. Perform write operation.
+ */
+void reset_cpu (unsigned long ignored)
+{
+	struct armd1mpmu_registers *mpmu =
+		(struct armd1mpmu_registers *) ARMD1_MPMU_BASE;
+	struct armd1tmr_registers *armd1timers =
+		(struct armd1tmr_registers *) ARMD1_TIMER_BASE;
+	u32 val;
+
+	/* negate hardware reset to the WDT after system reset */
+	val = readl(&mpmu->aprr);
+	val = val | MPMU_APRR_WDTR;
+	writel(val, &mpmu->aprr);
+
+	/* reset/enable WDT clock */
+	writel(APBC_APBCLK | APBC_FNCLK | APBC_RST, &mpmu->wdtpcr);
+	readl(&mpmu->wdtpcr);
+	writel(APBC_APBCLK | APBC_FNCLK, &mpmu->wdtpcr);
+	readl(&mpmu->wdtpcr);
+
+	/* clear previous WDT status */
+	writel(TMR_WFAR, &armd1timers->wfar);
+	writel(TMP_WSAR, &armd1timers->wsar);
+	writel(0, &armd1timers->wdt_sts);
+
+	/* set match counter */
+	writel(TMR_WFAR, &armd1timers->wfar);
+	writel(TMP_WSAR, &armd1timers->wsar);
+	writel(0xf, &armd1timers->wdt_match_r);
+
+	/* enable WDT reset */
+	writel(TMR_WFAR, &armd1timers->wfar);
+	writel(TMP_WSAR, &armd1timers->wsar);
+	writel(0x3, &armd1timers->wdt_match_en);
+
+	while(1);
+}
+
+/*
+ * This function is derived from PowerPC code (read timebase as long long).
+ * On ARM it just returns the timer value.
+ */
+unsigned long long get_ticks(void)
+{
+	return get_timer(0);
+}
+
+/*
+ * This function is derived from PowerPC code (timebase clock frequency).
+ * On ARM it returns the number of timer ticks per second.
+ */
+ulong get_tbclk (void)
+{
+	return (ulong)CONFIG_SYS_HZ;
+}

arch/arm/cpu/arm926ejs/cache.c

@@ -4,7 +4,6 @@
  * Ilya Yanok, EmCraft Systems
  */
 #include <cpu_func.h>
-#include <asm/cache.h>
 #include <linux/types.h>
 #include <common.h>
 
@@ -89,3 +88,4 @@ void enable_caches(void)
 	dcache_enable();
 #endif
 }
+

arch/arm/cpu/arm926ejs/cpu.c

@@ -16,24 +16,10 @@
 #include <command.h>
 #include <cpu_func.h>
 #include <irq_func.h>
-#include <asm/cache.h>
 #include <asm/system.h>
 
 static void cache_flush(void);
 
-/************************************************************
- * sdelay() - simple spin loop.  Will be constant time as
- *  its generally used in bypass conditions only.  This
- *  is necessary until timers are accessible.
- *
- *  not inline to increase chances its in cache when called
- *************************************************************/
-void sdelay(unsigned long loops)
-{
-	__asm__ volatile ("1:\n" "subs %0, %1, #1\n"
-			  "bne 1b":"=r" (loops):"0"(loops));
-}
-
 int cleanup_before_linux (void)
 {
 	/*

arch/arm/cpu/arm926ejs/lpc32xx/Kconfig

@@ -0,0 +1,20 @@
+if ARCH_LPC32XX
+
+config SYS_SOC
+	default "lpc32xx"
+
+choice
+	prompt "NXP LPC32xx board select"
+
+config TARGET_DEVKIT3250
+	bool "Timll DevKit3250"
+
+config TARGET_WORK_92105
+	bool "Work Microwave Work_92105"
+
+endchoice
+
+source "board/timll/devkit3250/Kconfig"
+source "board/work-microwave/work_92105/Kconfig"
+
+endif

arch/arm/cpu/arm926ejs/lpc32xx/clk.c

@@ -0,0 +1,137 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2011 by Vladimir Zapolskiy <vz@mleia.com>
+ */
+
+#include <common.h>
+#include <div64.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/clk.h>
+#include <asm/io.h>
+
+static struct clk_pm_regs *clk = (struct clk_pm_regs *)CLK_PM_BASE;
+
+unsigned int get_sys_clk_rate(void)
+{
+	if (readl(&clk->sysclk_ctrl) & CLK_SYSCLK_PLL397)
+		return RTC_CLK_FREQUENCY * 397;
+	else
+		return OSC_CLK_FREQUENCY;
+}
+
+unsigned int get_hclk_pll_rate(void)
+{
+	unsigned long long fin, fref, fcco, fout;
+	u32 val, m_div, n_div, p_div;
+
+	/*
+	 * Valid frequency ranges:
+	 *     1 * 10^6 <=  Fin <=  20 * 10^6
+	 *     1 * 10^6 <= Fref <=  27 * 10^6
+	 *   156 * 10^6 <= Fcco <= 320 * 10^6
+	 */
+
+	fref = fin = get_sys_clk_rate();
+	if (fin > 20000000ULL || fin < 1000000ULL)
+		return 0;
+
+	val = readl(&clk->hclkpll_ctrl);
+	m_div = ((val & CLK_HCLK_PLL_FEEDBACK_DIV_MASK) >> 1) + 1;
+	n_div = ((val & CLK_HCLK_PLL_PREDIV_MASK) >> 9) + 1;
+	if (val & CLK_HCLK_PLL_DIRECT)
+		p_div = 0;
+	else
+		p_div = ((val & CLK_HCLK_PLL_POSTDIV_MASK) >> 11) + 1;
+	p_div = 1 << p_div;
+
+	if (val & CLK_HCLK_PLL_BYPASS) {
+		do_div(fin, p_div);
+		return fin;
+	}
+
+	do_div(fref, n_div);
+	if (fref > 27000000ULL || fref < 1000000ULL)
+		return 0;
+
+	fcco = fref * m_div;
+	fout = fcco;
+	if (val & CLK_HCLK_PLL_FEEDBACK)
+		fcco *= p_div;
+	else
+		do_div(fout, p_div);
+
+	if (fcco > 320000000ULL || fcco < 156000000ULL)
+		return 0;
+
+	return fout;
+}
+
+unsigned int get_hclk_clk_div(void)
+{
+	u32 val;
+
+	val = readl(&clk->hclkdiv_ctrl) & CLK_HCLK_ARM_PLL_DIV_MASK;
+
+	return 1 << val;
+}
+
+unsigned int get_hclk_clk_rate(void)
+{
+	return get_hclk_pll_rate() / get_hclk_clk_div();
+}
+
+unsigned int get_periph_clk_div(void)
+{
+	u32 val;
+
+	val = readl(&clk->hclkdiv_ctrl) & CLK_HCLK_PERIPH_DIV_MASK;
+
+	return (val >> 2) + 1;
+}
+
+unsigned int get_periph_clk_rate(void)
+{
+	if (!(readl(&clk->pwr_ctrl) & CLK_PWR_NORMAL_RUN))
+		return get_sys_clk_rate();
+
+	return get_hclk_pll_rate() / get_periph_clk_div();
+}
+
+unsigned int get_sdram_clk_rate(void)
+{
+	unsigned int src_clk;
+
+	if (!(readl(&clk->pwr_ctrl) & CLK_PWR_NORMAL_RUN))
+		return get_sys_clk_rate();
+
+	src_clk = get_hclk_pll_rate();
+
+	if (readl(&clk->sdramclk_ctrl) & CLK_SDRAM_DDR_SEL) {
+		/* using DDR */
+		switch (readl(&clk->hclkdiv_ctrl) & CLK_HCLK_DDRAM_MASK) {
+		case CLK_HCLK_DDRAM_HALF:
+			return src_clk/2;
+		case CLK_HCLK_DDRAM_NOMINAL:
+			return src_clk;
+		default:
+			return 0;
+		}
+	} else {
+		/* using SDR */
+		switch (readl(&clk->hclkdiv_ctrl) & CLK_HCLK_ARM_PLL_DIV_MASK) {
+		case CLK_HCLK_ARM_PLL_DIV_4:
+			return src_clk/4;
+		case CLK_HCLK_ARM_PLL_DIV_2:
+			return src_clk/2;
+		case CLK_HCLK_ARM_PLL_DIV_1:
+			return src_clk;
+		default:
+			return 0;
+		}
+	}
+}
+
+int get_serial_clock(void)
+{
+	return get_periph_clk_rate();
+}

arch/arm/cpu/arm926ejs/lpc32xx/cpu.c

@@ -0,0 +1,78 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2011-2015 by Vladimir Zapolskiy <vz@mleia.com>
+ */
+
+#include <common.h>
+#include <cpu_func.h>
+#include <netdev.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/clk.h>
+#include <asm/arch/wdt.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/io.h>
+
+static struct clk_pm_regs *clk = (struct clk_pm_regs *)CLK_PM_BASE;
+static struct wdt_regs  *wdt = (struct wdt_regs *)WDT_BASE;
+
+void reset_cpu(ulong addr)
+{
+	/* Enable watchdog clock */
+	setbits_le32(&clk->timclk_ctrl, CLK_TIMCLK_WATCHDOG);
+
+	/* To be compatible with the original U-Boot code:
+	 * addr: - 0: perform hard reset.
+	 *       - !=0: perform a soft reset; i.e. "RESOUT_N" not asserted). */
+	if (addr == 0) {
+		/* Reset pulse length is 13005 peripheral clock frames */
+		writel(13000, &wdt->pulse);
+
+		/* Force WDOG_RESET2 and RESOUT_N signal active */
+		writel(WDTIM_MCTRL_RESFRC2 | WDTIM_MCTRL_RESFRC1
+		       | WDTIM_MCTRL_M_RES2, &wdt->mctrl);
+	} else {
+		/* Force match output active */
+		writel(0x01, &wdt->emr);
+
+		/* Internal reset on match output (no pulse on "RESOUT_N") */
+		writel(WDTIM_MCTRL_M_RES1, &wdt->mctrl);
+	}
+
+	while (1)
+		/* NOP */;
+}
+
+#if defined(CONFIG_ARCH_CPU_INIT)
+int arch_cpu_init(void)
+{
+	/*
+	 * It might be necessary to flush data cache, if U-Boot is loaded
+	 * from kickstart bootloader, e.g. from S1L loader
+	 */
+	flush_dcache_all();
+
+	return 0;
+}
+#else
+#error "You have to select CONFIG_ARCH_CPU_INIT"
+#endif
+
+#if defined(CONFIG_DISPLAY_CPUINFO)
+int print_cpuinfo(void)
+{
+	printf("CPU:   NXP LPC32XX\n");
+	printf("CPU clock:        %uMHz\n", get_hclk_pll_rate() / 1000000);
+	printf("AHB bus clock:    %uMHz\n", get_hclk_clk_rate() / 1000000);
+	printf("Peripheral clock: %uMHz\n", get_periph_clk_rate() / 1000000);
+
+	return 0;
+}
+#endif
+
+#ifdef CONFIG_LPC32XX_ETH
+int cpu_eth_init(bd_t *bis)
+{
+	lpc32xx_eth_initialize(bis);
+	return 0;
+}
+#endif

arch/arm/cpu/arm926ejs/lpc32xx/devices.c

@@ -23,7 +23,8 @@ void lpc32xx_uart_init(unsigned int uart_id)
 		return;
 
 	/* Disable loopback mode, if it is set by S1L bootloader */
-	clrbits_le32(&ctrl->loop, UART_LOOPBACK(uart_id));
+	clrbits_le32(&ctrl->loop,
+		     UART_LOOPBACK(CONFIG_SYS_LPC32XX_UART));
 
 	if (uart_id < 3 || uart_id > 6)
 		return;
@@ -42,7 +43,7 @@ void lpc32xx_uart_init(unsigned int uart_id)
 }
 
 #if !CONFIG_IS_ENABLED(OF_CONTROL)
-static const struct ns16550_plat lpc32xx_uart[] = {
+static const struct ns16550_platdata lpc32xx_uart[] = {
 	{ .base = UART3_BASE, .reg_shift = 2,
 	  .clock = CONFIG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, },
 	{ .base = UART4_BASE, .reg_shift = 2,
@@ -54,14 +55,14 @@ static const struct ns16550_plat lpc32xx_uart[] = {
 };
 
 #if defined(CONFIG_LPC32XX_HSUART)
-static const struct lpc32xx_hsuart_plat lpc32xx_hsuart[] = {
+static const struct lpc32xx_hsuart_platdata lpc32xx_hsuart[] = {
 	{ HS_UART1_BASE, },
 	{ HS_UART2_BASE, },
 	{ HS_UART7_BASE, },
 };
 #endif
 
-U_BOOT_DRVINFOS(lpc32xx_uarts) = {
+U_BOOT_DEVICES(lpc32xx_uarts) = {
 #if defined(CONFIG_LPC32XX_HSUART)
 	{ "lpc32xx_hsuart", &lpc32xx_hsuart[0], },
 	{ "lpc32xx_hsuart", &lpc32xx_hsuart[1], },
@@ -123,7 +124,7 @@ void lpc32xx_i2c_init(unsigned int devnum)
 	writel(ctrl, &clk->i2cclk_ctrl);
 }
 
-U_BOOT_DRVINFO(lpc32xx_gpios) = {
+U_BOOT_DEVICE(lpc32xx_gpios) = {
 	.name = "gpio_lpc32xx"
 };
 

arch/arm/cpu/arm926ejs/lpc32xx/dram.c

@@ -0,0 +1,73 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * LPC32xx dram init
+ *
+ * (C) Copyright 2014  DENX Software Engineering GmbH
+ * Written-by: Albert ARIBAUD <albert.aribaud@3adev.fr>
+ *
+ * This is called by SPL to gain access to the SDR DRAM.
+ *
+ * This code runs from SRAM.
+ */
+
+#include <common.h>
+#include <netdev.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/clk.h>
+#include <asm/arch/wdt.h>
+#include <asm/arch/emc.h>
+#include <asm/io.h>
+
+static struct clk_pm_regs *clk = (struct clk_pm_regs *)CLK_PM_BASE;
+static struct emc_regs *emc = (struct emc_regs *)EMC_BASE;
+
+void ddr_init(struct emc_dram_settings *dram)
+{
+	uint32_t ck;
+
+	/* Enable EMC interface and choose little endian mode */
+	writel(1, &emc->ctrl);
+	writel(0, &emc->config);
+	/* Select maximum EMC Dynamic Memory Refresh Time */
+	writel(0x7FF, &emc->refresh);
+	/* Determine CLK */
+	ck = get_sdram_clk_rate();
+	/* Configure SDRAM */
+	writel(dram->cmddelay, &clk->sdramclk_ctrl);
+	writel(dram->config0, &emc->config0);
+	writel(dram->rascas0, &emc->rascas0);
+	writel(dram->rdconfig, &emc->read_config);
+	/* Set timings */
+	writel((ck / dram->trp) & 0x0000000F, &emc->t_rp);
+	writel((ck / dram->tras) & 0x0000000F, &emc->t_ras);
+	writel((ck / dram->tsrex) & 0x0000007F, &emc->t_srex);
+	writel((ck / dram->twr) & 0x0000000F, &emc->t_wr);
+	writel((ck / dram->trc) & 0x0000001F, &emc->t_rc);
+	writel((ck / dram->trfc) & 0x0000001F, &emc->t_rfc);
+	writel((ck / dram->txsr) & 0x000000FF, &emc->t_xsr);
+	writel(dram->trrd, &emc->t_rrd);
+	writel(dram->tmrd, &emc->t_mrd);
+	writel(dram->tcdlr, &emc->t_cdlr);
+	/* Dynamic refresh */
+	writel((((ck / dram->refresh) >> 4) & 0x7FF), &emc->refresh);
+	udelay(10);
+	/* Force all clocks, enable inverted ck, issue NOP command */
+	writel(0x00000193, &emc->control);
+	udelay(100);
+	/* Keep all clocks enabled, issue a PRECHARGE ALL command */
+	writel(0x00000113, &emc->control);
+	/* Fast dynamic refresh for at least a few SDRAM ck cycles */
+	writel((((128) >> 4) & 0x7FF), &emc->refresh);
+	udelay(10);
+	/* set correct dynamic refresh timing */
+	writel((((ck / dram->refresh) >> 4) & 0x7FF), &emc->refresh);
+	udelay(10);
+	/* set normal mode to CAS=3 */
+	writel(0x00000093, &emc->control);
+	readl(EMC_DYCS0_BASE | dram->mode);
+	/* set extended mode to all zeroes */
+	writel(0x00000093, &emc->control);
+	readl(EMC_DYCS0_BASE | dram->emode);
+	/* stop forcing clocks, keep inverted clock, issue normal mode */
+	writel(0x00000010, &emc->control);
+}

arch/arm/cpu/arm926ejs/lpc32xx/timer.c

@@ -0,0 +1,85 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2011 Vladimir Zapolskiy <vz@mleia.com>
+ */
+
+#include <common.h>
+#include <time.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/clk.h>
+#include <asm/arch/timer.h>
+#include <asm/io.h>
+
+static struct timer_regs  *timer0 = (struct timer_regs *)TIMER0_BASE;
+static struct timer_regs  *timer1 = (struct timer_regs *)TIMER1_BASE;
+static struct clk_pm_regs *clk    = (struct clk_pm_regs *)CLK_PM_BASE;
+
+static void lpc32xx_timer_clock(u32 bit, int enable)
+{
+	if (enable)
+		setbits_le32(&clk->timclk_ctrl1, bit);
+	else
+		clrbits_le32(&clk->timclk_ctrl1, bit);
+}
+
+static void lpc32xx_timer_reset(struct timer_regs *timer, u32 freq)
+{
+	writel(TIMER_TCR_COUNTER_RESET,   &timer->tcr);
+	writel(TIMER_TCR_COUNTER_DISABLE, &timer->tcr);
+	writel(0, &timer->tc);
+	writel(0, &timer->pr);
+
+	/* Count mode is every rising PCLK edge */
+	writel(TIMER_CTCR_MODE_TIMER, &timer->ctcr);
+
+	/* Set prescale counter value */
+	writel((get_periph_clk_rate() / freq) - 1, &timer->pr);
+
+	/* Ensure that the counter is not reset when matching TC */
+	writel(0,  &timer->mcr);
+}
+
+static void lpc32xx_timer_count(struct timer_regs *timer, int enable)
+{
+	if (enable)
+		writel(TIMER_TCR_COUNTER_ENABLE,  &timer->tcr);
+	else
+		writel(TIMER_TCR_COUNTER_DISABLE, &timer->tcr);
+}
+
+int timer_init(void)
+{
+	lpc32xx_timer_clock(CLK_TIMCLK_TIMER0, 1);
+	lpc32xx_timer_reset(timer0, CONFIG_SYS_HZ);
+	lpc32xx_timer_count(timer0, 1);
+
+	return 0;
+}
+
+ulong get_timer(ulong base)
+{
+	return readl(&timer0->tc) - base;
+}
+
+void __udelay(unsigned long usec)
+{
+	lpc32xx_timer_clock(CLK_TIMCLK_TIMER1, 1);
+	lpc32xx_timer_reset(timer1, CONFIG_SYS_HZ * 1000);
+	lpc32xx_timer_count(timer1, 1);
+
+	while (readl(&timer1->tc) < usec)
+		/* NOP */;
+
+	lpc32xx_timer_count(timer1, 0);
+	lpc32xx_timer_clock(CLK_TIMCLK_TIMER1, 0);
+}
+
+unsigned long long get_ticks(void)
+{
+	return get_timer(0);
+}
+
+ulong get_tbclk(void)
+{
+	return CONFIG_SYS_HZ;
+}

arch/arm/cpu/arm926ejs/mx25/Makefile

@@ -0,0 +1,7 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+
+obj-y	+= generic.o timer.o reset.o relocate.o

arch/arm/cpu/arm926ejs/mx25/generic.c

@@ -0,0 +1,270 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2009 DENX Software Engineering
+ * Author: John Rigby <jrigby@gmail.com>
+ *
+ * Based on mx27/generic.c:
+ *  Copyright (c) 2008 Eric Jarrige <eric.jarrige@armadeus.org>
+ *  Copyright (c) 2009 Ilya Yanok <yanok@emcraft.com>
+ */
+
+#include <common.h>
+#include <div64.h>
+#include <netdev.h>
+#include <vsprintf.h>
+#include <asm/io.h>
+#include <asm/arch-imx/cpu.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/clock.h>
+
+#ifdef CONFIG_FSL_ESDHC_IMX
+#include <fsl_esdhc_imx.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+#endif
+
+/*
+ *  get the system pll clock in Hz
+ *
+ *                  mfi + mfn / (mfd +1)
+ *  f = 2 * f_ref * --------------------
+ *                        pd + 1
+ */
+static unsigned int imx_decode_pll(unsigned int pll, unsigned int f_ref)
+{
+	unsigned int mfi = (pll >> CCM_PLL_MFI_SHIFT)
+	    & CCM_PLL_MFI_MASK;
+	int mfn = (pll >> CCM_PLL_MFN_SHIFT)
+	    & CCM_PLL_MFN_MASK;
+	unsigned int mfd = (pll >> CCM_PLL_MFD_SHIFT)
+	    & CCM_PLL_MFD_MASK;
+	unsigned int pd = (pll >> CCM_PLL_PD_SHIFT)
+	    & CCM_PLL_PD_MASK;
+
+	mfi = mfi <= 5 ? 5 : mfi;
+	mfn = mfn >= 512 ? mfn - 1024 : mfn;
+	mfd += 1;
+	pd += 1;
+
+	return lldiv(2 * (u64) f_ref * (mfi * mfd + mfn),
+		     mfd * pd);
+}
+
+static ulong imx_get_mpllclk(void)
+{
+	struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE;
+	ulong fref = MXC_HCLK;
+
+	return imx_decode_pll(readl(&ccm->mpctl), fref);
+}
+
+static ulong imx_get_upllclk(void)
+{
+	struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE;
+	ulong fref = MXC_HCLK;
+
+	return imx_decode_pll(readl(&ccm->upctl), fref);
+}
+
+static ulong imx_get_armclk(void)
+{
+	struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE;
+	ulong cctl = readl(&ccm->cctl);
+	ulong fref = imx_get_mpllclk();
+	ulong div;
+
+	if (cctl & CCM_CCTL_ARM_SRC)
+		fref = lldiv((u64) fref * 3, 4);
+
+	div = ((cctl >> CCM_CCTL_ARM_DIV_SHIFT)
+	       & CCM_CCTL_ARM_DIV_MASK) + 1;
+
+	return fref / div;
+}
+
+static ulong imx_get_ahbclk(void)
+{
+	struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE;
+	ulong cctl = readl(&ccm->cctl);
+	ulong fref = imx_get_armclk();
+	ulong div;
+
+	div = ((cctl >> CCM_CCTL_AHB_DIV_SHIFT)
+	       & CCM_CCTL_AHB_DIV_MASK) + 1;
+
+	return fref / div;
+}
+
+static ulong imx_get_ipgclk(void)
+{
+	return imx_get_ahbclk() / 2;
+}
+
+static ulong imx_get_perclk(int clk)
+{
+	struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE;
+	ulong fref = readl(&ccm->mcr) & (1 << clk) ? imx_get_upllclk() :
+						     imx_get_ahbclk();
+	ulong div;
+
+	div = readl(&ccm->pcdr[CCM_PERCLK_REG(clk)]);
+	div = ((div >> CCM_PERCLK_SHIFT(clk)) & CCM_PERCLK_MASK) + 1;
+
+	return fref / div;
+}
+
+int imx_set_perclk(enum mxc_clock clk, bool from_upll, unsigned int freq)
+{
+	struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE;
+	ulong fref = from_upll ? imx_get_upllclk() : imx_get_ahbclk();
+	ulong div = (fref + freq - 1) / freq;
+
+	if (clk > MXC_UART_CLK || !div || --div > CCM_PERCLK_MASK)
+		return -EINVAL;
+
+	clrsetbits_le32(&ccm->pcdr[CCM_PERCLK_REG(clk)],
+			CCM_PERCLK_MASK << CCM_PERCLK_SHIFT(clk),
+			div << CCM_PERCLK_SHIFT(clk));
+	if (from_upll)
+		setbits_le32(&ccm->mcr, 1 << clk);
+	else
+		clrbits_le32(&ccm->mcr, 1 << clk);
+	return 0;
+}
+
+unsigned int mxc_get_clock(enum mxc_clock clk)
+{
+	if (clk >= MXC_CLK_NUM)
+		return -1;
+	switch (clk) {
+	case MXC_ARM_CLK:
+		return imx_get_armclk();
+	case MXC_AHB_CLK:
+		return imx_get_ahbclk();
+	case MXC_IPG_CLK:
+	case MXC_CSPI_CLK:
+	case MXC_FEC_CLK:
+		return imx_get_ipgclk();
+	default:
+		return imx_get_perclk(clk);
+	}
+}
+
+u32 get_cpu_rev(void)
+{
+	u32 srev;
+	u32 system_rev = 0x25000;
+
+	/* read SREV register from IIM module */
+	struct iim_regs *iim = (struct iim_regs *)IMX_IIM_BASE;
+	srev = readl(&iim->iim_srev);
+
+	switch (srev) {
+	case 0x00:
+		system_rev |= CHIP_REV_1_0;
+		break;
+	case 0x01:
+		system_rev |= CHIP_REV_1_1;
+		break;
+	case 0x02:
+		system_rev |= CHIP_REV_1_2;
+		break;
+	default:
+		system_rev |= 0x8000;
+		break;
+	}
+
+	return system_rev;
+}
+
+#if defined(CONFIG_DISPLAY_CPUINFO)
+static char *get_reset_cause(void)
+{
+	/* read RCSR register from CCM module */
+	struct ccm_regs *ccm =
+		(struct ccm_regs *)IMX_CCM_BASE;
+
+	u32 cause = readl(&ccm->rcsr) & 0x0f;
+
+	if (cause == 0)
+		return "POR";
+	else if (cause == 1)
+		return "RST";
+	else if ((cause & 2) == 2)
+		return "WDOG";
+	else if ((cause & 4) == 4)
+		return "SW RESET";
+	else if ((cause & 8) == 8)
+		return "JTAG";
+	else
+		return "unknown reset";
+
+}
+
+int print_cpuinfo(void)
+{
+	char buf[32];
+	u32 cpurev = get_cpu_rev();
+
+	printf("CPU:   Freescale i.MX25 rev%d.%d%s at %s MHz\n",
+		(cpurev & 0xF0) >> 4, (cpurev & 0x0F),
+		((cpurev & 0x8000) ? " unknown" : ""),
+		strmhz(buf, imx_get_armclk()));
+	printf("Reset cause: %s\n", get_reset_cause());
+	return 0;
+}
+#endif
+
+#if defined(CONFIG_FEC_MXC)
+/*
+ * Initializes on-chip ethernet controllers.
+ * to override, implement board_eth_init()
+ */
+int cpu_eth_init(bd_t *bis)
+{
+	struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE;
+	ulong val;
+
+	val = readl(&ccm->cgr0);
+	val |= (1 << 23);
+	writel(val, &ccm->cgr0);
+	return fecmxc_initialize(bis);
+}
+#endif
+
+int get_clocks(void)
+{
+#ifdef CONFIG_FSL_ESDHC_IMX
+#if CONFIG_SYS_FSL_ESDHC_ADDR == IMX_MMC_SDHC2_BASE
+	gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
+#else
+	gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC1_CLK);
+#endif
+#endif
+	return 0;
+}
+
+#ifdef CONFIG_FSL_ESDHC_IMX
+/*
+ * Initializes on-chip MMC controllers.
+ * to override, implement board_mmc_init()
+ */
+int cpu_mmc_init(bd_t *bis)
+{
+	return fsl_esdhc_mmc_init(bis);
+}
+#endif
+
+#ifdef CONFIG_FEC_MXC
+void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
+{
+	int i;
+	struct iim_regs *iim = (struct iim_regs *)IMX_IIM_BASE;
+	struct fuse_bank *bank = &iim->bank[0];
+	struct fuse_bank0_regs *fuse =
+			(struct fuse_bank0_regs *)bank->fuse_regs;
+
+	for (i = 0; i < 6; i++)
+		mac[i] = readl(&fuse->mac_addr[i]) & 0xff;
+}
+#endif /* CONFIG_FEC_MXC */

arch/arm/cpu/arm926ejs/mx25/relocate.S

@@ -0,0 +1,22 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ *  relocate - i.MX25-specific vector relocation
+ *
+ *  Copyright (c) 2013  Albert ARIBAUD <albert.u.boot@aribaud.net>
+ */
+
+#include <linux/linkage.h>
+
+/*
+ * The i.MX25 SoC is very specific with respect to exceptions: it
+ * does not provide RAM at the high vectors address (0xFFFF0000),
+ * thus only the low address (0x00000000) is useable; but that is
+ * in ROM, so let's avoid relocating the vectors.
+ */
+	.section	.text.relocate_vectors,"ax",%progbits
+
+ENTRY(relocate_vectors)
+
+	bx	lr
+
+ENDPROC(relocate_vectors)

arch/arm/cpu/arm926ejs/mx25/reset.c

@@ -0,0 +1,39 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Alex Zuepke <azu@sysgo.de>
+ *
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
+ *
+ * (C) Copyright 2009
+ * Ilya Yanok, Emcraft Systems Ltd, <yanok@emcraft.com>
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/imx-regs.h>
+
+/*
+ * Reset the cpu by setting up the watchdog timer and let it time out
+ */
+void reset_cpu(ulong ignored)
+{
+	struct wdog_regs *regs = (struct wdog_regs *)IMX_WDT_BASE;
+	/* Disable watchdog and set Time-Out field to 0 */
+	writew(0, &regs->wcr);
+
+	/* Write Service Sequence */
+	writew(WSR_UNLOCK1, &regs->wsr);
+	writew(WSR_UNLOCK2, &regs->wsr);
+
+	/* Enable watchdog */
+	writew(WCR_WDE, &regs->wcr);
+
+	while (1) ;
+}

arch/arm/cpu/arm926ejs/mx25/timer.c

@@ -0,0 +1,48 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Alex Zuepke <azu@sysgo.de>
+ *
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
+ *
+ * (C) Copyright 2009
+ * Ilya Yanok, Emcraft Systems Ltd, <yanok@emcraft.com>
+ *
+ * (C) Copyright 2009 DENX Software Engineering
+ * Author: John Rigby <jrigby@gmail.com>
+ *	Add support for MX25
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/imx-regs.h>
+
+/* nothing really to do with interrupts, just starts up a counter. */
+/* The 32KHz 32-bit timer overruns in 134217 seconds */
+int timer_init(void)
+{
+	int i;
+	struct gpt_regs *gpt = (struct gpt_regs *)IMX_GPT1_BASE;
+	struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE;
+
+	/* setup GP Timer 1 */
+	writel(GPT_CTRL_SWR, &gpt->ctrl);
+
+	writel(readl(&ccm->cgr1) | CCM_CGR1_GPT1, &ccm->cgr1);
+
+	for (i = 0; i < 100; i++)
+		writel(0, &gpt->ctrl); /* We have no udelay by now */
+	writel(0, &gpt->pre); /* prescaler = 1 */
+	/* Freerun Mode, 32KHz input */
+	writel(readl(&gpt->ctrl) | GPT_CTRL_CLKSOURCE_32 | GPT_CTRL_FRR,
+			&gpt->ctrl);
+	writel(readl(&gpt->ctrl) | GPT_CTRL_TEN, &gpt->ctrl);
+
+	return 0;
+}

arch/arm/cpu/arm926ejs/mx27/generic.c

@@ -6,7 +6,6 @@
 
 #include <common.h>
 #include <div64.h>
-#include <net.h>
 #include <netdev.h>
 #include <vsprintf.h>
 #include <asm/io.h>
@@ -177,7 +176,7 @@ int print_cpuinfo (void)
 }
 #endif
 
-int cpu_eth_init(struct bd_info *bis)
+int cpu_eth_init(bd_t *bis)
 {
 #if defined(CONFIG_FEC_MXC)
 	struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE;
@@ -195,7 +194,7 @@ int cpu_eth_init(struct bd_info *bis)
  * Initializes on-chip MMC controllers.
  * to override, implement board_mmc_init()
  */
-int cpu_mmc_init(struct bd_info *bis)
+int cpu_mmc_init(bd_t *bis)
 {
 #ifdef CONFIG_MMC_MXC
 	return mxc_mmc_init(bis);