Solve a issue with AXI_WIDTH_32 on a the 64 bytes cache line platform;
in this case the requested descriptor padding length should be 12 but the
associated parameter EQOS_DMA_CH0_CONTROL.DSL is limited at 3bits = 7.
As the DMA descriptor can't be correctly aligned with the cache line,
the maintenance of each descriptor can't be guarantee by a simple cache
line operation: flush or invalid.
To avoid all the maintenance issues, these descripto need to be allocated
in a NOT CACHEABLE memory, allocated by noncached_alloc() when
CONFIG_SYS_NONCACHED_MEMORY is enable.
This patch don't change the current behavior when the descriptor
can be cache-aligned with the filed "Descriptor Skip Length" of
the DMA channel control register, when eqos->desc_pad = true.
Change-Id: Iada23492743e3af977e07c1f1b8c2f32550436f7
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-on: https://gerrit.st.com/c/mpu/oe/st/u-boot/+/236650
Reviewed-by: CITOOLS <MDG-smet-aci-reviews@list.st.com>
Reviewed-by: Christophe ROULLIER <christophe.roullier@st.com>
6ee1aad5b6