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i2S-6UB:dts: add uart pinctrl

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Add uart2, uart5, uart6, uart7 pinctrl
This commit is contained in:
SteveChen
2019-06-20 23:35:07 +08:00
parent 14a076f580
commit b8b95282c9
1 changed files with 32 additions and 1 deletions
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33
arch/arm/boot/dts/i2s-6ull-14x14.dtsi
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@ -439,6 +439,11 @@
fsl,pins = <
MX6UL_PAD_UART2_TX_DATA__UART2_DCE_TX 0x1b0b1
MX6UL_PAD_UART2_RX_DATA__UART2_DCE_RX 0x1b0b1
>;
};
pinctrl_uart2dce_rtscts_alt1: uart2dcegrp_rtscts_alt1 {
fsl,pins = <
MX6UL_PAD_UART3_RX_DATA__UART2_DCE_RTS 0x1b0b1
MX6UL_PAD_UART3_TX_DATA__UART2_DCE_CTS 0x1b0b1
>;
@ -448,6 +453,11 @@
fsl,pins = <
MX6UL_PAD_UART2_TX_DATA__UART2_DTE_RX 0x1b0b1
MX6UL_PAD_UART2_RX_DATA__UART2_DTE_TX 0x1b0b1
>;
};
pinctrl_uart2dte_rtscts_alt1: uart2dtegrp_rtscts_alt1 {
fsl,pins = <
MX6UL_PAD_UART3_RX_DATA__UART2_DTE_CTS 0x1b0b1
MX6UL_PAD_UART3_TX_DATA__UART2_DTE_RTS 0x1b0b1
>;
@ -467,6 +477,27 @@
>;
};
pinctrl_uart5dce_alt1: uart5dcegrp_alt1 {
fsl,pins = <
MX6UL_PAD_CSI_DATA00__UART5_DCE_TX 0x1b0b1
MX6UL_PAD_CSI_DATA01__UART5_DCE_RX 0x1b0b1
>;
};
pinctrl_uart6dce_alt1: uart6dcegrp_alt1 {
fsl,pins = <
MX6UL_PAD_CSI_PIXCLK__UART6_DCE_RX 0x1b0b1
MX6UL_PAD_CSI_MCLK__UART6_DCE_TX 0x1b0b1
>;
};
pinctrl_uart7dce_alt1: uart7dcegrp_alt1 {
fsl,pins = <
MX6UL_PAD_LCD_DATA16__UART7_DCE_TX 0x1b0b1
MX6UL_PAD_LCD_DATA17__UART7_DCE_RX 0x1b0b1
>;
};
pinctrl_usdhc1: usdhc1grp {
fsl,pins = <
MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059
@ -693,7 +724,7 @@
};
&uart2 {
status = "disablefd";
status = "disabled";
};
&usbotg1 {