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MLK-17586-1 ARM64: dts: imx7ulp-evk: add eMMC HS200 support for B0 chip

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USDHC internal IC data handle bug already fixed on i.MX7ULP B0, so add
HS200 support first.

To let HS200 work on i.MX7ULP REV A3 board, need to do the following
rework, otherwise, switch to HS200 will always meet error, caused by
the voltage change make eMMC work not stable, this rework fix the eMMC
I/O voltage to 1.8v, align with the MMC spec.
	1,remove TF sd slot, replace eMMC chip
	2,fix eMMC I/O voltage to 1.8v, remove R183, short TP3 and TP89
	3,add R107, make eMMC boot work

For i.MX7ULP REV B1 board, do not need this rework, board already fix the
eMMC I/O voltage to 1.8v

Acked-by: Dong Aisheng <aisheng.dong@nxp.com>
Signed-off-by: Haibo Chen <haibo.chen@nxp.com>
This commit is contained in:
Haibo Chen
2018-02-11 16:27:41 +08:00
committed by Jason Liu
parent e92e641d74
commit 45881df35c
2 changed files with 12 additions and 3 deletions
Download Patch File Download Diff File Expand all files Collapse all files

10
arch/arm/boot/dts/imx7ulp-evk-emmc.dts
View File

@ -1,5 +1,6 @@
/*
* Copyright (C) 2016 Freescale Semiconductor, Inc.
* Copyright 2018 NXP.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
@ -8,10 +9,17 @@
#include "imx7ulp-evk.dts"
/* To support eMMC HS200/HS400, need to do the following reowrk:
* 1,remove TF sd slot, replace eMMC chip
* 2,fix eMMC I/O voltage to 1.8v, remove R183, short TP3 and TP89
* 3,add R107, make eMMC boot work
*/
&usdhc0 {
pinctrl-names = "default", "sleep";
pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep";
pinctrl-0 = <&pinctrl_usdhc0_8bit>;
pinctrl-1 = <&pinctrl_usdhc0_8bit>;
pinctrl-2 = <&pinctrl_usdhc0_8bit>;
pinctrl-3 = <&pinctrl_usdhc0_8bit>;
non-removable;
bus-width = <8>;
status = "okay";

5
arch/arm/boot/dts/imx7ulp-evk.dts
View File

@ -263,7 +263,7 @@
pinctrl_usdhc0: usdhc0grp {
fsl,pins = <
IMX7ULP_PAD_PTD1__SDHC0_CMD 0x43
IMX7ULP_PAD_PTD2__SDHC0_CLK 0x10043
IMX7ULP_PAD_PTD2__SDHC0_CLK 0x10042
IMX7ULP_PAD_PTD7__SDHC0_D3 0x43
IMX7ULP_PAD_PTD8__SDHC0_D2 0x43
IMX7ULP_PAD_PTD9__SDHC0_D1 0x43
@ -276,7 +276,7 @@
pinctrl_usdhc0_8bit: usdhc0grp_8bit {
fsl,pins = <
IMX7ULP_PAD_PTD1__SDHC0_CMD 0x43
IMX7ULP_PAD_PTD2__SDHC0_CLK 0x43
IMX7ULP_PAD_PTD2__SDHC0_CLK 0x10042
IMX7ULP_PAD_PTD3__SDHC0_D7 0x43
IMX7ULP_PAD_PTD4__SDHC0_D6 0x43
IMX7ULP_PAD_PTD5__SDHC0_D5 0x43
@ -285,6 +285,7 @@
IMX7ULP_PAD_PTD8__SDHC0_D2 0x43
IMX7ULP_PAD_PTD9__SDHC0_D1 0x43
IMX7ULP_PAD_PTD10__SDHC0_D0 0x43
IMX7ULP_PAD_PTD11__SDHC0_DQS 0x42
>;
};