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MLK-14968-2 ARM64: dts: fsl-imx8: add usdhc1 support HS400 mode

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Add usdhc1 support for HS200/HS400 mode for imx8qm and imx8qxp.

Signed-off-by: Haibo Chen <haibo.chen@nxp.com>
This commit is contained in:
Haibo Chen
2017-05-23 19:46:06 +08:00
committed by Jason Liu
parent 75ad6545ff
commit 685f55b58d
4 changed files with 88 additions and 8 deletions
Download Patch File Download Diff File Expand all files Collapse all files

43
arch/arm64/boot/dts/freescale/fsl-imx8qm-lpddr4-arm2.dts
View File

@ -130,7 +130,7 @@
pinctrl_usdhc1: usdhc1grp {
fsl,pins = <
SC_P_EMMC0_CLK_CONN_EMMC0_CLK 0x06000021
SC_P_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041
SC_P_EMMC0_CMD_CONN_EMMC0_CMD 0x00000021
SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000021
SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000021
@ -140,13 +140,48 @@
SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000021
SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000021
SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000021
SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE 0x06000041
SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x00000021
>;
};
pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
fsl,pins = <
SC_P_EMMC0_CLK_CONN_EMMC0_CLK 0x06000045
SC_P_EMMC0_CMD_CONN_EMMC0_CMD 0x00000025
SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000025
SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000025
SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000025
SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000025
SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000025
SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000025
SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000025
SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000025
SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE 0x06000045
SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x00000021
>;
};
pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
fsl,pins = <
SC_P_EMMC0_CLK_CONN_EMMC0_CLK 0x06000047
SC_P_EMMC0_CMD_CONN_EMMC0_CMD 0x00000027
SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000027
SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000027
SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000027
SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000027
SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000027
SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000027
SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000027
SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000027
SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE 0x06000047
SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x00000021
>;
};
pinctrl_usdhc2: usdhc2grp {
fsl,pins = <
SC_P_USDHC1_CLK_CONN_USDHC1_CLK 0x06000021
SC_P_USDHC1_CLK_CONN_USDHC1_CLK 0x06000041
SC_P_USDHC1_CMD_CONN_USDHC1_CMD 0x00000021
SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0 0x00000021
SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1 0x00000021
@ -229,8 +264,10 @@
};
&usdhc1 {
pinctrl-names = "default";
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc1>;
pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
bus-width = <8>;
non-removable;
status = "okay";

5
arch/arm64/boot/dts/freescale/fsl-imx8qm.dtsi
View File

@ -1379,8 +1379,11 @@
<&clk IMX8QM_SDHC0_CLK>,
<&clk IMX8QM_CLK_DUMMY>;
clock-names = "ipg", "per", "ahb";
assigned-clock-rates = <400000000>, <200000000>, <0>;
assigned-clocks = <&clk IMX8QM_SDHC0_DIV>;
assigned-clock-rates = <400000000>;
power-domains = <&pd_conn_sdch0>;
fsl,tuning-start-tap = <20>;
fsl,tuning-step= <2>;
status = "disabled";
};

43
arch/arm64/boot/dts/freescale/fsl-imx8qxp-lpddr4-arm2.dts
View File

@ -107,7 +107,7 @@
pinctrl_usdhc1: usdhc1grp {
fsl,pins = <
SC_P_EMMC0_CLK_CONN_EMMC0_CLK 0x06000021
SC_P_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041
SC_P_EMMC0_CMD_CONN_EMMC0_CMD 0x00000021
SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000021
SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000021
@ -117,6 +117,41 @@
SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000021
SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000021
SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000021
SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE 0x06000041
SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x00000021
>;
};
pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
fsl,pins = <
SC_P_EMMC0_CLK_CONN_EMMC0_CLK 0x06000045
SC_P_EMMC0_CMD_CONN_EMMC0_CMD 0x00000025
SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000025
SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000025
SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000025
SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000025
SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000025
SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000025
SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000025
SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000025
SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE 0x06000045
SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x00000021
>;
};
pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
fsl,pins = <
SC_P_EMMC0_CLK_CONN_EMMC0_CLK 0x06000047
SC_P_EMMC0_CMD_CONN_EMMC0_CMD 0x00000027
SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000027
SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000027
SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000027
SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000027
SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000027
SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000027
SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000027
SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000027
SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE 0x06000047
SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x00000021
>;
};
@ -129,7 +164,7 @@
pinctrl_usdhc2: usdhc2grp {
fsl,pins = <
SC_P_USDHC1_CLK_CONN_USDHC1_CLK 0x06000021
SC_P_USDHC1_CLK_CONN_USDHC1_CLK 0x06000041
SC_P_USDHC1_CMD_CONN_USDHC1_CMD 0x06000021
SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0 0x06000021
SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1 0x06000021
@ -200,8 +235,10 @@
};
&usdhc1 {
pinctrl-names = "default";
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc1>;
pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
bus-width = <8>;
non-removable;
status = "okay";

5
arch/arm64/boot/dts/freescale/fsl-imx8qxp.dtsi
View File

@ -913,8 +913,11 @@
<&clk IMX8QXP_SDHC0_CLK>,
<&clk IMX8QXP_CLK_DUMMY>;
clock-names = "ipg", "per", "ahb";
assigned-clock-rates = <400000000>, <200000000>, <0>;
assigned-clocks = <&clk IMX8QXP_SDHC0_DIV>;
assigned-clock-rates = <400000000>;
power-domains = <&pd_conn_sdch0>;
fsl,tuning-start-tap = <20>;
fsl,tuning-step= <2>;
status = "disabled";
};