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MLK-18211 gpu: imx: layerblend: Zero sec alpha when sec input is from scaler

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It turns out that local alpha value of the secondary input is set to
0xFF by the hardware if the secondary input is from scaler(hscaler or
vscaler).  This makes the layer on this secondary input accidentally
cover the layer with higher z-order(if it exists), even though the
layer with lower z-order doesn't supply local alpha.  This patch zeros
the secondary local alpha value to prevent the issue from happening.
Users are unlikely to expect local alpha to be correctly scaled, so
it looks fine to simply zero the alpha.  If we find the unlikely case,
the KMS driver may later explicitly do atomic check to invalidate the case.

Signed-off-by: Liu Ying <victor.liu@nxp.com>
This commit is contained in:
Liu Ying
2018-05-07 13:53:35 +08:00
committed by Jason Liu
parent 540bbd0580
commit 70e26962a5
3 changed files with 7 additions and 5 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
drivers/gpu/drm/imx/dpu/dpu-plane.c
View File

@ -646,7 +646,7 @@ static void dpu_plane_atomic_update(struct drm_plane *plane,
layerblend_pixengcfg_dynamic_prim_sel(lb, dpstate->stage);
layerblend_pixengcfg_dynamic_sec_sel(lb, lb_src);
layerblend_control(lb, LB_BLEND);
layerblend_blendcontrol(lb);
layerblend_blendcontrol(lb, need_hscaler || need_vscaler);
layerblend_pixengcfg_clken(lb, CLKEN__AUTOMATIC);
layerblend_position(lb, dpstate->layer_x, dpstate->layer_y);

8
drivers/gpu/imx/dpu/dpu-layerblend.c
View File

@ -64,6 +64,7 @@ static const lb_prim_sel_t prim_sels[] = {
#define PRIM_A_BLD_FUNC__ONE_MINUS_SEC_ALPHA (0x5 << 8)
#define PRIM_A_BLD_FUNC__ZERO (0x0 << 8)
#define SEC_A_BLD_FUNC__ONE (0x1 << 12)
#define SEC_A_BLD_FUNC__ZERO (0x0 << 12)
#define POSITION 0x14
#define XPOS(x) ((x) & 0x7FFF)
#define YPOS(y) (((y) & 0x7FFF) << 16)
@ -236,15 +237,16 @@ void layerblend_control(struct dpu_layerblend *lb, lb_mode_t mode)
}
EXPORT_SYMBOL_GPL(layerblend_control);
void layerblend_blendcontrol(struct dpu_layerblend *lb)
void layerblend_blendcontrol(struct dpu_layerblend *lb, bool sec_from_scaler)
{
u32 val;
val = ALPHA(0xff) |
PRIM_C_BLD_FUNC__PRIM_ALPHA |
SEC_C_BLD_FUNC__ONE_MINUS_PRIM_ALPHA |
PRIM_A_BLD_FUNC__ZERO |
SEC_A_BLD_FUNC__ONE;
PRIM_A_BLD_FUNC__ZERO;
val |= sec_from_scaler ? SEC_A_BLD_FUNC__ZERO : SEC_A_BLD_FUNC__ONE;
mutex_lock(&lb->mutex);
dpu_lb_write(lb, val, BLENDCONTROL);

2
include/video/dpu.h
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@ -631,7 +631,7 @@ void layerblend_shden(struct dpu_layerblend *lb, bool enable);
void layerblend_shdtoksel(struct dpu_layerblend *lb, lb_shadow_sel_t sel);
void layerblend_shdldsel(struct dpu_layerblend *lb, lb_shadow_sel_t sel);
void layerblend_control(struct dpu_layerblend *lb, lb_mode_t mode);
void layerblend_blendcontrol(struct dpu_layerblend *lb);
void layerblend_blendcontrol(struct dpu_layerblend *lb, bool sec_from_scaler);
void layerblend_position(struct dpu_layerblend *lb, int x, int y);
u32 layerblend_last_control_word(struct dpu_layerblend *lb);
void layerblend_pixel_cnt(struct dpu_layerblend *lb, u16 *x, u16 *y);