MLK-15052-3: mtd: spi-nor: enable octal read mode in spi framework
Enhanced spi-nor framework to support octal read mode Signed-off-by: Han Xu <han.xu@nxp.com> Acked-by: Frank Li <frank.li@nxp.com>
This commit is contained in:
@ -77,6 +77,7 @@ struct flash_info {
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* SPI_NOR_HAS_LOCK.
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*/
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#define SPI_NOR_DDR_QUAD_READ BIT(10) /* Flash supports DDR Quad Read */
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#define SPI_NOR_DDR_OCTAL_READ BIT(11) /* Flash supports DDR Octal Read */
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};
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#define JEDEC_MFR(info) ((info)->id[0])
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@ -149,6 +150,7 @@ static inline int spi_nor_read_dummy_cycles(struct spi_nor *nor)
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{
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switch (nor->flash_read) {
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case SPI_NOR_DDR_QUAD:
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case SPI_NOR_DDR_OCTAL:
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{
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struct device_node *np = spi_nor_get_flash_node(nor);
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u32 dummy;
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@ -161,11 +163,13 @@ static inline int spi_nor_read_dummy_cycles(struct spi_nor *nor)
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*/
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if (!of_property_read_u32(np, "spi-nor,ddr-quad-read-dummy",
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&dummy))
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pr_err("DUMMY CYCLE : %d !!!\n", dummy);
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return dummy;
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}
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case SPI_NOR_FAST:
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case SPI_NOR_DUAL:
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case SPI_NOR_QUAD:
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case SPI_NOR_OCTAL:
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return 8;
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case SPI_NOR_NORMAL:
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return 0;
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@ -907,6 +911,7 @@ static const struct flash_info spi_nor_ids[] = {
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{ "n25q512ax3", INFO(0x20ba20, 0, 64 * 1024, 1024, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ) },
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{ "n25q00", INFO(0x20ba21, 0, 64 * 1024, 2048, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ) },
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{ "n25q00a", INFO(0x20bb21, 0, 64 * 1024, 2048, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ) },
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{"mt35xu512aba", INFO(0x2c5b1a, 0, 128 * 1024, 512, SECT_4K | SPI_NOR_DDR_OCTAL_READ) },
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/* PMC */
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{ "pm25lv512", INFO(0, 0, 32 * 1024, 2, SECT_4K_PMC) },
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@ -1486,8 +1491,11 @@ int spi_nor_scan(struct spi_nor *nor, const char *name, enum read_mode mode)
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if (info->flags & SPI_NOR_NO_FR)
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nor->flash_read = SPI_NOR_NORMAL;
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/* DDR Quad/Quad/Dual-read mode takes precedence over fast/normal */
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if (mode == SPI_NOR_DDR_QUAD && info->flags & SPI_NOR_DDR_QUAD_READ) {
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/* DDR Octal/Quad/Dual-read mode takes precedence over fast/normal */
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if (mode == SPI_NOR_DDR_OCTAL && info->flags & SPI_NOR_DDR_OCTAL_READ) {
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nor->flash_read = SPI_NOR_DDR_OCTAL;
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} else if (mode == SPI_NOR_DDR_QUAD &&
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info->flags & SPI_NOR_DDR_QUAD_READ) {
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ret = set_ddr_quad_mode(nor, info);
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if (ret) {
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dev_err(dev, "DDR quad mode not supported\n");
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@ -1507,6 +1515,9 @@ int spi_nor_scan(struct spi_nor *nor, const char *name, enum read_mode mode)
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/* Default commands */
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switch (nor->flash_read) {
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case SPI_NOR_DDR_OCTAL:
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nor->read_opcode = SPINOR_OP_READ_1_1_8_D;
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break;
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case SPI_NOR_DDR_QUAD:
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if (JEDEC_MFR(info) == CFI_MFR_AMD) { /* Spansion */
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nor->read_opcode = SPINOR_OP_READ_1_4_4_D;
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@ -1546,6 +1557,10 @@ int spi_nor_scan(struct spi_nor *nor, const char *name, enum read_mode mode)
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if (JEDEC_MFR(info) == SNOR_MFR_SPANSION) {
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/* Dedicated 4-byte command set */
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switch (nor->flash_read) {
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case SPI_NOR_DDR_OCTAL:
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case SPI_NOR_OCTAL:
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nor->read_opcode = SPINOR_OP_READ_1_1_8_D;
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break;
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case SPI_NOR_DDR_QUAD:
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nor->read_opcode = SPINOR_OP_READ4_1_4_4_D;
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break;
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@ -46,8 +46,9 @@
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#define SPINOR_OP_READ_FAST 0x0b /* Read data bytes (high frequency) */
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#define SPINOR_OP_READ_1_1_2 0x3b /* Read data bytes (Dual SPI) */
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#define SPINOR_OP_READ_1_1_4 0x6b /* Read data bytes (Quad SPI) */
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#define SPINOR_OP_READ_1_1_4_D 0x6d /* Read data bytes (DDR Quad SPI) */
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#define SPINOR_OP_READ_1_4_4_D 0xed /* Read data bytes (DDR Quad SPI) */
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#define SPINOR_OP_READ_1_1_4_D 0x6d /* Read data bytes (DDR Quad SPI) */
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#define SPINOR_OP_READ_1_4_4_D 0xed /* Read data bytes (DDR Quad SPI) */
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#define SPINOR_OP_READ_1_1_8_D 0x9d /* Read data bytes (Octal Output SPI) */
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#define SPINOR_OP_PP 0x02 /* Page program (up to 256 bytes) */
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#define SPINOR_OP_BE_4K 0x20 /* Erase 4KiB block */
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#define SPINOR_OP_BE_4K_PMC 0xd7 /* Erase 4KiB block on PMC chips */
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@ -63,7 +64,7 @@
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#define SPINOR_OP_READ4_FAST 0x0c /* Read data bytes (high frequency) */
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#define SPINOR_OP_READ4_1_1_2 0x3c /* Read data bytes (Dual SPI) */
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#define SPINOR_OP_READ4_1_1_4 0x6c /* Read data bytes (Quad SPI) */
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#define SPINOR_OP_READ4_1_4_4_D 0xee /* Read data bytes (DDR Quad SPI) */
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#define SPINOR_OP_READ4_1_4_4_D 0xee /* Read data bytes (DDR Quad SPI) */
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#define SPINOR_OP_PP_4B 0x12 /* Page program (up to 256 bytes) */
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#define SPINOR_OP_SE_4B 0xdc /* Sector erase (usually 64KiB) */
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@ -112,6 +113,8 @@ enum read_mode {
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SPI_NOR_DUAL,
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SPI_NOR_QUAD,
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SPI_NOR_DDR_QUAD,
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SPI_NOR_OCTAL,
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SPI_NOR_DDR_OCTAL,
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};
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#define SPI_NOR_MAX_CMD_SIZE 8
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