MLK-17147 arm64: dts: imx8mq: Add DDR3l and DDR4 ARM2 boards support
Add two DTS files for supporting DDR3l and DDR4 ARM2 boards. Basic nodes like UART, SD/eMMC, i2c, Ethernet are added. Signed-off-by: Ye Li <ye.li@nxp.com> Reviewed-by: Bai Ping <ping.bai@nxp.com> Skipped &qspi during 4.14 rebase because quadspi was skipped Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com>
This commit is contained in:
Ye Li
@ -58,7 +58,9 @@ dtb-$(CONFIG_ARCH_FSL_IMX8QXP) += fsl-imx8qxp-lpddr4-arm2.dtb \
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fsl-imx8qxp-lpddr4-arm2-wm8962.dtb \
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fsl-imx8qxp-lpddr4-arm2-dsi-adv7535.dtb \
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fsl-imx8qxp-lpddr4-arm2-dsi-rm67191.dtb
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dtb-$(CONFIG_ARCH_FSL_IMX8MQ) += fsl-imx8mq-evk.dtb \
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dtb-$(CONFIG_ARCH_FSL_IMX8MQ) += fsl-imx8mq-ddr3l-arm2.dtb \
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fsl-imx8mq-ddr4-arm2.dtb \
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fsl-imx8mq-evk.dtb \
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fsl-imx8mq-evk-m4.dtb \
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fsl-imx8mq-evk-pcie1-m2.dtb \
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fsl-imx8mq-evk-lcdif-adv7535.dtb \
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354
arch/arm64/boot/dts/freescale/fsl-imx8mq-ddr3l-arm2.dts
Normal file
354
arch/arm64/boot/dts/freescale/fsl-imx8mq-ddr3l-arm2.dts
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@ -0,0 +1,354 @@
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/*
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* Copyright 2017 NXP
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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/dts-v1/;
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#include "fsl-imx8mq.dtsi"
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/ {
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model = "Freescale i.MX8MQ DDR3L ARM2";
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compatible = "fsl,imx8mq-evk", "fsl,imx8mq";
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chosen {
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bootargs = "console=ttymxc0,115200 earlycon=ec_imx6q,0x30860000,115200";
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stdout-path = &uart1;
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};
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regulators {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <0>;
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reg_usdhc2_vmmc: usdhc2_vmmc {
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compatible = "regulator-fixed";
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regulator-name = "VSD_3V3";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
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enable-active-high;
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};
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};
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busfreq {
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status = "disabled";
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};
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};
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&iomuxc {
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pinctrl-names = "default";
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imx8mq-arm2 {
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pinctrl_fec1: fec1grp {
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fsl,pins = <
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MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC 0x3
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MX8MQ_IOMUXC_ENET_MDIO_ENET1_MDIO 0x23
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MX8MQ_IOMUXC_ENET_TD2_ENET1_TX_CLK 0x4000001f
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MX8MQ_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x56
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MX8MQ_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x56
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MX8MQ_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x56
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MX8MQ_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x56
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MX8MQ_IOMUXC_ENET_RXC_ENET1_RX_ER 0x56
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MX8MQ_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x56
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MX8MQ_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x56
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>;
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};
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pinctrl_i2c1: i2c1grp {
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fsl,pins = <
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MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL 0x4000007f
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MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA 0x4000007f
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>;
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};
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pinctrl_i2c2: i2c2grp {
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fsl,pins = <
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MX8MQ_IOMUXC_I2C2_SCL_I2C2_SCL 0x4000007f
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MX8MQ_IOMUXC_I2C2_SDA_I2C2_SDA 0x4000007f
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>;
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};
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pinctrl_qspi: qspigrp {
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fsl,pins = <
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MX8MQ_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x82
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MX8MQ_IOMUXC_NAND_CLE_QSPI_B_SCLK 0x82
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MX8MQ_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x82
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MX8MQ_IOMUXC_NAND_CE2_B_QSPI_B_SS0_B 0x82
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MX8MQ_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x82
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MX8MQ_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x82
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MX8MQ_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x82
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MX8MQ_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x82
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MX8MQ_IOMUXC_NAND_DATA04_QSPI_B_DATA0 0x82
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MX8MQ_IOMUXC_NAND_DATA05_QSPI_B_DATA1 0x82
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MX8MQ_IOMUXC_NAND_DATA06_QSPI_B_DATA2 0x82
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MX8MQ_IOMUXC_NAND_DATA07_QSPI_B_DATA3 0x82
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>;
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};
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pinctrl_uart1: uart1grp {
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fsl,pins = <
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MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX 0x79
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MX8MQ_IOMUXC_UART1_TXD_UART1_DCE_TX 0x79
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>;
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};
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pinctrl_usdhc1: usdhc1grp {
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fsl,pins = <
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MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x83
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MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc3
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MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc3
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MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc3
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MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc3
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MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc3
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MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc3
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MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc3
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MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc3
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MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc3
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MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x83
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MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1
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>;
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};
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pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
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fsl,pins = <
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MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x85
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MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc5
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MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc5
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MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc5
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MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc5
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MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc5
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MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc5
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MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc5
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MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc5
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MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc5
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MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x85
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MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1
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>;
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};
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pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
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fsl,pins = <
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MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x87
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MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc7
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MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc7
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MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc7
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MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc7
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MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc7
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MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc7
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MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc7
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MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc7
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MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc7
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MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x87
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MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1
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>;
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};
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pinctrl_usdhc2_gpio: usdhc2grpgpio {
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fsl,pins = <
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MX8MQ_IOMUXC_SD2_CD_B_GPIO2_IO12 0x41
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MX8MQ_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41
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>;
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};
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pinctrl_usdhc2: usdhc2grp {
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fsl,pins = <
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MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x83
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MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc3
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MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc3
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MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc3
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MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc3
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MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc3
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MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1
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>;
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};
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pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
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fsl,pins = <
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MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x85
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MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc5
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MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc5
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MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc5
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MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc5
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MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc5
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MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1
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>;
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};
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pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
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fsl,pins = <
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MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x87
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MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc7
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MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc7
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MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc7
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MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc7
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MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc7
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MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1
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>;
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};
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};
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};
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&fec1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_fec1>;
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phy-mode = "rmii";
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phy-handle = <ðphy0>;
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fsl,magic-packet;
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assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_266M>,
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<&clk IMX8MQ_SYS2_PLL_100M>,
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<&clk IMX8MQ_SYS2_PLL_50M>;
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assigned-clock-rates = <0>, <0>, <50000000>, <100000000>;
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status = "okay";
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mdio {
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#address-cells = <1>;
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#size-cells = <0>;
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ethphy0: ethernet-phy@0 {
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compatible = "ethernet-phy-ieee802.3-c22";
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reg = <3>;
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};
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};
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};
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&i2c1 {
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clock-frequency = <100000>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_i2c1>;
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status = "okay";
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pmic: pfuze100@08 {
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compatible = "fsl,pfuze100";
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reg = <0x08>;
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regulators {
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sw1a_reg: sw1ab {
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regulator-min-microvolt = <300000>;
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regulator-max-microvolt = <1875000>;
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regulator-always-on;
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};
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sw1c_reg: sw1c {
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regulator-min-microvolt = <300000>;
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regulator-max-microvolt = <1875000>;
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regulator-always-on;
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};
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sw2_reg: sw2 {
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regulator-min-microvolt = <800000>;
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regulator-max-microvolt = <3300000>;
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regulator-always-on;
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};
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sw3a_reg: sw3ab {
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regulator-min-microvolt = <400000>;
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regulator-max-microvolt = <1975000>;
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regulator-always-on;
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};
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sw4_reg: sw4 {
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regulator-min-microvolt = <800000>;
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regulator-max-microvolt = <3300000>;
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regulator-always-on;
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};
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swbst_reg: swbst {
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regulator-min-microvolt = <5000000>;
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regulator-max-microvolt = <5150000>;
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};
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snvs_reg: vsnvs {
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regulator-min-microvolt = <1000000>;
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regulator-max-microvolt = <3000000>;
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regulator-always-on;
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};
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vref_reg: vrefddr {
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regulator-always-on;
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};
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vgen1_reg: vgen1 {
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regulator-min-microvolt = <800000>;
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regulator-max-microvolt = <1550000>;
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};
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vgen2_reg: vgen2 {
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regulator-min-microvolt = <800000>;
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regulator-max-microvolt = <1550000>;
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regulator-always-on;
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};
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vgen3_reg: vgen3 {
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <3300000>;
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regulator-always-on;
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};
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vgen4_reg: vgen4 {
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <3300000>;
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regulator-always-on;
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};
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vgen5_reg: vgen5 {
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <3300000>;
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regulator-always-on;
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};
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vgen6_reg: vgen6 {
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <3300000>;
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};
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};
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};
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};
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&i2c2 {
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clock-frequency = <100000>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_i2c2>;
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status = "okay";
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};
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&uart1 { /* console */
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_uart1>;
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assigned-clocks = <&clk IMX8MQ_CLK_UART1_SRC>;
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assigned-clock-parents = <&clk IMX8MQ_CLK_25M>;
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status = "okay";
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};
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&usdhc1 {
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pinctrl-names = "default", "state_100mhz", "state_200mhz";
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pinctrl-0 = <&pinctrl_usdhc1>;
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pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
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pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
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bus-width = <8>;
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non-removable;
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status = "okay";
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};
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&usdhc2 {
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pinctrl-names = "default", "state_100mhz", "state_200mhz";
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pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
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pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
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pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
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bus-width = <4>;
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cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
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vmmc-supply = <®_usdhc2_vmmc>;
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status = "okay";
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};
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350
arch/arm64/boot/dts/freescale/fsl-imx8mq-ddr4-arm2.dts
Normal file
350
arch/arm64/boot/dts/freescale/fsl-imx8mq-ddr4-arm2.dts
Normal file
@ -0,0 +1,350 @@
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/*
|
||||
* Copyright 2017 NXP
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License
|
||||
* as published by the Free Software Foundation; either version 2
|
||||
* of the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "fsl-imx8mq.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Freescale i.MX8MQ DDR4 ARM2";
|
||||
compatible = "fsl,imx8mq-evk", "fsl,imx8mq";
|
||||
|
||||
chosen {
|
||||
bootargs = "console=ttymxc0,115200 earlycon=ec_imx6q,0x30860000,115200";
|
||||
stdout-path = &uart1;
|
||||
};
|
||||
|
||||
regulators {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
reg_usdhc2_vmmc: usdhc2_vmmc {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "VSD_3V3";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
|
||||
enable-active-high;
|
||||
};
|
||||
};
|
||||
|
||||
busfreq {
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
&iomuxc {
|
||||
pinctrl-names = "default";
|
||||
|
||||
imx8mq-arm2 {
|
||||
pinctrl_fec1: fec1grp {
|
||||
fsl,pins = <
|
||||
MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC 0x3
|
||||
MX8MQ_IOMUXC_ENET_MDIO_ENET1_MDIO 0x23
|
||||
MX8MQ_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
|
||||
MX8MQ_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
|
||||
MX8MQ_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
|
||||
MX8MQ_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
|
||||
MX8MQ_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
|
||||
MX8MQ_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
|
||||
MX8MQ_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
|
||||
MX8MQ_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
|
||||
MX8MQ_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
|
||||
MX8MQ_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
|
||||
MX8MQ_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
|
||||
MX8MQ_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
|
||||
MX8MQ_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x19
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_i2c1: i2c1grp {
|
||||
fsl,pins = <
|
||||
MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL 0x4000007f
|
||||
MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA 0x4000007f
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_i2c2: i2c2grp {
|
||||
fsl,pins = <
|
||||
MX8MQ_IOMUXC_I2C2_SCL_I2C2_SCL 0x4000007f
|
||||
MX8MQ_IOMUXC_I2C2_SDA_I2C2_SDA 0x4000007f
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_uart1: uart1grp {
|
||||
fsl,pins = <
|
||||
MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX 0x79
|
||||
MX8MQ_IOMUXC_UART1_TXD_UART1_DCE_TX 0x79
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc1: usdhc1grp {
|
||||
fsl,pins = <
|
||||
MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x83
|
||||
MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc3
|
||||
MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc3
|
||||
MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc3
|
||||
MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc3
|
||||
MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc3
|
||||
MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc3
|
||||
MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc3
|
||||
MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc3
|
||||
MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc3
|
||||
MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x83
|
||||
MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
|
||||
fsl,pins = <
|
||||
MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x85
|
||||
MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc5
|
||||
MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc5
|
||||
MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc5
|
||||
MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc5
|
||||
MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc5
|
||||
MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc5
|
||||
MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc5
|
||||
MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc5
|
||||
MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc5
|
||||
MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x85
|
||||
MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
|
||||
fsl,pins = <
|
||||
MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x87
|
||||
MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc7
|
||||
MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc7
|
||||
MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc7
|
||||
MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc7
|
||||
MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc7
|
||||
MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc7
|
||||
MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc7
|
||||
MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc7
|
||||
MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc7
|
||||
MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x87
|
||||
MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc2_gpio: usdhc2grpgpio {
|
||||
fsl,pins = <
|
||||
MX8MQ_IOMUXC_SD2_CD_B_GPIO2_IO12 0x41
|
||||
MX8MQ_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc2: usdhc2grp {
|
||||
fsl,pins = <
|
||||
MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x83
|
||||
MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc3
|
||||
MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc3
|
||||
MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc3
|
||||
MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc3
|
||||
MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc3
|
||||
MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
|
||||
fsl,pins = <
|
||||
MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x85
|
||||
MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc5
|
||||
MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc5
|
||||
MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc5
|
||||
MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc5
|
||||
MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc5
|
||||
MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
|
||||
fsl,pins = <
|
||||
MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x87
|
||||
MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc7
|
||||
MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc7
|
||||
MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc7
|
||||
MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc7
|
||||
MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc7
|
||||
MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_wdog: wdoggrp {
|
||||
fsl,pins = <
|
||||
MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6
|
||||
>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&fec1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_fec1>;
|
||||
phy-mode = "rgmii-id";
|
||||
phy-handle = <ðphy0>;
|
||||
fsl,magic-packet;
|
||||
status = "okay";
|
||||
|
||||
mdio {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
ethphy0: ethernet-phy@0 {
|
||||
compatible = "ethernet-phy-ieee802.3-c22";
|
||||
reg = <0>;
|
||||
at803x,led-act-blind-workaround;
|
||||
at803x,eee-disabled;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&i2c1 {
|
||||
clock-frequency = <100000>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_i2c1>;
|
||||
status = "okay";
|
||||
|
||||
pmic: pfuze100@08 {
|
||||
compatible = "fsl,pfuze100";
|
||||
reg = <0x08>;
|
||||
|
||||
regulators {
|
||||
sw1a_reg: sw1ab {
|
||||
regulator-min-microvolt = <300000>;
|
||||
regulator-max-microvolt = <1875000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
sw1c_reg: sw1c {
|
||||
regulator-min-microvolt = <300000>;
|
||||
regulator-max-microvolt = <1875000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
sw2_reg: sw2 {
|
||||
regulator-min-microvolt = <800000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
sw3a_reg: sw3ab {
|
||||
regulator-min-microvolt = <400000>;
|
||||
regulator-max-microvolt = <1975000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
sw4_reg: sw4 {
|
||||
regulator-min-microvolt = <800000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
swbst_reg: swbst {
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5150000>;
|
||||
};
|
||||
|
||||
snvs_reg: vsnvs {
|
||||
regulator-min-microvolt = <1000000>;
|
||||
regulator-max-microvolt = <3000000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vref_reg: vrefddr {
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vgen1_reg: vgen1 {
|
||||
regulator-min-microvolt = <800000>;
|
||||
regulator-max-microvolt = <1550000>;
|
||||
};
|
||||
|
||||
vgen2_reg: vgen2 {
|
||||
regulator-min-microvolt = <800000>;
|
||||
regulator-max-microvolt = <1550000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vgen3_reg: vgen3 {
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vgen4_reg: vgen4 {
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vgen5_reg: vgen5 {
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vgen6_reg: vgen6 {
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&i2c2 {
|
||||
clock-frequency = <100000>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_i2c2>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart1 { /* console */
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_uart1>;
|
||||
assigned-clocks = <&clk IMX8MQ_CLK_UART1_SRC>;
|
||||
assigned-clock-parents = <&clk IMX8MQ_CLK_25M>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usdhc1 {
|
||||
pinctrl-names = "default", "state_100mhz", "state_200mhz";
|
||||
pinctrl-0 = <&pinctrl_usdhc1>;
|
||||
pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
|
||||
pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
|
||||
bus-width = <8>;
|
||||
non-removable;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usdhc2 {
|
||||
pinctrl-names = "default", "state_100mhz", "state_200mhz";
|
||||
pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
|
||||
pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
|
||||
pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
|
||||
bus-width = <4>;
|
||||
cd-gpios = <&gpio2 12 GPIO_ACTIVE_HIGH>;
|
||||
vmmc-supply = <®_usdhc2_vmmc>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&wdog1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_wdog>;
|
||||
fsl,ext-reset-output;
|
||||
status = "okay";
|
||||
};
|
||||
Reference in New Issue
Block a user