MLK-18222: CI_PI: fix CI_PI lost half of frame issue

As IC team recommended, it is better to set vsync pulse
width as 2 lines pixels, otherwise ISI will lost half
of frames.

Signed-off-by: Guoniu.Zhou <guoniu.zhou@nxp.com>
Reviewed-by: Sandor.Yu <sandor.yu@nxp.com>
This commit is contained in:
Guoniu.Zhou
2018-05-08 09:36:47 +08:00
committed by Jason Liu
parent 3820965172
commit d310398f65

View File

@ -193,7 +193,7 @@ static void mxc_pcsi_config_ctrl_reg1(struct mxc_parallel_csi_dev *pcsidev)
/* Config Pixel Width */
val = (CSI_CTRL_REG1_PIXEL_WIDTH(pcsidev->format.width - 1) |
CSI_CTRL_REG1_VSYNC_PULSE(3));
CSI_CTRL_REG1_VSYNC_PULSE(pcsidev->format.width << 1));
writel(val, pcsidev->csr_regs + CSI_CTRL_REG1);
}