MLK-18222: CI_PI: fix CI_PI lost half of frame issue
As IC team recommended, it is better to set vsync pulse width as 2 lines pixels, otherwise ISI will lost half of frames. Signed-off-by: Guoniu.Zhou <guoniu.zhou@nxp.com> Reviewed-by: Sandor.Yu <sandor.yu@nxp.com>
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@ -193,7 +193,7 @@ static void mxc_pcsi_config_ctrl_reg1(struct mxc_parallel_csi_dev *pcsidev)
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/* Config Pixel Width */
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val = (CSI_CTRL_REG1_PIXEL_WIDTH(pcsidev->format.width - 1) |
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CSI_CTRL_REG1_VSYNC_PULSE(3));
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CSI_CTRL_REG1_VSYNC_PULSE(pcsidev->format.width << 1));
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writel(val, pcsidev->csr_regs + CSI_CTRL_REG1);
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}
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