Commit Graph

5 Commits

Author SHA1 Message Date
5e276c76c4 MLK-18381-1 ARM64: dts: imx8mm: enable rpmsg
enable rpmsg on imx8mm

Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
2019-02-12 10:31:50 +08:00
7e6a686ac1 MLK-16938 ARM64: dts: imx8: refine the imx8 dts
- Add the clk_req property for imx8 pcie, make sure that
the clk_req would be active.
- Correct the spell mistake of pcie pinctrl on imx8qxp.
- Fix the potential conflication with the usage of SC MU,
remove the useless "fsl,imx8-mu" of rpmsg.

Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
2019-02-12 10:29:22 +08:00
1568dedc98 MLK-16586-2 ARM64: dts: imx: enable multi-core rpmsg support
Because there are two m4 cores on imx8qm,
enable imx8qm multi-core rpmsg support

BuildInfo:
- SCFW a6fd9a48, IMX-MKIMAGE 0, ATF 0
- U-Boot 2017.03-imx_v2017.03_4.9.11_imx8_alpha+g258936c

Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
Reviewed-by: Robin Gong <yibin.gong@nxp.com>
Reviewed-by: Dong Aisheng <aisheng.dong@nxp.com>
Reviewed-by: Andy Duan <fugang.duan@nxp.com>
Tested-by: Andy Duan <fugang.duan@nxp.com>
2019-02-12 10:28:48 +08:00
66ad1a15ca MLK-16371-1 arm64: dts: imx8qxp: add the rpmsg support
add the rpmsg support for imx8qxp.
Based on intmux, the int31 of mu0_a0 of m4 side is
used by rpmsg.

Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
2019-02-12 10:28:28 +08:00
85aef431ff MLK-14439-3 rpmsg: imx: setup the imx rpmsg driver
- move imx_rpmsg from arch/arm/ to drivers/rpmsg.
- use the new MU generic APIs in the rpmsg implementation.
- Validated the pingpong test on both imx6sx and imx7d sdb boards.

Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
2019-02-12 10:25:57 +08:00