According to ADD, the audio ahb and ipg clock should be in 1:1 mode
and the frequency is 400MHz
Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com>
Reviewed-by: Viorel Suman <viorel.suman@nxp.com>
(cherry picked from commit ee175a8cea1a7d27954a73c3447bb16edd71f4c8)
With the 800M clock source, there is noise on SAI5 (PDM, or AK5558)
recording with some chips, but it may be ok for other chips.
The reason is not clear.
This patch is to switch the clock source to 500M.
Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com>
(cherry picked from commit 3f4e34d26ceb8569eeb6cbb2e5a410d0332a9e62)
Need use LPCG_BASE to wrap the lpcg gate, otherwise XEN DomU
will dump when doing ioremap for the lpcgs, because the lpcg
conflicts with DomU RAM space.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
(cherry picked from commit caf4564bf4fe70fc6466ce18a84b5c73c80d21a0)
Signed-off-by: Daniel Baluta <daniel.baluta@nxp.com>
Reviewed-by: Shengjiu Wang <shengjiu.wang@nxp.com>
(cherry picked from commit 8bc09ad559237c136f88d93bd696fe10dc4658db)
Removed the IMX8QM_HDMI_AV_PLL_BYPASS_CLK because it is not supported by SCFW.
Changed the selector array to use the IMX8QM_HDMI_AV_PLL_CLK as the bypass parent.
Signed-off-by: Oliver Brown <oliver.brown@nxp.com>
Add a new init-on-array property, the clk driver will
parse this array and prepare enable the related clocks.
Previously, the clocks needs to be init on are hardcoded in SoC
clk driver. When we need to support two OSes, some clks
needs to be ini on, however such clocks does not need to be init on
for Single Linux OS environment.
At current stage using Jailhouse hypervisor supporting Two Linux OS,
OS1 use SDHC2, OS2 use SDHC3, they share one IMX8MM_CLK_NAND_USDHC_BUS_CG,
because no power management supported, so we need clk_ignore_unused
and make sure this clk being enabled, to make sure the 2nd OS
could has SDHC3 working.
The i.MX8MQ also has same code, but there is no good place to hold
it in common place, so duplicate it clk-imx8mm.c for now.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
(cherry picked from commit 58d25fb00099142f15bcf2a66432b25da75ef38e)
Remove unused ROMCP clks and related as LPCG
no longer exists
Signed-off-by: Teo Hall <teo.hall@nxp.com>
Reviewed-by: Anson Huang <Anson.Huang@nxp.com>
(cherry picked from commit 1c15332dffe7e41f0b9d367b96dd426798ec8b06)
No need to enable IMX7D_NAND_USDHC_BUS_ROOT_CLK during the imx7d clock
driver init, so remove it from the clks_init_on[].
Signed-off-by: Haibo Chen <haibo.chen@nxp.com>
(cherry picked from commit d63d8a2d501ddc93a3406111134242090a713c4a)
No need to enable IMX8MQ_CLK_NAND_USDHC_BUS_CG during the imx8mq clock driver
init, so remove it from the clks_init_on[].
Signed-off-by: Haibo Chen <haibo.chen@nxp.com>
(cherry picked from commit 6c90e1bfc38eab27921d26b1218993e5cd52a425)
No need to enable IMX8MM_CLK_NAND_USDHC_BUS_CG during the imx8mm clock driver
init, so remove it from the clks_init_on[].
Signed-off-by: Haibo Chen <haibo.chen@nxp.com>
(cherry picked from commit 7a8f9c1917dec30fc37b6b8ea74461e80ecdbc30)
No need to enable IMX8MQ_CLK_AUDIO_AHB_DIV during imx8mq clock
driver init, so remove it from the clks_init_on[].
Signed-off-by: Viorel Suman <viorel.suman@nxp.com>
(cherry picked from commit b13900ec3296f579f54581483858cc053d2bbff3)
No fail when no no_acm node. We do not have np_acm node
for the 2nd OS, so let's ignore np_acm.
Also we use partition for the 2nd OS, the registeration of some
clocks are not owned by the 2nd OS, so it will return -ENODEV.
Let's suppress the error message for -ENODEV.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Bai Ping <ping.bai@nxp.com>
(cherry picked from commit 39d196d84ed80237d0d9e669965903c785146727)
Add a new init-on-array property, the clk driver will
parse this array and prepare enable the related clocks.
Previously, the clocks needs to be init on are hardcoded in SoC
clk driver. When we need to support two OSes, some clks
needs to be ini on, however such clocks does not need to be init on
for Single Linux OS environment.
At current stage using Jailhouse hypervisor supporting Two Linux OS,
OS1 use SDHC2, OS2 use SDHC0, they share one IMX8MQ_CLK_NAND_USDHC_BUS_CG,
because no power management supported, so we need clk_ignore_unused
and make sure this clk being enabled, to make sure the 2nd OS
could has SDHC0 working.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Bai Ping <ping.bai@nxp.com>
(cherry picked from commit 9e6e0ffe8876d5f52ee372ec438ab30ef01c4a5d)
On i.MX8MM, it has an dram_alt clock source that can be used when
DDRC clock rate is lower than 667MHz, so add this clock.
Signed-off-by: Bai Ping <ping.bai@nxp.com>
Reviewed-by: Anson Huang <Anson.Huang@nxp.com>
(cherry picked from commit 303867c769e3c0758b9ee8fcf31d8cc3c632a80d)
Add LCDIF PLL resource and clocks, and power domain for it.
Add Pixel link clocks and set it from bypass path.
Muxes were added so that the slices can choose the bypass input
(lcd_pxl_bypass_div and elcdif_pll_div).
clk summary example:
lcd_pxl_bypass_div 2 2 24000000
lcd_pxl_sel 1 1 24000000
lcd_pxl_div 1 1 24000000
lcd_pxl_clk 1 1 24000000
elcdif_pll_div 1 1 792000000
elcdif_pll 2 2 792000000
lcd_sel 1 1 792000000
lcd_div 1 1 79200000
lcd_clk 1 1 79200000
Signed-off-by: Adriana Reus <adriana.reus@nxp.com>
correct the clock name typo.
change the MCLK to use osc_24m.
remove unnecessary rate setting for MCLK in dts file.
Signed-off-by: Robby Cai <robby.cai@nxp.com>
In order to replace the M4_MU# by the LSIO MU in the
RPMSG usage.
Define the clocks of the LSIO MU for iMX8
Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
Correct the power domain of the phyx1 per clk.
Otherwise, the system would be hang when SATA is not
built-in in the kernel config.
Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
This patch adds the MIPI PWM_DIV and PWM_CLK clock definitions.
The PWM_DIV clock is the parent clock of PWM_CLK clock.
The PWM_CLK will be used as the 'per' clock by the PWM driver.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
(cherry picked from commit a32d7b4bcca3da7bd154eaf46cf04852279d2c87)
The bit index of MIPI PWM IPG/IPG_S gate clocks in the LPCG register
is 16 instead of 0. This patch corrects the bit index.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
(cherry picked from commit 43cbe1a1dfcd3fa7bc7d41996d1b9b77d3fd3f3e)
The 'ipg_audio_root' clk rate must be 400MHz according to ADD.
Set SAI2/SAI3 IPG clk parent as 'ipg_audio_root' according to ADD.
Signed-off-by: Viorel Suman <viorel.suman@nxp.com>
(cherry picked from commit cbac7bbea2953e9cba0a9f6a6a84333ca85c5109)
External differential clock phy_27m can be set to all
plls, rename from VIDEO2_PHY_27M to CLK_PHY_27M to avoid
confusion as clock source is the same option for all plls
Signed-off-by: Adrian Alonso <adrian.alonso@nxp.com>
Reviewed-by: Laurentiu Palcu <laurentiu.palcu@nxp.com>
(cherry picked from commit 513eb64189903ca24c7f5ae140703831159b0578)
The 'video_pll1' PLL will be used as LCDIF pixel clock
source, and also used as MIPI DSI PHY reference clock
source. And 594MHz clock rate is better to derive the
27MHz PHY reference clock and the LCDIF pixel clocks
requied for most popular display modes.
Signed-off-by: Fancy Fang <chen.fang@nxp.com>
Change pixel clock register of qxp PI ss in order to
accommodate scfw change for PI ss
Signed-off-by: Guoniu.Zhou <guoniu.zhou@nxp.com>
(cherry picked from commit 1a769a426f)
Add 594MHz config support for video pll on imx8mm. lcdif
driver need this frequency setpoint.
Signed-off-by: Bai Ping <ping.bai@nxp.com>
Reviewed-by: Anson Huang <Anson.Huang@nxp.com>
Remove CSI0/1 GPIO related clocks to make sure all
GPIOs clocks are always ON.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Reviewed-by: Bai Ping <ping.bai@nxp.com>
Remove all GPIOs LPCG clock definition to make sure they
are always ON by SCFW default setting.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Reviewed-by: Bai Ping <ping.bai@nxp.com>
Tested-by: Peng Fan <peng.fan@nxp.com>
According to SPEC, when change the pll frequency and needs pll reset,
the t3 - t2 need to be greater than 1us and 1/FREF, respectively.
FREF is FIN / Prediv, the prediv is [1, 63], so choose
3us for safe.
The pll1443x does not have lock sel bit mask, so remove it.
Remove the bypass setting before changing frequency.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Bai Ping <ping.bai@nxp.com>
Removing all references to GPIO IPG clocks, this will leave all LPCG
clocks controlling GPIOs in an always ON state similar to earlier iMX
processors. By registering these clocks, unused GPIO clocks were disabled
at boot, causing issues during system suspend/resume as there is no easy
way to enable the clocks because the power domain associated with these
GPIOs are also disabled.
Signed-off-by: Ranjani Vaidyanathan <Ranjani.Vaidyanathan@nxp.com>
Add 1GHz, 800MHz, 700MHz, 600MHz pll clock rate setting in the pll
clock calculation table of imx8mm. These frequency point are needed
by VPU and GPU driver.
Signed-off-by: Bai Ping <ping.bai@nxp.com>
Reviewed-by: Anson Huang <Anson.Huang@nxp.com>
In order to avoid the name problem going forward with
integration with Qcom, Qcom has their own dsp and hifi
is competitor, so the hifi name should not be used in
our code.
So use the name of dsp instead of hifi to fix this
problem.
Signed-off-by: Weiguang Kong <weiguang.kong@nxp.com>
The logic of 'if' check for the mult is wrong, this will lead
to set rate to PLL type failed. Additionally, remove the
unnecessary 'CLK_IS_CRITICAL' flags.
Signed-off-by: Bai Ping <ping.bai@nxp.com>
Reviewed-by: Anson Huang <Anson.Huang@nxp.com>
Confirm with IC, HS400 MAX clock Freq for Instance 0 is 198Mhz
and for Instance 1 is 192MHz, so set the usdhc parent clock at
396MHz, due to current APLL is config to 529.2MHz, use the formula
APLL_PFD clock = APLL * 18 / i, the nearest clock is 381.024MHz when
the i is 25, so the usdhc root clock is 190.512MHz.
But eMMC HS400 can't pass stress test at 190.512MHz, will meet CRC
error sometimes, only when down to 176.4MHz can pass the stress test.
This patch make the usdhc0 and usdhc1 root clock both source from
IMX7ULP_CLK_APLL_PFD1, and set this APLL_PFD1 clcok rate at 352.8MHz,
and set the USDHC0 root clock at 352.8MHz, and set the USDHC1 root
clock at 176.4MHz.
Also remove the clk_prepare_enable() and clk_disable_unprepare() for
APLL_PFD2, bacause U-Boot already gate off APLL_PFD1, not need to do
this again.
Acked-by: Dong Aisheng <aisheng.dong@nxp.com>
Signed-off-by: Haibo Chen <haibo.chen@nxp.com>
