commit 7f3ff14b7e ("dmaengine: imx-sdma: add 1ms delay to ensure
SDMA channel is stopped") add 1ms delay to ensure no dma done interrupt
come in after channel disabled. This 1ms may cause SAI underrun issue
between two times playback, because ALSA framework stop SAI module after
dma terminate, thus the 1ms timing window trigger continuous 'underrun'
interrupt. Actually, don't need 1ms delay anymore since virt-dma could
handle the interrupt after channel terminated.
Signed-off-by: Robin Gong <yibin.gong@nxp.com>
Reviewed-by: Shengjiu Wang <shengjiu.wang@nxp.com>
Since sdma_resume will restore all context in case sdma power off after
suspend, sdma_channel_resume does not need to restore again. Besides,
'suspend_off' can be removed too.
Signed-off-by: Robin Gong <yibin.gong@nxp.com>
Reviewed-by: Shengjiu Wang <shengjiu.wang@nxp.com>
request_firmware_nowait() is async so that can't make sure sdma firmware
loaded when sdma_resume return back. Add wait code to make sure firmware
ready.
Signed-off-by: Robin Gong <yibin.gong@nxp.com>
Reviewed-by: Shengjiu Wang <shengjiu.wang@nxp.com>
Context switch mode should be set to static before channel0 running
after sdma bootup. Do that after sdma power up again in case mega/fast
mix off.
Signed-off-by: Robin Gong <yibin.gong@nxp.com>
Reviewed-by: Shengjiu Wang <shengjiu.wang@nxp.com>
The swap is swapped between the i.MX8QM RevA and RevB
this patch handle this difference to set swap correctly
otherwise, the eDMA will not work on the i.MX8QM RevB
Signed-off-by: Jason Liu <jason.hui.liu@nxp.com>
Reviewed-by: Anson Huang <anson.huang@nxp.com>
(cherry picked from commit 5f4d3549e5f61cb8e3c14dbeb406acfcccf32886)
Add device_synchronize for edma driver, since some driver such as
Audio need it to make sure dma done callback never come out after
resource related with dma channel free-ed by Audio driver. Android
team report such issue on MA-12087.
Signed-off-by: Robin Gong <yibin.gong@nxp.com>
(cherry picked from commit 483519c063b08fc1ce0dd297b6c186799cf639d6)
Add device_synchronize for edma driver, since some driver such as
Audio need it to make sure dma done callback never come out after
resource related with dma channel free-ed by Audio driver.
Signed-off-by: Robin Gong <yibin.gong@nxp.com>
(cherry picked from commit cd2d1200280fe573ac4eac5e27675f1b2ea638c4)
When the sdma engine is suspended firmware might get lost and need to be
reloaded. Right now fw_loaded is set to false in suspend code and SDMA
is disabled until FW is reloaded on resume.
However when entering standby mode the firmware is not lost, the resume
code detects this situation and skips reloading firmware and restoring
contexts. Unfortunately this incorrectly leaves fw_loaded set to false
so SDMA is unusable after a standby.
Fix by setting fw_loaded to false at the start of sdma_resume instead
of the end of sdma_suspend. This is the point at which we know that
firmware was lost and needs reloading.
Fixes: c5e50134e7b1 ("MLK-18315-1 dma: imx-sdma: add fw_loaded check")
Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com>
Acked-by: Fugang Duan <fugang.duan@nxp.com>
Add new cell for sw_done/sw_done_selector, because PDM need enable
software done feature in sdma script.
The new fourth cell defined as below:
Bit31: sw_done
Bit15~bit0: selector
For example: 0x80000000 means sw_done enabled for done0 sector which
is for PDM on i.mx8mm.
Signed-off-by: Robin Gong <yibin.gong@nxp.com>
Reviewed-by: Shengjiu Wang <shengjiu.wang@nxp.com>
Avoid touch unused edma channel register in susped/resume, otherwise,
kernel crash if XRDC enabled in scfw.
Signed-off-by: Robin Gong <yibin.gong@nxp.com>
Acked-by: Fugang Duan <fugang.duan@nxp.com>
Return failure if sdma firmware not loaded from rootfs before
any dma transfer started indeed. That assume no any dma tranfser
started in any driver probe function. Otherwise, some driver such
as spi may probe failed or defered probe until sdma firmware loaded
from rootfs.
Signed-off-by: Robin Gong <yibin.gong@nxp.com>
Acked-by: Fugang Duan <fugang.duan@nxp.com>
In SMP, the current running descriptor maybe freeed during done interrupt
because 'sdmac->vc.lock' will be unlock before driver callback run, thus
'sdmac->desc' maybe NULL and the memory also freeed if channel terminaed
in that time(sdma_terminate_all()), unfortunately, the local 'desc' in
sdma_update_channel_loop() which gets the old value of 'sdmac->desc'
still used to count 'desc->buftail', that cause memory currupt as below.
Check 'sdmac->desc' instead of local 'desc' in the while(), so do nothing
in this corner case. That make sense since this channel was already
terminated and no one care the callback coming after that.
[ 1863.117625] Unable to handle kernel paging request at virtual address bfffa1002
[ 1863.117629] pgd = ffff800008e1e000
[ 1863.117634] [bfffa1002] *pgd=0000000092ae8003, *pud=0000000000000000
[ 1863.117638] Internal error: Oops: 96000005 [#1] PREEMPT SMP
[ 1863.117646] Modules linked in: ath10k_pci ath10k_core ath
[ 1863.117653] CPU: 0 PID: 23381 Comm: id.printspooler Not tainted 4.9.78 #1
[ 1863.117654] Hardware name: Freescale i.MX8MQ EVK (DT)
[ 1863.117657] task: ffff80005249de80 task.stack: ffff8000506e4000
[ 1863.117670] PC is at sdma_int_handler+0x16c/0x34c
[ 1863.117674] LR is at sdma_int_handler+0x158/0x34c
[ 1863.117677] pc : [<ffff000008549b20>] lr : [<ffff000008549b0c>] pstate: 600001c5
[ 1863.117678] sp : ffff80005ff62eb0
[ 1863.117683] x29: ffff80005ff62eb0 x28: ffff80004e748300
[ 1863.117686] x27: 0000000000000003 x26: 0000000000000001
[ 1863.117690] x25: ffff800056a64018 x24: 0000000000000002
[ 1863.117694] x23: ffff800056a64258 x22: 0000000000000001
[ 1863.117698] x21: 0000000000000000 x20: ffff800056a64258
[ 1863.117701] x19: ffff800056a641b8 x18: 0000000000000008
[ 1863.117705] x17: 0000e2b0dbd9baa4 x16: 0000e2b0dbdd9dd0
[ 1863.117709] x15: 000000000000088e x14: 000000007173d1d8
[ 1863.117713] x13: 0000e2b0b97d1760 x12: 0000e2b0cd0794e0
[ 1863.117716] x11: 0000000000000008 x10: 0000000000000040
[ 1863.117720] x9 : 0000000040000000 x8 : 0012355ad191c9ca
[ 1863.117724] x7 : ffffffffa540c8fe x6 : 0000000000000018
[ 1863.117727] x5 : 000000003b9ac9ff x4 : 0000000000000000
[ 1863.117731] x3 : 0000000ffff80000 x2 : 0000000000000000
[ 1863.117735] x1 : 0000000bfffa0000 x0 : 0000000bfffa1000
[ 1863.117737]
[ 1863.117737] SP: 0xffff80005ff62e30:
Signed-off-by: Robin Gong <yibin.gong@nxp.com>
When output height is eight, yscale of ps engine will be
over two, it not support by pxp.
According to pxp doc, a factor greater than 2 is not
supported with the bilinear filter. so correct it when
this case happen in order to ensure that pxp will be
not hang up.
Reviewed-by: Robby.cai <robby.cai@nxp.com>
Signed-off-by: Guoniu.Zhou <guoniu.zhou@nxp.com>
When PxP convert yuyv to nv12 format, some color dots will
introdue to output image. IC recommend that YCBCR_MODE and
BYPASS bit of CSC1_COEF0 should be 1.
Reviewed-by: robby.cai <robby.cai@nxp.com>
Signed-off-by: Guoniu.Zhou <guoniu.zhou@nxp.com>
Fix below issue reported by Coverity, actually, don't need this
condition check here, remove it.
CID undefined (#1 of 1): Wrong operator used (CONSTANT_EXPRESSION_RESULT)operator_confusion:
(16UL /* 1UL << 4 */) | (__u16)(__le16)tcd->csr is always 1/true regardless of the values of its operand.
This occurs as the logical first operand of "&&".
Signed-off-by: Robin Gong <yibin.gong@nxp.com>
Reviewed-by: Shengjiu Wang <shengjiu.wang@nxp.com>
The type IMX_DMATYPE_MULTI_SAI is used for SAI multi-fifo mode,
in this mode, the fifo num parameter is configured through
dma_slave_config
The watermark definition is:
bit0~7: wartermark level
bit8~11: fifo number
bit16~19: fifo offset
bit27~24: sw done selector
bit23: sw done enabled
Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com>
Reviewed-by: Robin Gong<yibin.gong@nxp.com>
Add suspend to save channel registers and resume to restore them back since
edmav3 may powered off in suspend.
Signed-off-by: Robin Gong <yibin.gong@nxp.com>
The driver already supports DMA_DEV_TO_DEV in sdma_config(),
DMA_SLAVE_BUSWIDTH_2_BYTES and DMA_SLAVE_BUSWIDTH_1_BYTE in
sdma_prep_slave_sg(). So this patch adds them to the lists.
Signed-off-by: Nicolin Chen <nicoleotsuka@gmail.com>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>
On i.mx8 mscale B0 chip, AHB/SDMA clock ratio 2:1 can't be supportted,
since SDMA clock ration has to be increased to 250Mhz, AHB can't reach
to 500Mhz, so use 1:1 instead.
Signed-off-by: Robin Gong <yibin.gong@nxp.com>
mxs-dma init function will call runtime pm init, the redundant
pm_runtime_force_resume will mess up the counter. Also remove some
unnecessary code.
Signed-off-by: Han Xu <han.xu@nxp.com>
Reviewed-by: Frank Li <frank.li@nxp.com>
During 4.14 rebase squashed the following:
MLK-16800: dma: mxs-dma: correctly handle mxs-dma clock
enable mxs-dma clock before HW reset and disable clock after it.
Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com>
Enable PS and AS colorkey function if user enable and
set colorkey parameters of s0 and overlay buffer.
Signed-off-by: Guoniu.Zhou <guoniu.zhou@nxp.com>
(cherry picked from commit f2ed3bfca1)
In pxp lib, the unit of stride parameter is pixel and stride
is not equal with width parameter of out buffer in some cases.
In order to use latest pxp lib in old version rootfs, PXP_DEVICE_LEGACY
macro is used to distinguish pxp drvier version. Because the
new pxp driver define a new variable and pxp lib can know this
through PXP_DEVICE_LEGACY, and determine if use it.
Signed-off-by: Guoniu.Zhou <guoniu.zhou@nxp.com>
Reviewed-by: Fancy Fang <chen.fang@nxp.com>
(cherry picked from commit 91da74e81c)
1) add PXP_PIX_FMT_BGRA32 format support for AS buffer
2) add PXP_PIX_FMT_BGRA32 format support for OUT buffer
Signed-off-by: Guoniu.Zhou <guoniu.zhou@nxp.com>
Reviewed-by: Fancy Fang <chen.fang@nxp.com>
(cherry picked from commit 4eeefd54cd)
In support of both g2d and pxp lib alpha blending, there
must be two alpha blending versions. So there is one rule
that user should obey for different usage cases.
1) g2d alpha blending: user should set combine_enable
member of struct pxp_proc_data.
2) pxp lib alpha blending: user should set combine_enable
member of struct pxp_layer_param if the pxp_layer_param
describe overlay buffer parameters.
Signed-off-by: Guoniu.Zhou <guoniu.zhou@nxp.com>
Reviewed-by: Robby Cai <robby.cai@nxp.com>
Reviewed-by: Fancy Fang <chen.fang@nxp.com>
(cherry picked from commit 7c62393a55)
Since there are multi edmav3 instances on i.mx8, every edma channel name
is better unique.But so far, all edma channel name is 'edma-channel(id)-
tx',thus some edma channels which share the same channel id but different
edma instance will show the same channel name in kernel and this is not
friendly to debug in kernel.
Now the edma channel name(interrupt-names property) is define in dts
as below:
"edmaX-chanX-Xx"
| | |---> receive/transmit, r or t
| |---> channel id, the max number is 32
|---> edma controller instance, 0, 1, 2,..etc
and get below correct name with 'cat /proc/interrupts':
43: 0 0 0 0 GICv3 466 Level edma0-chan8-rx
44: 0 0 0 0 GICv3 467 Level edma0-chan9-tx
45: 79 0 0 0 GICv3 468 Level edma0-chan10-rx
46: 311 0 0 0 GICv3 469 Level edma0-chan11-tx
47: 0 0 0 0 GICv3 470 Level edma0-chan12-rx
48: 0 0 0 0 GICv3 471 Level edma0-chan13-tx
49: 0 0 0 0 GICv3 472 Level edma0-chan14-rx
50: 0 0 0 0 GICv3 473 Level edma0-chan15-tx
51: 0 0 0 0 GICv3 406 Level edma2-chan0-tx
52: 0 0 0 0 GICv3 407 Level edma2-chan1-tx
53: 0 0 0 0 GICv3 408 Level edma2-chan2-tx
54: 0 0 0 0 GICv3 409 Level edma2-chan3-tx
55: 0 0 0 0 GICv3 410 Level edma2-chan4-tx
56: 0 0 0 0 GICv3 411 Level edma2-chan5-tx
57: 0 0 0 0 GICv3 442 Level edma2-chan6-rx, edma2-chan7-tx
Signed-off-by: Robin Gong <yibin.gong@nxp.com>
Reviewed-by: Shengjiu Wang <shengjiu.wang@nxp.com>
There was no pxp background register setting, so the
background we see always black.
Signed-off-by: Guoniu.Zhou <guoniu.zhou@nxp.com>
Reviewed-by: Robby Cai <robby.cai@nxp.com>
(cherry picked from commit d3ee45e267)
PxP PS engine support YUV420 format, but not YVU420. The difference
between two format is U and V, if we exchange U and V base address,
the PxP driver can also support YVU420 format.
Signed-off-by: Guoniu.Zhou <guoniu.zhou@nxp.com>
Reviewed-by: Fancy Fang <chen.fang@nxp.com>
(cherry picked from commit cbc71da10a)
g2d code has different parameter setting about stride parameter.
For compatibility with all cases of using PxP, we need add this
improved feature.
Signed-off-by: Guoniu.Zhou <guoniu.zhou@nxp.com>
Reviewed-by: Robby Cai <robby.cai@nxp.com>
Reviewed-by: Fancy Fang <chen.fang@nxp.com>
(cherry picked from commit 53c8ffffec)
If pxp use crop x/y valuse as the upper left coordinate in
out buffer, pxp driver only need to write out buffer base
address to pxp out_buf register. If pxp driver use zero as
ps_ulc register value, pxp out_buf register need an offset
added with out buffer base address.
Signed-off-by: Guoniu.Zhou <guoniu.zhou@nxp.com>
Reviewed-by: Robby Cai <robby.cai@nxp.com>
Reviewed-by: Fancy Fang <chen.fang@nxp.com>
(cherry picked from commit 14c988f1eb)
Because of IC limitation, pxp only can use rotation0 engine to
do rotation operation.
Correct coordinate settings of ps and out buffer.
Signed-off-by: Guoniu.Zhou <guoniu.zhou@nxp.com>
Reviewed-by: Robby Cai <robby.cai@nxp.com>
Reviewed-by: Fancy Fang <chen.fang@nxp.com>
On i.mx8mscale, there are two sdma instances here, and common dma
frameowrk will get channel dynamicly from any available channel whatever
it's from the first sdma device or the second sdma device. But actually,
some IP like SAI only work in sdma2 not sdma1. To make sure get sdma
channel from the right sdma device, add index to match.
Signed-off-by: Robin Gong <yibin.gong@nxp.com>
When do epdc colormap test, the epdc need pxp lut function. But
if the data flow through mux0->mux1...or mux0->mux2..., the pxp
can not trigger interrupt but mux0->mux3... can. This issue only
occures on imx7d, so I set a constant data path when using lut function.
Signed-off-by: Guoniu.Zhou <guoniu.zhou@nxp.com>
Force to load context in sdma_config whatever context loaded or not,
since some configuration may change when the upper driver call sdma_config
such as bus width.
Signed-off-by: Robin Gong <yibin.gong@nxp.com>
(cherry picked from commit ee8930b657af0c9ce2cfb1a521530c7d31016675)
PxP block on imx6sll, imx6ull is different with imx7d, the node
path_ctrl should be different. So add path_ctrl for 6sll, 6ull.
Signed-off-by: Guoniu.Zhou <guoniu.zhou@nxp.com>
coefficient setting.
Because the caller of pxp-v3 does not set the stride parameter,
this will cause pitch parameter to be zero and pxp can't work.
Correct the csc1 coefficient when use pxp convert YUV to RGB format.
Signed-off-by: Guoniu.Zhou <guoniu.zhou@nxp.com>
There is Audio dual fifo cause that fill fifo one by one and
loop back after every minor loop:
-- fill the first 32bit width fifo
-- fill the next 32bit width fifo
-- +MLOFF signed offset after the above two FIFOs filled
-- loop back to the first step to handle the next minor loop.
Signed-off-by: Robin Gong <yibin.gong@nxp.com>
For dual fifo case, fsl-edma-v3 need add another cell. It's not friendly
for user and it's possible other cells maybe added to other use cases,
so combine two cells into one now, and for some special use cases such as
dual fifo property can directly be passed by one bit of cell3 rather than
another cell.
Signed-off-by: Robin Gong <yibin.gong@nxp.com>
It is possible for an irq triggered by channel0 to be received later,
after clks are disabled. If that happens then clearing them by writing
to SDMA_H_INTR won't work and the system will hang processing infinite
interrupts. Actually, don't need interrupt triggered on channel0 since
it's pollling to know channel0 done rather than interrupt in current
code, just clear BD setting to disable channel0 interrupt to avoid the
above case.
Reported-by: Leonard Crestez <leonard.crestez@nxp.com>
Signed-off-by: Robin Gong <yibin.gong@nxp.com>
This is obviously a bug but I don't know of a scenario where those errors
might happen.
Fixes: 7e84737c9c ("MLK-11385 dma: imx-sdma: enable clock before context restored")
Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com>
