Generally DDC function is not work with no edid.
Add max pixel clock support rate 297MHz for no edid case.
Signed-off-by: Sandor Yu <Sandor.yu@nxp.com>
Pixel combiner function is ready in patch set for MLK-19413.
Remove variable is_4kp60 from driver.
4Kp60 are supported for all platforms.
Signed-off-by: Sandor Yu <Sandor.yu@nxp.com>
VIC code check is introduced in 4.14.y,
if a mode is found in HDMI 1.4b 4K modes.
HDMI driver should send its VIC in vendor infoframes.
Add vendor infoframe setting.
Signed-off-by: Sandor Yu <Sandor.yu@nxp.com>
Merge CDN_1_0_38 release to HDP API.
v1_0_38 release notes:
DP: Added functionality for setting own PHY register values related to
voltage swing and pre-emphasis.
Signed-off-by: Sandor Yu <Sandor.yu@nxp.com>
This patch corrects master extdst when the relevant plane_ed of
the CRTC is slave. This is code change only because there is no
real usecase supported by existing hardwares may trigger the issue.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
This patch adds dual mode support in the i.MX HDP driver.
The single mode and dual mode can be switched dynamically
according to the input video mode(pixel clock rate and
active horizontal display width).
Signed-off-by: Liu Ying <victor.liu@nxp.com>
This patch adds pixel combiner support in the DPU KMS driver.
Pretty much logics are implemented to allocate/organize the
CRTC resources(extdst, framegen, tcon, pixel combiner, etc)
and plane resources(extdst, fetchunit, layerblend, etc) which
are needed to drive a high pixel rate display via pixel combiner.
Additional logics are implemented to support sync up mode fixup
found in the new version of DPU IP.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
This patch moves several basic structures and helpers of DPU CRTC from
the DPU CRTC driver to dpu-crtc.h so that more DPU CRTC information can
be exported there.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
Cache the auxiliary CRTC resources in struct dpu_crtc via the
dpu_aux_{unit}_peek() helpers so that the DPU CRTC driver may
use them later.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
The DPU CRTC device driver may get the CRTC group id from
the pdata of the device. Let's cache it in struct dpu_crtc
so that the driver may use it later.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
This patch adds side-by-side support for tcon so that
two tcons can participate in the dual display streams
to work with pixel combiner to drive a high pixel rate
display.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
This patch adds side-by-side support for framegen so that
two framegens can work in sync mode to participate in the
dual display streams to drive a high pixel rate display
via a pixel combiner.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
Tiled formats are supported only for YUV420 semi-planar formats.
However, the other formats should support at least the LINEAR modifier.
Some userspace app may pass on framebuffers with the linear modifier
attached and, currently, this is rejected for YUV422 and RGB formats.
This patch fixes that.
Signed-off-by: Laurentiu Palcu <laurentiu.palcu@nxp.com>
Reported-by: Jared Hu <jared.hu@nxp.com>
The dpu_crtc argument of dpu_crtc_get_resources() contains the stream ID
information, so it's unnecessary to pass the stream_id argument to this
function.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
Both CEC and HPD thread will access HDP register read/write
function, add mutex to support mulit-thread access.
Signed-off-by: Sandor Yu <Sandor.yu@nxp.com>
(cherry picked from commit 7e62bd0ad4b5d3187a3d1c0f2258c1d4e3ba66a6)
EDID function is not supported by i.MX8QM A0 SOC chip.
Signed-off-by: Sandor Yu <Sandor.yu@nxp.com>
(cherry picked from commit 6aeff3508919d584c6ce5661b14fadf3187298e7)
EDID function are default supported for all platform.
Remove is_edid variable.
Add no_edid for specific case.
such as EDID function is not supported
on iMX8QM ARM2 board with DP-HDMI converter.
Signed-off-by: Sandor Yu <Sandor.yu@nxp.com>
(cherry picked from commit 69d015ba610040cc0397b0c1335ef0e941f99d98)
dcss_drm_atomic_commit and dpu_drm_atomic_commit will overide the in-fence.
Remove the common code from the driver to make in-fence can work.
And call pepare_fb() to do the same thing of set dma_buf fence.
The only difference is pepare_fb() won't set dma_buf fence if in-fence exists.
Change-Id: Idbaf3a765321e6d049aa9e39695a450eb0c760f0
Signed-off-by: ivan.liu <xiaowen.liu@nxp.com>
Reviewed-by: Liu Ying <victor.liu@nxp.com>
Reviewed-by: Laurentiu Palcu <laurentiu.palcu@nxp.com>
Add channel map for hdmi audio, originally it is in
audio info frame function, but removed by
commit 6b97462b64 ("MLK-18690-3: hdp api: Remove
info frame API function")
Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com>
For framebuffer linear pixel formats, we calculate the buffer address
with an offset to do framebuffer start point x/y cropping. This way,
the src_x/y seen by fetchunit(including prefetch engine, if used) can
be zero. The reason why it still works with the existing nonzero
settings is very likely that the fetchunit or prefetch engine may
discard the initial invalid pixels by looking at the correct buffer
address, frame stride, frame width and frame height. However, it
would be good to correct the mistake in driver.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
(cherry picked from commit 8847a9b7c2)
There are prefetch engine fixups embedded in the updated i.MX8QM silicons.
So, prefetch engines in all i.MX8 variants should be the same. Let's
remove has_prefetech_fixup from devtypes which is no more needed.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
(cherry picked from commit 875c31a70f)
The pixel link validation and sync ctrl enablement should be the last
step to enable the display pipeline which involves the HDP encoder.
So, let's move the pixel link operations from initialization stage to
enc->enable/disable. Also, the pixel_link_init/deinit hooks are replaced
with pixel_link_validate/invalidate and pixel_link_sync_ctrl_enable/disable,
since the display controller driver has already initialized the pixel link
at the driver probe stage.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
(cherry picked from commit cb234bc95e)
The pixel link MST address is set by the display controller driver,
so let's remove the redundant setting from the hdp driver.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
(cherry picked from commit f0f0a1970f)
Comparing to 4.9 kernel, the generic irq chip core of 4.14 kernel
imposes more strict check on !irqd_irq_masked(&desc->irq_data) when
it tries to unmask an irq via unmask_irq(). For irq chips without
implementing ->irq_enable() and ->irq_disable() callbacks, like the
DPU irq chip, the IRQ_DISABLE_UNLAZY flag has to be set to irq status,
otherwise, irqs cannot be enabled again after disablement(due to things
like system power management).
Signed-off-by: Liu Ying <victor.liu@nxp.com>
When switching from a 10-bit to an 8-bit color depth, the PHY pixel engine
simply stops functioning correctly 90% of the time. This results in the
HDMI sink not detecting any signal.
This patch will reset the PHY pixel engine after the pipe clocks are ON,
in the bridge enable callback. This will make the pixel engine work
correctly when BPC changes. Resetting the pixel engine before all the pipe
clocks are on, produces no results.
Signed-off-by: Laurentiu Palcu <laurentiu.palcu@nxp.com>
(cherry picked from commit 72246ac9ccfa2074f4f575292af10d19a58c95c4)
4K@50 does not currently work. This patch will enable the scambler for
VIC96@50Hz.
Signed-off-by: Oliver Brown <oliver.brown@nxp.com>
Signed-off-by: Laurentiu Palcu <laurentiu.palcu@nxp.com>
(cherry picked from commit 0f13947a2fb72673b19c9f154eb202a9be916c4f)
This patch will allow userspace to rotate planes by setting the
'rotation' property. Generally, 0 and 180 rotations are allowed for
pretty much all 8-bit xRGB and 2-plane YUV420 formats. 90/270 rotations
can be performed only for non-compressed tiled GPU xRGB formats. Tiled
YUV420 formats do not allow rotations at all because these formats need
DTRC for de-tiling and DTRC has no rotation support.
For more info, consult the DPR Features chapter in the reference manual.
Test example:
modetest -M imx-drm -w 27:rotation:4 -w 32:rotation:33 -w 27:alpha:30 -s
42@31:3840x2160-60@XR24 -P 32@31:3840x2160@NV21
The above will perform:
* 180 degree rotation of primary plane (XR24);
* vertical flip of first overlay plane (rotate-0 | reflect-y);
* set primary plane alpha to 30;
Signed-off-by: Laurentiu Palcu <laurentiu.palcu@nxp.com>
Add the check to LCDIF CRTC atomic check for the requested bus
format by encoder with the bus format which can be supported by
LCDIF CRTC to refuse unsupported case.
Signed-off-by: Fancy Fang <chen.fang@nxp.com>
(cherry picked from commit e98afe9b6b20c2494c8570427b7811ed9ce202e8)
Since the LCDIF output data width can be different from the data
width of input pixel data, so the bus format check in the plane's
atomic check is not correct anymore, and need to be removed.
Signed-off-by: Fancy Fang <chen.fang@nxp.com>
(cherry picked from commit 2245702e7905fa7b75aec92fdbb9ffeb33bdb6de)
According to LCDIF specification, the input pixel data
width and the output pixel data width can be different,
and this conversion is done by LCDIF automatically. So
config the output data width according to the requested
bus format from the encoder, instead to be same with the
input pixel data width.
Signed-off-by: Fancy Fang <chen.fang@nxp.com>
(cherry picked from commit bfd27f6d71d86a7f2fc8314f082565db3682b925)
The connector's 'display_info' usually includes all the bus
formats the display peripheral device can be accepted. And
the DRM adjusted display mode's 'private_flags' includes
bus format the DSIM bridge requested according to the DSI
device display format. Add the bus format check to the DSIM
encoder's atomic check to make sure these two bus formats
have intersection.
Signed-off-by: Fancy Fang <chen.fang@nxp.com>
(cherry picked from commit 6d804db82b95411ebad9fcfb43b3acecee5941d9)
According to the comments of 'struct drm_framebuffer', its
'width' field refers to the logical width of the visible
area of the framebuffer. This may be unequal to the total
pixels number of a line. So use the 'pitches' field to
replace 'width' for the horizontal cropping feature.
Signed-off-by: Fancy Fang <chen.fang@nxp.com>
(cherry picked from commit 9a2bbbf971ed79b32ae1c7da2d62b8a72f3ccffd)
Add AVPLL support for DisplayPort on iMX8QM.
The AVPLL will be the default pixel clock source for DisplayPort.
Signed-off-by: Oliver Brown <oliver.brown@nxp.com>
Moving AFE_check_rate_supported to API_AFE.c (another commit).
Making private functions static to prevent conflicts with iMX8M (MCU2).
Signed-off-by: Oliver Brown <oliver.brown@nxp.com>
Add horizontal cropping support when atomic plane update is
running, and if the attached CRTC needs modeset. And if the
width of visible portion of plane is equal to the fb surface
width, the Pigeon Mode will be disabled, so cropping will be
disabled.
Signed-off-by: Fancy Fang <chen.fang@nxp.com>
(cherry picked from commit 30672b2b18a07a2926979cc533cbb84ea4a642dd)
In DRM atomic modeset check, it will not check the fb's width
change, so in later atomic commit, it will not disable the CRTC
which has no mode changed. But for LCDIF, the fb width related
registers configuration can not be done when LCDIF is running.
So force 'mode_changed' to be true when fb width changed.
Signed-off-by: Fancy Fang <chen.fang@nxp.com>
(cherry picked from commit 518ff82756a39ff2d2f750596295baa4f5fca4c5)
After supporting DISPMIX power domain, the LCDIF runtime
resume callback always write '0' to 'LCDIF_CTRL' register
which will clear previous pixel format related setting.
So the previous condition by comparing format change for
setting pixel format during plane atomic update is not
true anymore.
Signed-off-by: Fancy Fang <chen.fang@nxp.com>
(cherry picked from commit 5f84c69799456f28fd8182fd156e9067921e9a4e)
Add runtime PM status check during runtime suspend and resume
to avoid unnecessary jobs if it is already in that state which
can avoid possible kernel warnings of clock disable/unprepare
mismatch during system suspend if it is alreay in runtime
suspended state.
Signed-off-by: Fancy Fang <chen.fang@nxp.com>
(cherry picked from commit 6f95c6fdc0de2fd4fe1d835c164f5e3cfb23e17d)
Implement the suspend()/resume() callbacks to support system
power management functions for SEC DSIM.
Signed-off-by: Fancy Fang <chen.fang@nxp.com>
(cherry picked from commit db3e9faa0278af6de5aaac008478123d0ebecb73)
After the DISPMIX power domain enabled, all the related registers
will drop their values once runtime pm suspend called. So in the
pm runtime resume process, the SEC DSIM de-reset and some init jobs
need to be done, and these jobs are no longer necessary to be done
during probe bind anymore.
Signed-off-by: Fancy Fang <chen.fang@nxp.com>
(cherry picked from commit 7a7f17f5fb66135629ef20a2b4780dfef2f0f0ce)
Change the maximum height limitation to 1920 to support
'1080x1920' resolution mode. It is a temporary work
around and will be improved later.
Signed-off-by: Fancy Fang <chen.fang@nxp.com>
(cherry picked from commit 44d0209e97e0c574af30dd7a7d7e059d4ddf996d)
This patch fixes a warning message that's seen during 4.14 compilation.
CC drivers/gpu/drm/imx/dcss/dcss-plane.o
drivers/gpu/drm/imx/dcss/dcss-plane.c: In function ‘dcss_plane_atomic_set_base’:
drivers/gpu/drm/imx/dcss/dcss-plane.c:347:4: warning: ‘caddr’ may be used uninitialized in this function [-Wmaybe-uninitialized]
dcss_dec400d_addr_set(dcss_plane->dcss, p1_ba, caddr);
^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
The warning appeared because of a logic error in code that was
introduced by the following commit:
commit a46e1cd7df28 ("MGS-3560 [#imx-913] Enable DRM compression for
mscale board")
The above commit moved a piece of code, that was located under
switch-case branch, under a do-while() loop and converted all the
returns to breaks. However, a break makes the code exit the while loop
and will continue executing the code under the case branch. Hence, caddr
may be used whithout being initialized.
Signed-off-by: Laurentiu Palcu <laurentiu.palcu@nxp.com>
CC: Yong Gan <yong.gan@nxp.com>
This patch fixes a NULL pointer dereference error that can happen
randomly, in certain conditions. The reason for the oops were assignments
that were done before checking that the actual pointer was valid...
Additionally, add a crtc check when duplicating the state.
Signed-off-by: Laurentiu Palcu <laurentiu.palcu@nxp.com>
Refer to HDMI 1.4 section 6.5.3, non-zero CD data GCP should send in
deep color mode.
Now, when HDMI work in 24bpp, it will send non-zero CD(0x4 for 24bit)
data GCP to protocol analyzer.
It means current HDMI source is working in “24bit deep color mode”.
But HDMI 1.4 CTS 7-19 required DUT should in “No Deep Color support”.
Protocol analyzer expect received zero CD GCP or no GCP.
Disable GCP when bpp is 24 to pass CTS 7-19.
Signed-off-by: Sandor Yu <Sandor.yu@nxp.com>
