This patch corrects master extdst when the relevant plane_ed of
the CRTC is slave. This is code change only because there is no
real usecase supported by existing hardwares may trigger the issue.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
This patch adds pixel combiner support in the DPU KMS driver.
Pretty much logics are implemented to allocate/organize the
CRTC resources(extdst, framegen, tcon, pixel combiner, etc)
and plane resources(extdst, fetchunit, layerblend, etc) which
are needed to drive a high pixel rate display via pixel combiner.
Additional logics are implemented to support sync up mode fixup
found in the new version of DPU IP.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
This patch moves several basic structures and helpers of DPU CRTC from
the DPU CRTC driver to dpu-crtc.h so that more DPU CRTC information can
be exported there.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
Cache the auxiliary CRTC resources in struct dpu_crtc via the
dpu_aux_{unit}_peek() helpers so that the DPU CRTC driver may
use them later.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
The DPU CRTC device driver may get the CRTC group id from
the pdata of the device. Let's cache it in struct dpu_crtc
so that the driver may use it later.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
This patch adds side-by-side support for tcon so that
two tcons can participate in the dual display streams
to work with pixel combiner to drive a high pixel rate
display.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
This patch adds side-by-side support for framegen so that
two framegens can work in sync mode to participate in the
dual display streams to drive a high pixel rate display
via a pixel combiner.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
The dpu_crtc argument of dpu_crtc_get_resources() contains the stream ID
information, so it's unnecessary to pass the stream_id argument to this
function.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
dcss_drm_atomic_commit and dpu_drm_atomic_commit will overide the in-fence.
Remove the common code from the driver to make in-fence can work.
And call pepare_fb() to do the same thing of set dma_buf fence.
The only difference is pepare_fb() won't set dma_buf fence if in-fence exists.
Change-Id: Idbaf3a765321e6d049aa9e39695a450eb0c760f0
Signed-off-by: ivan.liu <xiaowen.liu@nxp.com>
Reviewed-by: Liu Ying <victor.liu@nxp.com>
Reviewed-by: Laurentiu Palcu <laurentiu.palcu@nxp.com>
For framebuffer linear pixel formats, we calculate the buffer address
with an offset to do framebuffer start point x/y cropping. This way,
the src_x/y seen by fetchunit(including prefetch engine, if used) can
be zero. The reason why it still works with the existing nonzero
settings is very likely that the fetchunit or prefetch engine may
discard the initial invalid pixels by looking at the correct buffer
address, frame stride, frame width and frame height. However, it
would be good to correct the mistake in driver.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
(cherry picked from commit 8847a9b7c2)
There are prefetch engine fixups embedded in the updated i.MX8QM silicons.
So, prefetch engines in all i.MX8 variants should be the same. Let's
remove has_prefetech_fixup from devtypes which is no more needed.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
(cherry picked from commit 875c31a70f)
Comparing to 4.9 kernel, the generic irq chip core of 4.14 kernel
imposes more strict check on !irqd_irq_masked(&desc->irq_data) when
it tries to unmask an irq via unmask_irq(). For irq chips without
implementing ->irq_enable() and ->irq_disable() callbacks, like the
DPU irq chip, the IRQ_DISABLE_UNLAZY flag has to be set to irq status,
otherwise, irqs cannot be enabled again after disablement(due to things
like system power management).
Signed-off-by: Liu Ying <victor.liu@nxp.com>
Framegen is a part of DPU display engine. The SACFG register of
framegen controls base_x/y, a.k.a., the left/top boundries of all
the planes(fetch units) built upon the framegen. And, framegen
has to be restarted after different x/y values are programmed to
SACFG. Thus, let's explicitly claim mode set is needed via asserting
crtc_state->mode_changed when base_x/y are changed.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
(cherry picked from commit fc6061c86f6ea6e4524c3e16a3c62c94a4ca7129)
i.MX8dx/dxp/qxp use two LDBs(one primary, one auxiliary) to support
dual channel mode. This patch adds the dual channel mode support
for i.MX8dx/dxp/qxp. Note that the drivers contain specific sequence
needed by this mode - LDB VSYNC polarity and channel selection settings
should be configured into the register a bit earlier in ->atomic_mode_set
instead of in ->enable, and DC subsystem pixel link enablement is moved
from the DPU driver to the LDB driver to make sure it happens later
than LDB clocks enablement in ->enable.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
The framegen driver should get PLL clock, bypass clock and display
selection/mux clock via device tree if available. It may use bypass
clock when a TMDS encoder is connected with the framegen, otherwise,
PLL clock is used. This way, the assigned-clocks and assigned-clock-parents
device tree properties can be removed from the dpu device tree node.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
We use PRG x/y offset to do in-micro-tile cropping for new DPR/PRG IPs.
When tile resolving is enabled by using the new IPs, the design team
indicates that DPU fetch unit base address and DPU/PRG stride need to be
calculated in the below steps:
1) prg_Baddr = dpr_Baddr
2) tmp_dpu_Baddr = prg_Baddr + prg_x_offset * bytes_per_pixel
3) tmp_burst_size = 1 << (ffs(tmp_dpu_Baddr) - 1)
tmp_burst_size = round_up(tmp_burst_size, 8)
burst_size = min(tmp_burst_size, 128)
4) tmp_dpu_stride = dpu_width * bytes_per_pixel
5) dpu_stride =
round_up(tmp_dpu_stride + round_up(tmp_dpu_Baddr % 8, 8), burst_size)
6) dpu_Baddr = tmp_dpu_Baddr + prg_y_offset * dpu_stride
7) prg_stride = dpu_stride
The legacy DPR/PRG IPs and linear formats driver logic should not be
essentially touched.
This patch implements the above calculation method in the drivers
so that all valid in-micro-tile x/y cropping arguments can be supported.
Without this, at least, some cropping cases with odd x value would fail.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
It turns out that local alpha value of the secondary input is set to
0xFF by the hardware if the secondary input is from scaler(hscaler or
vscaler). This makes the layer on this secondary input accidentally
cover the layer with higher z-order(if it exists), even though the
layer with lower z-order doesn't supply local alpha. This patch zeros
the secondary local alpha value to prevent the issue from happening.
Users are unlikely to expect local alpha to be correctly scaled, so
it looks fine to simply zero the alpha. If we find the unlikely case,
the KMS driver may later explicitly do atomic check to invalidate the case.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
This patch abstracts fetch unit concept for all the fetch units
we have - fetchdecode, fetcheco, fetchlayer and fetchwarp.
They have some similar features and operations which are suitable
to be abstracted. A lot of boilerplate code is removed.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
Fetchdecode may work together with vscaler to do bob deinterlacing.
This patch adds the deinterlacing support for DPU DRM plane by using them.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
The new DPR IP contains a fixup for the in-tile cropping issue(TKT344978).
The FRAME_2P_PIX_X/Y_CTRL(@F0h and @100h) register definitions are changed
to be FRAME_PIX_X/Y_ULC_CTRL. This patch uses the updated registers to
support tile framebuffer x/y offset.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
This patch tells crtc and plane if dpu prefetch engine has fixups
via the dpu_has_prefetch_fixup() helper.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
This patch adds the first subsidiary layer0(out of layer0 to layer7)
support for the fetchwarp2 fetch unit to be the backend of DRM plane.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
Fetchwarp is a type of dpu fetch unit with the additional
warping function. Each fetchwarp contains 8 subsidiary layers.
Fetchwarp2 can work with fetcheco2 to fetch planar YUV pixel
formats. Also, it may fetch RGB pixel formats. This patch
adds basic fetchwarp2 fetch unit support in the dpu common driver
so that it may fetch frames in RGB pixel formats. YUV pixel formats
and warping function could be supported later.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
This patch adds the first subsidiary layer0(out of layer0 to layer7)
support for the fetchlayer0/1 fetch units to be the backend of DRM plane.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
We don't have correct support for fb x/y source offset for tile formats.
The buffer address calculation is wrong when the offset is non-zero.
Also, finer offset needs a fix in silicon(TKT344978). So, let's do not
support the offset currently. We may add it back after we figure out
how the updated silicon supports the offset.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
We should enable irqs before HWs are triggered in ->enable and then
wait for shadow loads are done, otherwise we would miss the irqs if
the irqs come right after the triggers although it's not very likely
to happen.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
The DPR works in manual mode for the first frame and we need to
switch it to auto mode so that auto shadow load mechanism works.
The designers require us to switch the DPR manual mode to auto mode
directly for display controllers instead of using the DPR control
done irq handler, because the irq will not come in some cases(which
leads to shadow load failure). Finer switch operations on DPR
register bits are needed for SW_SHADOW_LOAD_SEL, SHADOW_LOAD_EN,
RUN_EN and REPEAT_EN. Also, for overlay planes, we need to wait for
a frame additionally in the "on-the-fly" cases to make sure the
switch is successful. In all, this patch should be able to address
frame dropping and screen tearing issue(due to the shadow load
failure) when users play video on overlay planes.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
The RGB888/BGR888/NV16/NV61/NV24/NV42 pixel formats are not supported
by DPR. They cannot get the benefits(i.e., tile resolving and
underrun-proof) from the prefetch engines. Also, 16bit and 32bit
RGB pixel formats are widely used by GUI, while NV12 pixel format
is the only pixel format supported by VPU. Thus, it makes little
sense to support the pixel formats which are not supported by DPR.
Another idea is that removing the pixel formats makes the driver
a bit simpler since we don't have to deal with the cases in which
prefetch engines are bypassed.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
The resources for a plane group are shared by the two display streams
of one DPU. Thus, the two Framegen(fg) instances of one DPU should be
in the plane group resource. The resource users may find the fg instance
onto which the resources are built via the stream id. This patch corrects
the number of fg instances in a plane group resource from one to two.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
The DPU spec tells us that we need to wait for all pending frames to
be completed when a display stream is disabled. It turns out
that the hardcoded 60-microsecond timeout value is not enough for
some low refresh rate video modes, e.g., 1920x1080@24, which makes
the display stream be disabled incorrectly(leave the hardware an
incorrect machine status). The SoC design indicates that there are
two pending frames to complete in the worst case. This patch waits
for at most three frame duration(which is enough for sure) so that
the hardware may flush out all the pending frames. In case the clock
subsystem provides us a pixel clock with wrong rate and causes the
timeout value be unreasonably long, we truncate it to wait for at
most three seconds.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
To workaround the errata TKT320950, DPR/PRG need to evade the first dumb frame
which is generated by DPU. The way we achieve that is to bypass TCON(but set
the TCON sync signals and KA_CHUCK strobe signal up) before enabling the DPU
display controller, and then enable the display controller, wait for the frame
index starting to move and finally switch TCON to operation mode.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
When we use prefetch, we use DPR and PRG to do frame input cropping.
Thus, the stride of fetcheco is the stride of cropped frame, which means
the value of the stride is cropped_width * bytes_per_pixel. Since the
pixel format has to be NV12 or NV21 when we use prefetch, we assume the
cropped_width stands for how many UV we have in bytes for one line, while
bytes_per_pixel should be 8bits for every U or V component. Also, to
address TKT339017, when we use prefetch engine for fetcheco, we need to
round the stride up to the fetcheco burst size, i.e., burst length
multiplies 8 bytes. According to TKT343664, the buffer base address has
to align to burst size, so we'll pick an appropriate burst size value in
fetcheco_source_stride().
Signed-off-by: Liu Ying <victor.liu@nxp.com>
When we use prefetch, we use DPR and PRG to do frame input cropping. Thus,
the stride of fetchdecode is the stride of cropped frame, which means the
value of the stride is cropped_width * bytes_per_pixel. Also, to address
TKT339017, when we use prefetch engine for fetchdecode, we need to round
the frame stride up to the fetchdecode burst size, i.e., burst length
multiplies 8 bytes. According to TKT343664, the buffer base address has
to align to burst size, so we'll pick an appropriate burst size value in
fetchdecode_source_stride().
Signed-off-by: Liu Ying <victor.liu@nxp.com>
We will support DPR interrupts via DPU core driver.
In order to distinguish bewteen the inner DPU interrupts and the DPR
interrupts, let's rename some software stuffs which are related to
DPU interrupts so that they may show they are DPU inner explicitly.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
We've got chance to commit update for one display stream only instead of
always binding two display streams together for commit since the below
commit. Thus, we should disable plane source stream ids where necessary
only for one CRTC in ->atomic_flush().
Fixes: 7798441bb25e ("MLK-16771 drm/imx: dpu: kms: Change to use a better KMS")
Signed-off-by: Liu Ying <victor.liu@nxp.com>
This patch adds safety_stream_cf_color module parameter support so that
users may set the default color generated by the constframe units(4 and 5)
of safety streams.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
This patch improves DPU KMS by the following means:
1) Wait for shadow registers being loaded in ->atomic_flush()
to make sure there is no intermediate register values being
loaded when doing atomic update.
2) Improve CRTC enablement/disablement sequences/configurations
according to spec.
3) Remove the FGDM__PRIM framegen display mode from ->mode_set_nofb()
and always use FGDM__SEC_ON_TOP mode so that we may prepare
for introducing a safety stream solution in the future.
4) Better vblank on/off and vblank event handling, though there
should be no essential improvements.
5) Some fixes for adding correct CRTC/plane/connector states
in the full atomic state in dpu_drm_atomic_check().
6) Remove CRTC and plane states from the full atomic state where
possible to improve atomic update performance.
7) Introduce a plane group mutex to protect plane source mask and
vproc source mask. This is a little bit superfluous due to
the protection provided by the atomic helper, but just one of
the DPU core itself.
The changes are in a bundle to avoid any unexpected drawbacks
of introducing them at a smaller granularity.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
No one is using the list in the dpu plane group to access dpu plane, so let's
take down dpu plane from the list so that we may remove the list entirely
from where it is defined.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
This patch adds several YUV pixel formats support for dpu kms.
The pixel formats are YUYV, UYVY, NV12, NV21, NV16, NV61, NV24 and NV42.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
This patch uses the helper drm_format_plane_cpp() to calculate base address
so that we can calculate correctly for the YUV pixel formats as well.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
The bit to enable/disable source buffer is embedded in the register
LAYERPORPERTY0. However, the other bits of the register may have
other functionalities. So, using fetchdecode_layerproperty() to
enable/disable source buffer isn't appropriate. This patch uses
new functions to enable/disable fetchdecode source buffer so that
the function names could be a bit specific about what they are doing.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
It's unnecessary to support active planes with relevant CRTC being disabled,
because we cannot see the planes on the screen. Let's reject the case
in the atomic check stage explicitly.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
