As suggested by designer for safety's sake, this patch tunes
kachuck from slave tcon to generate it 2 lines later than
master tcon.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
This patch adds extdst_pixengcfg_syncmode_master() helper support
so that the callers may control if a extdst is master or slave
when it works in sync mode. The bit16 of extdst's PIXENGCFG_STATIC
register controls this and it's a part of sync mode fixup logic.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
This patch adds framegen_secondary_is_syncup() and
framegen_wait_for_secondary_syncup() helpers support so that
the callers may know a framegen's syncup status for the
secondary input.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
Bit7 of framegen's SECSTATCONFIG register is used to control
the sync mode fixup logic implemented in framegen. This patch
adds framegen_syncmode_fixup() helper so that the callers
may enable/disable the fixup logic for a framegen.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
Bit16 of store9's PIXENGCFG_STATIC register is used to control
the sync mode fixup logic implemented in store9. So, let's
add store9 support in the DPU core driver and export a function
for users to enable/disable the fixup logic.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
This patch adds constframe_framedimenstions_copy_prim() helper support
so that callers may may copy frame dimensions from a primary constframe
to the relevant secondary constframe.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
This patch adds pixel combiner support in the DPU core driver.
Users may get and enable/disable/control a pixel combiner instant
via tcon functions and may tell if pixel combiner is available for
a particular DPU variant via the dpu_has_pc() helper and if it is
needed in a specific usecase via the dpu_get_syncmode_min_prate()
and dpu_get_singlemode_max_width() helpers.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
The pixel clock of the slave framegen comes from the master framegen
when the two framegens work in sync mode, so we cannot get pixel clock
from the pixel clock rate from the slave framegen directly to calculate
the timeout value when waiting for it's done. Instead, we can tell
the rate from the video mode. So, we take this fallback way to get
the rate in this case and don't warn.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
This patch adds side-by-side support for tcon so that
two tcons can participate in the dual display streams
to work with pixel combiner to drive a high pixel rate
display.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
This patch adds side-by-side support for framegen so that
two framegens can work in sync mode to participate in the
dual display streams to drive a high pixel rate display
via a pixel combiner.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
This patch adds tcon_is_master/slave() helpers support so that
callers may know if a tcon is a master or slave tcon.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
This patch adds extdst_is_master() helper support so that
callers may know if a extdst is a master extdst or not.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
This patch adds framegen_is_master/slave() helpers support so that
callers may know if a framegen is a master or slave framegen.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
This patch introduces a new has_syncmode_fixup entry in struct dpu_devtype and
specifies this flag for DPU variants found in existing SoCs.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
This patch adds helper framegen_syncmode() support so that callers may
control the sync mode of a framegen.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
This patch adds a new di_grp_id entry in display client pdev's data
so that the relevant display platform driver may know the display
group ID of the display device.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
If a DPU unit is already in use, the bailout path of dpu_{unit}_get()
would wrongly dereference the pointer of ERR_PTR(-EBUSY). This patch
fixes this issue.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
It takes 33 milliseconds to scanout a frame when display refresh rate
is 30fps, and 42 milliseconds for 24fps. So, if we wait for framegen
frame index moving, 30 milliseconds timeout value is not enough to
cover all reasonable display refresh rates. 50 milliseconds should not
be a bad choice.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
(cherry picked from commit 8564546882)
There are prefetch engine fixups embedded in the updated i.MX8QM silicons.
So, prefetch engines in all i.MX8 variants should be the same. Let's
remove has_prefetech_fixup from devtypes which is no more needed.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
(cherry picked from commit 875c31a70f)
The framegen driver knows the encoder type, so it may set pixel link
MST address according to the type. The MST address for the TMDS encoder
is special, while the address is zero for other encoders.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
(cherry picked from commit fb3e63cce0)
When TMDS encoder is used, the encoder would provide framegen display clock
directly via clk_bypass. So, we don't have to set clk_disp rate. This
should work with or without pixel combiner(pixel combiner would combine
two framegens' output to drive high pixel rate displays via TMDS encoder
only currently).
Signed-off-by: Liu Ying <victor.liu@nxp.com>
(cherry picked from commit 4b710fe10f)
This patch will allow userspace to rotate planes by setting the
'rotation' property. Generally, 0 and 180 rotations are allowed for
pretty much all 8-bit xRGB and 2-plane YUV420 formats. 90/270 rotations
can be performed only for non-compressed tiled GPU xRGB formats. Tiled
YUV420 formats do not allow rotations at all because these formats need
DTRC for de-tiling and DTRC has no rotation support.
For more info, consult the DPR Features chapter in the reference manual.
Test example:
modetest -M imx-drm -w 27:rotation:4 -w 32:rotation:33 -w 27:alpha:30 -s
42@31:3840x2160-60@XR24 -P 32@31:3840x2160@NV21
The above will perform:
* 180 degree rotation of primary plane (XR24);
* vertical flip of first overlay plane (rotate-0 | reflect-y);
* set primary plane alpha to 30;
Signed-off-by: Laurentiu Palcu <laurentiu.palcu@nxp.com>
The 16bpp BGR order pixel formats 'DRM_FORMAT_ABGR1555' and
'DRM_FORMAT_XBGR1555' also require to be re-ordered to RGB
order for display, just like the format 'DRM_FORMAT_BGR565'
does.
Signed-off-by: Fancy Fang <chen.fang@nxp.com>
(cherry picked from commit f5cc4f4699570fe697d21cb47c54aa91b82c8458)
According to LCDIF specification, the input pixel data
width and the output pixel data width can be different,
and this conversion is done by LCDIF automatically. So
config the output data width according to the requested
bus format from the encoder, instead to be same with the
input pixel data width.
Signed-off-by: Fancy Fang <chen.fang@nxp.com>
(cherry picked from commit bfd27f6d71d86a7f2fc8314f082565db3682b925)
According to the LCDIF specification, the Legacy Mode does not
support cropping function in the horizontal direction, so add
Pigeon Mode which can support this kind of function. And when
enable this mode, the legacy horizontal timings configuration
should use stride value but not the active width, and related
pigeon configuration should use the active width but not the
stride value.
Signed-off-by: Fancy Fang <chen.fang@nxp.com>
(cherry picked from commit e6da9542693dd585972897f62748a101f5726a74)
Change the 'rpm_suspended' field to be an atomic type from
boolean type to make it have the counting ability which can
help to detect and avoid runtime suspend and resume calls
mismatch caused problems.
Signed-off-by: Fancy Fang <chen.fang@nxp.com>
(cherry picked from commit dece6fbe51f9c0ea3cd42c52e1c174bd26ae70f1)
Implement the suspend()/resume() callbacks to support system
power management functions for LCDIF.
Signed-off-by: Fancy Fang <chen.fang@nxp.com>
(cherry picked from commit 7e00487012753cb370eab4ff5c05f76f7361297f)
After the DISPMIX power domain enabled, all the related registers
will drop their values once runtime pm suspend called. So in the
pm runtime resume process, the LCDIF de-reset and some init jobs
need to be done, and these jobs are no longer necessary to be done
during probe stage anymore.
Signed-off-by: Fancy Fang <chen.fang@nxp.com>
(cherry picked from commit f83aaaecaeb54d8b1231be2cb7175ce58682dae7)
The DCSS RM states that the maximum upscale ratio is 1:8. However, DCSS
HW team suggested some time back that upscale ratios of 1:16 could be
achieved with DCSS scaler, though these ratios were not validated.
Unfortunately there are corner cases, when the upscale ratio nears
1:16, that fail. At the recommendation of DCSS designers, we revert the
maximum ratio to 1:8 until further notice.
Signed-off-by: Laurentiu Palcu <laurentiu.palcu@nxp.com>
(cherry picked from commit bafb5a9481c289951872923d4bbbbcf24a8910b5)
If DCSS is suspended, the clocks are disabled. Dumping the registers,
with the following command:
cat /sys/kernel/debug/imx-dcss/dump_registers
will hang the system, because of DTG.
This patch makes sure clocks are enabled before dumping the registers
and will immediately release them afterwards.
Signed-off-by: Laurentiu Palcu <laurentiu.palcu@nxp.com>
DCSS needs PM QoS in order to keep interrupt latency low. Otherwise,
page flipping will not work smooth enough because CTXLD will not be
triggered in time.
Currently, PM QoS is requested all the time but that does not allow the
CPUs to go idle. Hence, this leads to increased power consumption.
This patch will change how PM QoS is requested by doing it only when
VBLANK is enabled/disabled. The VBLANK interrupt is enabled just before
a commit takes place and disabled after one second after last commit.
This will allow DCSS to function properly and, also, allow CPUs to go
idle whenever there's no buffer submitted.
Exception to this is when DTRC is used (when DCSS is passed tiled
buffers). In this case, PM QoS will always be active, even if no buffer
is submitted, because DTRC banks need to be switched in CTXLD ISR, so
that DCSS does not underrun. DTRC does not have the REPEAT feature, as
the rest of DCSS does.
Signed-off-by: Laurentiu Palcu <laurentiu.palcu@nxp.com>
resume will increase unlock counter, max allowed value is 15.
suspend need decrease unlock counter to avoid overflow panic.
Signed-off-by: Xianzhong <xianzhong.li@nxp.com>
Currently, there's a hardcoded wait time (500ms) after enabling DTG
clocks. This is supposed to avoid VBLANK timeout warning messages.
However, this time is quite big. This patch changes this by lowering this
time as much as possible, with the use of completion events. After
enabling CRTC we just block until the first VBLANK interrupt comes. This
way, we know for sure that we'll never get a VBLANK timeout.
Signed-off-by: Laurentiu Palcu <laurentiu.palcu@nxp.com>
This patch activates DPR completion interrupts, just for tracing and
detecting green screen issues.
Signed-off-by: Laurentiu Palcu <laurentiu.palcu@nxp.com>
DTRC interrupts will not be used for switching the banks, as the CTXLD
will be used for that, however these are useful for tracing and
debugging green screen issues when DTRC is used.
Signed-off-by: Laurentiu Palcu <laurentiu.palcu@nxp.com>
This patch will add traces for the following events:
* CTXLD arm, completion and kick;
* VBLANKs;
* atomic flushes;
* plane updates (printing the DPR buffer base address);
These will allow us to measure and analyze where bottlenecks are:
application or driver.
Signed-off-by: Laurentiu Palcu <laurentiu.palcu@nxp.com>
This patch adds a DCSS tracing mechanism that introduces as low latency
as possible, so that it does not affect timings. Instead of text, 64 bit
tags will be logged, together with the system time in nanoseconds. Based
on these, post-processing can be done on any PC to compute deltas,
delays, missed buffers, etc.
Example usage:
echo 1 > /sys/module/imx_dcss_core/parameters/tracing
gplay-1.0 movie.mpg
echo 0 > /sys/module/imx_dcss_core/parameters/tracing
To dump the trace:
cat /sys/kernel/debug/imx-dcss/dump_trace_log > trace.txt
With the help of a scripting language (awk), the trace can then be
post-processed and analyzed on the PC.
Signed-off-by: Laurentiu Palcu <laurentiu.palcu@nxp.com>
The video tearing appeared only when the application used 2 buffers.
That's because, sometimes, the context loader could be armed after the
DB event came in the frame trace. That made a buffer submitted in frame
N end up on screen in frame N+2 because the context loader waits for the
next DB event. Since vblank events are sent at the end of the frame, by
the time the buffer lands on screen, the application will reuse it while
it's being displayed, hence the tearing effect.
This patch moves the CTXLD trigger moment all the way to the end of the
frame trace, just before DB event arrives. This will leave the
application plenty of time to submit new buffers.
In the event that the trigger moment is missed (application submits a
buffer right at the end of a frame trace), then we're not signalling the
next VBLANK event to application. This way, application will know that
the buffer is still needed and will not submit a new one.
Signed-off-by: Laurentiu Palcu <laurentiu.palcu@nxp.com>
i.MX8dx/dxp/qxp use two LDBs(one primary, one auxiliary) to support
dual channel mode. This patch adds the dual channel mode support
for i.MX8dx/dxp/qxp. Note that the drivers contain specific sequence
needed by this mode - LDB VSYNC polarity and channel selection settings
should be configured into the register a bit earlier in ->atomic_mode_set
instead of in ->enable, and DC subsystem pixel link enablement is moved
from the DPU driver to the LDB driver to make sure it happens later
than LDB clocks enablement in ->enable.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
Add an function to get the LCDIF controller supported bus
formats according to the pixel format bpp. And change the
bus format sanity check in the plane's atomic check to see
if the bus format required by the peripheral attached to
LCDIF can be supported by LCDIF.
Signed-off-by: Fancy Fang <chen.fang@nxp.com>
Simplify the code to sync command sequncer in conditions:
1. tile work with dprc/prg (baddr)
2. switch tile to linear (!start)
revert 686c717fef
MLK-18398 gpu: imx: imx8_dprc: dpu-blit: Wait the dprc idle before
disable it
Signed-off-by: Xianzhong <xianzhong.li@nxp.com>
the previous programming does not flush command sequence,
that cause the obvious flicker when run glmark2 in full-screen,
also the wrong logic cause wayland hang in strict conditions.
need program event trigger to sync command sequencer properly.
also revert workaround: 4767f9aaad
MLK-18283-3 gpu: imx: dpu-blit: sync for cmd sequence finished
Signed-off-by: Xianzhong <xianzhong.li@nxp.com>
chrome browser hang is reproduced with mouse connected,
the first frame handler trigger the problem in below scenario:
tile (dprc-enable) --> linear (dprc->disable) --> tile (handle first frame wrongly).
need_handle_start is set following dprc_enable, need reset it with dprc_disable.
Signed-off-by: Xianzhong <xianzhong.li@nxp.com>
