This patch will allow userspace to rotate planes by setting the
'rotation' property. Generally, 0 and 180 rotations are allowed for
pretty much all 8-bit xRGB and 2-plane YUV420 formats. 90/270 rotations
can be performed only for non-compressed tiled GPU xRGB formats. Tiled
YUV420 formats do not allow rotations at all because these formats need
DTRC for de-tiling and DTRC has no rotation support.
For more info, consult the DPR Features chapter in the reference manual.
Test example:
modetest -M imx-drm -w 27:rotation:4 -w 32:rotation:33 -w 27:alpha:30 -s
42@31:3840x2160-60@XR24 -P 32@31:3840x2160@NV21
The above will perform:
* 180 degree rotation of primary plane (XR24);
* vertical flip of first overlay plane (rotate-0 | reflect-y);
* set primary plane alpha to 30;
Signed-off-by: Laurentiu Palcu <laurentiu.palcu@nxp.com>
The DCSS RM states that the maximum upscale ratio is 1:8. However, DCSS
HW team suggested some time back that upscale ratios of 1:16 could be
achieved with DCSS scaler, though these ratios were not validated.
Unfortunately there are corner cases, when the upscale ratio nears
1:16, that fail. At the recommendation of DCSS designers, we revert the
maximum ratio to 1:8 until further notice.
Signed-off-by: Laurentiu Palcu <laurentiu.palcu@nxp.com>
(cherry picked from commit bafb5a9481c289951872923d4bbbbcf24a8910b5)
If DCSS is suspended, the clocks are disabled. Dumping the registers,
with the following command:
cat /sys/kernel/debug/imx-dcss/dump_registers
will hang the system, because of DTG.
This patch makes sure clocks are enabled before dumping the registers
and will immediately release them afterwards.
Signed-off-by: Laurentiu Palcu <laurentiu.palcu@nxp.com>
DCSS needs PM QoS in order to keep interrupt latency low. Otherwise,
page flipping will not work smooth enough because CTXLD will not be
triggered in time.
Currently, PM QoS is requested all the time but that does not allow the
CPUs to go idle. Hence, this leads to increased power consumption.
This patch will change how PM QoS is requested by doing it only when
VBLANK is enabled/disabled. The VBLANK interrupt is enabled just before
a commit takes place and disabled after one second after last commit.
This will allow DCSS to function properly and, also, allow CPUs to go
idle whenever there's no buffer submitted.
Exception to this is when DTRC is used (when DCSS is passed tiled
buffers). In this case, PM QoS will always be active, even if no buffer
is submitted, because DTRC banks need to be switched in CTXLD ISR, so
that DCSS does not underrun. DTRC does not have the REPEAT feature, as
the rest of DCSS does.
Signed-off-by: Laurentiu Palcu <laurentiu.palcu@nxp.com>
Currently, there's a hardcoded wait time (500ms) after enabling DTG
clocks. This is supposed to avoid VBLANK timeout warning messages.
However, this time is quite big. This patch changes this by lowering this
time as much as possible, with the use of completion events. After
enabling CRTC we just block until the first VBLANK interrupt comes. This
way, we know for sure that we'll never get a VBLANK timeout.
Signed-off-by: Laurentiu Palcu <laurentiu.palcu@nxp.com>
This patch activates DPR completion interrupts, just for tracing and
detecting green screen issues.
Signed-off-by: Laurentiu Palcu <laurentiu.palcu@nxp.com>
DTRC interrupts will not be used for switching the banks, as the CTXLD
will be used for that, however these are useful for tracing and
debugging green screen issues when DTRC is used.
Signed-off-by: Laurentiu Palcu <laurentiu.palcu@nxp.com>
This patch will add traces for the following events:
* CTXLD arm, completion and kick;
* VBLANKs;
* atomic flushes;
* plane updates (printing the DPR buffer base address);
These will allow us to measure and analyze where bottlenecks are:
application or driver.
Signed-off-by: Laurentiu Palcu <laurentiu.palcu@nxp.com>
This patch adds a DCSS tracing mechanism that introduces as low latency
as possible, so that it does not affect timings. Instead of text, 64 bit
tags will be logged, together with the system time in nanoseconds. Based
on these, post-processing can be done on any PC to compute deltas,
delays, missed buffers, etc.
Example usage:
echo 1 > /sys/module/imx_dcss_core/parameters/tracing
gplay-1.0 movie.mpg
echo 0 > /sys/module/imx_dcss_core/parameters/tracing
To dump the trace:
cat /sys/kernel/debug/imx-dcss/dump_trace_log > trace.txt
With the help of a scripting language (awk), the trace can then be
post-processed and analyzed on the PC.
Signed-off-by: Laurentiu Palcu <laurentiu.palcu@nxp.com>
The video tearing appeared only when the application used 2 buffers.
That's because, sometimes, the context loader could be armed after the
DB event came in the frame trace. That made a buffer submitted in frame
N end up on screen in frame N+2 because the context loader waits for the
next DB event. Since vblank events are sent at the end of the frame, by
the time the buffer lands on screen, the application will reuse it while
it's being displayed, hence the tearing effect.
This patch moves the CTXLD trigger moment all the way to the end of the
frame trace, just before DB event arrives. This will leave the
application plenty of time to submit new buffers.
In the event that the trigger moment is missed (application submits a
buffer right at the end of a frame trace), then we're not signalling the
next VBLANK event to application. This way, application will know that
the buffer is still needed and will not submit a new one.
Signed-off-by: Laurentiu Palcu <laurentiu.palcu@nxp.com>
Currently, the maximum upscale ratio is 1:7. However, DCSS can support
upscale ratios up to 1:16, even though the RM states the maximum upscale
ratio is 1:8.
Signed-off-by: Laurentiu Palcu <laurentiu.palcu@nxp.com>
(cherry picked from commit 361a057cee)
In certain conditions, i.e. YUV mode, pixel_depth variable will be used
uninitialized. This can lead to unpredictable behavior.
Signed-off-by: Laurentiu Palcu <laurentiu.palcu@nxp.com>
Currently, scaler filter coefficients are hardcoded. However, they need
to be re-computed, based on input/output resolution as well.
Also, in order to use the scaler 7-tap filter, DPR RTRAM rows need to be
changed accordingly.
Signed-off-by: Dzung Hoang <dzung.hoang@nxp.com>
Signed-off-by: Laurentiu Palcu <laurentiu.palcu@nxp.com>
Since the input of HDR10 is always 10-bit, ignore 8-bit flags when
setting up the output pipe.
Signed-off-by: Laurentiu Palcu <laurentiu.palcu@nxp.com>
The old tables had incorrect CSCBs when YUV formats were being used. That's
because the application used to generate the tables always assumed channel 0 is
graphics even if it was configured as YUV.
Signed-off-by: Laurentiu Palcu <laurentiu.palcu@nxp.com>
This commit allows one to select if a firmware file is used, for loading
the HDR10 tables, or a header. By default, this will be header file.
This is until a proper way of passing the file from bootloader is found.
Also, fix a minor bug which made parsing the tables over the actual data
limit.
Signed-off-by: Laurentiu Palcu <laurentiu.palcu@nxp.com>
This commit adds HDR10 tables as a header. Using a FW file is
problematic since the tables need to be available immediately after
boot. After the rootfs is mounted, as is the case for loading a FW file,
it's already too late if some conversion tables are needed.
This usually happens if the output pipe is configured as YUV420.
Signed-off-by: Laurentiu Palcu <laurentiu.palcu@nxp.com>
The following commit:
af01350 - MLK-17634-18: drm: imx: dcss: optimize context loading and DDR
bus load
introduced a regression. During my attempts to fix various green screen
issues, I modified the DTRC start routine by enabling the other register
bank, not the current one.
Unfortunately, this was committed by mistake...
Signed-off-by: Laurentiu Palcu <laurentiu.palcu@nxp.com>
DCSS needs some time to stabilize after switching to a new pixel clock.
All interrupts will delayed till the clock stabilizes and we'll end up
getting warnings about VBLANK interrupt taking more than 50ms to arrive.
This patch adds a 500ms delay after switching to a new clock. This will
allow DCSS to stabilize before enabling CRTC and DTG channels.
Signed-off-by: Laurentiu Palcu <laurentiu.palcu@nxp.com>
The problem arised because of a combination of 2 commits:
Commit 1:
"2a70f32 - MLK-17232-2: drm: imx: dcss: ignore SB_PEND_DISP_ACTIVE
interrupt"
disabled the SB_PEND_DISP_ACTIVE interrupt because of a problem in SOC.
However, it did not remove the flag from CTXLD_IRQ_ERROR macro.
Commit 2:
"f0e3911 - MLK-17459-1: drm: imx: dcss: change ctxld irq handling"
moved the bottom half interrupt handling to top half. By doing that, the
top half did not exit immediately if IRQ_COMPLETION condition was met
and continued evaluating if any interrupts in CTXLD_IRQ_ERROR flags
were triggered.
This patch removes SB_PEND_DISP_ACTIVE interrupt flag from
CTXLD_IRQ_ERROR macro.
Signed-off-by: Laurentiu Palcu <laurentiu.palcu@nxp.com>
This will lower the amount of ctxld entries sent, if configuration has
not changed much. Also, disable channel 0 if alpha is 0 and global alpha
is used. This will lower the DDR load, depending on graphics channel
resolution.
Signed-off-by: Laurentiu Palcu <laurentiu.palcu@nxp.com>
The tables header is no longer necessary as dcss.fw file will be used
from now on to store LUT and CSC tables.
Signed-off-by: Laurentiu Palcu <laurentiu.palcu@nxp.com>
This clock is needed by HDR10 so this patch makes DCSS use VIDEO2_PLL2
for the rest of the resolutions as well.
Signed-off-by: Laurentiu Palcu <laurentiu.palcu@nxp.com>
This patch fixes an issue introduced by the cropping patches which made
weston look bad. That's because use_dtrc flag was enabled if modifiers
were present. However, graphics plane can have modifiers too. This patch
adds an extra check.
Also, remove an unnecessary debug message.
Signed-off-by: Laurentiu Palcu <laurentiu.palcu@nxp.com>
Cropping of compressed formats seems problematic and we cannot up-align
in this case. For compressed formats we need to down-align both the
width and height.
Signed-off-by: Laurentiu Palcu <laurentiu.palcu@nxp.com>
This patch fixes playback for movies with unaligned widths/heights and
adds cropping functionality for tiled formats. Untiled formats will not
have this feature as cropping is a DTRC function.
Signed-off-by: Laurentiu Palcu <laurentiu.palcu@nxp.com>
To remove any possible latencies introduced by scheduling the bottom
half interrupt handler, do everything in the top half handler and get
rid of the IRQ worker thread handler. Also, that needs all mutexes
changed to spinlocks since mutexes can sleep.
Signed-off-by: Laurentiu Palcu <laurentiu.palcu@nxp.com>
When the DEC400D is set to bypass mode from decompressed mode,
the read config should be set to disable compression along with
the control register. Otherwise, the DEC400D cannot really leave
the decompressed mode. And the value '0x0' is suitable to be set
to read config register in this case.
Signed-off-by: Fancy Fang <chen.fang@nxp.com>
The register base of DEC400D which is passed to context loader
should be the physical address but not the ioremaped virtual
address.
Signed-off-by: Fancy Fang <chen.fang@nxp.com>
Do not really do shadow regiters trigger in'dcss_dec400d_shadow_trig()'
when dec400d is bypassed, since in 'dcss_dec400d_bypass()', the shadow
registers have already been triggerd.
Signed-off-by: Fancy Fang <chen.fang@nxp.com>
Current setting uses a 256 bytes/request for anything less than 1080p.
This works when DTRC is not involved. However, with DTRC, the
MAX_BYTES_PREQ needs to be fine tuned a little.
Signed-off-by: Laurentiu Palcu <laurentiu.palcu@nxp.com>
Using WRSCL for downscaling ratios between 3 and 5 can lead to more
DDR bandwidth beeing used (~400MB/s).
Hence, use WR_SCL only for downscaling ratios from 5 to 7.
Signed-off-by: Laurentiu Palcu <laurentiu.palcu@nxp.com>
Add handling code to support tiled and compressed pixel source
layout. The tiled only layout will bypass DEC400D and be resolved
by DPR, since DEC400D is only responsible for decompression.
Signed-off-by: Fancy Fang <chen.fang@nxp.com>
Under certain circumstances (corner cases) the scaling fractions were
not set properly. This patch fixes this.
Signed-off-by: Laurentiu Palcu <laurentiu.palcu@nxp.com>
This patch effectively enables DTRC module in DCSS to decode tiled
formats from VPU:
* uncompressed G1;
* uncompressed G2;
* compressed G2;
Compressed G2 formats need to pass on the decompression table offsets,
by using the 'dtrc_dec_ofs' property. This is a 64 bit value like below:
64--------48----------32---------16---------0
|<- chroma table ofs ->|<- luma table ofs ->|
Signed-off-by: Laurentiu Palcu <laurentiu.palcu@nxp.com>
In order for DTRC to work properly, we need to be able to write the DCTL
registers (to switch banks), just before activating CTXLD. However,
__dcss_ctxld_enable() function is usually called from irq context, or
whn the mutex is taken. Hence, create a function the can be called from
irq context.
Signed-off-by: Laurentiu Palcu <laurentiu.palcu@nxp.com>
This patch makes the necessary changes so that, for downscaling ratios
more than 3:1 and up to 7:1 (for video) and 5:1 (for graphics), the
WRSCL/RDSRC path will be used. This way the DRAM bandwidth will be lower
and spread evenly across the frame time.
Signed-off-by: Laurentiu Palcu <laurentiu.palcu@nxp.com>
WRSCL and RDSRC modules will be needed when downscaling ratios starting
from 3:1 up to 7:1 are needed. Otherwise, if the usual scaling path is
used, the DRAM bandwidth needed will be too much and performance will be
affected.
Signed-off-by: Laurentiu Palcu <laurentiu.palcu@nxp.com>
already enabled
If the channel is already enabled, or it doesn't need a mode set, then
the dcss_dtg_global_alpha_changed() will always return false for formats
with per-pixel alpha. Hence, the plane will not be updated. This patch
removes the check for image format and the check will be done for all
image formats.
Signed-off-by: Laurentiu Palcu <laurentiu.palcu@nxp.com>
