As suggested by designer for safety's sake, this patch tunes
kachuck from slave tcon to generate it 2 lines later than
master tcon.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
This patch adds extdst_pixengcfg_syncmode_master() helper support
so that the callers may control if a extdst is master or slave
when it works in sync mode. The bit16 of extdst's PIXENGCFG_STATIC
register controls this and it's a part of sync mode fixup logic.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
This patch adds framegen_secondary_is_syncup() and
framegen_wait_for_secondary_syncup() helpers support so that
the callers may know a framegen's syncup status for the
secondary input.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
Bit7 of framegen's SECSTATCONFIG register is used to control
the sync mode fixup logic implemented in framegen. This patch
adds framegen_syncmode_fixup() helper so that the callers
may enable/disable the fixup logic for a framegen.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
Bit16 of store9's PIXENGCFG_STATIC register is used to control
the sync mode fixup logic implemented in store9. So, let's
add store9 support in the DPU core driver and export a function
for users to enable/disable the fixup logic.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
This patch adds constframe_framedimenstions_copy_prim() helper support
so that callers may may copy frame dimensions from a primary constframe
to the relevant secondary constframe.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
This patch adds pixel combiner support in the DPU core driver.
Users may get and enable/disable/control a pixel combiner instant
via tcon functions and may tell if pixel combiner is available for
a particular DPU variant via the dpu_has_pc() helper and if it is
needed in a specific usecase via the dpu_get_syncmode_min_prate()
and dpu_get_singlemode_max_width() helpers.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
The pixel clock of the slave framegen comes from the master framegen
when the two framegens work in sync mode, so we cannot get pixel clock
from the pixel clock rate from the slave framegen directly to calculate
the timeout value when waiting for it's done. Instead, we can tell
the rate from the video mode. So, we take this fallback way to get
the rate in this case and don't warn.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
This patch adds side-by-side support for tcon so that
two tcons can participate in the dual display streams
to work with pixel combiner to drive a high pixel rate
display.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
This patch adds side-by-side support for framegen so that
two framegens can work in sync mode to participate in the
dual display streams to drive a high pixel rate display
via a pixel combiner.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
This patch adds tcon_is_master/slave() helpers support so that
callers may know if a tcon is a master or slave tcon.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
This patch adds extdst_is_master() helper support so that
callers may know if a extdst is a master extdst or not.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
This patch adds framegen_is_master/slave() helpers support so that
callers may know if a framegen is a master or slave framegen.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
This patch introduces a new has_syncmode_fixup entry in struct dpu_devtype and
specifies this flag for DPU variants found in existing SoCs.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
This patch adds helper framegen_syncmode() support so that callers may
control the sync mode of a framegen.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
This patch adds a new di_grp_id entry in display client pdev's data
so that the relevant display platform driver may know the display
group ID of the display device.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
If a DPU unit is already in use, the bailout path of dpu_{unit}_get()
would wrongly dereference the pointer of ERR_PTR(-EBUSY). This patch
fixes this issue.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
It takes 33 milliseconds to scanout a frame when display refresh rate
is 30fps, and 42 milliseconds for 24fps. So, if we wait for framegen
frame index moving, 30 milliseconds timeout value is not enough to
cover all reasonable display refresh rates. 50 milliseconds should not
be a bad choice.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
(cherry picked from commit 8564546882)
There are prefetch engine fixups embedded in the updated i.MX8QM silicons.
So, prefetch engines in all i.MX8 variants should be the same. Let's
remove has_prefetech_fixup from devtypes which is no more needed.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
(cherry picked from commit 875c31a70f)
The framegen driver knows the encoder type, so it may set pixel link
MST address according to the type. The MST address for the TMDS encoder
is special, while the address is zero for other encoders.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
(cherry picked from commit fb3e63cce0)
When TMDS encoder is used, the encoder would provide framegen display clock
directly via clk_bypass. So, we don't have to set clk_disp rate. This
should work with or without pixel combiner(pixel combiner would combine
two framegens' output to drive high pixel rate displays via TMDS encoder
only currently).
Signed-off-by: Liu Ying <victor.liu@nxp.com>
(cherry picked from commit 4b710fe10f)
i.MX8dx/dxp/qxp use two LDBs(one primary, one auxiliary) to support
dual channel mode. This patch adds the dual channel mode support
for i.MX8dx/dxp/qxp. Note that the drivers contain specific sequence
needed by this mode - LDB VSYNC polarity and channel selection settings
should be configured into the register a bit earlier in ->atomic_mode_set
instead of in ->enable, and DC subsystem pixel link enablement is moved
from the DPU driver to the LDB driver to make sure it happens later
than LDB clocks enablement in ->enable.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
The framegen driver should get PLL clock, bypass clock and display
selection/mux clock via device tree if available. It may use bypass
clock when a TMDS encoder is connected with the framegen, otherwise,
PLL clock is used. This way, the assigned-clocks and assigned-clock-parents
device tree properties can be removed from the dpu device tree node.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
We use PRG x/y offset to do in-micro-tile cropping for new DPR/PRG IPs.
When tile resolving is enabled by using the new IPs, the design team
indicates that DPU fetch unit base address and DPU/PRG stride need to be
calculated in the below steps:
1) prg_Baddr = dpr_Baddr
2) tmp_dpu_Baddr = prg_Baddr + prg_x_offset * bytes_per_pixel
3) tmp_burst_size = 1 << (ffs(tmp_dpu_Baddr) - 1)
tmp_burst_size = round_up(tmp_burst_size, 8)
burst_size = min(tmp_burst_size, 128)
4) tmp_dpu_stride = dpu_width * bytes_per_pixel
5) dpu_stride =
round_up(tmp_dpu_stride + round_up(tmp_dpu_Baddr % 8, 8), burst_size)
6) dpu_Baddr = tmp_dpu_Baddr + prg_y_offset * dpu_stride
7) prg_stride = dpu_stride
The legacy DPR/PRG IPs and linear formats driver logic should not be
essentially touched.
This patch implements the above calculation method in the drivers
so that all valid in-micro-tile x/y cropping arguments can be supported.
Without this, at least, some cropping cases with odd x value would fail.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
We get pll and display clock rates twice in framegen_cfg_videomode().
This patch removes the redundant code so that the rates are got once.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
It turns out that local alpha value of the secondary input is set to
0xFF by the hardware if the secondary input is from scaler(hscaler or
vscaler). This makes the layer on this secondary input accidentally
cover the layer with higher z-order(if it exists), even though the
layer with lower z-order doesn't supply local alpha. This patch zeros
the secondary local alpha value to prevent the issue from happening.
Users are unlikely to expect local alpha to be correctly scaled, so
it looks fine to simply zero the alpha. If we find the unlikely case,
the KMS driver may later explicitly do atomic check to invalidate the case.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
This patch abstracts fetch unit concept for all the fetch units
we have - fetchdecode, fetcheco, fetchlayer and fetchwarp.
They have some similar features and operations which are suitable
to be abstracted. A lot of boilerplate code is removed.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
This patch changes layerblend alpha blend settings so that
the layerblend reads local alpha value from the primary
input to blend color components and generates alpha values
from the secondary input for the layer with the lowest zorder.
This makes KMS support local alpha for the primary DRM plane.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
Fetchdecode may work together with vscaler to do bob deinterlacing.
This patch adds the deinterlacing support for DPU DRM plane by using them.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
This patch adds dpu_has_prefetch_fixup() helper support.
Users may use it to tell if a DPU has fixups for prefetch
engines in silicon or not.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
DPR may prefetch linear frames and resolve tile frames for DPU.
New i.MX8QXP SoCs have DPR fixups in silicon.
This patch differentiates DPUs with or without DPR fixups
via OF device ID's data.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
This patch adds the first subsidiary layer0(out of layer0 to layer7)
support for the fetchwarp2 fetch unit to be the backend of DRM plane.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
Fetchwarp is a type of dpu fetch unit with the additional
warping function. Each fetchwarp contains 8 subsidiary layers.
Fetchwarp2 can work with fetcheco2 to fetch planar YUV pixel
formats. Also, it may fetch RGB pixel formats. This patch
adds basic fetchwarp2 fetch unit support in the dpu common driver
so that it may fetch frames in RGB pixel formats. YUV pixel formats
and warping function could be supported later.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
This patch adds the first subsidiary layer0(out of layer0 to layer7)
support for the fetchlayer0/1 fetch units to be the backend of DRM plane.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
This patch adds some prefetch engine helpers support
in the dpu common driver so that callers may deal with
the prefetch engines of the fetch units the callers
are interested in.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
Fetchlayer is a type of dpu fetch unit. Each fetchlayer
contains 8 subsidiary layers. Fetchlayer cannot work with
fetcheco to fetch planar YUV pixel formats. However, it may
fetch RGB pixel formats. This patch adds basic fetchlayer0/1
fetch units support in the dpu common driver.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
We don't have correct support for fb x/y source offset for tile formats.
The buffer address calculation is wrong when the offset is non-zero.
Also, finer offset needs a fix in silicon(TKT344978). So, let's do not
support the offset currently. We may add it back after we figure out
how the updated silicon supports the offset.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
The DPR works in manual mode for the first frame and we need to
switch it to auto mode so that auto shadow load mechanism works.
The designers require us to switch the DPR manual mode to auto mode
directly for display controllers instead of using the DPR control
done irq handler, because the irq will not come in some cases(which
leads to shadow load failure). Finer switch operations on DPR
register bits are needed for SW_SHADOW_LOAD_SEL, SHADOW_LOAD_EN,
RUN_EN and REPEAT_EN. Also, for overlay planes, we need to wait for
a frame additionally in the "on-the-fly" cases to make sure the
switch is successful. In all, this patch should be able to address
frame dropping and screen tearing issue(due to the shadow load
failure) when users play video on overlay planes.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
The DPU spec tells us that we need to wait for all pending frames to
be completed when a display stream is disabled. It turns out
that the hardcoded 60-microsecond timeout value is not enough for
some low refresh rate video modes, e.g., 1920x1080@24, which makes
the display stream be disabled incorrectly(leave the hardware an
incorrect machine status). The SoC design indicates that there are
two pending frames to complete in the worst case. This patch waits
for at most three frame duration(which is enough for sure) so that
the hardware may flush out all the pending frames. In case the clock
subsystem provides us a pixel clock with wrong rate and causes the
timeout value be unreasonably long, we truncate it to wait for at
most three seconds.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
The SC_C_KACHUNK_CNT is for dpu blit and represents
how many cycle counts is need to trigger DPR after
DPU shadow being loaded. The initial value is 0x20,
and will change to 0 after the first frame if not set.
So it need be set with a value greater than 0x20.
Signed-off-by: Meng Mingming <mingming.meng@nxp.com>
To workaround the errata TKT320950, DPR/PRG need to evade the first dumb frame
which is generated by DPU. The way we achieve that is to bypass TCON(but set
the TCON sync signals and KA_CHUCK strobe signal up) before enabling the DPU
display controller, and then enable the display controller, wait for the frame
index starting to move and finally switch TCON to operation mode.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
