For some eMMC, after switch to HS400ES mode, it need to config the strobe
dll target dealy even if the clock is 50MHZ or 25MHz, otherwise will meet
CMD index/crc error when send CMD13 to check the switch status. Take
imx8MM-EVK board as example, without this patch, it will meet:
[ 2.473915] IRQ status 0x000a8001
[ 2.473930] the mmc send status get -84
[ 2.473934] mmc2: mmc_select_hs400es failed, error -84
[ 2.473938] mmc2: error -84 whilst initialising MMC card
And we also meet some customer require to let eMMC work at 80MHz HS400ES
mode, so here remove the 100MHz limitation for Strobe DLL target delay
setting.
Signed-off-by: Haibo Chen <haibo.chen@nxp.com>
It's observed that uSDHC needed delay between tuning cycles for
HS200 successful tuning. This patch is to set 1ms delay for that.
Signed-off-by: Haibo Chen <haibo.chen@nxp.com>
When using jailhouse to support two Linux on i.MX8MQ EVK,
we use the 1st Linux to configure pinctrl for the 2nd Linux.
Then the 2nd Linux could use the mmc without pinctrl driver.
So give a warning message when no pinctrl available, but no fail probe.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
(cherry picked from commit 0ededa450d69016a72755b428f89d149666d7968)
Add HS400 support for iMX7ULP B0.
According to IC suggest, need to clear the STROBE_DLL_CTRL_RESET
before any setting of STROBE_DLL_CTRL register.
USDHC has register bits(bit[27~20] of register STROBE_DLL_CTRL)
for slave sel vaule. If this register bits value is 0, it needs
256 ref_clk cycles to update slave sel value. IC suggest to set
bit[27~20] to 0x4, it only need 4 ref_clk cycle to update slave
sel vaule. This will short the lock time of slave.
i.MX7ULP B0 will need more time to lock the REF and SLV, so change
to add another 5us delay.
Acked-by: Dong Aisheng <aisheng.dong@nxp.com>
Signed-off-by: Haibo Chen <haibo.chen@nxp.com>
Android report data timeout issue on the Micron eMMC of i.mx8mscale
evk board. Before using CMD25 to write multi block data, driver will
use CMD6 to flush cache. But some CMD25 will get both data timeout
interrupt and transfer complete interrupt. If add delay after busy
check, and before sending CMD13, this issue gone.
We meet similar issue on Sandisk eMMC before, and already have a
commit 581925fe32 ("MLK-11685-1 mmc: add delay after CMD6 befoer
sending CMD13 for sandisk"), but when cherry-pick to 4.9 branch,
meet conflicts, put the delay in the wrong place. So meet the similar
issue again.
This patch fix this, move the dealy in the right place, right before
CMD13.
Reviewed-by: Dong Aisheng <Aisheng.dong@nxp.com>
Signed-off-by: Haibo Chen <haibo.chen@nxp.com>
Add feature of setting slot index via devicetree alias, to hard code the
mmc/sd root device.
The patch requires additional alias_id fix or it won't work.
Note: minor device number keep independent with this device alias.
Refer to the commit 35928d6c6a76 ("mmc: Allow setting slot index via
devicetree alias").
Acked-by: Leonard Crestez <leonard.crestez@nxp.com>
Reviewed-by: Dong Aisheng <aisheng.dong@nxp.com>
Signed-off-by: Haibo Chen <haibo.chen@nxp.com>
strobe-dll-delay-target is the delay cell add on the strobe line.
Strobe line the the uSDHC loopback read clock which is use in HS400
mode. Different strobe-dll-delay-target may need to set for different
board/SoC. If this delay cell is not set to an appropriate value,
we may see some read operation meet CRC error after HS400 mode select
which already pass the tuning.
This patch add the strobe-dll-delay-target setting in driver, so that
user can easily config this delay cell in dts file.
Signed-off-by: Haibo Chen <haibo.chen@nxp.com>
Reviewed-by: Dong Aisheng <aisheng.dong@nxp.com>
The default max segment size of IOMMU is 64KB, which exceed the ADMA
limitation. ADMA only support max to 65535, 64KB - 1Byte. IOMMU will
optimize the segments it received, merge the little segment into one
big segment. If we use the default IOMMU config, then ADMA will get
some segments which it's size is 64KB. Then ADMA error will shows up.
Currently, when use standard tuning, driver default disable DMA. But
on i.MX usdhc, this is not enough. Need also clear DMA_SEL. If not,
once the DMA_SEL select AMDA2, even dma already disabled, when send
tuning command, usdhc will still prefetch the ADMA script from wrong
DMA address, then we will see IOMMU report some error which show
lack of TLB mapping.
This patch fix these two issue, make sure usdhc can work well by
operate data through IOMMU.
Signed-off-by: Haibo Chen <haibo.chen@nxp.com>
The commit 304419d8a7 ("mmc: core: Allocate per-request data using the
block layer core") refactored mechanism of queue handling caused
mmc_init_request() can be called just after mmc_cleanup_queue() caused null
pointer dereference.
Another commit bbdc74dc19 ("mmc: block: Prevent new req entering queue
after its cleanup") tried to fix the problem. However it actually miss one
corner case.
We could still reproduce the issue mentioned with these steps:
(1) insert a SD card and mount it
(2) hotplug it, so it will leave md->usage still be counted
(3) reboot the system which will sync data and umount the card
[Unable to handle kernel NULL pointer dereference at virtual address
00000000
[user pgtable: 4k pages, 48-bit VAs, pgd = ffff80007bab3000
[[0000000000000000] *pgd=000000007a828003, *pud=0000000078dce003,
*pmd=000000007aab6003, *pte=0000000000000000
[Internal error: Oops: 96000007 [#1] PREEMPT SMP
[Modules linked in:
[CPU: 3 PID: 3507 Comm: umount Tainted: G W
4.13.0-rc1-next-20170720-00012-g9d9bf45 #33
[Hardware name: Firefly-RK3399 Board (DT)
[task: ffff80007a1de200 task.stack: ffff80007a01c000
[PC is at mmc_init_request+0x14/0xc4
[LR is at alloc_request_size+0x4c/0x74
[pc : [<ffff0000087d7150>] lr : [<ffff000008378fe0>] pstate: 600001c5
[sp : ffff80007a01f8f0
....
[[<ffff0000087d7150>] mmc_init_request+0x14/0xc4
[[<ffff000008378fe0>] alloc_request_size+0x4c/0x74
[[<ffff00000817ac28>] mempool_create_node+0xb8/0x17c
[[<ffff00000837aadc>] blk_init_rl+0x9c/0x120
[[<ffff000008396580>] blkg_alloc+0x110/0x234
[[<ffff000008396ac8>] blkg_create+0x424/0x468
[[<ffff00000839877c>] blkg_lookup_create+0xd8/0x14c
[[<ffff0000083796bc>] generic_make_request_checks+0x368/0x3b0
[[<ffff00000837b050>] generic_make_request+0x1c/0x240
So mmc_blk_put wouldn't calling blk_cleanup_queue which actually the
QUEUE_FLAG_DYING and QUEUE_FLAG_BYPASS should stay. Block core expect
blk_queue_bypass_{start, end} internally to bypass/drain the queue before
actually dying the queue, so it didn't expose API to set the queue bypass.
I think we should set QUEUE_FLAG_BYPASS whenever queue is removed, although
the md->usage is still counted, as no dispatch queue could be found then.
Fixes: 304419d8a7 ("mmc: core: Allocate per-request data using the block layer core")
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
(cherry picked from commit 7c84b8b43d)
When the last ready-buffer-ready is set, then usdhc execute-tuning
bit is clear, this means usdhc finish the tuning process, but at
this time, sd/mmc card may still out put the tuning data, can't
response to any command. So this patch add 1ms delay when usdhc
finish the tuning, make sure sd/mmc card finish sending the tuning
data, then sd/mmc can response the following command normally.
Signed-off-by: Haibo Chen <haibo.chen@nxp.com>
Reviewed-by: Dong Aisheng <aisheng.dong@nxp.com>
Currently, USDHC do not generate transfer complete interrupt
when send a non-data-command with R1b response. But if want
to support DCMD in CMDQ, need to change this, the DCMD IC
logic require the USDHC to enable this function, otherwise
DCMD will never get a CC(command complete) interrupt.
This patch set ESDHC_VEND_SPEC2_EN_BUSY_IRQ and add DCMD support.
Signed-off-by: Haibo Chen <haibo.chen@nxp.com>
Reviewed-by: Dong Aisheng <aisheng.dong@nxp.com>
Priority use the callback set_timeout() to set the maximum timeout
if the host has.
Signed-off-by: Haibo Chen <haibo.chen@nxp.com>
Reviewed-by: Dong Aisheng <aisheng.dong@nxp.com>
Add CQE support to the block driver, including:
- optionally using DCMD for flush requests
- "manually" issuing discard requests
- issuing read / write requests to the CQE
- supporting block-layer timeouts
- handling recovery
- supporting re-tuning
CQE offers 25% - 50% better random multi-threaded I/O. There is a slight
(e.g. 2%) drop in sequential read speed but no observable change to sequential
write.
CQE automatically sends the commands to complete requests. However it only
supports reads / writes and so-called "direct commands" (DCMD). Furthermore
DCMD is limited to one command at a time, but discards require 3 commands.
That makes issuing discards through CQE very awkward, but some CQE's don't
support DCMD anyway. So for discards, the existing non-CQE approach is
taken, where the mmc core code issues the 3 commands one at a time i.e.
mmc_erase(). Where DCMD is used, is for issuing flushes.
Signed-off-by: Adrian Hunter <adrian.hunter@intel.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
Tested-by: Linus Walleij <linus.walleij@linaro.org>
(cherry picked from commit 1e8e55b670)
Define and use a blk-mq queue. Discards and flushes are processed
synchronously, but reads and writes asynchronously. In order to support
slow DMA unmapping, DMA unmapping is not done until after the next request
is started. That means the request is not completed until then. If there is
no next request then the completion is done by queued work.
Signed-off-by: Adrian Hunter <adrian.hunter@intel.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
Tested-by: Linus Walleij <linus.walleij@linaro.org>
(cherry picked from commit 81196976ed)
Until mmc has blk-mq support fully implemented and tested, add a parameter
use_blk_mq, set to true if config option MMC_MQ_DEFAULT is selected, which
it is by default.
Signed-off-by: Adrian Hunter <adrian.hunter@intel.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
Tested-by: Linus Walleij <linus.walleij@linaro.org>
(cherry picked from commit c3d53d0da6)
Use blk_cleanup_queue() to shutdown the queue when the driver is removed,
and instead get an extra reference to the queue to prevent the queue being
freed before the final mmc_blk_put().
Signed-off-by: Adrian Hunter <adrian.hunter@intel.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
Tested-by: Linus Walleij <linus.walleij@linaro.org>
(cherry picked from commit 41e3efd07d)
The following functions are needed by the mmc block device driver, once it
converts to blkmq, therefore let's export them.
mmc_start_bkops()
mmc_start_request()
mmc_retune_hold_now()
mmc_retune_release()
Signed-off-by: Adrian Hunter <adrian.hunter@intel.com>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
(cherry picked from commit cb39f61e9b)
Currently the host can be claimed by a task. Change this so that the host
can be claimed by a context that may or may not be a task. This provides
for the host to be claimed by a block driver queue to support blk-mq, while
maintaining compatibility with the existing use of mmc_claim_host().
Signed-off-by: Adrian Hunter <adrian.hunter@intel.com>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
(cherry picked from commit 6c0cedd1ef)
Adjust for small imx changes in debugfs
Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com>
Enhance mmc_blk_data_prep() to support CQE requests. That means adding
some things that for non-CQE requests would be encoded into the command
arguments - such as the block address, reliable-write flag, and data tag
flag. Also the request tag is needed to provide the command queue task id,
and a comment is added to explain the future possibility of defining a
priority.
Signed-off-by: Adrian Hunter <adrian.hunter@intel.com>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
(cherry picked from commit 93482b3d70)
Use local variables in mmc_blk_data_prep() in preparation for adding CQE
support which doesn't use the output variables.
Signed-off-by: Adrian Hunter <adrian.hunter@intel.com>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
(cherry picked from commit d3377c012f)
Enable the Command Queue if the host controller supports a command queue
engine. It is not compatible with Packed Commands, so make a note of that in the
comment.
Signed-off-by: Adrian Hunter <adrian.hunter@intel.com>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
(cherry picked from commit 98d4f7809d)
When pm_runtime_suspend is run, a call to SCFW power off the SS in
which the resource resides is made. The SCFW can power off the SS
if no other resource in active in tha SS. If so, all state associated
with all the resources within the SS that is powered off is lost,
this includes the clock rates, clock state etc. When pm_runtime_resume
is called, the SS associated with that resource is powered up. But
the clocks are left in the default state.
This patch restore clock rate in pm_runtime_resume, make sure the
clock is right rather than depending on the default state setting
by SCFW.
Signed-off-by: Haibo Chen <haibo.chen@nxp.com>
i.MX8QXP and i.MX8QM support Enhanced Strobe HS400 mode. This patch
add HS400_ES mode support, due to HS400_ES do not need tuning, select
HS400_ES mode should be faster than select HS400/HS200 mode.
Signed-off-by: Haibo Chen <haibo.chen@nxp.com>
commit 3f0191b80cf1 ("MLK-14381 mmc: sdhci-esdhc-imx: reset tuning
circuit when system resume") add tuning reset when the timing is
MMC_TIMING_LEGACY/MMC_TIMING_MMC_HS/MMC_TIMING_SD_HS. For timing
MMC_TIMING_MMC_HS, we can not do tuning reset, otherwise HS400
timing is not right.
Here is the process of config HS400, it do tuning in HS200 mode,
then switch to HS mode and 8 bit DDR mode, finally switch to HS400
mode. If we do tuning reset in HS mode, this will cause HS400 mode
lost the tuning setting, which will cause CRC error.
Signed-off-by: Haibo Chen <haibo.chen@nxp.com>
commit 70f2d20917bc ("MLK-14884 mmc: sdhci: make DDR50 tuning optionally")
want to make DDR50 card tuning optionally, but the code logic is not
right, the tuning of DDR50 card will also be impacted by the flag
'SDHCI_SDR50_NEEDS_TUNING'. e.g. imx6sl/imx6sx/imx6ul/imx7d default set
USE_TUNING_SDR50, which means on these SoC, DDR50 card still do tuning
even haven't the flag 'SDHCI_DDR50_NEEDS_TUNING'.
This patch fix the logic issue, separate DDR50 and SDR50 card.
Signed-off-by: Haibo Chen <haibo.chen@nxp.com>
After commit 3e3274ab9f ("mmc: sdhci-esdhc-imx: Use common
sdhci_suspend|resume_host()"), we lost the pins state store and save
in common sdhci_pltfm_{suspend|resume} API which results in the
pins state lost in state un-retainable suspend/resume, then
CMD transfer will meet timeout subsequently.
Due to sdhci_pltfm_{suspend|resume} API becomes static after
that commit later, we then do manual pins state save and restore
in our platform suspend/resume API instead.
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
DDR50 tuning is optinally defined in sd 3.0 spec. Per IC guys
suggestion, it internally already uses a fixed optimized timing
and normally does not require tuning.
Make it optionally and platform can claim SDHCI_DDR50_NEEDS_TUNING
support if it wants tuning.
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
MMC core code add 'MMC_CAP_RUNTIME_RESUME', postpone the real card
resume operation from bus_resume to bus_runtime_resume. So after
system resume, for non-removable-card, it still not really resume.
At this point, if user cat the ios or clock node, only get zero
data although the mmc/sd card is still present.
This patch add mmc_get_card() to make sure card really resume back
when user cat ios or clock debugfs file node, then user can get the
correct information.
Signed-off-by: Haibo Chen <haibo.chen@nxp.com>
MMC SDHCI maintainer Adrian Hunter Introduce SDHCI flags for signal
voltage support and set them based on the supported transfer modes,
except in the case where 3V DDR52 is supported but 1.8V is not.
This patch add the support to make eMMC DDR52 only work at 3.3v when
property 'no-1-8-v' defined.
Signed-off-by: Haibo Chen <haibo.chen@nxp.com>
On some SoCs such as i.MX7ULP, there is no busfreq
driver, but cpuidle has some levels which may disable
system/bus clocks, so need to add pm_qos to prevent
cpuidle from entering low level idles and make sure
system/bus clocks are enabled when usdhc is active.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
When suspend usdhc, it will access usdhc register. So usdhc clock
should be enabled, otherwise the access usdhc register will return
error or cause system.
Take this into consideration, if system enable a usdhc and do not
connect any SD/SDIO/MMC card, after system boot up, this usdhc
will do runtime suspend, and close all usdhc clock. At this time,
if suspend the system, due to no card persent, usdhc runtime resume
will not be called. So usdhc clock still closed, then in suspend,
once access usdhc register, system hung or bus error return.
This patch make sure usdhc clock always enabled while doing usdhc
suspend.
Signed-off-by: Haibo Chen <haibo.chen@nxp.com>
This reverts commit 2c01452f4d.
Besides, add other SoC request high bus freq. This is because
only imx6qdl do not implement low bus idle, so imx6qdl can work
well under low power mode without request high bus freq which
also can save power. For other SoC, need to request high bus
freq when usdhc is active.
Also can refer to commit 312979d1fc.
i.MX6ULL has errata ERR010450, which says due to SOC I/O timing
limit, eMMC HS200 and SD/SDIO 3.0 SDR104 at 1.8v can only work
below or equal to 150MHz. And eMMC DDR52 and SD/SDIO DDR50 at
1.8v can only work below or equal to 45MHz.
This patch add this limit for imx6ull.
Signed-off-by: Haibo Chen <haibo.chen@nxp.com>
For Mega/Mix enabled SoCs like MX7D and MX6SX, uSDHC will lost power in
LP mode no matter whether the MMC_KEEP_POWER flag is set or not.
This may cause state misalign between kernel and HW, especially for
SDIO3.0 WiFi cards.
e.g. SDIO WiFi driver usually will keep power during system suspend.
And after resume, no card re-enumeration called.
But the tuning state is lost due to Mega/Mix.
Then CRC error may happen during next data transfer.
So we should always fire a mmc_retune_needed() for such type SoC
to tell MMC core retuning is needed for next data transfer.
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
