Signed-off-by: Daniel Baluta <daniel.baluta@nxp.com>
Reviewed-by: Shengjiu Wang <shengjiu.wang@nxp.com>
(cherry picked from commit 8bc09ad559237c136f88d93bd696fe10dc4658db)
By default, imx8qm b0 silicon set the IO voltage to 2.5v, but the arm2
board is designed as 1.8v voltage for enet IO, so force the IO voltage
to 1.8 by setting COMP_CTL_GPIO_1V8_3V3 pins like:
For ENET0: SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB
For ENET1: SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETA
The pin setting:
1.8V/3.3V : bit4=0, bit[30]=1, bit[2:0]=000
2.5V : bit4=1, bit[30]=1, bit[2:0]=010
For 2.5v IO timing test, HW board need to do some rework:
- Force PHY work at 2.5v mode
- Supply 1.8v voltage to VDD_ENETx
Signed-off-by: Fugang Duan <fugang.duan@nxp.com>
In the L1.1 ASPM implementation, the CLK_REQ# should be
configured as open drain, pull up and input mode.
Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
In the L1.1 ASPM implementation, the CLK_REQ# should be
configured as open drain, pull up and input mode.
Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
Add SAI1 PDM pin definitions for imx8mm SoC.
Signed-off-by: Adrian Alonso <adrian.alonso@nxp.com>
(cherry picked from commit 1ada53b6b48dc6e7360b75403bd0796b4bf52cf9)
On i.MX8MM, it has an dram_alt clock source that can be used when
DDRC clock rate is lower than 667MHz, so add this clock.
Signed-off-by: Bai Ping <ping.bai@nxp.com>
Reviewed-by: Anson Huang <Anson.Huang@nxp.com>
(cherry picked from commit 303867c769e3c0758b9ee8fcf31d8cc3c632a80d)
Add LCDIF PLL resource and clocks, and power domain for it.
Add Pixel link clocks and set it from bypass path.
Muxes were added so that the slices can choose the bypass input
(lcd_pxl_bypass_div and elcdif_pll_div).
clk summary example:
lcd_pxl_bypass_div 2 2 24000000
lcd_pxl_sel 1 1 24000000
lcd_pxl_div 1 1 24000000
lcd_pxl_clk 1 1 24000000
elcdif_pll_div 1 1 792000000
elcdif_pll 2 2 792000000
lcd_sel 1 1 792000000
lcd_div 1 1 79200000
lcd_clk 1 1 79200000
Signed-off-by: Adriana Reus <adriana.reus@nxp.com>
In order to replace the M4_MU# by the LSIO MU in the
RPMSG usage.
Define the PD and LPCG address of the LSIO MU for iMX8.
Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
This patch adds the MIPI PWM_DIV and PWM_CLK clock definitions.
The PWM_DIV clock is the parent clock of PWM_CLK clock.
The PWM_CLK will be used as the 'per' clock by the PWM driver.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
(cherry picked from commit a32d7b4bcca3da7bd154eaf46cf04852279d2c87)
External differential clock phy_27m can be set to all
plls, rename from VIDEO2_PHY_27M to CLK_PHY_27M to avoid
confusion as clock source is the same option for all plls
Signed-off-by: Adrian Alonso <adrian.alonso@nxp.com>
Reviewed-by: Laurentiu Palcu <laurentiu.palcu@nxp.com>
(cherry picked from commit e4ac6dff8fa2eda6f5c2ed35cfea3550c59916da)
In order to avoid the name problem going forward with
integration with Qcom, Qcom has their own dsp and hifi
is competitor, so the hifi name should not be used in
our code.
So use the name of dsp instead of hifi to fix this
problem.
Signed-off-by: Weiguang Kong <weiguang.kong@nxp.com>
i.MX8QXP B0 silicon config enet IO voltage as 2.5V setting in default,
but MEK and ARM2 board only support 1.8V IO. So change the IO voltage
as 1.8V setting.
Set the MAC RGMII timing as TX no delay and RX delay mode as the default
setting for MEK and ARM2 board.
Since i.MX8QXP B0 silicon ENET IO timing change, to reach better timing
and avoid CRC error, MEK base board and ARM2 cpu board should remove the
driver device for the secord enet port.
Signed-off-by: Fugang Duan <fugang.duan@nxp.com>
Add missing sosc_bus_clk/firc_bus_clk/spll_bus_clk clocks which will be used
by other devices later.
All these clocks use the same divider as ddr_div, so ulp_div_table is used.
Besides that, all these clocks need to be controlled by M4, so
CLK_DIVIDER_READ_ONLY is also specified.
Fixes: aacf0b70af26 ("MLK-13441-6 ARM: imx: add i.mx7ulp clock driver")
Cc: Anson Huang <Anson.Huang@nxp.com>
Reviewed-by: Bai Ping <ping.bai@nxp.com>
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
'CKIL' clock name is derived from MX6 SoC series which is invalid for
MX7ULP (can't find it from RM). Changing it to the correct 'ROSC'
which is defined in RM.
The exist 'OSC' name is also changed accordingly which should be SOSC
(System OSC).
Fixes: aacf0b70af26 ("MLK-13441-6 ARM: imx: add i.mx7ulp clock driver")
Cc: Anson Huang <Anson.Huang@nxp.com>
Reviewed-by: Bai Ping <ping.bai@nxp.com>
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
The CCGR RAWNAND is shared by apbh-dma and gpmi clocks, so must use
imx_clk_gate2_shared2 to produce two clocks. Otherwise, apbh-dma clock
won't be enabled individually.
Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Bai Ping <ping.bai@nxp.com>
Add uSDHC clock MUX to allow uSDHC driver to select
parent, currently only support PLL0 and PLL1 as
uSDHC clock's parent.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Reviewed-by: Bai Ping <ping.bai@nxp.com>
Tested-by: Haibo Chen <haibo.chen@nxp.com>
Add CLKO2 for i.MX8MQ
Set parent for MIPI CSI1/2 CORE/PHY_REF/ESC
Signed-off-by: Robby Cai <robby.cai@nxp.com>
Reviewed-by: Sandor Yu <Sandor.yu@nxp.com>
The Video PLL2 has a output enable bit to do clk gate,
So we need to register this gate to save power.
Signed-off-by: Bai Ping <ping.bai@nxp.com>
Reviewed-by: Anson Huang <anson.huang@nxp.com>
Add missing clocks for MIPI-DSI SS: RX_ESC and TX_ESC
Also added the posibility to select clock parents for MIPI-DSI versus
LVDS.
The SCFW was changed, so now the LVDS pixel and phy clocks need to
specify their parrents.
Also, the TX_ESC and RX_ESC clocks from MIPI-DSI need to specify their
parrents in DTS files.
Signed-off-by: Robert Chiras <robert.chiras@nxp.com>
Signed-off-by: Oliver Brown <oliver.brown@nxp.com>
On i.MX8MQ, the dram core clock can be sourced from dram_pll or
the dram_alt clock, when sourced from the dram_alt, it has a fix
divider(1/4). When the DDRC core clock is lower than 800MHz, we
can swith the core clock to dram_alt source.
The dram apb clock's mux option 2 should be sys1_pll_40m, so fixed it.
Signed-off-by: Bai Ping <ping.bai@nxp.com>
Reviewed-by: Anson Huang <Anson.Huang@nxp.com>
DC clocks can choose their clock source between PLL1, PLL2 and
bypass input.
This patch introduces a multiplexer in the dc clock topology to
allow this choice and introduces one set of parents that will be used
for both display0 and display1 clocks.
Clock paths tested:
1. PLL2(dc0_pll1_clk)->DC0_DISP1(dc0_disp1_clk)->LVDS
2. BYP(dc0_bypass0_clk)->DC0_DISP1(dc0_disp1_clk)->LVDS
(BuildInfo: SCFW 9e9f6ec6, IMX-MKIMAGE 0, ATF 0)
Signed-off-by: Adriana Reus <adriana.reus@nxp.com>
Reviewed by: Ranjani Vaidyanathan <Ranjani.vaidyanathan@nxp.com>
Add focaltech new touch panel ft5246 support.
Set the ft5426 as default panel for dts. If want to use the old panel, then
it needs to boot with imx7ulp-evk-ft5416.dtb file.
Signed-off-by: Fugang Duan <fugang.duan@nxp.com>
(cherry picked from commit:963fea909ef5e42294cb2e656e5e3870a2171c01)
Define three root clocks for DCSS module:
.IMX8MQ_CLK_DISP_AXI_ROOT
.IMX8MQ_CLK_DISP_APB_ROOT
.IMX8MQ_CLK_DISP_RTRM_ROOT
These root clocks share one clock gate along with
'IMX8MQ_CLK_DISP_ROOT' clock. So change its type
to be shared gate clock too.
Signed-off-by: Fancy Fang <chen.fang@nxp.com>
