update the noc QoS setting for CPU & VPU on i.MX8MQ.
Signed-off-by: Bai Ping <ping.bai@nxp.com>
Reviewed-by: Jian Li <jian.li@nxp.com>
(cherry picked from commit 45d2dcaecce6d83e5c4a7e9488c651a05b0f05ac)
This patch adds SC_C_SYNC_CTRL into enum sc_ctrl_e to sync with SCU
firmware commit <1db854d7d521> (SCF-151: Added new SC_C_SYNC_CTRL to
control both control signals at the same time.).
Signed-off-by: Liu Ying <victor.liu@nxp.com>
(cherry picked from commit 9e4a5892da)
Add PAD wakeup support for i.MX8 platforms with system
controller present, with PAD wakeup feature enabled,
the corresponding resource's power is no need to be
kept enabled when linux suspend, thus save a sub-system's
power consumption.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Reviewed-by: Bai Ping <ping.bai@nxp.com>
(cherry picked from commit 3b5d781273b22461de9aaea337f9da9b2fdb643e)
Signed-off-by: Daniel Baluta <daniel.baluta@nxp.com>
Reviewed-by: Shengjiu Wang <shengjiu.wang@nxp.com>
(cherry picked from commit 8bc09ad559237c136f88d93bd696fe10dc4658db)
Remove unused ROMCP clks and related as LPCG
no longer exists
Signed-off-by: Teo Hall <teo.hall@nxp.com>
Reviewed-by: Anson Huang <Anson.Huang@nxp.com>
(cherry picked from commit 1c15332dffe7e41f0b9d367b96dd426798ec8b06)
Add LCDIF PLL resource and clocks, and power domain for it.
Add Pixel link clocks and set it from bypass path.
Muxes were added so that the slices can choose the bypass input
(lcd_pxl_bypass_div and elcdif_pll_div).
clk summary example:
lcd_pxl_bypass_div 2 2 24000000
lcd_pxl_sel 1 1 24000000
lcd_pxl_div 1 1 24000000
lcd_pxl_clk 1 1 24000000
elcdif_pll_div 1 1 792000000
elcdif_pll 2 2 792000000
lcd_sel 1 1 792000000
lcd_div 1 1 79200000
lcd_clk 1 1 79200000
Signed-off-by: Adriana Reus <adriana.reus@nxp.com>
In order to replace the M4_MU# by the LSIO MU in the
RPMSG usage.
Define the PD and LPCG address of the LSIO MU for iMX8.
Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
To support lowest power mode for suspend, if no wakeup source
from non-secure partition is enabled, IRQSTEER can be powered
off when suspend, otherwise, IRQSTEER needs to be powered on
to support wakeup, so need to pass WU domain wakeup source
info to ATF, then ATF will decide if to power off IRQSTEER
when system suspend.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Reviewed-by: Bai Ping <ping.bai@nxp.com>
Let Dom0 use hvc to trap to xen to communicate with SCU.
xen could reuse the MU used by Dom0 before. By reusing
the MU in Dom0, xen has power to control resources owned
by DomU.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
- Sync with scu firmware commit 576011819ce3 (SCF-81: Added API to
control MIPI CSI calibration.) and commit 095a0d7dbc0b (SCF-85: Add
direct control of ENET IPG stop control)
- Add ipg stop misc controls for CONN ENET.
Reviewed-by: Richard Zhu <hongxing.zhu@nxp.com>
Signed-off-by: Fugang Duan <fugang.duan@nxp.com>
In order to avoid the name problem going forward with
integration with Qcom, Qcom has their own dsp and hifi
is competitor, so the hifi name should not be used in
our code.
So use the name of dsp instead of hifi to fix this
problem.
Signed-off-by: Weiguang Kong <weiguang.kong@nxp.com>
"
commit cfdb9821531da523fd1f01536eb67c8b8451477f
Author: Oliver Brown <oliver.brown@nxp.com>
Date: Tue Jan 2 07:46:06 2018 -0600
dc: Add controls for display controller resets.
"
Signed-off-by: Oliver Brown <oliver.brown@nxp.com>
Config NOC to limit bandwidth to 4GB for both VPU
and CPU to avoid lcdif flickering only when lcdif is enabled.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Acked-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Bai Ping <ping.bai@nxp.com>
(cherry picked from commit 8ab89ebeb94a423792bf588bdf2354c5960d8f13)
On i.MX8MQ, the new revision SoC does NOT update the
revision info in ANATOP_DIGPROG register, to support
dynamic SOC id/revision detection, only reading info
from ANATOP_DIGPROG is not working now, change to read
SOC id/revision from ATF which is in secure world.
The ATF will read the ANATOP_DIGPROG as well as ROM
version to decide the SOC revision.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Reviewed-by: Bai Ping <ping.bai@nxp.com>
Support M4/A53 work together
1. add imx_src_is_m4_enabled
2. introduce a new dts dedicated for m4
3. add more pwm nodes
4. Since clk initialization is at very early stage, add m4 enabled check
in the beginning of clk code.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Richard Zhu <hongxing.zhu@nxp.com>
Add busfreq driver support on i.MX8MQ. The busfreq driver is
mainly used for dynamic DDR frequency change for power saving
feature. When there is no peripheral or DMA device has direct
access to DDR memory, we can lower the DDR frequency to save
power. Currently, we support frequency setpoint for LPDDR4:
(1): 3200mts, the DDRC core clock is sourced from 800MHz
dram_pll, the DDRC apb clock is 200MHz.
(2): 400mts, the DDRC core clock is source from sys1_pll_400m,
the DDRC apb clock is is sourced from sys1_pll_40m.
(3): 100mts, the DDRC core clock is sourced from sys1_pll_100m,
the DDRC apb clock is sourced from sys1_pll_40m.
In our busfreq driver, we have three mode supported:
* high bus mode <-----> 3200mts;
* audio bus mode <-----> 400mts;
* low bus mode <-----> 100mts;
The actual DDR frequency is done in ARM trusted firmware by calling
the SMCC SiP service call.
BuildInfo:
- IMX-MKIMAGE: 05d3d4a7d7, ATF: 724cc2b890
- SPL/Uboot: f72c10d2db;
Signed-off-by: Bai Ping <ping.bai@nxp.com>
Reviewed-by: Anson Huang <Anson.Huang@nxp.com>
This watchdog driver is a virtual driver in Linux and call ATF interface
where call SCFW eventually. In SCFW, it's done by SCU timer tick instead
of hardware watchdog.This is why we have to call ATF because such system
resource owned by secure patition.Currently, booard reset happen if not
ping this software watchdog in time in linux side, may change to partition
reboot once SCFW support this feature in the future.
BuildInfo:
- SCFW 93c142a9, IMX-MKIMAGE 2522fd70, ATF f2547fb
- U-Boot 2017.03-00097-gd7599cf
Signed-off-by: Robin Gong <yibin.gong@nxp.com>
Reviewed-by: Anson Huang <Anson.Huang@nxp.com>
For system controller RTC, as it belongs SC_R_SYSTEM,
and SC_R_SYSTEM is assigned in ARM-Trusted-Firmware,
so here needs to use SIP to trap into ATF to do set
time, or system controller firmware will return
error since linux kernel does NOT own this system
resource.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Add SIP cpu-freq support, the CPU hardware frequency
scale will be performed by ARM Trusted Firmware,
and add cpu-freq suspend support, MAX frequency will
be used during suspend.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
This patch is to refine the imx8 soc revision support. The imx8qm and
imx8qxp will go through the SCU API to get the silicon ID and REVISION.
imx8mq will go through the anatop interface to get the ID/REV.
Since the silicon ID/REV need be set as early as possible, thus refine it
by using the early_initcall for the early initialization. For the SCU API
interface, this need be called after the MU interface initialized.
Signed-off-by: Jason Liu <jason.hui.liu@nxp.com>
Reviewed-by: Anson Huang <anson.huang@nxp.com>
Add generic power domain driver support on i.mx8mq. The power
domain on/off operations need to use the SIP service call to
trap into secure monitor to handle it.
Signed-off-by: Bai Ping <ping.bai@nxp.com>
Add i.MX8 SCFW API support.
Based on below commit:
(fcd0efb5f2550712bd7d27f1279e51f7f687f71d)
Fix MX8 MU driver to follow Linux coding conventions.
Remove unused functions.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Signed-off-by: Ranjani Vaidyanathan <Ranjani.Vaidyanathan@nxp.com>
Added to drivers/soc/imx instead of drivers/soc/imx8
Skipped imx8 imx_rpmsg code
Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com>
As A9 and M4 share many resources on i.MX6SX, especially for
clk and power related resource, so we need to handle the hardware
conflict between these two cores, there are two cases that we
need to consider currently:
clk management: for every clk node, only when both A9 and
M4 do NOT need it, then we can disable it from hardware;
Here we use MU and hardware SEMA4 to achieve our goal, MU is
for communiation between A9 and M4, SEMA4 is to protect the
shared memory.
For clk management, we use shared memory to maintain the clk
status for both A9 and M4 side, and this shared memory is
protected by hardware SEMA4, A9 and M4 will maintain their
own clk tree info in their SW environment, and get other
CORE's clk tree info from shared memory to decide whether
to perform a hardware setting change when they plan to.
Signed-off-by: Anson Huang <b20788@freescale.com>
Also made SOC_IMX6SX select IMX_SEMA4 as part of this commit to fix
build failures.
Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com>
[ Upstream commit 1c74d5c0de ]
Currently we are enabling handling of interrupts specific to Tegra124+
which happen to overlap with previous generations. Let's specify
interrupts mask per SoC generation for consistency and in a preparation
of squashing of Tegra20 driver into the common one that will enable
handling of GART faults which may be undesirable by newer generations.
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Sasha Levin <alexander.levin@microsoft.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
[ Upstream commit 144345a4a8 ]
If CONFIG_RASPBERRYPI_FIRMWARE=n:
drivers/gpio/gpio-raspberrypi-exp.c: In function ‘rpi_exp_gpio_get_polarity’:
drivers/gpio/gpio-raspberrypi-exp.c:71: warning: ‘get.polarity’ is used uninitialized in this function
drivers/gpio/gpio-raspberrypi-exp.c: In function ‘rpi_exp_gpio_get_direction’:
drivers/gpio/gpio-raspberrypi-exp.c:150: warning: ‘get.direction’ is used uninitialized in this function
The dummy firmware interface functions return 0, which means success,
causing subsequent code to make use of the never initialized output
parameter.
Fix this by making the dummy functions return an error code (-ENOSYS)
instead.
Note that this assumes the firmware always fills in the requested data
in the CONFIG_RASPBERRYPI_FIRMWARE=y case.
Fixes: d45f1a563b ("staging: vc04_services: fix up rpi firmware functions")
Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
Signed-off-by: Sasha Levin <alexander.levin@microsoft.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
[ Upstream commit f3205de98d ]
As of today we use hardcoded MCIP debug mask, so if we launch
kernel via debugger and kick fever cores than HW has all cpus
hang at the momemt of setup MCIP debug mask.
So update MCIP debug mask when the new cpu came online, instead of
use hardcoded MCIP debug mask.
Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
Signed-off-by: Sasha Levin <alexander.levin@microsoft.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
[ Upstream commit 07423d00a2 ]
In SMP systems, GFRC is used for clocksource. However by default the
counter keeps running even when core is halted (say when debugging via a
JTAG debugger). This confuses Linux timekeeping and triggers flase RCU stall
splat such as below:
| [ARCLinux]# while true; do ./shm_open_23-1.run-test ; done
| Running with 1000 processes for 1000 objects
| hrtimer: interrupt took 485060 ns
|
| create_cnt: 1000
| Running with 1000 processes for 1000 objects
| [ARCLinux]# INFO: rcu_preempt self-detected stall on CPU
| 2-...: (1 GPs behind) idle=a01/1/0 softirq=135770/135773 fqs=0
| INFO: rcu_preempt detected stalls on CPUs/tasks:
| 0-...: (1 GPs behind) idle=71e/0/0 softirq=135264/135264 fqs=0
| 2-...: (1 GPs behind) idle=a01/1/0 softirq=135770/135773 fqs=0
| 3-...: (1 GPs behind) idle=4e0/0/0 softirq=134304/134304 fqs=0
| (detected by 1, t=13648 jiffies, g=31493, c=31492, q=1)
Starting from ARC HS v3.0 it's possible to tie GFRC to state of up-to 4
ARC cores with help of GFRC's CORE register where we set a mask for
cores which state we need to rely on.
We update cpu mask every time new cpu came online instead of using
hardcoded one or using mask generated from "possible_cpus" as we
want it set correctly even if we run kernel on HW which has fewer cores
than expected (or we launch kernel via debugger and kick fever cores
than HW has)
Note that GFRC halts when all cores have halted and thus relies on
programming of Inter-Core-dEbug register to halt all cores when one
halts.
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
[vgupta: rewrote changelog]
Signed-off-by: Sasha Levin <alexander.levin@microsoft.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Pull ARM SoC driver updates from Olof Johansson:
"This branch contains platform-related driver updates for ARM and ARM64.
Among them:
- Reset driver updates:
+ New API for dealing with arrays of resets
+ Make unimplemented {de,}assert return success on shared resets
+ MSDKv1 driver
+ Removal of obsolete Gemini reset driver
+ Misc updates for sunxi and Uniphier
- SoC drivers:
+ Platform SoC driver registration on Tegra
+ Shuffle of Qualcomm drivers into a submenu
+ Allwinner A64 support for SRAM
+ Renesas R-Car R3 support
+ Power domains for Rockchip RK3366
- Misc updates and smaller fixes for TEE and memory driver
subsystems"
* tag 'armsoc-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (54 commits)
firmware: arm_scpi: fix endianness of dev_id in struct dev_pstate_set
soc/tegra: fuse: Add missing semi-colon
soc/tegra: Restrict SoC device registration to Tegra
drivers: soc: sunxi: add support for A64 and its SRAM C
drivers: soc: sunxi: add support for remapping func value to reg value
drivers: soc: sunxi: fix error processing on base address when claiming
dt-bindings: add binding for Allwinner A64 SRAM controller and SRAM C
bus: sunxi-rsb: Enable by default for ARM64
soc/tegra: Register SoC device
firmware: tegra: set drvdata earlier
memory: Convert to using %pOF instead of full_name
soc: Convert to using %pOF instead of full_name
bus: Convert to using %pOF instead of full_name
firmware: Convert to using %pOF instead of full_name
soc: mediatek: add SCPSYS power domain driver for MediaTek MT7622 SoC
soc: mediatek: add header files required for MT7622 SCPSYS dt-binding
soc: mediatek: reduce code duplication of scpsys_probe across all SoCs
dt-bindings: soc: update the binding document for SCPSYS on MediaTek MT7622 SoC
reset: uniphier: add analog amplifiers reset control
reset: uniphier: add video input subsystem reset control
...
The M4U IP blocks in mt2712 is MTK's generation2 M4U which use the
ARM Short-descriptor like mt8173, and most of the HW registers are
the same.
The difference is that there are 2 M4U HWs in mt2712 while there's
only one in mt8173. The purpose of 2 M4U HWs is for balance the
bandwidth.
Normally if there are 2 M4U HWs, there should be 2 iommu domains,
each M4U has a iommu domain.
Signed-off-by: Yong Wu <yong.wu@mediatek.com>
Signed-off-by: Joerg Roedel <jroedel@suse.de>
Move this code from arch/arm/mach-tegra and make it common among 32-bit
and 64-bit Tegra SoCs. This is slightly complicated by the fact that on
32-bit Tegra, the SoC device is used as the parent for all devices that
are instantiated from device tree.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Pull networking updates from David Miller:
"Reasonably busy this cycle, but perhaps not as busy as in the 4.12
merge window:
1) Several optimizations for UDP processing under high load from
Paolo Abeni.
2) Support pacing internally in TCP when using the sch_fq packet
scheduler for this is not practical. From Eric Dumazet.
3) Support mutliple filter chains per qdisc, from Jiri Pirko.
4) Move to 1ms TCP timestamp clock, from Eric Dumazet.
5) Add batch dequeueing to vhost_net, from Jason Wang.
6) Flesh out more completely SCTP checksum offload support, from
Davide Caratti.
7) More plumbing of extended netlink ACKs, from David Ahern, Pablo
Neira Ayuso, and Matthias Schiffer.
8) Add devlink support to nfp driver, from Simon Horman.
9) Add RTM_F_FIB_MATCH flag to RTM_GETROUTE queries, from Roopa
Prabhu.
10) Add stack depth tracking to BPF verifier and use this information
in the various eBPF JITs. From Alexei Starovoitov.
11) Support XDP on qed device VFs, from Yuval Mintz.
12) Introduce BPF PROG ID for better introspection of installed BPF
programs. From Martin KaFai Lau.
13) Add bpf_set_hash helper for TC bpf programs, from Daniel Borkmann.
14) For loads, allow narrower accesses in bpf verifier checking, from
Yonghong Song.
15) Support MIPS in the BPF selftests and samples infrastructure, the
MIPS eBPF JIT will be merged in via the MIPS GIT tree. From David
Daney.
16) Support kernel based TLS, from Dave Watson and others.
17) Remove completely DST garbage collection, from Wei Wang.
18) Allow installing TCP MD5 rules using prefixes, from Ivan
Delalande.
19) Add XDP support to Intel i40e driver, from Björn Töpel
20) Add support for TC flower offload in nfp driver, from Simon
Horman, Pieter Jansen van Vuuren, Benjamin LaHaise, Jakub
Kicinski, and Bert van Leeuwen.
21) IPSEC offloading support in mlx5, from Ilan Tayari.
22) Add HW PTP support to macb driver, from Rafal Ozieblo.
23) Networking refcount_t conversions, From Elena Reshetova.
24) Add sock_ops support to BPF, from Lawrence Brako. This is useful
for tuning the TCP sockopt settings of a group of applications,
currently via CGROUPs"
* git://git.kernel.org/pub/scm/linux/kernel/git/davem/net-next: (1899 commits)
net: phy: dp83867: add workaround for incorrect RX_CTRL pin strap
dt-bindings: phy: dp83867: provide a workaround for incorrect RX_CTRL pin strap
cxgb4: Support for get_ts_info ethtool method
cxgb4: Add PTP Hardware Clock (PHC) support
cxgb4: time stamping interface for PTP
nfp: default to chained metadata prepend format
nfp: remove legacy MAC address lookup
nfp: improve order of interfaces in breakout mode
net: macb: remove extraneous return when MACB_EXT_DESC is defined
bpf: add missing break in for the TCP_BPF_SNDCWND_CLAMP case
bpf: fix return in load_bpf_file
mpls: fix rtm policy in mpls_getroute
net, ax25: convert ax25_cb.refcount from atomic_t to refcount_t
net, ax25: convert ax25_route.refcount from atomic_t to refcount_t
net, ax25: convert ax25_uid_assoc.refcount from atomic_t to refcount_t
net, sctp: convert sctp_ep_common.refcnt from atomic_t to refcount_t
net, sctp: convert sctp_transport.refcnt from atomic_t to refcount_t
net, sctp: convert sctp_chunk.refcnt from atomic_t to refcount_t
net, sctp: convert sctp_datamsg.refcnt from atomic_t to refcount_t
net, sctp: convert sctp_auth_bytes.refcnt from atomic_t to refcount_t
...
The BPMP firmware, found on Tegra186 and later, provides an ABI that can
be used to enable and disable power to several power partitions in Tegra
SoCs. The ABI allows for enumeration of the available power partitions,
so the driver can be reused on future generations, provided the BPMP ABI
remains stable.
Based on work by Stefan Kristiansson <stefank@nvidia.com> and Mikko
Perttunen <mperttunen@nvidia.com>.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Update the BPMP ABI header to a more recent version. The new version
adds support for a new powergating ABI as well as access to the ring
buffer console, which allows debug messages to be output to the BPMP
debug console.
Some of the previously undocumented fields have been documented and
missing bitmasks have been added. Furthermore the MRQ_RESET request
now has a sub-command that allows to determine the maximum ID which
in turn allows the resets to be enumerated, thereby allowing drivers
to become agnostic of the Tegra generation.
Signed-off-by: Thierry Reding <treding@nvidia.com>
This adds support for hdlc-bus mode to the fsl_ucc_hdlc driver. This can
be enabled with the "fsl,hdlc-bus" property in the DTS node of the
corresponding ucc.
This aligns the configuration of the UPSMR and GUMR registers to what is
done in our ucc_hdlc driver (that only support hdlc-bus mode) and with
the QuickEngine's documentation for hdlc-bus mode.
GUMR/SYNL is set to AUTO for the busmode as in this case the CD signal
is ignored. The brkpt_support is enabled to set the HBM1 bit in the
CMXUCR register to configure an open-drain connected HDLC bus.
Signed-off-by: Holger Brunck <holger.brunck@keymile.com>
Cc: Zhao Qiang <qiang.zhao@nxp.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Pull more powerpc updates from Michael Ellerman:
"The change to the Linux page table geometry was delayed for more
testing with 16G pages, and there's the new CPU features stuff which
just needed one more polish before going in. Plus a few changes from
Scott which came in a bit late. And then various fixes, mostly minor.
Summary highlights:
- rework the Linux page table geometry to lower memory usage on
64-bit Book3S (IBM chips) using the Hash MMU.
- support for a new device tree binding for discovering CPU features
on future firmwares.
- Freescale updates from Scott:
"Includes a fix for a powerpc/next mm regression on 64e, a fix for
a kernel hang on 64e when using a debugger inside a relocated
kernel, a qman fix, and misc qe improvements."
Thanks to: Christophe Leroy, Gavin Shan, Horia Geantă, LiuHailong,
Nicholas Piggin, Roy Pledge, Scott Wood, Valentin Longchamp"
* tag 'powerpc-4.12-2' of git://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux:
powerpc/64s: Support new device tree binding for discovering CPU features
powerpc: Don't print cpu_spec->cpu_name if it's NULL
of/fdt: introduce of_scan_flat_dt_subnodes and of_get_flat_dt_phandle
powerpc/64s: Fix unnecessary machine check handler relocation branch
powerpc/mm/book3s/64: Rework page table geometry for lower memory usage
powerpc: Fix distclean with Makefile.postlink
powerpc/64e: Don't place the stack beyond TASK_SIZE
powerpc/powernv: Block PCI config access on BCM5718 during EEH recovery
powerpc/8xx: Adding support of IRQ in MPC8xx GPIO
soc/fsl/qbman: Disable IRQs for deferred QBMan work
soc/fsl/qe: add EXPORT_SYMBOL for the 2 qe_tdm functions
soc/fsl/qe: only apply QE_General4 workaround on affected SoCs
soc/fsl/qe: round brg_freq to 1kHz granularity
soc/fsl/qe: get rid of immrbar_virt_to_phys()
net: ethernet: ucc_geth: fix MEM_PART_MURAM mode
powerpc/64e: Fix hang when debugging programs with relocated kernel
Pull ARM SoC driver updates from Olof Johansson:
"Driver updates for ARM SoCs:
Reset subsystem, merged through arm-soc by tradition:
- Make bool drivers explicitly non-modular
- New support for i.MX7 and Arria10 reset controllers
PATA driver for Palmchip BK371 (acked by Tejun)
Power domain drivers for i.MX (GPC, GPCv2)
- Moved out of mach-imx for GPC
- Bunch of tweaks, fixes, etc
PMC support for Tegra186
SoC detection support for Renesas RZ/G1H and RZ/G1N
Move Tegra flow controller driver from mach directory to drivers/soc
- (Power management / CPU power driver)
Misc smaller tweaks for other platforms"
* tag 'armsoc-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (60 commits)
soc: pm-domain: Fix the mangled urls
soc: renesas: rcar-sysc: Add support for R-Car H3 ES2.0
soc: renesas: rcar-sysc: Add support for fixing up power area tables
soc: renesas: Register SoC device early
soc: imx: gpc: add workaround for i.MX6QP to the GPC PD driver
dt-bindings: imx-gpc: add i.MX6 QuadPlus compatible
soc: imx: gpc: add defines for domain index
soc: imx: Add GPCv2 power gating driver
dt-bindings: Add GPCv2 power gating driver
ARM/clk: move the ICST library to drivers/clk
ARM: plat-versatile: remove stale clock header
ARM: keystone: Drop PM domain support for k2g
soc: ti: Add ti_sci_pm_domains driver
dt-bindings: Add TI SCI PM Domains
PM / Domains: Do not check if simple providers have phandle cells
PM / Domains: Add generic data pointer to genpd data struct
soc/tegra: Add initial flowctrl support for Tegra132/210
soc/tegra: flowctrl: Add basic platform driver
soc/tegra: Move Tegra flowctrl driver
ARM: tegra: Remove unnecessary inclusion of flowctrl header
...
