Because of the delay of auto suspend, the nand clocks are delayed to
disable when calling the clk_set_rate. This causes the clk_set_rate
failed on some platforms like 6q/6qp, and finally lead the NAND not
working.
Signed-off-by: Ye.Li <Ye.Li@freescale.com>
Signed-off-by: Fugang Duan <B38611@freescale.com>
(cherry picked from commit: 1334dd236d4401d6635accb6c8472d8a5ed088b5)
support runtime PM on gpmi nand to save the cost to enable/disable clock
in each NAND IO. The driver also claim high-freq bus when resumed.
Signed-off-by: Han Xu <b45815@freescale.com>
The per1_bch was moved in patch below since it was never mentioned in
any GPMI/BCH/APBH documents, but actually it is necessary for BCH module
since BCH use AXI bus transfer data through fabric, need to enable this
clock for BCH at fabric side.
This patch enabled this clock for all i.MX6 platforms and has been
tested on i.MX6Q/i.MX6QP/i.MX6SX and i.MX6UL.
commit 9aa0fb0a606a583e2b6e19892ac2cab1b0e726c4
Author: Han Xu <b45815@freescale.com>
Date: Thu May 28 16:49:18 2015 -0500
mtd: nand: support NAND on i.MX6UL
support i.MX6UL GPMI NAND driver and removed the unecessary clock
per1_bch.
Signed-off-by: Han Xu <b45815@freescale.com>
Fixed in 4.14 rebase for different clock array.
Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com>
support i.MX6UL GPMI NAND driver and removed the unecessary clock
per1_bch.
Signed-off-by: Han Xu <b45815@freescale.com>
During 4.14 rebase fixed for upstream moving clocks to gpmi_devdata
Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com>
when the maximum ecc NAND oob can afford exceed the ecc strength
controller can provide, use the maximum ecc strength controller can
support instead of the minimum ecc NAND spec required.
kobs-ng will also use the same ecc strength to align with kernel to make
sure all NAND chips can boot.
Signed-off-by: Han Xu <b45815@freescale.com>
(cherry picked from commit: 958a2c5b07524f3502cfdefe66724a9a1f8ad608)
i.MX6QP and i.MX7D BCH module integrated a new feature to detect the
bitflip number for erased NAND page. So for these two platform, set the
erase threshold to gf/2 and if bitflip detected, GPMI driver will
correct the data to all 0xFF.
Also updated the imx6qp dts file to ditinguish the GPMI module for i.MX6Q
with the one for i.MX6QP.
Signed-off-by: Han Xu <b45815@freescale.com>
Modified during 4.14 rebase to use GPMI_IS_MX7D instead of GPMI_IS_MX7
because upstream never added GPMI_IS_MX7 when adding mx7 support.
Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com>
This patch adds pll1, pll_bypass and pll1_bypass_src that
will be used in ARM clock switching code.
Signed-off-by: Bai Ping <b51503@freescale.com>
Updated during 4.14 rebase
Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com>
Currently, the dma engine driver don't support runtime pm,
and it is not necessary to support the feature since it support
slave sg and cyclic mode, and clock enable/disable during dma
chans allocate and release.
The patch remove the runtime pm dummy code.
Signed-off-by: Fugang Duan <B38611@freescale.com>
(cherry picked from commit: 2c8f8e3e6a21184e6cf8b8e5ba3ec8e76794c951)
After dma init by calling .mxs_dma_init(), disable dma_io and
dma_bch clocks. When dma chans are requested by devices, clocks
are enabled in .device_alloc_chan_resources(). The patch is to
fix clock enable count mismatch issue.
Signed-off-by: Fugang Duan <B38611@freescale.com>
(cherry picked from commit: 4868cf5e39a0aeb1ad12c5c1a453d233c0f472ce)
* iMX7D dma-apbh support add additional clock dependency
* Add clock for mxs-dma support dma_apbh_bch dma_apbh_io
Signed-off-by: Adrian Alonso <aalonso@freescale.com>
Signed-off-by: Fugang Duan <B38611@freescale.com>
(cherry picked from commit: aea75669daac9101592de2cfbadc7aaacbc7d887)
this patch adds power management support for mxs-dma driver.
Signed-off-by: Huang Shijie <b32955@freescale.com>
Signed-off-by: Allen Xu <b45815@freescale.com>
Signed-off-by: Fugang Duan <B38611@freescale.com>
(cherry picked from commit 7a59828eeda36457e6e60383705a0bc5831ffbf7)
Enable fec1 and fec2 for lpsr mode.
Signed-off-by: Fugang Duan <B38611@freescale.com>
(cherry picked from commit: 1fe7e098efc52abecdd3cf4a2ed8add5582393dc)
Also disable rx fifo overrun interrupt during uart port shutdown.
Signed-off-by: Fugang Duan <B38611@freescale.com>
(cherry picked from commit: 39eb703f6c9f9359723f3fa22e798b1d21b44c67)
Add return value check for clk_set_rate() to avoid set clock
rate fail.
Signed-off-by: Fugang Duan <B38611@freescale.com>
(cherry picked from commit: bcd9d743ef534cf58d2d007e6333270be12c9f06)
When UART module clock is great than 80Mhz, there may have risk after
confirming with IC owner. So set the maximum module clock to 80Mhz.
Signed-off-by: Fugang Duan <B38611@freescale.com>
(cherry picked from commit: 330a1245cb91583d9bc916bbb6d8c7d2c86b26f3)
There exists one issue in Android environment when do power key on/off
test that cause system hang. Because suspend function disable enet all
clocks while timer interrupt comming that introduces registers access.
When link down and suspend, the timer interrupt is not necessary
to enable, so disable it.
Signed-off-by: Fugang Duan <B38611@freescale.com>
Tested-by: Fugang Duan <B38611@freescale.com>
Tested-by: Chen Guoyin <B07211@freescale.com>
Tested-by: Zhu Wenbo <B52619@freescale.com>
(cherry picked from commit: 048f62891bc4936991fd58dbaf4a606a30282404)
The API devm_request_and_ioremap meets compile error
on branch imx_4.1.y. It is recommend to replace the api
with devm_ioremap_resource.
Signed-off-by: Gao Pan <b54642@freescale.com>
Add the option to enable SIM driver build.
Signed-off-by: Luwei Zhou <b45643@freescale.com>
Signed-off-by: Gao Pan <b45643@freescale.com>
(cherry picked from 0f7a6fa3c141bfc7333d9056639b7a5b1154ed1d)
The EMV4.3 has strict requirement about the reset sequence. The old code use the mdelay, udelay to
achievet, which is not precise enough. Replace it with the timer interrupt. The EMV4.3 requires
40000~45000 clock cycles duration when reset is low.
Signed-off-by: Luwei Zhou <b45643@freescale.com>
(cherry picked from a006fe283c8b97f0a711cb0829bfbdaaf4a5f31f)
In EMV4.3 after warm/cold reset, there would be a receiving window. The receiving
window would be 42000 clock length.If the receiving window expires without receiving
one byte, IFD need to take actions as EMV4.3 spec. The driver need to support this
to identify the sequence of the receiving window expiring event and the receiving event.
Since theinterrupt latency in linux OS is not certain, we need to tune this setting to
pass the cases. Current tuning parameter can work.
Signed-off-by: Luwei Zhou <b45643@freescale.com>
(cherry picked from faf1d8d881a6ad2c6b88fdf312cef142996937c1)
The CWT timer is used to detect the the character interval in the data traffic.
When tx, SIM IP can guarantee the interval based our setting. When RX, we need
to enalbe the CWT timer to check whether the interval is in the range. This patch
fix this.
Signed-off-by: Luwei Zhou <b45643@freescale.com>
(cherry picked from 9c92dfd070e7427eb1e0166f368b89b4a7ac1bff)
Modify the driver to support the SIM on i.MX6UL-EVK platform. The main modification is:
1. Add port index to support different port on platform.
2. Add POS-CARD support. The POS card has external IC to assert when SVEN to low. Add support.
3. Using a function to calculate the strict timing delay.
Signed-off-by: Luwei Zhou <b45643@freescale.com>
(cherry picked from 17d1315b0704e2db63ee6bd7aaefa0c796f53104)
This driver is based on the current code which runs the the EMV test on the i.MX258 platform.
Since there are still many cases that can't pass on the i.MX258 and i.MX7d platform. The
driver will need to be improved after per-test work. Just check in as a base code. There
would be definitly some timing improvement work to do in the future.
Signed-off-by: Luwei Zhou <b45643@freescale.com>
(cherry picked from 3ac1ad5b2a68ecb052ccacca4ac7459ead04415e)
Enable cpuidle for i.MX7D, total 3 level idle supported:
1. ARM WFI;
2. WAIT mode;
3. Low power idle with ARM/SCU platform power off.
Only when system in low bus freq mode, system is able to
enter low power idle, and only when both of 2 cores are
in low power idle, ARM/SCU platform will be powered off.
DDR will be put into low power mode when low power idle
is entered.
Signed-off-by: Anson Huang <b20788@freescale.com>
To achieve low power, debug uart clk should be from OSC, so that
it does NOT need to keep PLL on, especially for low power idle
case.
Signed-off-by: Anson Huang <b20788@freescale.com>
We set both wartermark of txfifo and rxfifo 32 as half of fifo length 64.
That will cause easy rxfifo overflow:
If there is 31 bytes in rxfifo, rx script will wait the next dma request
(the 32th data come into the rxfifo) and schedule out to tx script. Once
tx script start to run, the rx script need to wait tx script finish even
if its priority higher than tx. Meanwhile, spi slave device may input
data continous, plus the rx data which triggered by new tx script(32 bytes).
That will quickly consume whole 64 bytes fifo, so we keep 16bytes availbale
even in the worst case new tx script triggered during two rx transfer. That
may slow down tx slightly, but better than overflow and RX DMA timeout.
Signed-off-by: Robin Gong <b38343@freescale.com>
(cherry picked from commit 16043ad0ad96aa04a90614e473aa17980af4b8af)
(cherry picked from commit 819efee83b7b1f47685dca6fad6bbe17f1c42092)
(cherry picked from commit 5c4c7d05bbba0ea2b26ef2f3ae83119d5eada235)
There is occasion that dma callback come late after the substream is released.
Then there will be kernel dump.
[<805866b0>] (imx_pcm_dma_complete) from [<802fad9c>] (sdma_handle_channel_loop.isra.25+0x48/0x54)
[<802fad9c>] (sdma_handle_channel_loop.isra.25) from [<802fae48>] (sdma_tasklet+0xa0/0x1d4)
[<802fae48>] (sdma_tasklet) from [<800356e0>] (tasklet_action+0x64/0xf8)
[<800356e0>] (tasklet_action) from [<80034ea0>] (__do_softirq+0x104/0x218)
[<80034ea0>] (__do_softirq) from [<80035220>] (irq_exit+0xa8/0xec)
[<80035220>] (irq_exit) from [<8000ed44>] (handle_IRQ+0x3c/0x90)
[<8000ed44>] (handle_IRQ) from [<80008578>] (gic_handle_irq+0x28/0x5c)
[<80008578>] (gic_handle_irq) from [<80012100>] (__irq_svc+0x40/0x70)
The reason is the sdma tasklet is async with audio substream release. ALSA
think when terminate dma, the dma should be stopped and no callback be called.
This patch is to add new api dma_sync_wait_tasklet(), which is called in
snd_dmaengine_pcm_close(). It will make sure the callback not be called
after this funtion. Tasklet_kill is to wait scheduled tasklet end.
Tasklet_kill can't be added to terminate dma function, because terminate dma
function may be called in interrupt, but tasklet_kill can't be called in
interrupt context.
Signed-off-by: Shengjiu Wang <shengjiu.wang@freescale.com>
(cherry picked from commit 9815881b6acaa72a705e1fa3c26a852fc81bfce5)
As SSI has dual fifo, add src_dualfifo and dst_dualfifo in imx_dma_data
to support dual fifo in DMA_DEV_TO_DEV.
Signed-off-by: Shengjiu Wang <shengjiu.wang@freescale.com>
(cherry picked from commit cfde1308f170166a0099ca39ee8733895f9626f0)
Use SET_LATE_SYSTEM_SLEEP_PM_OPS rather than the common sleep pm ops to ensure
sdma has resumed back before all other module drivers which use sdma resume
back.
Signed-off-by: Robin Gong <b38343@freescale.com>
(cherry picked from commit a7f8725509b494c3073b1bcca63252d5c61bb80d)
Enable Mega/Fast support for i.mx7d. Need save and restore SDMA registers.
Signed-off-by: Robin Gong <b38343@freescale.com>
(cherry picked from commit 4e1ea64c5d360ebc4f8168c1fcdee314b547bd13)
The SDMA driver not consider the case of event_id0 is 0. That make uart6 rx
not working.
Signed-off-by: Robin Gong <b38343@freescale.com>
(cherry picked from commit dbcacbcb3a885d7569e9e415035b1dd06c4a117b)
(cherry picked from commit 6dfdbe41a7d6ab7e6fae5d6fb4d73435839beff3)
Current ecspi rom script didn't take care of rxfifo overflow risk. Add new
ecspi tx script to check the rxfifo status, if it is near to full(>=48 bytes),
do not copy data to txfifo which will trigger data push into rxfifo. Because
rx script may not read rxfifo in time, we have to consider it.
Signed-off-by: Robin Gong <b38343@freescale.com>
(cherry picked from commit 17f472aa698aba0af5da4566df447e23306f4289)
(cherry picked from commit 90c929d7d1a3f8e196641b5ed7a33d2ee03bd63c)
(cherry picked from commit 6d76bdcf2097e4198217edf27363cf6ba2e6542a)
cherry-pick below patch from v3.14.y:
ENGR00319473: dma: imx-sdma: support sdma restore from
mega/fast power down status
Support sdma suspend and resume interface to restore from mega/fast power down.
Signed-off-by: Robin Gong <b38343@freescale.com>
(cherry picked from commit 682fd1f47ab9cb69382fa0e8d20a830ae99c26fc)
(cherry picked from commit dd17fa18b9a0c11f8bce3b87f792775d96e461c1)
This patch is just created by so many confilict while cherry-pick
from v3.10 a6a6cf911f85a3a09f763195478d422c571b9565.
Signed-off-by: Robin Gong <b38343@freescale.com>
Leonard: Fixed minor conflicts while rebasing on 4.14
Removed sdma_prep_memcpy_sg because API removed from upstream
Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com>
cherry-pick below patch from v3.14.y:
ENGR00329948-3: dma: imx-sdma: Add hdmi audio support
in sdma
There's a missing script for hdmi audio support in current sdma driver,
thus add it.
This HDMI script doesn't use bd to copy memory like a normal one does
but only to update the memory address for HDMI internal AHB DMA and
then trigger its procedure automatically.
Signed-off-by: Shengjiu Wang <shengjiu.wang@freescale.com>
Signed-off-by: Robin Gong <b38343@freescale.com>
(cherry picked from commit dafddac916a03ae4477e2de7c1b7ad291f956f68)
