- HIST_A as collision, need set to 1 for wfb_store
- WFE-A flag0~3 changed to WFE-B flag4~7 on i.MX6ULL
This patch fixes the collision issue and some part of
updated region can not display with auto waveform mode.
Signed-off-by: Robby Cai <robby.cai@nxp.com>
When CPU/AXI/AHB are running at 24MHz, IPG at
12MHz, two consecutive reads of RTC timer registers
never get same value, so we need to skip the low
15 bits, only make sure the second value are same
during two consecutive reads.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
There are two states in i.MX6Q cpuidle driver.
state[1]: ARM WFI mode
state[2]: i.MX6Q WAIT mode
Take i.MX6DL as example, think out such a case:
1. CPU0/1 both run at normal mode
2. On CPU0, `sleep 1` is executed. And there are no workload on CPU1.
3. CPU0 first runs into state[2] and 'wfi' instruction. Switched to use
GPT broadcast.
4. CPU1 runs into state[2] and configure CCM to WAIT MODE,
then 'wfi' instruction. Now arm_clk and local timer clock are
shutdown. Switched to use GPT broadcast
5. GPT broadcast timer interrupt comes to GPC/GIC, then CPU0 wakes up.
CPU0 switched to use arm local timer. CPU1 is still sleeping.
6. No workload on CPU0, CPU0 runs into state[1]. But CCM register
is still not restored to Normal RUN mode. 'wfi' + CCM WAIT will
cause arm_clk and arm core clk.
Now CPU0 stops, which is not correct.
So, need to make sure CCM configured to RUN mode when any cpu exit
state[2].
In this patch,
When CPU exits state[2], it configures CCM to RUN mode.
When all CPUs enters state[2], the last CPU needs to check
whether it's ok to configure CCM to WAIT mode or not.
In imx6q_set_lpm, we only need to unmask GINT when not WAIT_CLOCKED,
so add a check condition.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Using pull-up or pull down will cause that codec can get
big data in right channel. using keeper to fix this issue.
Signed-off-by: Shengjiu Wang <shengjiu.wang@freescale.com>
Mipi CSI PHY regulator will enabled in function of s_power.
So remove regulator enable code when driver probe.
Signed-off-by: Sandor Yu <Sandor.yu@nxp.com>
(cherry picked from commit c29dda8f40)
Add HSIC support for imx7d. We have not supported HSIC as system
wakeup as well as HSIC remote wakeup function at DSM mode, since
the 24M OSC can't be off and the SoC internal regulators can't be
off at this mode, that will keep power consumption much higher.
Signed-off-by: Peter Chen <peter.chen@freescale.com>
The MQS can only work when the mclk1 is selected as the mclk
of sai. On other hand, the mclk0 use same clock root
(sai_clk_root) as mclk1. so removing mclk0 won't impact the sai
features.
Signed-off-by: Shengjiu Wang <shengjiu.wang@freescale.com>
When Mega/Fast Mix off in DSM mode, RDC recovery needs PCIe/PXP/EIM
clock to be enabled, otherwise, with M4 enabled, DSM resume will fail.
We only enable them before entering DSM and hardware will disable
them when DSM is entered and they will be re-enabled after resume,
then in low level resume phase, we will disable them again.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
(cherry picked from commit e28ae270b6)
For i.MX7D, current runtime clock management code will skip all
PLL/PFD/GATE enable/disable when M4 is enabled, this is NOT good
for power number in low power idle and audio playback, as M4 only
uses one high speed PFD which is from system PLL, it is never
disabled runtimely, so we can just enable the hardware operation of
PLL/PFD/GATE for A7.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
(cherry picked from commit 02a2e8d73b)
Since TSC has pin conflict with I2C1 which is used by PMIC and Camera,
we need to move TSC setting from LCDIF dts file into a separated one to
achieve the LCDIF and Camera feature in one DTS file. After the change,
we can get the supported features as follows.
-lcdif.dtb: lcd and camera, but no tsc
-tsc.dtb: lcd and tsc, but no camera
Signed-off-by: Robby Cai <robby.cai@nxp.com>
Add pinctrls for usbotg1 and usbotg2 vbus control. This missing keeps
the vbus enable pin is high after power up, so vbus is on and otg port
will not enter suspend in device mode, as active usb port has high
bus freq requested, this prevents system enter low bus freq.
Signed-off-by: Li Jun <jun.li@nxp.com>
The same issue: "MLK-9773: warm reset fail in kernel when booting from QSPI
NOR Flash", thus enable WDOG_B on the reworked board to make sure power off
the QSPI-NOR Flash.
Signed-off-by: Robin Gong <yibin.gong@nxp.com>
on i.MX6ULL, the WFE_A is removed due to die size, but instead use WFE_B
to the task for WFE_A. We may call this version as V3P - V3 patch.
use device_id to differentiate the operations on different version.
Signed-off-by: Robby Cai <robby.cai@nxp.com>
On i.MX6ULL, the pin MUX and CTRL register of BOOT_MODEx and TAMPERx
pins have been move to the IOMUXC_SNVS. Add additional pinfunc define
and correct the pinctrl binding.
Signed-off-by: Bai Ping <ping.bai@nxp.com>
On i.MX6ULL, the BOOT_MODEx and TAMPERx pin MUX and CTRL register
have been moved from IOMUXC to IOMUXC_SNVS, so the pinctrl driver
should be modified to support the IOMUXC_SNVS.
Signed-off-by: Bai Ping <ping.bai@nxp.com>
Move usdhc1 wp/cd/reset/vselect pin setting and usdhc2 reset pin
setting out of hog. Due to many pin conflict with usdhc1 and usdhc2,
this patch can let other modules do not touch the iomuxc.
Signed-off-by: Haibo Chen <haibo.chen@nxp.com>
The maximum divider of asrc clock is 1024, but there is no judgement
for this limitaion in driver, which may cause the divider setting not
correct.
When IDEAL_RATIO_RATE 200kHZ, the cost time of conversion from 192kHz
to 96kHz is 24ms every 1024 sample, but these sample's playback time
is 1024/96=11ms, so there will be underrun. So need to enlarge this RATE.
Signed-off-by: Shengjiu Wang <shengjiu.wang@freescale.com>
Add codec-master property for imx-wm8962. If set this in device
tree, the codec will work as master, if don't set it, the cpu dai
will work as master.
Signed-off-by: Shengjiu Wang <shengjiu.wang@freescale.com>
SAI has 4 clock source, even the mclk0 is always same as
the mclk1, but it is need to add in device tree.
Signed-off-by: Shengjiu Wang <shengjiu.wang@freescale.com>
Add the dize size info in the ARM2 board dts file name to align with
i.MX6UL, so mfgtool and yocto script can handle the naming rule easily.
Signed-off-by: Bai Ping <ping.bai@nxp.com>
GPIO0~GPIO7 part:
- Commit(c8cabda5ab) add some wrong input sel value for uart, return
them to origin setting.
- Add uart DTE pin mode setting.
UART2_TX_DATA pin part:
- RM doc "iMX7D_RM_Rev0_Approval.pdf" (2016.04.25 updated in compass)
updated input sel define for UART2_RX_DATA, then set the correct input
sel for the pin.
Signed-off-by: Fugang Duan <fugang.duan@nxp.com>
(cherry picked from commit: 90a8b06b9735dd5b8d2023ff3b95886441e0e8d9)
This dts is only for USB HSIC controller test which needs
Validation Port Card on it.
Disable controller 3 due to strange signal on it at arm2 board.
Signed-off-by: Peter Chen <peter.chen@nxp.com>
On i.MX7D, per design team's require, need to make sure
DLL is locked after DDR frequency scaled done. Although
normally there should be no issue, but it is better to
add it.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
(cherry picked from commit 07c9f26b19)
On i.MX7D lpddr3, retention mode exit flow should restore
more registers to make sure the ddr controller and ddr phy
settings restored properly, otherwise, some of the boards
can NOT pass memtester after retention mode exited.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
i.MX7D TO1.2 removes the DDR PAD retention mode setting
in IOMUXC GPR, it is same as TO1.0, so only apply the
IOMUXC GPR setting for TO1.1.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
For imx6ull-ddr3-arm2 board, eMMC and SD1 slot share usdhc1, so
this patch add another dts file imx6ull-ddr3-arm2-emmc.dts to
support eMMC.
eMMC data4~data7 share the same I/O domain with sd2, so this patch
only enable eMMC 4bit mode.
Due to the eMMC on imx6ull-ddr3-arm2 board support HS200 mode, and
need the VCCQ to be 1.8v, this patch keep usdhc vselect, let usdhc
to change the I/O voltage to 1.8v automatically. Otherwise, another
rework needed: remove R95, add R94.
Signed-off-by: Haibo Chen <haibo.chen@nxp.com>
Add usdhc2 support, due to cd/wp pin conflict with usdhc1, this
patch drop these two pins, and make usdhc2 as no removeable.
Moreover, due to VSELECT pin is not connected by default, we also
add no-1-8-v property.
Signed-off-by: Haibo Chen <haibo.chen@nxp.com>
According to Hardware team's suggestion, for usdhc2, this patch change
the drive strength for clock pin and data pin, which can make the signal
meet the requirement for DDR50 mode.
Signed-off-by: Haibo Chen <haibo.chen@nxp.com>
When A7 platform is in low power mode while M4 is NOT,
M4 should be able to send message to wake up A7, so
MU must be always as wake up source.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
