Enable chipidea usb controller driver and mxs usb phy driver for imx8.
Acked-by: Peter Chen <peter.chen@nxp.com>
Signed-off-by: Li Jun <jun.li@nxp.com>
If the vbus is controlled by ehci port power bit, we need set power
polarity of vbus enable signal according to the vbus power supply
chip on board.
Acked-by: Peter Chen <peter.chen@nxp.com>
Signed-off-by: Li Jun <jun.li@nxp.com>
Set the OTG1 vbus power polarity to be active high on
fsl-imx8qm-lpddr4-arm2.dts.
Acked-by: Peter Chen <peter.chen@nxp.com>
Signed-off-by: Li Jun <jun.li@nxp.com>
USB host vbus control can be via port power(PP) bit of ehci, there
is a polarity setting in controller register for this signal, if
power supply chip use active high, add this property.
Acked-by: Peter Chen <peter.chen@nxp.com>
Signed-off-by: Li Jun <jun.li@nxp.com>
When starting a playback the initialization data used to reduce underruns
was send to the transmit data register after the DMA requests were enabled.
This patch moves the initialization phase before enabling the DMA so the
data is transmitted in correct order.
Signed-off-by: Mihai Serban <mihai.serban@nxp.com>
Auto Enable LOCALVERSION_AUTO
so show git commit hash value in boot log
Linux version 4.9.11-02242-gf4b0aff-dirty
Signed-off-by: Frank Li <Frank.Li@nxp.com>
For samples with more than 2 and odd number of channels the I2S mode
does not work correctly. In I2S mode we are required to activate an even
number of channels (possibly on multiple datalines) and thus configure
the BCLK for even channels. In this case samples with odd (smaller) number
of channels are played faster and the sound is distorted.
To fix this behavior we can enable TDM mode for the special cases of
samples with 3, 5 or 7 channels. But even TDM has some restrictions that
prevent us from having full support for the special cases:
1. TDM is not supported by codec in master mode so 3, 5 and 7 channels
usage is denied.
2. In codec slave mode TDM works only with 8 slots and slot width of 32
bits. For an often used MCLK frequency of 24MHz and the above restrictions
the maximum sample rate is limited to 48KHz = 24576000/(2*8*32).
The 2 denominator is required by ESAI BCLK divisors.
Signed-off-by: Mihai Serban <mihai.serban@nxp.com>
switch to use new format. Split mux out from pad config.
Change the high two bits in pad config to 0, because driver
will automatically set that two bits to 1.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
In upstream, IMX7D_ARM_A7_ROOT_SRC uses imx_clk_mux2 for initialization,
while our code uses imx_clk_mux_flags_bus with additional flags
CLK_SET_RATE_NO_REPARENT | CLK_OPS_PARENT_ENABLE. In the end, both calls
set the flags of IMX7D_ARM_A7_ROOT_SRC clock to
CLK_SET_RATE_NO_REPARENT | CLK_OPS_PARENT_ENABLE.
To align our code to upstream, we can safely use imx_clk_mux2.
Signed-off-by: Irina Tirdea <irina.tirdea@nxp.com>
Remove dependency of ARCH_MXC to support GPIO driver on
both ARMv7 and ARMv8 i.MX platforms.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Debug info should not be printed using pr_info on init. Use pr_debug
instead.
Also, verify the cable state before reading the EDID. There is no point
in trying to read EDID (and print an error message), when there is no
device connected to HDMI connector.
Signed-off-by: Robert Chiras <robert.chiras@nxp.com>
Debug info should not be printed using pr_info on init. Use pr_debug
instead.
Also, use the driver name, since there is more than one MIPI DSI driver.
Signed-off-by: Robert Chiras <robert.chiras@nxp.com>
Debug info should not be printed using pr_info on init. Use pr_debug
instead.
Also, use the driver name, since there is more than one MIPI DSI driver.
Signed-off-by: Robert Chiras <robert.chiras@nxp.com>
Debug info should not be printed using pr_info on init. Use pr_debug
instead.
Also, use the driver name, since there is more than one MIPI DSI driver.
Signed-off-by: Robert Chiras <robert.chiras@nxp.com>
When using fb_find_mode from fbdev/core with a specified user more,
it will return a screeninfo structure with the pixclock corresponding to
a different refresh rate than the requested one. For example, for
1920x1080@60 it will return pixclock=5780. When we get the videmode for
this screeninfo, it will have a refresh of 59Hz, instead of 60Hz.
If we use this mode as default mode when EDID cannot be read, on a
monitor with fixed refresh rate of 60Hz, it won't work. Therefore, we
should save the default mode, the nearest mode from CEA modes defined by
our own driver (which will have the correct refresh rate and pixclock for
the requested resolution).
Signed-off-by: Robert Chiras <robert.chiras@nxp.com>
commit 70f2d20917bc ("MLK-14884 mmc: sdhci: make DDR50 tuning optionally")
want to make DDR50 card tuning optionally, but the code logic is not
right, the tuning of DDR50 card will also be impacted by the flag
'SDHCI_SDR50_NEEDS_TUNING'. e.g. imx6sl/imx6sx/imx6ul/imx7d default set
USE_TUNING_SDR50, which means on these SoC, DDR50 card still do tuning
even haven't the flag 'SDHCI_DDR50_NEEDS_TUNING'.
This patch fix the logic issue, separate DDR50 and SDR50 card.
Signed-off-by: Haibo Chen <haibo.chen@nxp.com>
restore pin setting for i2c in suspend/resume
Signed-off-by: Gao Pan <gaopan@freescale.com>
(cherry picked from commit 8aed73af218f25e0677b8980b3706246dd68790d)
Signed-off-by: Robin Gong <yibin.gong@nxp.com>
Conflicts:
drivers/i2c/busses/i2c-imx.c
Change dtb's core settings as below on i.MX8QM:
boot up 4 CA53 and 2 CA72 (using CA53 specific flash.bin)
fsl-imx8qm-lpddr4-arm2.dts
boot up 4 CA53 (using CA53 specific flash.bin)
fsl-imx8qm-lpddr4-arm2_ca53.dts
boot up 2 CA72 (using CA72 specific flash.bin)
fsl-imx8qm-lpddr4-arm2_ca72.dts
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Add CA72 only dtb to support booting up kernel with
CA72 cluster only, need to use CA72 specific flash.bin
and CA72 specific dtb to boot up kernel.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
After commit 3e3274ab9f ("mmc: sdhci-esdhc-imx: Use common
sdhci_suspend|resume_host()"), we lost the pins state store and save
in common sdhci_pltfm_{suspend|resume} API which results in the
pins state lost in state un-retainable suspend/resume, then
CMD transfer will meet timeout subsequently.
Due to sdhci_pltfm_{suspend|resume} API becomes static after
that commit later, we then do manual pins state save and restore
in our platform suspend/resume API instead.
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
DDR50 tuning is optinally defined in sd 3.0 spec. Per IC guys
suggestion, it internally already uses a fixed optimized timing
and normally does not require tuning.
Make it optionally and platform can claim SDHCI_DDR50_NEEDS_TUNING
support if it wants tuning.
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
According to RM, Bit[11-8] is MUX_MODE which is configured by
the PIN_FUNC_ID automatically, specify it in config part is wrong
and violates the binding doc. So remove them all.
It can also avoid the future confusing when customer wants to
configure a pad by following the exist code.
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
'vin-supply' property used in ldo-bypass mode while 'vin-supply' deleted
in ldo-enable mode on v4.9 rather than dirctly switch 'supply' to internal
regulator and external pmic regulator on v4.1. Correct it for all *-ldo.dts,
otherwise, still work in ldo-bypass mode.
Signed-off-by: Robin Gong <yibin.gong@nxp.com>
I2C2 have to be disabled on hdcp board since those I2C2 bus pins
used for others, that said there is no all pmic regulators. In this
case, ldo-enable mode should be used and reg_arm/reg_soc/reg_pu should
be swithed to internal ldo instead. Otherwise, no reg_pu regulator
probed successfully by gpu driver, and cause gpu probe failed. Also,
cause cpufreq probe failed too.
Signed-off-by: Robin Gong <yibin.gong@nxp.com>
