The wait time is short that cause recording failed sometimes
Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com>
Reviewed-by: Sandor.yu <sandor.yu@nxp.com>
After enable the boost circuit of tx_ana_ctrl_reg_5, the noise
issue with ARC is gone.
Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com>
Reviewed-by: Sandor.yu <sandor.yu@nxp.com>
After changing the deemphasis to 0dB in TX_DIG_CTRL_REG_1
the issue that ARC can't work with 4k resolution is fixed
Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com>
Reviewed-by: Sandor.yu <sandor.yu@nxp.com>
specify the spdif in imx8mm for the ipg clock is higher that
it can support 192kHz
Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com>
Reviewed-by: Viorel Suman <viorel.suman@nxp.com>
This block implements the required digital interface to provide a
16-bit audio signal from a PDM microphone bitstream in a
configurable output sampling rate 11025kHz - 48000kHz.
Signed-off-by: Cosmin-Gabriel Samoila <cosmin.samoila@nxp.com>
Reviewed-by: Shengjiu Wang <shengjiu.wang@nxp.com>
Add an function to get the LCDIF controller supported bus
formats according to the pixel format bpp. And change the
bus format sanity check in the plane's atomic check to see
if the bus format required by the peripheral attached to
LCDIF can be supported by LCDIF.
Signed-off-by: Fancy Fang <chen.fang@nxp.com>
Confirmed from CDNS, this code is from bare metal, and not needed
for Linux. Below are their response:
This is alternative deferred interrupt.
This is intended to be used in Bare Metal to not block system in
interrupt.
This was not fully checked in Linux, so we do not recommend to use it
there.
Reviewed-by: Li Jun <jun.li@nxp.com>
Signed-off-by: Peter Chen <peter.chen@nxp.com>
If the user buffer is not 8-byte aligned, it needs to use debounce
buffer for DMA transfer, and in this commit, we do below two
improvements:
- Copy back the request buffer when the transfer has completed
- Using Macro for default debounce buffer size
Reviewed-by: Li Jun <jun.li@nxp.com>
Signed-off-by: Peter Chen <peter.chen@nxp.com>
There's probability there's no interrupt from CSI for the resolution
of 2592x1944 at 15 fps due to timing problem.
Need refine hs_settle value to fix this.
Signed-off-by: Robby Cai <robby.cai@nxp.com>
Reviewed-by: Guoniu.Zhou <guoniu.zhou@nxp.com>
In PTN5110 design, DisableSourceVBUS command also disables the sink
enable signal because the EN_SNK can be used to source higher voltage,
and, there is only one TCPC command to disable sourcing voltage without
telling whether to disable 5V or the high voltage, and to keep the
design simple they designed the PTN5110 to disable both. with this
fact, we use the flag drive_vbus to check if the source vbus enable was
issued, if yes we then do vbus source disable, in dead battery case,
we never did vbus source enable, so will not issue vbus source disable
command.
Acked-by: Peter Chen <peter.chen@nxp.com>
Signed-off-by: Li Jun <jun.li@nxp.com>
set scale divider for mipi in reg 0x3035 to 0x11 to achieve 15fps
Signed-off-by: Robby Cai <robby.cai@nxp.com>
Reviewed-by: Guoniu.Zhou <guoniu.zhou@nxp.com>
On i.MX8MM, IC design uses registers from CSI to do MIPI PHY reset. Need enable
disp_axi and disp_apb before the access, otherwise meet hang issue.
Signed-off-by: Robby Cai <robby.cai@nxp.com>
Reviewed-by: Guoniu.Zhou <guoniu.zhou@nxp.com>
Add nodes for clock disp_axi and disp_apb for access to avoid hang issue.
On i.MX8MM, use the register in CSI to do MIPI PHY reset, so add these
clocks for MIPI CSI driver as well.
Signed-off-by: Robby Cai <robby.cai@nxp.com>
Reviewed-by: Guoniu.Zhou <guoniu.zhou@nxp.com>
Mark micfil stat register as volatile since status
flags should not be read from cache.
Signed-off-by: Cosmin-Gabriel Samoila <cosmin.samoila@nxp.com>
Reviewed-by: Shengjiu Wang <shengjiu.wang@nxp.com>
MICFIL is using multi-fifo dma and maxburst must
be set proportional to number of channels.
Signed-off-by: Cosmin-Gabriel Samoila <cosmin.samoila@nxp.com>
Reviewed-by: Shengjiu Wang <shengjiu.wang@nxp.com>
Change the micfil clock rate to 196MHz. With lower
clock rate, performance is poor when recording more
than two channels.
Signed-off-by: Cosmin-Gabriel Samoila <cosmin.samoila@nxp.com>
Reviewed-by: Shengjiu Wang <shengjiu.wang@nxp.com>
Simplify the code to sync command sequncer in conditions:
1. tile work with dprc/prg (baddr)
2. switch tile to linear (!start)
revert 686c717fef
MLK-18398 gpu: imx: imx8_dprc: dpu-blit: Wait the dprc idle before
disable it
Signed-off-by: Xianzhong <xianzhong.li@nxp.com>
the previous programming does not flush command sequence,
that cause the obvious flicker when run glmark2 in full-screen,
also the wrong logic cause wayland hang in strict conditions.
need program event trigger to sync command sequencer properly.
also revert workaround: 4767f9aaad
MLK-18283-3 gpu: imx: dpu-blit: sync for cmd sequence finished
Signed-off-by: Xianzhong <xianzhong.li@nxp.com>
chrome browser hang is reproduced with mouse connected,
the first frame handler trigger the problem in below scenario:
tile (dprc-enable) --> linear (dprc->disable) --> tile (handle first frame wrongly).
need_handle_start is set following dprc_enable, need reset it with dprc_disable.
Signed-off-by: Xianzhong <xianzhong.li@nxp.com>
For now, the higher resolution than '1920x1080' is not supported
yet. So limit the 'max_width' and 'max_height' of mode_config
to be 1920 and 1080.
Signed-off-by: Fancy Fang <chen.fang@nxp.com>
The Samsung DSIM host driver mainly focuses on the config
related with soc platforms. And the controller itself config
has been moved to the sec-dsim bridge driver.
Signed-off-by: Fancy Fang <chen.fang@nxp.com>
This is the abstracted bridge driver for Samsung MIPI DSIM
controller. This driver only foucses on the DSIM controller
itself configurations and never care about any config about
the platforms. So it can be shared by different platforms
without any modifications.
Signed-off-by: Fancy Fang <chen.fang@nxp.com>
Allows the LCDIF to be one of the supported client
components. And set the 'legacyfb_depth' of LCDIF
to be 32.
Signed-off-by: Fancy Fang <chen.fang@nxp.com>
This is a new DRM/KMS driver for LCDIF which conforms
to the IMX DRM Core framework. It provides support for
CRTCs, Planes and mode config of KMS.
Signed-off-by: Fancy Fang <chen.fang@nxp.com>
The LCDIF core driver is responsible to provide controller
registers configuration and create the platform devices for
the child port nodes. And the platform devices later will
attach to the corresponding DRM/KMS drivers via name match.
Signed-off-by: Fancy Fang <chen.fang@nxp.com>
The 'video_pll1' PLL will be used as LCDIF pixel clock
source, and also used as MIPI DSI PHY reference clock
source. And 594MHz clock rate is better to derive the
27MHz PHY reference clock and the LCDIF pixel clocks
requied for most popular display modes.
Signed-off-by: Fancy Fang <chen.fang@nxp.com>
The display pipeline provided by IMX8MM soc is: LCDIF --> MIPI DSI.
This patch re-organize the LCDIF and MIPI DSI device nodes to be
suitable for DRM/KMS drivers. Besides, a new device node 'dispmix_gpr'
which is required by LCDIF and MIPI DSI is added.
Signed-off-by: Fancy Fang <chen.fang@nxp.com>
Fix the crash when pcie request the reserved memory region
after the -EPROBE_DEFER in the probe.
The pointer of the resource parameter would be invalided
in the second probe. Use one structure varible to replace
it.
Put node after done with it, after call of_parse_phandle.
Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
PCIe ep rc validation is one remote processors communications.
Remove the hard-coded ep rc ddr test region on imx8 platforms.
Get the reserved region for ep rc ddr test region.
Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
PCIe ep rc validation system is one remote processors
communications.
Add the reserved region in pcie node, and use this region as
ddr test region in pcie ep rc validation system.
Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
The perst signal shouldn't be asserted during imx6q/dl
pcie suspend.
Otherwise, the link would be down during resume,
and system would be hang.
Fix it by one return in imx6q switch case.
Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
Add dtsi and board configurations for DXP/DX 8QXP derivatives.
Separate out the arm2 board individual details for transparency
of board and device specifics.
Signed-off-by: Teo Hall <teo.hall@nxp.com>
Add dtsi and ARM2 board configurations for QP/DM 8QM derivatives.
Separate out ARM2 specific details from device details.
Signed-off-by: Teo Hall <teo.hall@nxp.com>
Since IP version 3.01 (845s) SAI has support for 1:1 bclk:mclk ratio.
Given this the specific DSD512 pinctrl option can be removed and SAI mclk
frequency decreased.
Signed-off-by: Viorel Suman <viorel.suman@nxp.com>
600000000 (-22)" and "clk: couldn't set vpu_enc_clk clk rate to
600000000 (-22), current rate: 0" when boot up. 100%
vpu clock is not settable, remove the assigned-clock-rates from the dts
Signed-off-by: Huang Chaofan <chaofan.huang@nxp.com>
