For now, the higher resolution than '1920x1080' is not supported
yet. So limit the 'max_width' and 'max_height' of mode_config
to be 1920 and 1080.
Signed-off-by: Fancy Fang <chen.fang@nxp.com>
The Samsung DSIM host driver mainly focuses on the config
related with soc platforms. And the controller itself config
has been moved to the sec-dsim bridge driver.
Signed-off-by: Fancy Fang <chen.fang@nxp.com>
This is the abstracted bridge driver for Samsung MIPI DSIM
controller. This driver only foucses on the DSIM controller
itself configurations and never care about any config about
the platforms. So it can be shared by different platforms
without any modifications.
Signed-off-by: Fancy Fang <chen.fang@nxp.com>
Allows the LCDIF to be one of the supported client
components. And set the 'legacyfb_depth' of LCDIF
to be 32.
Signed-off-by: Fancy Fang <chen.fang@nxp.com>
This is a new DRM/KMS driver for LCDIF which conforms
to the IMX DRM Core framework. It provides support for
CRTCs, Planes and mode config of KMS.
Signed-off-by: Fancy Fang <chen.fang@nxp.com>
The LCDIF core driver is responsible to provide controller
registers configuration and create the platform devices for
the child port nodes. And the platform devices later will
attach to the corresponding DRM/KMS drivers via name match.
Signed-off-by: Fancy Fang <chen.fang@nxp.com>
The 'video_pll1' PLL will be used as LCDIF pixel clock
source, and also used as MIPI DSI PHY reference clock
source. And 594MHz clock rate is better to derive the
27MHz PHY reference clock and the LCDIF pixel clocks
requied for most popular display modes.
Signed-off-by: Fancy Fang <chen.fang@nxp.com>
The display pipeline provided by IMX8MM soc is: LCDIF --> MIPI DSI.
This patch re-organize the LCDIF and MIPI DSI device nodes to be
suitable for DRM/KMS drivers. Besides, a new device node 'dispmix_gpr'
which is required by LCDIF and MIPI DSI is added.
Signed-off-by: Fancy Fang <chen.fang@nxp.com>
Fix the crash when pcie request the reserved memory region
after the -EPROBE_DEFER in the probe.
The pointer of the resource parameter would be invalided
in the second probe. Use one structure varible to replace
it.
Put node after done with it, after call of_parse_phandle.
Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
PCIe ep rc validation is one remote processors communications.
Remove the hard-coded ep rc ddr test region on imx8 platforms.
Get the reserved region for ep rc ddr test region.
Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
PCIe ep rc validation system is one remote processors
communications.
Add the reserved region in pcie node, and use this region as
ddr test region in pcie ep rc validation system.
Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
The perst signal shouldn't be asserted during imx6q/dl
pcie suspend.
Otherwise, the link would be down during resume,
and system would be hang.
Fix it by one return in imx6q switch case.
Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
Add dtsi and board configurations for DXP/DX 8QXP derivatives.
Separate out the arm2 board individual details for transparency
of board and device specifics.
Signed-off-by: Teo Hall <teo.hall@nxp.com>
Add dtsi and ARM2 board configurations for QP/DM 8QM derivatives.
Separate out ARM2 specific details from device details.
Signed-off-by: Teo Hall <teo.hall@nxp.com>
Since IP version 3.01 (845s) SAI has support for 1:1 bclk:mclk ratio.
Given this the specific DSD512 pinctrl option can be removed and SAI mclk
frequency decreased.
Signed-off-by: Viorel Suman <viorel.suman@nxp.com>
600000000 (-22)" and "clk: couldn't set vpu_enc_clk clk rate to
600000000 (-22), current rate: 0" when boot up. 100%
vpu clock is not settable, remove the assigned-clock-rates from the dts
Signed-off-by: Huang Chaofan <chaofan.huang@nxp.com>
- Sync with scu firmware commit 576011819ce3 (SCF-81: Added API to
control MIPI CSI calibration.) and commit 095a0d7dbc0b (SCF-85: Add
direct control of ENET IPG stop control)
- Add ipg stop misc controls for CONN ENET.
Reviewed-by: Richard Zhu <hongxing.zhu@nxp.com>
Signed-off-by: Fugang Duan <fugang.duan@nxp.com>
Support ASRC P2P with ESAI to show the multichannel capibility.
And make this setting align with other platform like imx6
Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com>
Reviewed-by: Viorel Suman <viorel.suman@nxp.com>
In imx6qdl-sabresd.dtsi imx_4.9.y defines ov564x_mipi@3c with
compatible="ovti,ov564x_mipi". Upstream added camera@3c with
compatible="ovti,ov5640" on the same bus and this results in i2c errors
on boot:
i2c i2c-1: Failed to register i2c client ov564x_mipi at 0x3c (-16)
i2c i2c-1: of_i2c: Failure registering /soc/aips-bus@02100000/i2c@021a4000/ov564x_mipi@3c
i2c i2c-1: Failed to create I2C device for /soc/aips-bus@02100000/i2c@021a4000/ov564x_mipi@3c
Fix by removing upstream definition.
The other camera camera added by upstream, &ov5642: camera@3c on &i2c0
was already removed/overwritten with our definition during porting.
Fixes: 2b48156760e5 ("MLK-11508-5: dts: Add imx v4l2 capture driver")
Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com>
Reviewed-by: Laurentiu Palcu <laurentiu.palcu@nxp.com>
Suspend fails on sabreauto because the i2c mux is set to the default
state before suspending sensors:
dpm_run_callback(): isl29023_suspend+0x0/0x3c returns -11
PM: Device 2-0044 failed to suspend: error -11
PM: Some devices failed to suspend, or early wake event detected
Fix this by moving sensons to i2cmux/i2c@1 just like the rest of I2C3
devices. This is a porting issue, in imx_4.9.y there is no dynamic
muxing for i2c3.
Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com>
Acked-by: Fugang Duan <fugang.duan@nxp.com>
Upstream added new separate pinctrl groups:
* pinctrl_i2c3mux for MX6QDL_PAD_EIM_A24__GPIO5_IO04
* pinctrl_max7310 for MX6QDL_PAD_SD2_DAT0__GPIO1_IO15
During imx_4.9.y porting these were both added to pinctrl_hog instead
and this now causes a pin conflict. Drop this part and keep them in
per-device pin groups.
Fixes: 2b48156760e5 ("MLK-11508-5: dts: Add imx v4l2 capture driver")
Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com>
Acked-by: Fugang Duan <fugang.duan@nxp.com>
Upstream added i2c-mux-gpio to imx6qdl-sabreauto and CONFIG_I2C_MUX_GPIO
to imx_v6_v7_defconfig. We need to copy this to imx_v7_defconfig or
several devices won't probe.
Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com>
Acked-by: Fugang Duan <fugang.duan@nxp.com>
Enable CWT for ATR, and switch to RX_DATA_IM to detect receiving data
in fifo.
Signed-off-by: Gao Pan <pandy.gao@nxp.com>
Acked-by: Fugang Duan <fugang.duan@nxp.com>
Camera sensor need to be enabled before ISI when
resolution of caputure image is less than 640*480,
but hdmi need to be enabled after ISI, so add this
patch to compatible these two cases
Signed-off-by: Guoniu.Zhou <guoniu.zhou@nxp.com>
(cherry picked from commit c8d17ffcb0)
Add NV12 output format support. Because nv12 is multi
planes format, so driver need add device for every planes
Reviewed-by: Sandor.yu <sandor.yu@nxp.com>
Signed-off-by: Guoniu.Zhou <guoniu.zhou@nxp.com>
Before the kernel starts, optee uses M4 SRAM to allocate its
suspend function. When imx7ulp_pm_map_io() executes, the psci
driver and psci_ops.cpu_suspend are not initialized yet. This
causes the memset to always wipe the optee suspend code in the
M4 SRAM.
Signed-off-by: Clement Faure <clement.faure@nxp.com>
gpu tiling is not enabled in vg3d, need bypass dprc/prg process,
dprc stuck since no pipeline sync when switch linear to tile.
add force sync for command sequence pipeline when switch to tile,
remove the frequent dprc config for the contigous linear blit.
Signed-off-by: Xianzhong <xianzhong.li@nxp.com>
The dpu driver may properly handle display clock parent selection now.
Thus, let's remove the assigned-clock and assigned-clock-parent
device tree properties from the dpu device tree node.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
The dpu driver may properly handle display clock parent selection now.
Thus, let's remove the assigned-clocks and assigned-clock-parents
device tree properties from the dpu device tree nodes.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
The framegen driver should get PLL clock, bypass clock and display
selection/mux clock via device tree if available. It may use bypass
clock when a TMDS encoder is connected with the framegen, otherwise,
PLL clock is used. This way, the assigned-clocks and assigned-clock-parents
device tree properties can be removed from the dpu device tree node.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
