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MA-7455-1 Pico: modify Pico configuration for Brillo.

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Modify the picosom to be suit for Brillo configurations.

Signed-off-by: Haoran Wang <Haoran.Wang@freescale.com>
(cherry picked from commit 864fd4f019)
To align with 2016.03, fix several places.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
This commit is contained in:
Peng Fan
2016-03-08 18:04:47 +08:00
committed by Ye Li
parent 59c76a7c82
commit 7f43a79956
6 changed files with 47 additions and 157 deletions
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1
arch/arm/cpu/armv7/mx6/Kconfig
View File

@ -218,6 +218,7 @@ source "board/kosagi/novena/Kconfig"
source "board/seco/Kconfig"
source "board/solidrun/mx6cuboxi/Kconfig"
source "board/tbs/tbs2910/Kconfig"
source "board/technexion/picosom-imx6ul/Kconfig"
source "board/tqc/tqma6/Kconfig"
source "board/udoo/Kconfig"
source "board/wandboard/Kconfig"

3
board/technexion/picosom-imx6ul/Kconfig
View File

@ -6,9 +6,6 @@ config SYS_BOARD
config SYS_VENDOR
default "technexion"
config SYS_SOC
default "mx6"
config SYS_CONFIG_NAME
default "picosom-imx6ul"

89
board/technexion/picosom-imx6ul/picosom-imx6ul.c
View File

@ -31,7 +31,7 @@
#ifdef CONFIG_POWER
#include <power/pmic.h>
#include <power/pfuze300_pmic.h>
#include <power/pfuze3000_pmic.h>
#include "../../freescale/common/pfuze.h"
#endif
@ -379,16 +379,9 @@ static iomux_v3_cfg_t const lcd_pads[] = {
MX6_PAD_GPIO1_IO08__GPIO1_IO08 | MUX_PAD_CTRL(NO_PAD_CTRL),
};
struct lcd_panel_info_t {
unsigned int lcdif_base_addr;
int depth;
void (*enable)(struct lcd_panel_info_t const *dev);
struct fb_videomode mode;
};
void do_enable_parallel_lcd(struct lcd_panel_info_t const *dev)
void do_enable_parallel_lcd(struct display_info_t const *dev)
{
enable_lcdif_clock(dev->lcdif_base_addr);
enable_lcdif_clock(dev->bus);
imx_iomux_v3_setup_multiple_pads(lcd_pads, ARRAY_SIZE(lcd_pads));
@ -401,9 +394,10 @@ void do_enable_parallel_lcd(struct lcd_panel_info_t const *dev)
gpio_direction_output(IMX_GPIO_NR(1, 8) , 1);
}
static struct lcd_panel_info_t const displays[] = {{
.lcdif_base_addr = LCDIF1_BASE_ADDR,
.depth = 24,
static struct display_info_t const displays[] = {{
.lcdif_base_addr = MX6UL_LCDIF1_BASE_ADDR,
.addr = 0,
.pixfmt = 24,
.enable = do_enable_parallel_lcd,
.mode = {
.name = "TFT43AB",
@ -419,42 +413,7 @@ static struct lcd_panel_info_t const displays[] = {{
.sync = 0,
.vmode = FB_VMODE_NONINTERLACED
} } };
int board_video_skip(void)
{
int i;
int ret;
char const *panel = getenv("panel");
if (!panel) {
panel = displays[0].mode.name;
printf("No panel detected: default to %s\n", panel);
i = 0;
} else {
for (i = 0; i < ARRAY_SIZE(displays); i++) {
if (!strcmp(panel, displays[i].mode.name))
break;
}
}
if (i < ARRAY_SIZE(displays)) {
ret = mxs_lcd_panel_setup(displays[i].mode, displays[i].depth,
displays[i].lcdif_base_addr);
if (!ret) {
if (displays[i].enable)
displays[i].enable(displays+i);
printf("Display: %s (%ux%u)\n",
displays[i].mode.name,
displays[i].mode.xres,
displays[i].mode.yres);
} else
printf("LCD %s cannot be configured: %d\n",
displays[i].mode.name, ret);
} else {
printf("unsupported panel %s\n", panel);
return -EINVAL;
}
return 0;
}
size_t display_count = ARRAY_SIZE(displays);
#endif
#ifdef CONFIG_FEC_MXC
@ -568,35 +527,35 @@ int power_init_board(void)
int ret;
unsigned int reg, rev_id;
ret = power_pfuze300_init(I2C_PMIC);
ret = power_pfuze3000_init(I2C_PMIC);
if (ret)
return ret;
pfuze = pmic_get("PFUZE300");
pfuze = pmic_get("PFUZE3000");
ret = pmic_probe(pfuze);
if (ret)
return ret;
pmic_reg_read(pfuze, PFUZE300_DEVICEID, &reg);
pmic_reg_read(pfuze, PFUZE300_REVID, &rev_id);
printf("PMIC: PFUZE300 DEV_ID=0x%x REV_ID=0x%x\n", reg, rev_id);
pmic_reg_read(pfuze, PFUZE3000_DEVICEID, &reg);
pmic_reg_read(pfuze, PFUZE3000_REVID, &rev_id);
printf("PMIC: PFUZE3000 DEV_ID=0x%x REV_ID=0x%x\n", reg, rev_id);
/* disable Low Power Mode during standby mode */
pmic_reg_read(pfuze, PFUZE300_LDOGCTL, &reg);
pmic_reg_read(pfuze, PFUZE3000_LDOGCTL, &reg);
reg |= 0x1;
pmic_reg_write(pfuze, PFUZE300_LDOGCTL, reg);
pmic_reg_write(pfuze, PFUZE3000_LDOGCTL, reg);
/* SW1B step ramp up time from 2us to 4us/25mV */
reg = 0x40;
pmic_reg_write(pfuze, PFUZE300_SW1BCONF, reg);
pmic_reg_write(pfuze, PFUZE3000_SW1BCONF, reg);
/* SW1B mode to APS/PFM */
reg = 0xc;
pmic_reg_write(pfuze, PFUZE300_SW1BMODE, reg);
pmic_reg_write(pfuze, PFUZE3000_SW1BMODE, reg);
/* SW1B standby voltage set to 0.975V */
reg = 0xb;
pmic_reg_write(pfuze, PFUZE300_SW1BSTBY, reg);
pmic_reg_write(pfuze, PFUZE3000_SW1BSTBY, reg);
return 0;
}
@ -618,18 +577,18 @@ void ldo_mode_set(int ldo_bypass)
if (ldo_bypass) {
prep_anatop_bypass();
/* decrease VDDARM to 1.275V */
pmic_reg_read(pfuze, PFUZE300_SW1BVOLT, &value);
pmic_reg_read(pfuze, PFUZE3000_SW1BVOLT, &value);
value &= ~0x1f;
value |= PFUZE300_SW1AB_SETP(1275);
pmic_reg_write(pfuze, PFUZE300_SW1BVOLT, value);
value |= PFUZE3000_SW1AB_SETP(1275);
pmic_reg_write(pfuze, PFUZE3000_SW1BVOLT, value);
set_anatop_bypass(1);
vddarm = PFUZE300_SW1AB_SETP(1175);
vddarm = PFUZE3000_SW1AB_SETP(1175);
pmic_reg_read(pfuze, PFUZE300_SW1BVOLT, &value);
pmic_reg_read(pfuze, PFUZE3000_SW1BVOLT, &value);
value &= ~0x1f;
value |= vddarm;
pmic_reg_write(pfuze, PFUZE300_SW1BVOLT, value);
pmic_reg_write(pfuze, PFUZE3000_SW1BVOLT, value);
finish_anatop_bypass();

4
configs/picosom-imx6ul-qspi_defconfig
View File

@ -1,3 +1,7 @@
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/technexion/picosom-imx6ul/imximage.cfg,SYS_BOOT_QSPI"
CONFIG_ARM=y
CONFIG_ARCH_MX6=y
CONFIG_TARGET_PICOSOM_IMX6UL=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_PING=y

6
configs/picosom-imx6ul_defconfig
View File

@ -1,3 +1,7 @@
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/technexion/picosom-imx6ul/imximage.cfg"
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/technexion/picosom-imx6ul/imximage.cfg,ANDROID_SUPPORT,BRILLO_SUPPORT"
CONFIG_ARM=y
CONFIG_ARCH_MX6=y
CONFIG_TARGET_PICOSOM_IMX6UL=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_PING=y

101
include/configs/picosom-imx6ul.h
View File

@ -14,12 +14,6 @@
#include "mx6_common.h"
#include <asm/imx-common/gpio.h>
#define CONFIG_MX6
#define CONFIG_ROM_UNIFIED_SECTIONS
#define CONFIG_SYS_GENERIC_BOARD
#define CONFIG_DISPLAY_CPUINFO
#define CONFIG_DISPLAY_BOARDINFO
/* uncomment for SECURE mode support */
/* #define CONFIG_SECURE_BOOT */
@ -29,59 +23,21 @@
#endif
#endif
#define CONFIG_CMDLINE_TAG
#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_INITRD_TAG
#define CONFIG_REVISION_TAG
/* Size of malloc() pool */
#define CONFIG_SYS_MALLOC_LEN (16 * SZ_1M)
#define CONFIG_BOARD_EARLY_INIT_F
#define CONFIG_BOARD_LATE_INIT
#define CONFIG_MXC_GPIO
#define CONFIG_MXC_UART
#define CONFIG_MXC_UART_BASE UART6_BASE_ADDR
/* allow to overwrite serial and ethaddr */
#define CONFIG_ENV_OVERWRITE
#define CONFIG_CONS_INDEX 1
#define CONFIG_BAUDRATE 115200
#define CONFIG_CMD_FUSE
#ifdef CONFIG_CMD_FUSE
#define CONFIG_MXC_OCOTP
#endif
#define CONFIG_MXC_UART_BASE MX6UL_UART6_BASE_ADDR
/* MMC Configs */
#define CONFIG_FSL_USDHC
#ifdef CONFIG_FSL_USDHC
#define CONFIG_FSL_ESDHC
#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC2_BASE_ADDR
#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC1_BASE_ADDR
#define CONFIG_SYS_FSL_USDHC_NUM 1
#define CONFIG_MMC
#define CONFIG_CMD_MMC
#define CONFIG_GENERIC_MMC
#define CONFIG_CMD_FAT
#define CONFIG_DOS_PARTITION
#define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */
#endif
#undef CONFIG_BOOTM_NETBSD
#undef CONFIG_BOOTM_PLAN9
#undef CONFIG_BOOTM_RTEMS
#undef CONFIG_CMD_EXPORTENV
#undef CONFIG_CMD_IMPORTENV
#define CONFIG_CMD_NET
#ifdef CONFIG_CMD_NET
#define CONFIG_CMD_PING
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_MII
#define CONFIG_FEC_MXC
#define CONFIG_MII
#define CONFIG_FEC_ENET_DEV 1
@ -99,18 +55,15 @@
#define CONFIG_PHYLIB
#define CONFIG_PHY_MICREL
#define CONFIG_FEC_DMA_MINALIGN 64
#endif
/* allow to overwrite serial and ethaddr */
#define CONFIG_ENV_OVERWRITE
#define CONFIG_CONS_INDEX 1
/* I2C configs */
#define CONFIG_CMD_I2C
#ifdef CONFIG_CMD_I2C
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_MXC
#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
#define CONFIG_SYS_I2C_SPEED 100000
#endif
@ -122,22 +75,12 @@
/* PMIC */
#define CONFIG_POWER
#define CONFIG_POWER_I2C
#define CONFIG_POWER_PFUZE300
#define CONFIG_POWER_PFUZE300_I2C_ADDR 0x08
#define CONFIG_POWER_PFUZE3000
#define CONFIG_POWER_PFUZE3000_I2C_ADDR 0x08
/* #define CONFIG_VIDEO */
/* Command definition */
#include <config_cmd_default.h>
#undef CONFIG_CMD_IMLS
#define CONFIG_BOOTDELAY 3
#define CONFIG_LOADADDR 0x80800000
#define CONFIG_SYS_TEXT_BASE 0x87800000
#define CONFIG_SYS_MMC_IMG_LOAD_PART 1
#ifdef CONFIG_SYS_BOOT_NAND
#define CONFIG_MFG_NAND_PARTITION "mtdparts=gpmi-nand:64m(boot),16m(kernel),16m(dtb),-(rootfs) "
@ -236,18 +179,6 @@
"else run netboot; fi"
#endif
/* Miscellaneous configurable options */
#define CONFIG_SYS_LONGHELP
#define CONFIG_SYS_HUSH_PARSER
#define CONFIG_SYS_PROMPT "=> "
#define CONFIG_AUTO_COMPLETE
#define CONFIG_SYS_CBSIZE 1024
/* Print Buffer Size */
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
#define CONFIG_SYS_MAXARGS 256
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
#define CONFIG_CMD_MEMTEST
#define CONFIG_SYS_MEMTEST_START 0x80000000
#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + (PHYS_SDRAM_SIZE >> 1))
@ -255,7 +186,6 @@
#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
#define CONFIG_SYS_HZ 1000
#define CONFIG_CMDLINE_EDITING
#define CONFIG_STACKSIZE SZ_128K
/* Physical Memory Map */
@ -271,9 +201,6 @@
#define CONFIG_SYS_INIT_SP_ADDR \
(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
/* FLASH and environment organization */
#define CONFIG_SYS_NO_FLASH
#define CONFIG_ENV_SIZE SZ_8K
#ifdef CONFIG_SYS_BOOT_QSPI
@ -305,8 +232,8 @@
#endif
#ifdef CONFIG_FSL_QSPI
#define CONFIG_QSPI_BASE QSPI1_BASE_ADDR
#define CONFIG_QSPI_MEMMAP_BASE QSPI1_ARB_BASE_ADDR
#define CONFIG_QSPI_BASE QSPI0_BASE_ADDR
#define CONFIG_QSPI_MEMMAP_BASE QSPI0_AMBA_BASE
#define CONFIG_CMD_SF
#define CONFIG_SPI_FLASH
@ -338,15 +265,8 @@
#define CONFIG_SYS_MMC_ENV_PART 0 /* user area */
#define CONFIG_MMCROOT "/dev/mmcblk1p2" /* USDHC2 */
#define CONFIG_OF_LIBFDT
#define CONFIG_CMD_BOOTZ
#define CONFIG_CMD_BMODE
#ifndef CONFIG_SYS_DCACHE_OFF
#define CONFIG_CMD_CACHE
#endif
#ifdef CONFIG_VIDEO
#define CONFIG_CFB_CONSOLE
#define CONFIG_VIDEO_MXS
@ -360,6 +280,7 @@
#define CONFIG_BMP_16BPP
#define CONFIG_VIDEO_BMP_RLE8
#define CONFIG_VIDEO_BMP_LOGO
#define CONFIG_IMX_VIDEO_SKIP
#endif
/* USB Configs */
@ -380,4 +301,8 @@
#include "mx6ul_14x14_evk_android.h"
#endif
#if defined(CONFIG_BRILLO_SUPPORT)
#include "mx6ul_14x14_evk_brillo.h"
#endif
#endif