MLK-13132: mx6qarm2: mt128x64mx32: adjust ahb/axi podf dividers
Adjust ahb/axi clock root podf dividers to be divided by 1 to allow ahb/axi clock root to be 24Mhz when sourced from osc_clk. Signed-off-by: Adrian Alonso <adrian.alonso@nxp.com> (Cherry picked from commit 9e80234c823d6a2a0d9e10ab4c4c605bf646bd22)
This commit is contained in:
@ -44,7 +44,7 @@ CSF CONFIG_CSF_SIZE
|
||||
#ifdef CONFIG_MX6DQ_POP_LPDDR2
|
||||
/* set ddr to 400Mhz */
|
||||
DATA 4 0x020C4018 0x21324
|
||||
DATA 4 0x020C4014 0x2018900
|
||||
DATA 4 0x020C4014 0x2018100
|
||||
CHECK_BITS_CLR 4 0x020C4048 0x3F
|
||||
DATA 4 0x020C4018 0x61324
|
||||
DATA 4 0x020C4014 0x18900
|
||||
|
||||
Reference in New Issue
Block a user