When dfu_fill_entity fail, need to free dfu to avoid memory leak.
Reported by Coverity:
"
Resource leak (RESOURCE_LEAK)
leaked_storage: Variable dfu going out of scope leaks the storage
it points to.
"
Signed-off-by: Peng Fan <van.freenix@gmail.com>
Cc: "Łukasz Majewski" <l.majewski@samsung.com>
Cc: Marek Vasut <marex@denx.de>
(cherry picked from commit 5d8fae79163e94671956c99654abf48cf49757ba)
Per to design team, on i.MX6UL, the LDO 1.2V bandgap voltage
is 30mV higher, so we need to adjust the REFTOP_VBGADJ(anatop MISC0
bit[6:4]) setting to 2b'110.
Signed-off-by: Bai Ping <ping.bai@nxp.com>
File:
IMX6ULL_DDR3L_400MHz_1GB_16bit_V2.2.inc
Changes:
Change MMDC_MDMISC.WALAT to 1
setmem /32 0x021B0018 = 0x00211740
Test:
Passed memtester on two mx6ull ddr3 arm2 boards
Signed-off-by: Ye Li <ye.li@nxp.com>
If the usb controller is not running, no need to shutdown it,
otherwise `usb stop` complains about:
"EHCI failed to shut down host controller".
To i.MX7D SDB, there are two usb ports, one Host, one OTG.
If we only plug one udisk to the Host port and then `usb start`,
the OTG controller for OTG port does not run actually. Then,
if `usb stop`, the OTG controller for OTG port will also be
shutdown, but it is not running.
This patch adds a check that only shutdown the running controller.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
For Some USB mass storage devices, such as:
"
- Kingston DataTraveler 2.0 001D7D06CF09B04199C7B3EA
- Class: (from Interface) Mass Storage
- PacketSize: 64 Configurations: 1
- Vendor: 0x0930 Product 0x6545 Version 1.16
"
When `usb read 0x80000000 0 0x2000`, we met
"EHCI timed out on TD - token=0x80008d80".
The devices does not support scsi VPD page, we are not able
to get the maximum transfer length for READ(10)/WRITE(10).
So we limit this to 256 blocks as READ(6).
Signed-off-by: Peng Fan <peng.fan@nxp.com>
LCD_PWR_EN controls the G pin of Q13 PMOS which needs low voltage to connect
D to S for outputting LCD 3.3V. If LCD_PWR_EN is high, we measured the LCD 3v3
is actually 1.2V.
Signed-off-by: Ye Li <ye.li@nxp.com>
(cherry picked from commit 28eb616b6c49de492cc0cdb3ad5b618bed77960f)
Bank 7 and Bank 8 only supports 4 words each. 'bank << 3 | word'
is not correct when program bank 8, since ocotp controller actully
use word index.
For example: fuse prog 8 3 1; The word index is (8 << 3 | 3) --> 67.
But actully it should be (7 << 3 | 7) ---> 63.
So fix it.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Due to TSC pin conflict with I2C1 bus, and PMIC is this I2C1 bus's
slave, this patch add new TSC config for i.mx6ull_14x14_ddr3_arm2
board, disable PMIC and ldo bypass check.
Signed-off-by: Haibo Chen <haibo.chen@nxp.com>
add new NAND config for i.MX6UL 14x14 EVK board, and disable USDHC2 when
NAND enabled due to pin conflict.
Signed-off-by: Han Xu <han.xu@nxp.com>
(cherry picked from commit 81e175bcc07792fab6010761daf6576bd600edda)
SNVS TAMPER pin and BOOT MODE pins are in SNVS IOMUXC module,
not in IOMUXC, so correct the related registers' offset.
Use IOMUX_CONFIG_LPSR flag for these pins, so we can differentiate
them from iomuxc pins.
Define CONFIG_IOMUX_LPSR for mx6ull_ddr3_arm2 board to enable
using these pins.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
In u-boot, i.MX6QP sabresd board uses 125Mhz ref clock from PHY,
While kernel uses the clock from internal PLL by setting GPR5 bit 9.
When doing warm reset in kernel, the GPR regigster is not reset, so
the clock source still is the PLL. This causes ENET in u-boot can't work.
In this patch, we change the u-boot to use internal PLL to align with
kernel for i.MX6QP. This also fixes the ENET issue after kernel warm reset.
Signed-off-by: Ye Li <ye.li@nxp.com>
To align with i.MX6UL, add the chip package size info to the i.MX6ULL ARM2 board
build target and loading dtb file name. So that mfgtool and yocto can follow i.MX6UL
naming rule to process i.MX6ULL.
Signed-off-by: Ye Li <ye.li@nxp.com>
Several UART input selects are missing. The fourth input select
for UART2_TX_DATA_ALT0 is actually also missing in the documentation.
(at least in Rev. B of the i.MX 7Dual Reference Manual). However,
when looking at the tables of other input selects, it is very natural
that there must be an input select for the UART2_TX_DATA_ALT0 pad.
The Colibri iMX7 also uses that pad for UART2 RX (in DTE mode), and
it was required to set that particular input select register to get a
working UART2.
From https://www.mail-archive.com/u-boot@lists.denx.de/msg211942.html
Signed-off-by: Peng Fan <peng.fan@nxp.com>
The MIB RAM and FIFO receive start register does not exist on
i.MX6ULL. Accessing these register will cause enet not work well or
cause system report fault.
Reported-by: Bai Ping <ping.bai@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
On i.MX7D lpddr3, retention mode exit flow should restore
more registers to make sure the ddr controller and ddr phy
settings restored properly, otherwise, some of the boards
can NOT pass memtester after retention mode exited.
For LPSR mode, ddr resume flow is same as retention mode,
just adjust it accordingly.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
i.MX7D TO1.2 removes the DDR PADs retention mode setting
in IOMUXC GPR, it is same as TO1.0, so only apply the
IOMUXC GPR setting for TO1.1.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
This patch is a porting of
http://git.freescale.com/git/cgit.cgi/imx/linux-2.6-imx.git/commit/?h=imx_4.1.15_1.0.0_ga&id=e4dacc44d22e9474ec456cb330df525cd805ea38
"
i.MX6QP and i.MX7D BCH module integrated a new feature to detect the
bitflip number for erased NAND page. So for these two platform, set the
erase threshold to gf/2 and if bitflip detected, GPMI driver will
correct the data to all 0xFF.
Also updated the imx6qp dts file to ditinguish the GPMI module for i.MX6Q
with the one for i.MX6QP.
"
In this patch, i.MX6UL is added and threshold changed to use ecc_strength.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
This patch is porting from linux:
http://git.freescale.com/git/cgit.cgi/imx/linux-2.6-imx.git/commit/?h=imx_4.1.15_1.0.0_ga&id=3d42fcece496224fde59f9343763fb2dfc5b0768
"
We may meet the bitflips in reading an erased page(contains all 0xFF),
this may causes the UBIFS corrupt, please see the log from Elie:
-----------------------------------------------------------------
[ 3.831323] UBI warning: ubi_io_read: error -74 (ECC error) while reading 16384 bytes from PEB 443:245760, read only 16384 bytes, retry
[ 3.845026] UBI warning: ubi_io_read: error -74 (ECC error) while reading 16384 bytes from PEB 443:245760, read only 16384 bytes, retry
[ 3.858710] UBI warning: ubi_io_read: error -74 (ECC error) while reading 16384 bytes from PEB 443:245760, read only 16384 bytes, retry
[ 3.872408] UBI error: ubi_io_read: error -74 (ECC error) while reading 16384 bytes from PEB 443:245760, read 16384 bytes
...
[ 4.011529] UBIFS error (pid 36): ubifs_recover_leb: corrupt empty space LEB 27:237568, corruption starts at 9815
[ 4.021897] UBIFS error (pid 36): ubifs_scanned_corruption: corruption at LEB 27:247383
[ 4.030000] UBIFS error (pid 36): ubifs_scanned_corruption: first 6569 bytes from LEB 27:247383
-----------------------------------------------------------------
This patch does a check for the uncorrectable failure in the following steps:
[0] set the threshold.
The threshold is set based on the truth:
"A single 0 bit will lead to gf_len(13 or 14) bits 0 after the BCH
do the ECC."
For the sake of safe, we will set the threshold with half the gf_len, and
do not make it bigger the ECC strength.
[1] count the bitflips of the current ECC chunk, assume it is N.
[2] if the (N <= threshold) is true, we continue to read out the page with
ECC disabled. and we count the bitflips again, assume it is N2.
(We read out the whole page, not just a chunk, this makes the check
more strictly, and make the code more simple.)
[3] if the (N2 <= threshold) is true again, we can regard this is a erased
page. This is because a real erased page is full of 0xFF(maybe also has
several bitflips), while a page contains the 0xFF data will definitely
has many bitflips in the ECC parity areas.
[4] if the [3] fails, we can regard this is a page filled with the '0xFF'
data.
"
Signed-off-by: Peng Fan <peng.fan@nxp.com>
The clock parent of the AHB root clock when using mux option 1
is the SYS PLL 270MHz clock. This is specified in Table 5-11
Clock Root Table of the i.MX 7Dual Applications Processor
Reference Manual.
While it could be a documentation error, the 270MHz parent is
also mentioned in the boot ROM configuration in Table 6-28: The
clock is by default at 135MHz due to a POST_PODF value of 1
(=> divider of 2).
Signed-off-by: Stefan Agner <stefan@agner.ch>
Current environment offset on NAND is 37MB, this will cause a alignment
issue when erasing if nand erase block is 2MB. The saveenv is failed.
=> saveenv
Saving Environment to NAND...
Erasing NAND...
Attempt to erase non block-aligned data
Since the max erase block we supported is 4MB, adjust the env offset to 60MB,
where is the last 4MB in 64MB reserved area for boot.
Signed-off-by: Ye Li <ye.li@nxp.com>
According PL310 TRM, Auxiliary Control Register
"
The register must be written to using a secure access, and it can be
read using either a secure or a NS access. If you write to this register
with a NS access, it results in a write response with a DECERR response,
and the register is not updated. Writing to this register with the L2
cache enabled, that is, bit[0] of L2 Control Register set to 1,
results in a SLVERR.
"
So If L2 cache is already enabled, chaning value of ACR will cause SLVERR,
uboot hangs.
In some cases, such as plugin, L2 Cache enabled bit is not cleared,
then "Set bit 22 in the auxiliary control register" cause uboot hangs.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Fix incorrect parametr in CMD_CHECK_BITS_CLR command
Pass CLR parameter to DCD header for CMD_CHECK_BITS_CLR
Signed-off-by: Adrian Alonso <adrian.alonso@nxp.com>
Signed-off-by: Ye Li <ye.li@nxp.com>
2016 u-boot added dummy CPU types for the i.MX6QP and i.MX6DP. When
doing runtime cpu type checking, we can't use CPU type of i.MX6Q and
i.MX6D for them more, which is ok in 2015 u-boot.
This patch adds the MXC_CPU_MX6QP and MXC_CPU_MX6DP at some places missed to
do the checking.
Signed-off-by: Ye Li <ye.li@nxp.com>
The build target mx6ul_14x14_evk_android_defconfig is obsoleted.
It is replaced by mx6ul_14x14_evk_brillo_defconfig. So remove this old file.
Signed-off-by: Ye Li <ye.li@nxp.com>
Since the CD pin of SD2 is DNP on the mx6ull arm2 board, this will cause
SD2 access problem even the card is inserted. Hard code the CD result to
1 to assume the card is always on.
The SD driver will return other errors if the card does not exist.
Signed-off-by: Ye Li <ye.li@nxp.com>
(cherry picked from commit 47efe2fda62297ab1da8594828cd7bd928ecbda7)
To align with other i.mx6 platforms, update config file to remove some
unnecessary settings. Also enable the GPIO command.
Signed-off-by: Ye Li <ye.li@nxp.com>
1. Bind the macro CONFIG_MX6ULL_DDR3_ARM2_EMMC_REWORK to eMMC 8 bits rework, which
conflicts with QSPIA and NAND, that we have to disable them at same time.
2. Bind the macro CONFIG_MX6ULL_DDR3_ARM2_QSPIB_REWORK to QSPI B port rework, which
conflicts with SD2 and NAND, that we have to disable them at same time.
3. Fix a typo issue of CONFIG_MX6ULL_DDR3_ARM2_EMMC_REWORK
4. Enable QSPI support for default SD boot case.
Signed-off-by: Ye Li <ye.li@nxp.com>
(cherry picked from commit 00f36b3e9445ff47ed68262ef2d656e410cd8fcd)
Fix build error for Plugin
"Can't stat board/freescale/mx6ul_14x14_ddr3_arm2/plugin.bin: Bad file descriptor"
Signed-off-by: Peng Fan <peng.fan@nxp.com>
(cherry picked from commit 95860f1213c038ef2e5900d1874ff5398ac0be2a)
provide one config "CONFIG_NAND_MXS_BCH_LEGACY_GEO" to keep using legacy
bch geometry.
NOTICE: the feature must be enabled/disabled in both u-boot and kernel.
Signed-off-by: Han Xu <han.xu@nxp.com>
(cherry picked from commit 0abc9c182c)
Support mx6ull ddr3 arm2 board.
DDR script version 1.1. Passed memtester on 3 boards.
Take mx6ul 14x14 ddr3 arm2 as reference.
Note:
LCD/NAND/ECSPI not tested, need hardware rework.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
(cherry picked from commit 584050b98c)
Update memory map address for mx6ull which uses AIPS3 and adjust UART8
to AIPS3 by replacing for ESAI.
Signed-off-by: Ye Li <ye.li@nxp.com>
(cherry picked from commit 5154e0c159)
The PFD reset is not needed for mx6ull, since it uses runtime cpu id
checking here, add codes to skip it.
Signed-off-by: Ye Li <ye.li@nxp.com>
(cherry picked from commit 4543971c60)
The MX6ULL has GPT with supporting OSC clock source, update the driver
accordingly.
Signed-off-by: Ye Li <ye.li@nxp.com>
(cherry picked from commit b2740fd7a0)
The MX6ULL has two 128 bits fuse banks, bank 7 and bank 8, while other
banks use 256 bits. So we have to adjust the word and bank index when accessing
the bank 8.
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
(cherry picked from commit bb71569f51)
