ENGR00177587 MX6Q_ARM2: add android config for this board.

add android config to this board.
only basic boot support.

Signed-off-by: Zhang Jiejing <jiejing.zhang@freescale.com>

.gitignore

@@ -13,6 +13,7 @@
 *~
 *.swp
 *.patch
+*.swp
 
 #
 # Top-level generic files

Makefile

@@ -1,4 +1,4 @@
-#
+
 # (C) Copyright 2000-2009
 # Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 #
@@ -223,6 +223,7 @@ LIBS += drivers/pci/libpci.a
 LIBS += drivers/pcmcia/libpcmcia.a
 LIBS += drivers/power/libpower.a
 LIBS += drivers/spi/libspi.a
+LIBS += drivers/fastboot/libfastboot.a
 ifeq ($(CPU),mpc83xx)
 LIBS += drivers/qe/qe.a
 endif
@@ -3204,6 +3205,16 @@ apollon_config		: unconfig
 	@$(MKCONFIG) $(@:_config=) arm arm1136 apollon NULL omap24xx
 	@echo "CONFIG_ONENAND_U_BOOT = y" >> $(obj)include/config.mk
 
+mx23_evk_config : unconfig
+	@$(MKCONFIG) $(@:_config=) arm arm926ejs mx23_evk freescale mx23
+
+mx25_3stack_mfg_config \
+mx25_3stack_config	:	unconfig
+	@$(MKCONFIG) $(@:_config=) arm arm926ejs mx25_3stack freescale mx25
+
+mx28_evk_config : unconfig
+	@$(MKCONFIG) $(@:_config=) arm arm926ejs mx28_evk freescale mx28
+
 imx31_litekit_config	: unconfig
 	@$(MKCONFIG) $(@:_config=) arm arm1136 imx31_litekit NULL mx31
 
@@ -3229,6 +3240,107 @@ mx31pdk_nand_config	: unconfig
 	fi
 	@$(MKCONFIG) -a mx31pdk arm arm1136 mx31pdk freescale mx31
 
+mx31_3stack_config	: unconfig
+	@$(MKCONFIG) $(@:_config=) arm arm1136 mx31_3stack freescale mx31
+
+mx35_3stack_config      \
+mx35_3stack_mfg_config \
+mx35_3stack_mmc_config: unconfig
+	@$(MKCONFIG) $(@:_config=) arm arm1136 mx35_3stack freescale mx35
+
+mx50_arm2_lpddr2_config \
+mx50_arm2_ddr2_config \
+mx50_arm2_iram_config \
+mx50_arm2_config  \
+mx50_arm2_mfg_config \
+mx50_rdp_iram_config \
+mx50_rd3_config \
+mx50_rd3_mfg_config \
+mx50_rdp_mfg_config \
+mx50_rdp_android_config \
+mx50_rd3_android_config \
+mx50_rdp_config      : unconfig
+	@[ -z "$(findstring iram_,$@)" ] || \
+		{ echo "TEXT_BASE = 0xF8008400" >$(obj)board/freescale/mx50_rdp/config.tmp ; \
+		  echo "... with iram configuration" ; \
+		}
+	@$(MKCONFIG) $(@:_config=) arm arm_cortexa8 mx50_rdp freescale mx50
+
+mx51_bbg_android_config	\
+mx51_bbg_mfg_config \
+mx51_bbg_iram_config \
+mx51_bbg_config		: unconfig
+	@[ -z "$(findstring iram_,$@)" ] || \
+		{ echo "TEXT_BASE = 0x1FFE5000" >$(obj)board/freescale/mx51_bbg/config.tmp ; \
+		  echo "... with iram configuration" ; \
+		}
+	@$(MKCONFIG) $(@:_config=) arm arm_cortexa8 mx51_bbg freescale mx51
+
+mx51_3stack_android_config	\
+mx51_3stack_config	: unconfig
+	@$(MKCONFIG) $(@:_config=) arm arm_cortexa8 mx51_3stack freescale mx51
+
+mx53_pcba_android_mfg_config	\
+mx53_pcba_android_config	:unconfig
+	$(MKCONFIG) $(@:_config=) arm arm_cortexa8 mx53_pcba freescale mx53
+
+mx53_smd_mfg_config             \
+mx53_smd_android_config		\
+mx53_smd_config		:unconfig
+	$(MKCONFIG) $(@:_config=) arm arm_cortexa8 mx53_smd freescale mx53
+
+mx53_loco_mfg_config		\
+mx53_loco_config	:unconfig
+	$(MKCONFIG) $(@:_config=) arm arm_cortexa8 mx53_loco freescale mx53
+
+mx53_ard_ddr3_mfg_config	\
+mx53_ard_ddr3_config		\
+mx53_ard_mfg_config		\
+mx53_ard_config		: unconfig
+	$(MKCONFIG) $(@:_config=) arm arm_cortexa8 mx53_ard freescale mx53
+
+mx53_arm2_ddr3_config		\
+mx53_arm2_ddr3_android_config	\
+mx53_evk_android_config		\
+mx53_evk_mfg_config             \
+mx53_evk_config      : unconfig
+	@$(MKCONFIG) $(@:_config=) arm arm_cortexa8 mx53_evk freescale mx53
+
+mx6dl_arm2_config		\
+mx6dl_arm2_iram_config		\
+mx6dl_arm2_mfg_config		\
+mx6dl_arm2_lpddr2_config	\
+mx6q_arm2_config		\
+mx6q_arm2_android_config        \
+mx6q_arm2_mfg_config		\
+mx6q_arm2_lpddr2_config		\
+mx6q_arm2_lpddr2pop_config	\
+mx6q_arm2_iram_config	: unconfig
+	@[ -z "$(findstring iram_,$@)" ] || \
+		{ echo "TEXT_BASE = 0x00907000" >$(obj)board/freescale/mx6q_arm2/config.tmp ; \
+		  echo "... with iram configuration" ; \
+		}
+	@$(MKCONFIG) $(@:_config=) arm arm_cortexa8 mx6q_arm2 freescale mx6
+
+mx6q_sabresd_config			\
+mx6q_sabresd_android_config             \
+mx6q_sabresd_mfg_config			\
+mx6q_sabresd_iram_config	: unconfig
+	@[ -z "$(findstring iram_,$@)" ] || \
+		{ echo "TEXT_BASE = 0x00907000" >$(obj)board/freescale/mx6q_sabresd/config.tmp ; \
+		  echo "... with iram configuration" ; \
+		}
+	@$(MKCONFIG) $(@:_config=) arm arm_cortexa8 mx6q_sabresd freescale mx6
+
+mx6q_sabrelite_config			\
+mx6q_sabrelite_android_config 		\
+mx6q_sabrelite_mfg_config   : unconfig
+	@$(MKCONFIG) $(@:_config=) arm arm_cortexa8 mx6q_sabrelite freescale mx6
+
+mx6q_sabreauto_mfg_config	\
+mx6q_sabreauto_config    : unconfig
+	@$(MKCONFIG) $(@:_config=) arm arm_cortexa8 mx6q_sabreauto freescale mx6
+
 omap2420h4_config	: unconfig
 	@$(MKCONFIG) $(@:_config=) arm arm1136 omap2420h4 NULL omap24xx
 

board/freescale/common/Makefile

@@ -36,11 +36,13 @@ COBJS-${CONFIG_FSL_PIXIS}	+= pixis.o
 COBJS-${CONFIG_PQ_MDS_PIB}	+= pq-mds-pib.o
 COBJS-${CONFIG_ID_EEPROM}	+= sys_eeprom.o
 COBJS-${CONFIG_FSL_SGMII_RISER}	+= sgmii_riser.o
+COBJS-${CONFIG_VIDEO_MX5}	+= fsl_bmp_600x400.o
 
 COBJS-${CONFIG_MPC8541CDS}	+= cds_pci_ft.o
 COBJS-${CONFIG_MPC8548CDS}	+= cds_pci_ft.o
 COBJS-${CONFIG_MPC8555CDS}	+= cds_pci_ft.o
 
+COBJS-${CONFIG_ANDROID_RECOVERY} += recovery.o
 
 SRCS	:= $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
 OBJS	:= $(addprefix $(obj),$(COBJS-y))

board/freescale/common/recovery.c

@@ -0,0 +1,109 @@
+/*
+ * Freescale Android Recovery mode checking routing
+ *
+ * Copyright (C) 2010-2012 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ *
+ */
+#include <common.h>
+#include <malloc.h>
+#include "recovery.h"
+#ifdef CONFIG_MXC_KPD
+#include <mxc_keyb.h>
+#endif
+
+extern int check_recovery_cmd_file(void);
+extern enum boot_device get_boot_device(void);
+
+#ifdef CONFIG_MXC_KPD
+
+#define PRESSED_HOME	0x01
+#define PRESSED_POWER	0x02
+#define RECOVERY_KEY_MASK (PRESSED_HOME | PRESSED_POWER)
+
+inline int test_key(int value, struct kpp_key_info *ki)
+{
+	return (ki->val == value) && (ki->evt == KDepress);
+}
+
+int check_key_pressing(void)
+{
+	struct kpp_key_info *key_info;
+	int state = 0, keys, i;
+
+	mxc_kpp_init();
+
+	puts("Detecting HOME+POWER key for recovery ...\n");
+
+	/* Check for home + power */
+	keys = mxc_kpp_getc(&key_info);
+	if (keys < 2)
+		return 0;
+
+	for (i = 0; i < keys; i++) {
+		if (test_key(CONFIG_POWER_KEY, &key_info[i]))
+			state |= PRESSED_HOME;
+		else if (test_key(CONFIG_HOME_KEY, &key_info[i]))
+			state |= PRESSED_POWER;
+	}
+
+	free(key_info);
+
+	if ((state & RECOVERY_KEY_MASK) == RECOVERY_KEY_MASK)
+		return 1;
+
+	return 0;
+}
+#else
+/* If not using mxc keypad, currently we will detect power key on board */
+int check_key_pressing(void)
+{
+	return 0;
+}
+#endif
+
+extern struct reco_envs supported_reco_envs[];
+
+void setup_recovery_env(void)
+{
+	char *env, *boot_args, *boot_cmd;
+	int bootdev = get_boot_device();
+
+	boot_cmd = supported_reco_envs[bootdev].cmd;
+
+	if (boot_cmd == NULL) {
+		printf("Unsupported bootup device for recovery\n");
+		return;
+	}
+
+	printf("setup env for recovery..\n");
+
+	env = getenv("bootcmd_android_recovery");
+	if (!env)
+		setenv("bootcmd_android_recovery", boot_cmd);
+	setenv("bootcmd", "run bootcmd_android_recovery");
+}
+
+/* export to lib_arm/board.c */
+void check_recovery_mode(void)
+{
+	if (check_key_pressing())
+		setup_recovery_env();
+	else if (check_recovery_cmd_file()) {
+		puts("Recovery command file founded!\n");
+		setup_recovery_env();
+	}
+}

board/freescale/common/recovery.h

@@ -0,0 +1,30 @@
+/*
+ * Android Recovery supported header file
+ *
+ * Copyright (C) 2010 Freescale Semiconductor.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ *
+ */
+
+#ifndef __RECOVERY_H_
+#define __RECOVERY_H_
+
+struct reco_envs {
+	char *cmd;
+	char *args;
+};
+
+#endif

board/freescale/mx23_evk/Makefile

@@ -0,0 +1,52 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).a
+
+COBJS	:= mx23_evk.o
+SOBJS	:= lowlevel_init.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
+

board/freescale/mx23_evk/config.mk

@@ -0,0 +1,6 @@
+#
+# image should be loaded at 0x41008000
+#
+LDSCRIPT := $(SRCTREE)/board/$(VENDOR)/$(BOARD)/u-boot.lds
+
+TEXT_BASE = 0x41008000

board/freescale/mx23_evk/lowlevel_init.S

@@ -0,0 +1,36 @@
+/*
+ * Board specific setup info
+ *
+ * (C) Copyright 2003, ARM Ltd.
+ * Philippe Robin, <philippe.robin@arm.com>
+ *
+ * Copyright (C) 2009-2011 Freescale Semiconductor, Inc.
+
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <version.h>
+
+/* Set up the platform, once the cpu has been initialized */
+.globl lowlevel_init
+lowlevel_init:
+
+	/* All SDRAM settings are done by sdram_prep */
+	mov pc, lr

board/freescale/mx23_evk/mx23_evk.c

@@ -0,0 +1,158 @@
+/*
+ *
+ * (c) 2008 Embedded Alley Solutions, Inc.
+ *
+ * Copyright (C) 2009-2011 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+
+#include <common.h>
+#include <asm/arch/mx23.h>
+#include <asm/arch/clkctrl.h>
+#include <asm/arch/pinmux.h>
+#include <asm/arch/spi.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define KHz	1000
+#define MHz	(1000 * KHz)
+
+static void set_pinmux(void)
+{
+
+#if defined(CONFIG_SPI_SSP1)
+
+	/* Configure SSP1 pins for ENC28j60: 8maA */
+	REG_CLR(PINCTRL_BASE + PINCTRL_MUXSEL(4), 0x00003fff);
+
+	REG_CLR(PINCTRL_BASE + PINCTRL_DRIVE(8), 0X03333333);
+	REG_SET(PINCTRL_BASE + PINCTRL_DRIVE(8), 0x01111111);
+
+	REG_CLR(PINCTRL_BASE + PINCTRL_PULL(2), 0x0000003f);
+#endif
+
+#if defined(CONFIG_SPI_SSP2)
+
+	/* Configure SSP2 pins for ENC28j60: 8maA */
+	REG_CLR(PINCTRL_BASE + PINCTRL_MUXSEL(0), 0x00000fc3);
+	REG_SET(PINCTRL_BASE + PINCTRL_MUXSEL(0), 0x00000a82);
+
+	REG_CLR(PINCTRL_BASE + PINCTRL_MUXSEL(1), 0x00030300);
+	REG_SET(PINCTRL_BASE + PINCTRL_MUXSEL(1), 0x00020200);
+
+	REG_CLR(PINCTRL_BASE + PINCTRL_DRIVE(0), 0X00333003);
+	REG_SET(PINCTRL_BASE + PINCTRL_DRIVE(0), 0x00111001);
+
+	REG_CLR(PINCTRL_BASE + PINCTRL_DRIVE(2), 0x00030000);
+	REG_SET(PINCTRL_BASE + PINCTRL_DRIVE(2), 0x00010000);
+
+	REG_CLR(PINCTRL_BASE + PINCTRL_DRIVE(3), 0x00000003);
+	REG_SET(PINCTRL_BASE + PINCTRL_DRIVE(3), 0x00000001);
+
+	REG_CLR(PINCTRL_BASE + PINCTRL_PULL(0), 0x00100039);
+#endif
+
+}
+
+#define IO_DIVIDER	18
+static void set_clocks(void)
+{
+	u32 ssp_source_clk, ssp_clk;
+	u32 ssp_div = 1;
+	u32 val = 0;
+
+	/*
+	 * Configure 480Mhz IO clock
+	 */
+
+	/* Ungate IO_CLK and set divider */
+	REG_CLR(CLKCTRL_BASE + CLKCTRL_FRAC, FRAC_CLKGATEIO);
+	REG_CLR(CLKCTRL_BASE + CLKCTRL_FRAC, 0x3f << FRAC_IOFRAC);
+	REG_SET(CLKCTRL_BASE + CLKCTRL_FRAC, IO_DIVIDER << FRAC_IOFRAC);
+
+	/*
+	 * Set SSP CLK to desired value
+	 */
+
+	/* Calculate SSP_CLK divider relatively to 480Mhz IO_CLK*/
+	ssp_source_clk = 480 * MHz;
+	ssp_clk = CONFIG_SSP_CLK;
+	ssp_div = (ssp_source_clk + ssp_clk - 1) / ssp_clk;
+
+	/* Enable SSP clock */
+	val = REG_RD(CLKCTRL_BASE + CLKCTRL_SSP);
+	val &= ~SSP_CLKGATE;
+	REG_WR(CLKCTRL_BASE + CLKCTRL_SSP, val);
+
+	/* Wait while clock is gated */
+	while (REG_RD(CLKCTRL_BASE + CLKCTRL_SSP) & SSP_CLKGATE)
+		;
+
+	/* Set SSP clock divider */
+	val &= ~(0x1ff << SSP_DIV);
+	val |= ssp_div << SSP_DIV;
+	REG_WR(CLKCTRL_BASE + CLKCTRL_SSP, val);
+
+	/* Wait until new divider value is set */
+	while (REG_RD(CLKCTRL_BASE + CLKCTRL_SSP) & SSP_BUSY)
+		;
+
+	/* Set SSP clock source to IO_CLK */
+	REG_SET(CLKCTRL_BASE + CLKCTRL_CLKSEQ, CLKSEQ_BYPASS_SSP);
+	REG_CLR(CLKCTRL_BASE + CLKCTRL_CLKSEQ, CLKSEQ_BYPASS_SSP);
+}
+
+int dram_init(void)
+{
+	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+
+	return 0;
+}
+
+int board_init(void)
+{
+	/* arch number of Freescale STMP 378x development board */
+	gd->bd->bi_arch_number = MACH_TYPE_MX23EVK;
+
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = LINUX_BOOT_PARAM_ADDR;
+
+	set_clocks();
+
+	set_pinmux();
+
+	/* Configure SPI on SSP1 or SSP2 */
+	spi_init();
+
+	return 0;
+}
+
+int misc_init_r(void)
+{
+	return 0;
+}
+
+int checkboard(void)
+{
+	printf("Board: MX23 EVK. \n");
+	return 0;
+}

board/freescale/mx23_evk/u-boot.lds

@@ -0,0 +1,51 @@
+/*
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+	. = 0x00000000;
+	. = ALIGN(4);
+	.text	:
+	{
+	  cpu/arm926ejs/start.o	(.text)
+	  *(.text)
+	}
+	.rodata : { *(.rodata) }
+	. = ALIGN(4);
+	.data : { *(.data) }
+	. = ALIGN(4);
+	.got : { *(.got) }
+
+	. = .;
+	__u_boot_cmd_start = .;
+	.u_boot_cmd : { *(.u_boot_cmd) }
+	__u_boot_cmd_end = .;
+
+	. = ALIGN(4);
+	__bss_start = .;
+	.bss (NOLOAD) : { *(.bss) }
+	_end = .;
+}

board/freescale/mx25_3stack/Makefile

@@ -0,0 +1,53 @@
+#
+# (c) Copyright 2009 Freescale Semiconductor
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).a
+
+COBJS	:= mx25_3stack.o
+SOBJS	:= lowlevel_init.o dcdheader.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################

board/freescale/mx25_3stack/config.mk

@@ -0,0 +1,3 @@
+LDSCRIPT := $(SRCTREE)/board/$(VENDOR)/$(BOARD)/u-boot.lds
+
+TEXT_BASE = 0x83F00000

board/freescale/mx25_3stack/dcdheader.S

@@ -0,0 +1,99 @@
+/*
+ *  Copyright (c) 2009  Freescale Semiconductor
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+
+#include <config.h>
+#include <version.h>
+
+.extern reset
+
+#define DCDGEN(i,type, addr, data) \
+dcd_##i:			;\
+    .long type			;\
+    .long addr			;\
+    .long data
+
+.globl _initheader
+_initheader:
+	b	reset
+	.org 0x400
+app_code_jump_v:	.long reset
+app_code_barker:	.long 0xB1
+app_code_csf:		.long 0
+hwcfg_ptr_ptr:		.long hwcfg_ptr
+super_root_key:		.long 0
+hwcfg_ptr:		.long dcd_data
+app_dest_ptr:		.long TEXT_BASE
+dcd_data:		.long 0xB17219E9
+
+#ifdef MXC_MEMORY_MDDR
+dcd_len:		.long 12*15
+#else
+dcd_len:		.long 12*24
+#endif
+
+/* WEIM config-CS5 init -- CPLD */
+DCDGEN( 1, 4, 0xB8002050, 0x0000D843) /* CS5_CSCRU */
+DCDGEN( 2, 4, 0xB8002054, 0x22252521) /* CS5_CSCRL */
+DCDGEN( 3, 4, 0xB8002058, 0x22220A00) /* CS5_CSCRA */
+#ifdef MXC_MEMORY_MDDR
+/* MDDR init */
+DCDGEN( 4, 4, 0xB8001010, 0x00000004) /* enable mDDR */
+DCDGEN( 5, 4, 0xB8001000, 0x92100000) /* precharge command */
+DCDGEN( 6, 1, 0x80000400, 0x12344321) /* precharge all dummy write */
+DCDGEN( 7, 4, 0xB8001000, 0xA2100000) /* auto-refresh command */
+DCDGEN( 8, 4, 0x80000000, 0x12344321) /* dummy write for refresh */
+DCDGEN( 9, 4, 0x80000000, 0x12344321) /* dummy write for refresh */
+DCDGEN(10, 4, 0xB8001000, 0xB2100000) /* Load Mode Reg command - cas=3 bl=8 */
+DCDGEN(11, 1, 0x80000033, 0xda)	/* dummy write -- address has the mode bits */
+DCDGEN(12, 1, 0x81000000, 0xff) /* dummy write -- address has the mode bits */
+DCDGEN(13, 4, 0xB8001000, 0x82216880)
+DCDGEN(14, 4, 0xB8001004, 0x00295729)
+#else
+/* DDR2 init */
+DCDGEN( 4, 4, 0xB8001004, 0x0076E83A)	/* initial value for ESDCFG0 */
+DCDGEN( 5, 4, 0xB8001010, 0x00000204)	/* ESD_MISC */
+DCDGEN( 6, 4, 0xB8001000, 0x92210000)	/* CS0 precharge command */
+DCDGEN( 7, 4, 0x80000f00, 0x12344321)	/* precharge all dummy write */
+DCDGEN( 8, 4, 0xB8001000, 0xB2210000)	/* Load Mode Register command */
+DCDGEN( 9, 1, 0x82000000, 0xda)		/* dummy write Load EMR2 */
+DCDGEN(10, 1, 0x83000000, 0xda)		/* dummy write Load EMR3 */
+DCDGEN(11, 1, 0x81000400, 0xda)		/* dummy write Load EMR1; enable DLL */
+DCDGEN(12, 1, 0x80000333, 0xda)		/* dummy write Load MR; reset DLL */
+
+DCDGEN(13, 4, 0xB8001000, 0x92210000)	/* CS0 precharge command */
+DCDGEN(14, 1, 0x80000400, 0x12345678)	/* precharge all dummy write */
+
+DCDGEN(15, 4, 0xB8001000, 0xA2210000)	/* select manual refresh mode */
+DCDGEN(16, 4, 0x80000000, 0x87654321)	/* manual refresh */
+DCDGEN(17, 4, 0x80000000, 0x87654321)	/* manual refresh twice */
+
+DCDGEN(18, 4, 0xB8001000, 0xB2210000)	/* Load Mode Register command */
+DCDGEN(19, 1, 0x80000233, 0xda)		/* Load MR; CL=3, BL=8, end DLL reset */
+DCDGEN(20, 1, 0x81000780, 0xda)		/* Load EMR1; OCD default */
+DCDGEN(21, 1, 0x81000400, 0xda)		/* Load EMR1; OCD exit */
+DCDGEN(22, 4, 0xB8001000, 0x82216080)	/* normal mode */
+DCDGEN(23, 4, 0x43FAC454, 0x00001000)	/* IOMUXC_SW_PAD_CTL_GRP_DDRTYPE(1-5) */
+#endif
+
+DCDGEN(99, 4, 0x53F80008, 0x20034000) /* CLKCTL ARM=400 AHB=133 */
+card_cfg:	.long UBOOT_IMAGE_SIZE

board/freescale/mx25_3stack/lowlevel_init.S

@@ -0,0 +1,97 @@
+/*
+ * Copyright (c) 2009  Freescale Semiconductor
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <asm/arch/mx25-regs.h>
+
+.macro REG reg, val
+	ldr r2, =\reg
+	ldr r3, =\val
+	str r3, [r2]
+.endm
+
+.macro REG8 reg, val
+	ldr r2, =\reg
+	ldr r3, =\val
+	strb r3, [r2]
+.endm
+
+.globl lowlevel_init
+lowlevel_init:
+
+	REG 0x53F80008, 0x20034000 // ARM clk = 399, AHB clk = 133
+
+	/* Init Debug Board CS5 */
+	REG 0xB8002050, 0x0000D843
+	REG 0xB8002054, 0x22252521
+	REG 0xB8002058, 0x22220A00
+
+	/* MAX (Multi-Layer AHB Crossbar Switch) setup */
+	/* MAX - priority for MX25 is (SDHC2/SDMA)>USBOTG>RTIC>IAHB>DAHB */
+	ldr r0, =MAX_BASE
+	ldr r1, =0x00002143
+	str r1, [r0, #0x000]        /* for S0 */
+	str r1, [r0, #0x100]        /* for S1 */
+	str r1, [r0, #0x200]        /* for S2 */
+	str r1, [r0, #0x300]        /* for S3 */
+	str r1, [r0, #0x400]        /* for S4 */
+	/* SGPCR - always park on last master */
+	ldr r1, =0x10
+	str r1, [r0, #0x010]        /* for S0 */
+	str r1, [r0, #0x110]        /* for S1 */
+	str r1, [r0, #0x210]        /* for S2 */
+	str r1, [r0, #0x310]        /* for S3 */
+	str r1, [r0, #0x410]        /* for S4 */
+	/* MGPCR - restore default values */
+	ldr r1, =0x0
+	str r1, [r0, #0x800]        /* for M0 */
+	str r1, [r0, #0x900]        /* for M1 */
+	str r1, [r0, #0xA00]        /* for M2 */
+	str r1, [r0, #0xB00]        /* for M3 */
+	str r1, [r0, #0xC00]        /* for M4 */
+
+	/* M3IF setup */
+	ldr r1, =M3IF_BASE
+	ldr r0, =0x00000001
+	str r0, [r1]  /* M3IF control reg */
+
+	/* default CLKO to 1/32 of the ARM core */
+	ldr r0, =CCM_MCR
+	ldr r1, =CCM_MCR
+	bic r1, r1, #0x00F00000
+	bic r1, r1, #0x7F000000
+	mov r2,     #0x5F000000
+	add r2, r2, #0x00200000
+	orr r1, r1, r2
+	str r1, [r0]
+
+	/* enable all the clocks */
+	ldr r2, =0x1FFFFFFF
+	ldr r0, =CCM_CGR0
+	str r2, [r0]
+	ldr r2, =0xFFFFFFFF
+	ldr r0, =CCM_CGR1
+	str r2, [r0]
+	ldr r2, =0x000FDFFF
+	ldr r0, =CCM_CGR2
+	str r2, [r0]
+	mov	pc, lr
+

board/freescale/mx25_3stack/mx25_3stack.c

@@ -0,0 +1,489 @@
+/*
+ * (c) Copyright 2009-2010 Freescale Semiconductor
+ *
+ * (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/errno.h>
+#include <asm/arch/mx25.h>
+#include <asm/arch/mx25-regs.h>
+#include <asm/arch/mx25_pins.h>
+#include <asm/arch/iomux.h>
+#include <asm/arch/gpio.h>
+#include <imx_spi.h>
+
+#ifdef CONFIG_LCD
+#include <mx2fb.h>
+#include <lcd.h>
+#endif
+
+#ifdef CONFIG_GET_FEC_MAC_ADDR_FROM_IIM
+#include <asm/imx_iim.h>
+#endif
+
+#ifdef CONFIG_CMD_MMC
+#include <mmc.h>
+#include <fsl_esdhc.h>
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static u32 system_rev;
+#ifdef CONFIG_LCD
+char lcd_cmap[256];
+#endif
+
+u32 get_board_rev(void)
+{
+	return system_rev;
+}
+
+static inline void setup_soc_rev(void)
+{
+	int reg;
+	reg = __REG(IIM_BASE + IIM_SREV);
+	if (!reg) {
+		reg = __REG(ROMPATCH_REV);
+		reg <<= 4;
+	} else
+		reg += CHIP_REV_1_0;
+	system_rev = 0x25000 + (reg & 0xFF);
+}
+
+inline int is_soc_rev(int rev)
+{
+	return (system_rev & 0xFF) - rev;
+}
+
+int dram_init(void)
+{
+	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+
+	return 0;
+}
+
+#ifdef CONFIG_CMD_MMC
+
+struct fsl_esdhc_cfg esdhc_cfg[2] = {
+	{MMC_SDHC1_BASE, 1, 1},
+	{MMC_SDHC2_BASE, 1, 1},
+};
+
+int esdhc_gpio_init(bd_t *bis)
+{
+	s32 status = 0;
+	u32 index = 0;
+	u32 val = 0;
+
+	for (index = 0; index < CONFIG_SYS_FSL_ESDHC_NUM;
+		++index) {
+		switch (index) {
+		case 0:
+			/* Pins */
+			writel(0x10, IOMUXC_BASE + 0x190); /* SD1_CMD */
+			writel(0x10, IOMUXC_BASE + 0x194); /* SD1_CLK */
+			writel(0x00, IOMUXC_BASE + 0x198); /* SD1_DATA0 */
+			writel(0x00, IOMUXC_BASE + 0x19c); /* SD1_DATA1 */
+			writel(0x00, IOMUXC_BASE + 0x1a0); /* SD1_DATA2 */
+			writel(0x00, IOMUXC_BASE + 0x1a4); /* SD1_DATA3 */
+			writel(0x06, IOMUXC_BASE + 0x094); /* D12 (SD1_DATA4) */
+			writel(0x06, IOMUXC_BASE + 0x090); /* D13 (SD1_DATA5) */
+			writel(0x06, IOMUXC_BASE + 0x08c); /* D14 (SD1_DATA6) */
+			writel(0x06, IOMUXC_BASE + 0x088); /* D15 (SD1_DATA7) */
+			writel(0x05, IOMUXC_BASE + 0x010); /* A14 (SD1_WP) */
+			writel(0x05, IOMUXC_BASE + 0x014); /* A15 (SD1_DET) */
+
+			/* Pads */
+			writel(0xD1, IOMUXC_BASE + 0x388); /* SD1_CMD */
+			writel(0xD1, IOMUXC_BASE + 0x38c); /* SD1_CLK */
+			writel(0xD1, IOMUXC_BASE + 0x390); /* SD1_DATA0 */
+			writel(0xD1, IOMUXC_BASE + 0x394); /* SD1_DATA1 */
+			writel(0xD1, IOMUXC_BASE + 0x398); /* SD1_DATA2 */
+			writel(0xD1, IOMUXC_BASE + 0x39c); /* SD1_DATA3 */
+			writel(0xD1, IOMUXC_BASE + 0x28c); /* D12 (SD1_DATA4) */
+			writel(0xD1, IOMUXC_BASE + 0x288); /* D13 (SD1_DATA5) */
+			writel(0xD1, IOMUXC_BASE + 0x284); /* D14 (SD1_DATA6) */
+			writel(0xD1, IOMUXC_BASE + 0x280); /* D15 (SD1_DATA7) */
+			writel(0xD1, IOMUXC_BASE + 0x230); /* A14 (SD1_WP) */
+			writel(0xD1, IOMUXC_BASE + 0x234); /* A15 (SD1_DET) */
+
+			/*
+			 * Set write protect and card detect gpio as inputs
+			 * A14 (SD1_WP) and A15 (SD1_DET)
+			 */
+			val = ~(3 << 0) & readl(GPIO1_BASE + GPIO_GDIR);
+			writel(val, GPIO1_BASE + GPIO_GDIR);
+			break;
+		case 1:
+			/* Pins */
+			writel(0x16, IOMUXC_BASE + 0x0e8); /* LD8 (SD1_CMD) */
+			writel(0x16, IOMUXC_BASE + 0x0ec); /* LD9 (SD1_CLK) */
+			writel(0x06, IOMUXC_BASE + 0x0f0); /* LD10 (SD1_DATA0)*/
+			writel(0x06, IOMUXC_BASE + 0x0f4); /* LD11 (SD1_DATA1)*/
+			writel(0x06, IOMUXC_BASE + 0x0f8); /* LD12 (SD1_DATA2)*/
+			writel(0x06, IOMUXC_BASE + 0x0fc); /* LD13 (SD1_DATA3)*/
+			/* CSI_D2 (SD1_DATA4) */
+			writel(0x02, IOMUXC_BASE + 0x120);
+			/* CSI_D3 (SD1_DATA5) */
+			writel(0x02, IOMUXC_BASE + 0x124);
+			/* CSI_D4 (SD1_DATA6) */
+			writel(0x02, IOMUXC_BASE + 0x128);
+			/* CSI_D5 (SD1_DATA7) */
+			writel(0x02, IOMUXC_BASE + 0x12c);
+
+			/* Pads */
+			writel(0xD1, IOMUXC_BASE + 0x2e0); /* LD8 (SD1_CMD) */
+			writel(0xD1, IOMUXC_BASE + 0x2e4); /* LD9 (SD1_CLK) */
+			writel(0xD1, IOMUXC_BASE + 0x2e8); /* LD10 (SD1_DATA0)*/
+			writel(0xD1, IOMUXC_BASE + 0x2ec); /* LD11 (SD1_DATA1)*/
+			writel(0xD1, IOMUXC_BASE + 0x2f0); /* LD12 (SD1_DATA2)*/
+			writel(0xD1, IOMUXC_BASE + 0x2f4); /* LD13 (SD1_DATA3)*/
+			/* CSI_D2 (SD1_DATA4) */
+			writel(0xD1, IOMUXC_BASE + 0x318);
+			/* CSI_D3 (SD1_DATA5) */
+			writel(0xD1, IOMUXC_BASE + 0x31c);
+			/* CSI_D4 (SD1_DATA6) */
+			writel(0xD1, IOMUXC_BASE + 0x320);
+			/* CSI_D5 (SD1_DATA7) */
+			writel(0xD1, IOMUXC_BASE + 0x324);
+			break;
+		default:
+			printf("Warning: you configured more ESDHC controller"
+				"(%d) as supported by the board(2)\n",
+				CONFIG_SYS_FSL_ESDHC_NUM);
+			return status;
+			break;
+		}
+		status |= fsl_esdhc_initialize(bis, &esdhc_cfg[index]);
+	}
+	return 0;
+}
+
+int board_mmc_init(bd_t *bis)
+{
+	if (!esdhc_gpio_init(bis))
+		return 0;
+	else
+		return -1;
+}
+#endif
+
+s32 spi_get_cfg(struct imx_spi_dev_t *dev)
+{
+	switch (dev->slave.cs) {
+	case 0:
+		/* cpld */
+		dev->base = CSPI1_BASE;
+		dev->freq = 25000000;
+		dev->ss_pol = IMX_SPI_ACTIVE_LOW;
+		dev->ss = 0;
+		dev->fifo_sz = 32;
+		dev->us_delay = 0;
+		break;
+	default:
+		printf("Invalid Bus ID! \n");
+		break;
+	}
+
+	return 0;
+}
+
+void spi_io_init(struct imx_spi_dev_t *dev)
+{
+	switch (dev->base) {
+	case CSPI1_BASE:
+		writel(0, IOMUXC_BASE + 0x180);		/* CSPI1 SCLK */
+		writel(0x1C0, IOMUXC_BASE + 0x5c4);
+		writel(0, IOMUXC_BASE + 0x184);		/* SPI_RDY */
+		writel(0x1E0, IOMUXC_BASE + 0x5c8);
+		writel(0, IOMUXC_BASE + 0x170);		/* MOSI */
+		writel(0x1C0, IOMUXC_BASE + 0x5b4);
+		writel(0, IOMUXC_BASE + 0x174);		/* MISO */
+		writel(0x1C0, IOMUXC_BASE + 0x5b8);
+		writel(0, IOMUXC_BASE + 0x17C);		/* SS1 */
+		writel(0x1E0, IOMUXC_BASE + 0x5C0);
+		break;
+	default:
+		break;
+	}
+}
+
+#ifdef CONFIG_LCD
+
+vidinfo_t panel_info = {
+	vl_refresh:60,
+	vl_col:640,
+	vl_row:480,
+	vl_pixclock:39683,
+	vl_left_margin:45,
+	vl_right_margin:114,
+	vl_upper_margin:33,
+	vl_lower_margin:11,
+	vl_hsync:1,
+	vl_vsync:1,
+	vl_sync : FB_SYNC_CLK_LAT_FALL,
+	vl_mode:0,
+	vl_flag:0,
+	vl_bpix:4,
+	cmap : (void *)lcd_cmap,
+};
+
+void lcdc_hw_init(void)
+{
+	/* Set VSTBY_REQ as GPIO3[17] on ALT5 */
+	mxc_request_iomux(MX25_PIN_VSTBY_REQ, MUX_CONFIG_ALT5);
+
+	/* Set GPIO3[17] as output */
+	writel(0x20000, GPIO3_BASE + 0x04);
+
+	/* Set GPIOE as LCDC_LD[16] on ALT2 */
+	mxc_request_iomux(MX25_PIN_GPIO_E, MUX_CONFIG_ALT2);
+
+	/* Set GPIOF as LCDC_LD[17] on ALT2 */
+	mxc_request_iomux(MX25_PIN_GPIO_F, MUX_CONFIG_ALT2);
+
+	/* Enable pull up on LCDC_LD[16]	*/
+	mxc_iomux_set_pad(MX25_PIN_GPIO_E,
+			PAD_CTL_PKE_ENABLE | PAD_CTL_100K_PU);
+
+	/* Enable pull up on LCDC_LD[17]	*/
+	mxc_iomux_set_pad(MX25_PIN_GPIO_F,
+			PAD_CTL_PKE_ENABLE | PAD_CTL_100K_PU);
+
+	/* Enable Pull/Keeper for pad LSCKL */
+	mxc_iomux_set_pad(MX25_PIN_LSCLK,
+			PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_PUD |
+			PAD_CTL_100K_PU | PAD_CTL_SRE_FAST);
+
+	gd->fb_base = CONFIG_FB_BASE;
+}
+
+#ifdef CONFIG_SPLASH_SCREEN
+int setup_splash_img()
+{
+#ifdef CONFIG_SPLASH_IS_IN_MMC
+	int mmc_dev = CONFIG_SPLASH_IMG_MMC_DEV;
+	ulong offset = CONFIG_SPLASH_IMG_OFFSET;
+	ulong size = CONFIG_SPLASH_IMG_SIZE;
+	ulong addr = 0;
+	char *s = NULL;
+	struct mmc *mmc = find_mmc_device(mmc_dev);
+	uint blk_start, blk_cnt, n;
+
+	s = getenv("splashimage");
+
+	if (NULL == s) {
+		puts("env splashimage not found!\n");
+		return -1;
+	}
+	addr = simple_strtoul(s, NULL, 16);
+
+	if (!mmc) {
+		printf("MMC Device %d not found\n",
+			mmc_dev);
+		return -1;
+	}
+
+	if (mmc_init(mmc)) {
+		puts("MMC init failed\n");
+		return  -1;
+	}
+
+	blk_start = ALIGN(offset, mmc->read_bl_len) / mmc->read_bl_len;
+	blk_cnt   = ALIGN(size, mmc->read_bl_len) / mmc->read_bl_len;
+	n = mmc->block_dev.block_read(mmc_dev, blk_start,
+					blk_cnt, (u_char *)addr);
+	flush_cache((ulong)addr, blk_cnt * mmc->read_bl_len);
+
+	return (n == blk_cnt) ? 0 : -1;
+#endif
+}
+#endif
+#endif
+
+#ifdef CONFIG_GET_FEC_MAC_ADDR_FROM_IIM
+
+int fec_get_mac_addr(unsigned char *mac)
+{
+	u32 *iim0_mac_base =
+		(u32 *)(IIM_BASE + IIM_BANK_AREA_0_OFFSET +
+			CONFIG_IIM_MAC_ADDR_OFFSET);
+	int i;
+
+	for (i = 0; i < 6; ++i, ++iim0_mac_base)
+		mac[i] = readl(iim0_mac_base);
+
+	return 0;
+}
+#endif
+
+int board_init(void)
+{
+
+#ifdef CONFIG_MFG
+	/* MFG firmware need reset usb to avoid host crash firstly */
+#define USBCMD 0x140
+	int val = readl(USB_BASE + USBCMD);
+	val &= ~0x1; /*RS bit*/
+	writel(val, USB_BASE + USBCMD);
+#endif
+
+	setup_soc_rev();
+
+	/* setup pins for UART1 */
+	/* UART 1 IOMUX Configs */
+	mxc_request_iomux(MX25_PIN_UART1_RXD, MUX_CONFIG_FUNC);
+	mxc_request_iomux(MX25_PIN_UART1_TXD, MUX_CONFIG_FUNC);
+	mxc_request_iomux(MX25_PIN_UART1_RTS, MUX_CONFIG_FUNC);
+	mxc_request_iomux(MX25_PIN_UART1_CTS, MUX_CONFIG_FUNC);
+	mxc_iomux_set_pad(MX25_PIN_UART1_RXD,
+			PAD_CTL_HYS_SCHMITZ | PAD_CTL_PKE_ENABLE |
+			PAD_CTL_PUE_PUD | PAD_CTL_100K_PU);
+	mxc_iomux_set_pad(MX25_PIN_UART1_TXD,
+			PAD_CTL_PUE_PUD | PAD_CTL_100K_PD);
+	mxc_iomux_set_pad(MX25_PIN_UART1_RTS,
+			PAD_CTL_HYS_SCHMITZ | PAD_CTL_PKE_ENABLE |
+			PAD_CTL_PUE_PUD | PAD_CTL_100K_PU);
+	mxc_iomux_set_pad(MX25_PIN_UART1_CTS,
+			PAD_CTL_PUE_PUD | PAD_CTL_100K_PD);
+
+	/* setup pins for FEC */
+	mxc_request_iomux(MX25_PIN_FEC_TX_CLK, MUX_CONFIG_FUNC);
+	mxc_request_iomux(MX25_PIN_FEC_RX_DV, MUX_CONFIG_FUNC);
+	mxc_request_iomux(MX25_PIN_FEC_RDATA0, MUX_CONFIG_FUNC);
+	mxc_request_iomux(MX25_PIN_FEC_TDATA0, MUX_CONFIG_FUNC);
+	mxc_request_iomux(MX25_PIN_FEC_TX_EN, MUX_CONFIG_FUNC);
+	mxc_request_iomux(MX25_PIN_FEC_MDC, MUX_CONFIG_FUNC);
+	mxc_request_iomux(MX25_PIN_FEC_MDIO, MUX_CONFIG_FUNC);
+	mxc_request_iomux(MX25_PIN_FEC_RDATA1, MUX_CONFIG_FUNC);
+	mxc_request_iomux(MX25_PIN_FEC_TDATA1, MUX_CONFIG_FUNC);
+	mxc_request_iomux(MX25_PIN_POWER_FAIL, MUX_CONFIG_FUNC); /* PHY INT */
+
+#define FEC_PAD_CTL1 (PAD_CTL_HYS_SCHMITZ | PAD_CTL_PUE_PUD | \
+			PAD_CTL_PKE_ENABLE)
+#define FEC_PAD_CTL2 (PAD_CTL_PUE_PUD)
+
+	mxc_iomux_set_pad(MX25_PIN_FEC_TX_CLK, FEC_PAD_CTL1);
+	mxc_iomux_set_pad(MX25_PIN_FEC_RX_DV, FEC_PAD_CTL1);
+	mxc_iomux_set_pad(MX25_PIN_FEC_RDATA0, FEC_PAD_CTL1);
+	mxc_iomux_set_pad(MX25_PIN_FEC_TDATA0, FEC_PAD_CTL2);
+	mxc_iomux_set_pad(MX25_PIN_FEC_TX_EN, FEC_PAD_CTL2);
+	mxc_iomux_set_pad(MX25_PIN_FEC_MDC, FEC_PAD_CTL2);
+	mxc_iomux_set_pad(MX25_PIN_FEC_MDIO, FEC_PAD_CTL1 | PAD_CTL_22K_PU);
+	mxc_iomux_set_pad(MX25_PIN_FEC_RDATA1, FEC_PAD_CTL1);
+	mxc_iomux_set_pad(MX25_PIN_FEC_TDATA1, FEC_PAD_CTL2);
+	mxc_iomux_set_pad(MX25_PIN_POWER_FAIL, FEC_PAD_CTL1);
+
+	/*
+	 * Set up the FEC_RESET_B and FEC_ENABLE GPIO pins.
+	 * Assert FEC_RESET_B, then power up the PHY by asserting
+	 * FEC_ENABLE, at the same time lifting FEC_RESET_B.
+	 *
+	 * FEC_RESET_B: gpio2[3] is ALT 5 mode of pin D12
+	 * FEC_ENABLE_B: gpio4[8] is ALT 5 mode of pin A17
+	 */
+	mxc_request_iomux(MX25_PIN_A17, MUX_CONFIG_ALT5); /* FEC_EN */
+	mxc_request_iomux(MX25_PIN_D12, MUX_CONFIG_ALT5); /* FEC_RESET_B */
+
+	mxc_iomux_set_pad(MX25_PIN_A17, PAD_CTL_ODE_OpenDrain);
+	mxc_iomux_set_pad(MX25_PIN_D12, 0);
+
+	mxc_set_gpio_direction(MX25_PIN_A17, 0); /* FEC_EN */
+	mxc_set_gpio_direction(MX25_PIN_D12, 0); /* FEC_RESET_B */
+
+	/* drop PHY power */
+	mxc_set_gpio_dataout(MX25_PIN_A17, 0);	/* FEC_EN */
+
+	/* assert reset */
+	mxc_set_gpio_dataout(MX25_PIN_D12, 0);	/* FEC_RESET_B */
+	udelay(2);		/* spec says 1us min */
+
+	/* turn on PHY power and lift reset */
+	mxc_set_gpio_dataout(MX25_PIN_A17, 1);	/* FEC_EN */
+	mxc_set_gpio_dataout(MX25_PIN_D12, 1);	/* FEC_RESET_B */
+
+#define I2C_PAD_CTL (PAD_CTL_HYS_SCHMITZ | PAD_CTL_PKE_ENABLE | \
+		PAD_CTL_PUE_PUD | PAD_CTL_100K_PU | PAD_CTL_ODE_OpenDrain)
+
+	mxc_request_iomux(MX25_PIN_I2C1_CLK, MUX_CONFIG_SION);
+	mxc_request_iomux(MX25_PIN_I2C1_DAT, MUX_CONFIG_SION);
+	mxc_iomux_set_pad(MX25_PIN_I2C1_CLK, 0x1E8);
+	mxc_iomux_set_pad(MX25_PIN_I2C1_DAT, 0x1E8);
+
+#ifdef CONFIG_LCD
+	lcdc_hw_init();
+#endif
+
+	gd->bd->bi_arch_number = MACH_TYPE_MX25_3DS;    /* board id for linux */
+	gd->bd->bi_boot_params = 0x80000100;    /* address of boot parameters */
+
+	return 0;
+
+#undef FEC_PAD_CTL1
+#undef FEC_PAD_CTL2
+#undef I2C_PAD_CTL
+}
+
+#ifdef BOARD_LATE_INIT
+int board_late_init(void)
+{
+	u8 reg[4];
+
+	/* Turn PMIC On*/
+	reg[0] = 0x09;
+	i2c_write(0x54, 0x02, 1, reg, 1);
+
+#ifdef CONFIG_IMX_SPI_CPLD
+	mxc_cpld_spi_init();
+#endif
+
+#ifdef CONFIG_SPLASH_SCREEN
+	if (!setup_splash_img())
+		printf("Read splash screen failed!\n");
+#endif
+
+	return 0;
+}
+#endif
+
+
+int checkboard(void)
+{
+	printf("Board: i.MX25 MAX PDK (3DS)\n");
+	return 0;
+}
+
+int board_eth_init(bd_t *bis)
+{
+	int rc = -ENODEV;
+#if defined(CONFIG_SMC911X)
+	rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);
+#endif
+
+	cpu_eth_init(bis);
+
+	return rc;
+}
+

board/freescale/mx25_3stack/u-boot.lds

@@ -0,0 +1,62 @@
+/*
+ * (c) Copyright 2009 Freescale Semiconductor
+ *
+ * January 2004 - Changed to support H4 device
+ * Copyright (c) 2004 Texas Instruments
+ *
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+	. = 0x00000000;
+
+	. = ALIGN(4);
+	.text	   :
+	{
+	  board/freescale/mx25_3stack/dcdheader.o (.text)
+	  cpu/arm926ejs/start.o	(.text)
+	  *(.text)
+	}
+
+	. = ALIGN(4);
+	.rodata : { *(.rodata) }
+
+	. = ALIGN(4);
+	.data : { *(.data) }
+
+	. = ALIGN(4);
+	.got : { *(.got) }
+
+	. = .;
+	__u_boot_cmd_start = .;
+	.u_boot_cmd : { *(.u_boot_cmd) }
+	__u_boot_cmd_end = .;
+
+	. = ALIGN(4);
+	__bss_start = .;
+	.bss : { *(.bss) }
+	_end = .;
+}

board/freescale/mx28_evk/Makefile

@@ -0,0 +1,52 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).a
+
+COBJS	:= mx28_evk.o
+SOBJS	:= lowlevel_init.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
+

board/freescale/mx28_evk/config.mk

@@ -0,0 +1,6 @@
+#
+# image should be loaded at 0x41008000
+#
+LDSCRIPT := $(SRCTREE)/board/$(VENDOR)/$(BOARD)/u-boot.lds
+
+TEXT_BASE = 0x41008000

board/freescale/mx28_evk/lowlevel_init.S

@@ -0,0 +1,33 @@
+/*
+ * Board specific setup info
+ *
+ * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <version.h>
+
+/* Set up the platform, once the cpu has been initialized */
+.globl lowlevel_init
+lowlevel_init:
+
+	/* All SDRAM settings are done by sdram_prep */
+	mov pc, lr

board/freescale/mx28_evk/mx28_evk.c

@@ -0,0 +1,287 @@
+/*
+ * Copyright (C) 2010 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/arch/regs-pinctrl.h>
+#include <asm/arch/pinctrl.h>
+#include <asm/arch/regs-clkctrl.h>
+#include <asm/arch/regs-ocotp.h>
+
+#include <mmc.h>
+#include <imx_ssp_mmc.h>
+
+/* This should be removed after it's added into mach-types.h */
+#ifndef MACH_TYPE_MX28EVK
+#define MACH_TYPE_MX28EVK	2531
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#ifdef CONFIG_IMX_SSP_MMC
+
+/* MMC pins */
+static struct pin_desc mmc0_pins_desc[] = {
+	{ PINID_SSP0_DATA0, PIN_FUN1, PAD_8MA, PAD_3V3, 1 },
+	{ PINID_SSP0_DATA1, PIN_FUN1, PAD_8MA, PAD_3V3, 1 },
+	{ PINID_SSP0_DATA2, PIN_FUN1, PAD_8MA, PAD_3V3, 1 },
+	{ PINID_SSP0_DATA3, PIN_FUN1, PAD_8MA, PAD_3V3, 1 },
+	{ PINID_SSP0_DATA4, PIN_FUN1, PAD_8MA, PAD_3V3, 1 },
+	{ PINID_SSP0_DATA5, PIN_FUN1, PAD_8MA, PAD_3V3, 1 },
+	{ PINID_SSP0_DATA6, PIN_FUN1, PAD_8MA, PAD_3V3, 1 },
+	{ PINID_SSP0_DATA7, PIN_FUN1, PAD_8MA, PAD_3V3, 1 },
+	{ PINID_SSP0_CMD, PIN_FUN1, PAD_8MA, PAD_3V3, 1 },
+	{ PINID_SSP0_DETECT, PIN_FUN1, PAD_8MA, PAD_3V3, 1 },
+	{ PINID_SSP0_SCK, PIN_FUN1, PAD_8MA, PAD_3V3, 1 },
+};
+
+static struct pin_desc mmc1_pins_desc[] = {
+	{ PINID_GPMI_D00, PIN_FUN2, PAD_8MA, PAD_3V3, 1 },
+	{ PINID_GPMI_D01, PIN_FUN2, PAD_8MA, PAD_3V3, 1 },
+	{ PINID_GPMI_D02, PIN_FUN2, PAD_8MA, PAD_3V3, 1 },
+	{ PINID_GPMI_D03, PIN_FUN2, PAD_8MA, PAD_3V3, 1 },
+	{ PINID_GPMI_D04, PIN_FUN2, PAD_8MA, PAD_3V3, 1 },
+	{ PINID_GPMI_D05, PIN_FUN2, PAD_8MA, PAD_3V3, 1 },
+	{ PINID_GPMI_D06, PIN_FUN2, PAD_8MA, PAD_3V3, 1 },
+	{ PINID_GPMI_D07, PIN_FUN2, PAD_8MA, PAD_3V3, 1 },
+	{ PINID_GPMI_RDY1, PIN_FUN2, PAD_8MA, PAD_3V3, 1 },
+	{ PINID_GPMI_RDY0, PIN_FUN2, PAD_8MA, PAD_3V3, 1 },
+	{ PINID_GPMI_WRN, PIN_FUN2, PAD_8MA, PAD_3V3, 1 }
+};
+
+static struct pin_group mmc0_pins = {
+	.pins		= mmc0_pins_desc,
+	.nr_pins	= ARRAY_SIZE(mmc0_pins_desc)
+};
+
+static struct pin_group mmc1_pins = {
+	.pins		= mmc1_pins_desc,
+	.nr_pins	= ARRAY_SIZE(mmc1_pins_desc)
+};
+
+struct imx_ssp_mmc_cfg ssp_mmc_cfg[2] = {
+	{REGS_SSP0_BASE, HW_CLKCTRL_SSP0, BM_CLKCTRL_CLKSEQ_BYPASS_SSP0},
+	{REGS_SSP1_BASE, HW_CLKCTRL_SSP1, BM_CLKCTRL_CLKSEQ_BYPASS_SSP1},
+};
+#endif
+
+/* ENET pins */
+static struct pin_desc enet_pins_desc[] = {
+	{ PINID_ENET0_MDC, PIN_FUN1, PAD_8MA, PAD_3V3, 1 },
+	{ PINID_ENET0_MDIO, PIN_FUN1, PAD_8MA, PAD_3V3, 1 },
+	{ PINID_ENET0_RX_EN, PIN_FUN1, PAD_8MA, PAD_3V3, 1 },
+	{ PINID_ENET0_RXD0, PIN_FUN1, PAD_8MA, PAD_3V3, 1 },
+	{ PINID_ENET0_RXD1, PIN_FUN1, PAD_8MA, PAD_3V3, 1 },
+	{ PINID_ENET0_TX_EN, PIN_FUN1, PAD_8MA, PAD_3V3, 1 },
+	{ PINID_ENET0_TXD0, PIN_FUN1, PAD_8MA, PAD_3V3, 1 },
+	{ PINID_ENET0_TXD1, PIN_FUN1, PAD_8MA, PAD_3V3, 1 },
+	{ PINID_ENET_CLK, PIN_FUN1, PAD_8MA, PAD_3V3, 1 }
+};
+
+/* Gpmi pins */
+static struct pin_desc gpmi_pins_desc[] = {
+	{ PINID_GPMI_D00, PIN_FUN1, PAD_4MA, PAD_3V3, 0 },
+	{ PINID_GPMI_D01, PIN_FUN1, PAD_4MA, PAD_3V3, 0 },
+	{ PINID_GPMI_D02, PIN_FUN1, PAD_4MA, PAD_3V3, 0 },
+	{ PINID_GPMI_D03, PIN_FUN1, PAD_4MA, PAD_3V3, 0 },
+	{ PINID_GPMI_D04, PIN_FUN1, PAD_4MA, PAD_3V3, 0 },
+	{ PINID_GPMI_D05, PIN_FUN1, PAD_4MA, PAD_3V3, 0 },
+	{ PINID_GPMI_D06, PIN_FUN1, PAD_4MA, PAD_3V3, 0 },
+	{ PINID_GPMI_D07, PIN_FUN1, PAD_4MA, PAD_3V3, 0 },
+	{ PINID_GPMI_RDN, PIN_FUN1, PAD_8MA, PAD_1V8, 1 },
+	{ PINID_GPMI_WRN, PIN_FUN1, PAD_4MA, PAD_3V3, 0 },
+	{ PINID_GPMI_ALE, PIN_FUN1, PAD_4MA, PAD_3V3, 0 },
+	{ PINID_GPMI_CLE, PIN_FUN1, PAD_4MA, PAD_3V3, 0 },
+	{ PINID_GPMI_RDY0, PIN_FUN1, PAD_4MA, PAD_3V3, 0 },
+	{ PINID_GPMI_RDY1, PIN_FUN1, PAD_4MA, PAD_3V3, 0 },
+	{ PINID_GPMI_CE0N, PIN_FUN1, PAD_4MA, PAD_3V3, 0 },
+	{ PINID_GPMI_CE1N, PIN_FUN1, PAD_4MA, PAD_3V3, 0 },
+	{ PINID_GPMI_RESETN, PIN_FUN1, PAD_4MA, PAD_3V3, 0 }
+};
+static struct pin_group enet_pins = {
+	.pins		= enet_pins_desc,
+	.nr_pins	= ARRAY_SIZE(enet_pins_desc)
+};
+static struct pin_group gpmi_pins = {
+	.pins		= gpmi_pins_desc,
+	.nr_pins	= ARRAY_SIZE(gpmi_pins_desc)
+};
+
+/*
+ * Functions
+ */
+int board_init(void)
+{
+	/* Will change it for MX28 EVK later */
+	gd->bd->bi_arch_number = MACH_TYPE_MX28EVK;
+	/* Adress of boot parameters */
+	gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
+#ifdef CONFIG_NAND_GPMI
+	setup_gpmi_nand();
+#endif
+	return 0;
+}
+
+int dram_init(void)
+{
+	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+
+	return 0;
+}
+
+#ifdef CONFIG_IMX_SSP_MMC
+
+#ifdef CONFIG_DYNAMIC_MMC_DEVNO
+int get_mmc_env_devno()
+{
+	unsigned long global_boot_mode;
+
+	global_boot_mode = REG_RD_ADDR(GLOBAL_BOOT_MODE_ADDR);
+	return ((global_boot_mode & 0xf) == BOOT_MODE_SD1) ? 1 : 0;
+}
+#endif
+
+#define PINID_SSP0_GPIO_WP PINID_SSP1_SCK
+#define PINID_SSP1_GPIO_WP PINID_GPMI_RESETN
+
+u32 ssp_mmc_is_wp(struct mmc *mmc)
+{
+	return (mmc->block_dev.dev == 0) ?
+		pin_gpio_get(PINID_SSP0_GPIO_WP) :
+		pin_gpio_get(PINID_SSP1_GPIO_WP);
+}
+
+int ssp_mmc_gpio_init(bd_t *bis)
+{
+	s32 status = 0;
+	u32 index = 0;
+
+	for (index = 0; index < CONFIG_SYS_SSP_MMC_NUM;
+		++index) {
+		switch (index) {
+		case 0:
+			/* Set up MMC pins */
+			pin_set_group(&mmc0_pins);
+
+			/* Power on the card slot 0 */
+			pin_set_type(PINID_PWM3, PIN_GPIO);
+			pin_gpio_direction(PINID_PWM3, 1);
+			pin_gpio_set(PINID_PWM3, 0);
+
+			/* Wait 10 ms for card ramping up */
+			udelay(10000);
+
+			/* Set up SD0 WP pin */
+			pin_set_type(PINID_SSP0_GPIO_WP, PIN_GPIO);
+			pin_gpio_direction(PINID_SSP0_GPIO_WP, 0);
+
+			break;
+		case 1:
+#ifdef CONFIG_CMD_MMC
+			/* Set up MMC pins */
+			pin_set_group(&mmc1_pins);
+
+			/* Power on the card slot 1 */
+			pin_set_type(PINID_PWM4, PIN_GPIO);
+			pin_gpio_direction(PINID_PWM4, 1);
+			pin_gpio_set(PINID_PWM4, 0);
+
+			/* Wait 10 ms for card ramping up */
+			udelay(10000);
+
+			/* Set up SD1 WP pin */
+			pin_set_type(PINID_SSP1_GPIO_WP, PIN_GPIO);
+			pin_gpio_direction(PINID_SSP1_GPIO_WP, 0);
+#endif
+			break;
+		default:
+			printf("Warning: you configured more ssp mmc controller"
+				"(%d) as supported by the board(2)\n",
+				CONFIG_SYS_SSP_MMC_NUM);
+			return status;
+		}
+		status |= imx_ssp_mmc_initialize(bis, &ssp_mmc_cfg[index]);
+	}
+
+	return status;
+}
+
+int board_mmc_init(bd_t *bis)
+{
+	if (!ssp_mmc_gpio_init(bis))
+		return 0;
+	else
+		return -1;
+}
+
+#endif
+
+#ifdef CONFIG_MXC_FEC
+#ifdef CONFIG_GET_FEC_MAC_ADDR_FROM_IIM
+int fec_get_mac_addr(unsigned char *mac)
+{
+	u32 val;
+
+	/*set this bit to open the OTP banks for reading*/
+	REG_WR(REGS_OCOTP_BASE, HW_OCOTP_CTRL_SET,
+		BM_OCOTP_CTRL_RD_BANK_OPEN);
+
+	/*wait until OTP contents are readable*/
+	while (BM_OCOTP_CTRL_BUSY & REG_RD(REGS_OCOTP_BASE, HW_OCOTP_CTRL))
+		udelay(100);
+
+	mac[0] = 0x00;
+	mac[1] = 0x04;
+	val = REG_RD(REGS_OCOTP_BASE, HW_OCOTP_CUSTn(0));
+	mac[2] = (val >> 24) & 0xFF;
+	mac[3] = (val >> 16) & 0xFF;
+	mac[4] = (val >> 8) & 0xFF;
+	mac[5] = (val >> 0) & 0xFF;
+	return 0;
+}
+#endif
+#endif
+
+void enet_board_init(void)
+{
+	/* Set up ENET pins */
+	pin_set_group(&enet_pins);
+
+	/* Power on the external phy */
+	pin_set_type(PINID_SSP1_DATA3, PIN_GPIO);
+	pin_gpio_direction(PINID_SSP1_DATA3, 1);
+	pin_gpio_set(PINID_SSP1_DATA3, 0);
+
+	/* Reset the external phy */
+	pin_set_type(PINID_ENET0_RX_CLK, PIN_GPIO);
+	pin_gpio_direction(PINID_ENET0_RX_CLK, 1);
+	pin_gpio_set(PINID_ENET0_RX_CLK, 0);
+	udelay(200);
+	pin_gpio_set(PINID_ENET0_RX_CLK, 1);
+}
+#ifdef CONFIG_NAND_GPMI
+void setup_gpmi_nand()
+{
+	/* Set up GPMI pins */
+	pin_set_group(&gpmi_pins);
+}
+#endif

board/freescale/mx28_evk/u-boot.lds

@@ -0,0 +1,51 @@
+/*
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+	. = 0x00000000;
+	. = ALIGN(4);
+	.text	:
+	{
+	  cpu/arm926ejs/start.o (.text)
+	  *(.text)
+	}
+	.rodata : { *(.rodata) }
+	. = ALIGN(4);
+	.data : { *(.data) }
+	. = ALIGN(4);
+	.got : { *(.got) }
+
+	. = .;
+	__u_boot_cmd_start = .;
+	.u_boot_cmd : { *(.u_boot_cmd) }
+	__u_boot_cmd_end = .;
+
+	. = ALIGN(4);
+	__bss_start = .;
+	.bss (NOLOAD) : { *(.bss) }
+	_end = .;
+}

board/freescale/mx31_3stack/Makefile

@@ -0,0 +1,47 @@
+#
+# Copyright (C) 2008, Guennadi Liakhovetski <lg@denx.de>
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).a
+
+COBJS	:= mx31_3stack.o
+SOBJS	:= lowlevel_init.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################

board/freescale/mx31_3stack/config.mk

@@ -0,0 +1,3 @@
+LDSCRIPT := $(SRCTREE)/board/$(VENDOR)/$(BOARD)/u-boot.lds
+
+TEXT_BASE = 0x87f00000

board/freescale/mx31_3stack/lowlevel_init.S

@@ -0,0 +1,248 @@
+/*
+ * Copyright (C) 2008, Guennadi Liakhovetski <lg@denx.de>
+ * Copyright (C) 2008, Freescale Semiconductor
+ * 	Modifications for MX31 3Stack board
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <asm/arch/mx31-regs.h>
+
+.macro REG reg, val
+	ldr r2, =\reg
+	ldr r3, =\val
+	str r3, [r2]
+.endm
+
+.macro REG8 reg, val
+	ldr r2, =\reg
+	ldr r3, =\val
+	strb r3, [r2]
+.endm
+
+.macro DELAY loops
+	ldr r2, =\loops
+1:
+	subs	r2, r2, #1
+	nop
+	bcs 1b
+.endm
+
+.macro init_aips
+	/*
+	 * Set all MPROTx to be non-bufferable, trusted for R/W,
+	 * not forced to user-mode.
+	 */
+	ldr r0, =0x43F00000
+	ldr r1, =0x77777777
+	str r1, [r0, #0x00]
+	str r1, [r0, #0x04]
+	ldr r0, =0x53F00000
+	str r1, [r0, #0x00]
+	str r1, [r0, #0x04]
+
+	/*
+	 * Clear the on and off peripheral modules Supervisor Protect bit
+	 * for SDMA to access them. Did not change the AIPS control registers
+	 * (offset 0x20) access type
+	 */
+	ldr r0, =0x43F00000
+	ldr r1, =0x0
+	str r1, [r0, #0x40]
+	str r1, [r0, #0x44]
+	str r1, [r0, #0x48]
+	str r1, [r0, #0x4C]
+	ldr r1, [r0, #0x50]
+	and r1, r1, #0x00FFFFFF
+	str r1, [r0, #0x50]
+
+	ldr r0, =0x53F00000
+	ldr r1, =0x0
+	str r1, [r0, #0x40]
+	str r1, [r0, #0x44]
+	str r1, [r0, #0x48]
+	str r1, [r0, #0x4C]
+	ldr r1, [r0, #0x50]
+	and r1, r1, #0x00FFFFFF
+	str r1, [r0, #0x50]
+.endm /* init_aips */
+
+.macro init_max
+	ldr r0, =0x43F04000
+	/* MPR - priority is M4 > M2 > M3 > M5 > M0 > M1 */
+	ldr r1, =0x00302154
+	str r1, [r0, #0x000]        /* for S0 */
+	str r1, [r0, #0x100]        /* for S1 */
+	str r1, [r0, #0x200]        /* for S2 */
+	str r1, [r0, #0x300]        /* for S3 */
+	str r1, [r0, #0x400]        /* for S4 */
+	/* SGPCR - always park on last master */
+	ldr r1, =0x10
+	str r1, [r0, #0x010]        /* for S0 */
+	str r1, [r0, #0x110]        /* for S1 */
+	str r1, [r0, #0x210]        /* for S2 */
+	str r1, [r0, #0x310]        /* for S3 */
+	str r1, [r0, #0x410]        /* for S4 */
+	/* MGPCR - restore default values */
+	ldr r1, =0x0
+	str r1, [r0, #0x800]        /* for M0 */
+	str r1, [r0, #0x900]        /* for M1 */
+	str r1, [r0, #0xA00]        /* for M2 */
+	str r1, [r0, #0xB00]        /* for M3 */
+	str r1, [r0, #0xC00]        /* for M4 */
+	str r1, [r0, #0xD00]        /* for M5 */
+.endm /* init_max */
+
+.macro init_m3if
+	/* Configure M3IF registers */
+	ldr r1, =0xB8003000
+	/*
+	* M3IF Control Register (M3IFCTL)
+	* MRRP[0] = L2CC0 not on priority list (0 << 0)	= 0x00000000
+	* MRRP[1] = L2CC1 not on priority list (0 << 0)	= 0x00000000
+	* MRRP[2] = MBX not on priority list (0 << 0)	= 0x00000000
+	* MRRP[3] = MAX1 not on priority list (0 << 0)	= 0x00000000
+	* MRRP[4] = SDMA not on priority list (0 << 0)	= 0x00000000
+	* MRRP[5] = MPEG4 not on priority list (0 << 0)	= 0x00000000
+	* MRRP[6] = IPU1 on priority list (1 << 6)	= 0x00000040
+	* MRRP[7] = IPU2 not on priority list (0 << 0)	= 0x00000000
+	*						------------
+	*						  0x00000040
+	*/
+	ldr r0, =0x00000040
+	str r0, [r1]  /* M3IF control reg */
+.endm /* init_m3if */
+
+.macro  init_drive_strength
+	/*
+	 * Disable maximum drive strength SDRAM/DDR lines by clearing DSE1 bits
+	 * in SW_PAD_CTL registers
+	 */
+
+	/* SDCLK */
+	ldr r1, =0x43FAC200
+	ldr r0, [r1, #0x6C]
+	bic r0, r0, #(1 << 12)
+	str r0, [r1, #0x6C]
+
+	/* CAS */
+	ldr r0, [r1, #0x70]
+	bic r0, r0, #(1 << 22)
+	str r0, [r1, #0x70]
+
+	/* RAS */
+	ldr r0, [r1, #0x74]
+	bic r0, r0, #(1 << 2)
+	str r0, [r1, #0x74]
+
+	/* CS2 (CSD0) */
+	ldr r0, [r1, #0x7C]
+	bic r0, r0, #(1 << 22)
+	str r0, [r1, #0x7C]
+
+	/* DQM3 */
+	ldr r0, [r1, #0x84]
+	bic r0, r0, #(1 << 22)
+	str r0, [r1, #0x84]
+
+	/* DQM2, DQM1, DQM0, SD31-SD0, A25-A0, MA10 (0x288..0x2DC) */
+	ldr r2, =22	/* (0x2E0 - 0x288) / 4 = 22 */
+pad_loop:
+	ldr r0, [r1, #0x88]
+	bic r0, r0, #(1 << 22)
+	bic r0, r0, #(1 << 12)
+	bic r0, r0, #(1 << 2)
+	str r0, [r1, #0x88]
+	add r1, r1, #4
+	subs r2, r2, #0x1
+	bne pad_loop
+.endm /* init_drive_strength */
+
+.section ".text.init", "x"
+
+.globl lowlevel_init
+lowlevel_init:
+
+	ldr r0, =0x40000015        /* start from AIPS 2GB region */
+	mcr p15, 0, r0, c15, c2, 4
+
+	init_aips
+
+	init_max
+
+	init_m3if
+
+	init_drive_strength
+
+	/* Image Processing Unit: */
+	/* Too early to switch display on? */
+	REG	IPU_CONF, IPU_CONF_DI_EN
+	/* Clock Control Module: */
+	REG	CCM_CCMR, 0x074B0BF5	/* Use CKIH, MCU PLL off */
+
+	DELAY 0x40000
+
+	REG	CCM_CCMR, 0x074B0BF5 | CCMR_MPE		/* MCU PLL on */
+	/* Switch to MCU PLL */
+	REG	CCM_CCMR, (0x074B0BF5 | CCMR_MPE) & ~CCMR_MDS
+
+	/* 532-133-66.5 */
+	ldr	r0, =CCM_BASE
+	ldr	r1, =0xFF871D58
+	/* PDR0 */
+	str	r1, [r0, #0x4]
+	ldr	r1, MPCTL_PARAM_532
+	/* MPCTL */
+	str	r1, [r0, #0x10]
+
+	/* Set UPLL=240MHz, USB=60MHz */
+	ldr	r1, =0x49FCFE7F
+	/* PDR1 */
+	str	r1, [r0, #0x8]
+	ldr	r1, UPCTL_PARAM_240
+	/* UPCTL */
+	str	r1, [r0, #0x14]
+	/* default CLKO to 1/8 of the ARM core */
+	mov	r1, #0x000002C0
+	add	r1, r1, #0x00000006
+	/* COSR */
+	str	r1, [r0, #0x1c]
+
+	/* initial CSD0 MDDR */
+	REG	0xB8001004, 0x0075E73A
+	REG	0xB8001010, 0x00000002 /* reset */
+	REG	0xB8001010, 0x00000004
+	DELAY	0x10000
+
+	REG	0xB8001000, 0x92100000
+	REG	0x80000F00, 0x0
+	REG	0xB8001000, 0xA2100000
+	REG	0x80000000, 0x0
+	REG	0xB8001000, 0xB2100000
+	REG8	0x80000033, 0x0
+	REG8	0x81000000, 0xff
+	REG	0xB8001000, 0x82226080
+	REG	0x80000000, 0x0
+	REG	0xB8001010, 0x0000000c
+
+	mov	r13, ip
+	/* copy blocks of total uboot to DDR */
+	b	mxc_nand_load
+
+MPCTL_PARAM_532:
+	.word (((1-1) << 26) + ((52-1) << 16) + (10 << 10) + (12 << 0))
+UPCTL_PARAM_240:
+	.word (((2-1) << 26) + ((13-1) << 16) + (9  << 10) + (3  << 0))

board/freescale/mx31_3stack/mx31_3stack.c

@@ -0,0 +1,75 @@
+/*
+ * Copyright (C) 2008, Guennadi Liakhovetski <lg@denx.de>
+ * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved.
+ * 	Modifications for MX31 3Stack board
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/mx31.h>
+#include <asm/arch/mx31-regs.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int dram_init(void)
+{
+	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+
+	return 0;
+}
+
+int board_init(void)
+{
+	/* CS5: Debug board for ethernet */
+	__REG(CSCR_U(5)) = 0x0000D843;
+	__REG(CSCR_L(5)) = 0x22252521;
+	__REG(CSCR_A(5)) = 0x22220A00;
+
+	/* setup pins for UART1 */
+	mx31_gpio_mux(MUX_RXD1__UART1_RXD_MUX);
+	mx31_gpio_mux(MUX_TXD1__UART1_TXD_MUX);
+	mx31_gpio_mux(MUX_RTS1__UART1_RTS_B);
+	mx31_gpio_mux(MUX_CTS1__UART1_CTS_B);
+
+	/* SPI2 */
+	mx31_gpio_mux((MUX_CTL_FUNC << 8) | MUX_CTL_CSPI2_SS2);
+	mx31_gpio_mux((MUX_CTL_FUNC << 8) | MUX_CTL_CSPI2_SCLK);
+	mx31_gpio_mux((MUX_CTL_FUNC << 8) | MUX_CTL_CSPI2_SPI_RDY);
+	mx31_gpio_mux((MUX_CTL_FUNC << 8) | MUX_CTL_CSPI2_MOSI);
+	mx31_gpio_mux((MUX_CTL_FUNC << 8) | MUX_CTL_CSPI2_MISO);
+	mx31_gpio_mux((MUX_CTL_FUNC << 8) | MUX_CTL_CSPI2_SS0);
+	mx31_gpio_mux((MUX_CTL_FUNC << 8) | MUX_CTL_CSPI2_SS1);
+
+	/* start SPI2 clock */
+	__REG(CCM_CGR2) = __REG(CCM_CGR2) | (3 << 4);
+
+	gd->bd->bi_arch_number = MACH_TYPE_MX31_3DS;	/* board id for linux */
+	gd->bd->bi_boot_params = 0x80000100;	/* adress of boot parameters */
+
+	return 0;
+}
+
+int checkboard(void)
+{
+	printf("Board: MX31 3Stack\n");
+	return 0;
+}

board/freescale/mx31_3stack/u-boot.lds

@@ -0,0 +1,72 @@
+/*
+ * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(reset)
+SECTIONS
+{
+	. = 0x00000000;
+
+	. = ALIGN(4);
+	.text	   :
+	{
+	  /* WARNING - the following is hand-optimized to fit within	*/
+	  /* the sector layout of our flash chips!	XXX FIXME XXX	*/
+
+	  * (.text.head)	/* arm reset handler */
+	  * (.text.init)	/* lowlevel initial */
+	  * (.text.load)	/* nand copy and load */
+	  * (.text.setup)
+	  board/freescale/mx31_3stack/libmx31_3stack.a	(.text)
+	  lib_arm/libarm.a		(.text)
+	  net/libnet.a			(.text)
+	  drivers/mtd/libmtd.a		(.text)
+
+	  . = DEFINED(env_offset) ? env_offset : .;
+	  common/env_embedded.o(.text)
+
+	  *(.text)
+	}
+
+	. = ALIGN(4);
+	.rodata : { *(.rodata) }
+
+	. = ALIGN(4);
+	.data : { *(.data) }
+
+	. = ALIGN(4);
+	.got : { *(.got) }
+
+	. = .;
+	__u_boot_cmd_start = .;
+	.u_boot_cmd : { *(.u_boot_cmd) }
+	__u_boot_cmd_end = .;
+
+	. = ALIGN(4);
+	__bss_start = .;
+	.bss : { *(.bss) }
+	_end = .;
+}

board/freescale/mx35_3stack/Makefile

@@ -0,0 +1,50 @@
+#
+# Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
+#
+# (C) Copyright 2008-2009 Freescale Semiconductor, Inc.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).a
+
+COBJS	:= mx35_3stack.o
+SOBJS	:= lowlevel_init.o
+SOBJS	+= flash_header.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################

board/freescale/mx35_3stack/board-mx35_3stack.h

@@ -0,0 +1,123 @@
+/*
+ *
+ * (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
+ *
+ * (C) Copyright 2008-2011 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __BOARD_MX35_3STACK_H
+#define __BOARD_MX35_3STACK_H
+
+#define UNALIGNED_ACCESS_ENABLE
+#define LOW_INT_LATENCY_ENABLE
+#define BRANCH_PREDICTION_ENABLE
+
+#define L2CC_AUX_CTL_CONFIG	0x00030024
+
+#define AIPS_MPR_CONFIG		0x77777777
+#define AIPS_PACR_CONFIG	0x00000000
+#define AIPS_PACR0_CONFIG	0x40000000
+
+/* MPR - priority is M4 > M2 > M3 > M5 > M0 > M1 */
+#define MAX_MPR_CONFIG		0x00032154
+/* SGPCR - always park on last master */
+#define MAX_SGPCR_CONFIG	0x00000010
+/* MGPCR - restore default values */
+#define MAX_MGPCR_CONFIG	0x00000001
+
+/*
+ * M3IF Control Register (M3IFCTL)
+ * MRRP[0] = L2CC0 not on priority list (0 << 0) = 0x00000000
+ * MRRP[1] = L2CC1 not on priority list (0 << 0) = 0x00000000
+ * MRRP[2] = MBX not on priority list (0 << 0)   = 0x00000000
+ * MRRP[3] = MAX1 not on priority list (0 << 0)  = 0x00000000
+ * MRRP[4] = SDMA not on priority list (0 << 0)  = 0x00000000
+ * MRRP[5] = MPEG4 not on priority list (0 << 0) = 0x00000000
+ * MRRP[6] = IPU1 on priority list (1 << 6)      = 0x00000040
+ * MRRP[7] = IPU2 not on priority list (0 << 0)  = 0x00000000
+ *                                               ------------
+ *                                                 0x00000040
+ */
+#define M3IF_CONFIG	0x000000C0
+
+#define DBG_BASE_ADDR		WEIM_CTRL_CS5
+#define DBG_CSCR_U_CONFIG	0x0000D000
+#define DBG_CSCR_L_CONFIG	0x22252521
+#define DBG_CSCR_A_CONFIG	0x22220A00
+
+#define CCM_CCMR_CONFIG		0x003F4208
+#define CCM_PDR0_CONFIG		0x00801000
+
+#define PLL_BRM_OFFSET	31
+#define PLL_PD_OFFSET	26
+#define PLL_MFD_OFFSET	16
+#define PLL_MFI_OFFSET	10
+
+#define _PLL_BRM(x)	((x) << PLL_BRM_OFFSET)
+#define _PLL_PD(x)	(((x) - 1) << PLL_PD_OFFSET)
+#define _PLL_MFD(x)	(((x) - 1) << PLL_MFD_OFFSET)
+#define _PLL_MFI(x)	((x) << PLL_MFI_OFFSET)
+#define _PLL_MFN(x)	(x)
+#define _PLL_SETTING(brm, pd, mfd, mfi, mfn) \
+	(_PLL_BRM(brm) | _PLL_PD(pd) | _PLL_MFD(mfd) | _PLL_MFI(mfi) |\
+	 _PLL_MFN(mfn))
+
+#define CCM_MPLL_532_HZ	_PLL_SETTING(1, 1, 12, 11, 1)
+#define CCM_MPLL_399_HZ _PLL_SETTING(0, 1, 16, 8, 5)
+#define CCM_PPLL_300_HZ _PLL_SETTING(0, 1, 4, 6, 1)
+
+/*MEMORY SETING*/
+/*
+ * ESDCTL constants
+ */
+#define ESDCTL_ESDCTL0_OFFSET		0x0000
+#define ESDCTL_ESDCFG0_OFFSET		0x0004
+#define ESDCTL_ESDCTL1_OFFSET		0x0008
+#define ESDCTL_ESDCFG1_OFFSET		0x000C
+#define ESDCTL_ESDMISC_OFFSET		0x0010
+#define ESDCTL_ESDDLY1_OFFSET		0x0020
+#define ESDCTL_ESDDLY2_OFFSET		0x0024
+#define ESDCTL_ESDDLY3_OFFSET		0x0028
+#define ESDCTL_ESDDLY4_OFFSET		0x002C
+#define ESDCTL_ESDDLY5_OFFSET		0x0030
+
+#define ESDCTL_0x92220000	0x92220000
+#define ESDCTL_0xA2220000	0xA2220000
+#define ESDCTL_0xB2220000	0xB2220000
+#define ESDCTL_0x82228080 	0x82228080
+#define ESDCTL_0x82226080	0x82226080
+
+#define ESDCTL_PRECHARGE	0x00000400
+
+#define ESDCTL_MDDR_CONFIG 	0x007FFC3F
+#define ESDCTL_MDDR_MR		0x00000033
+#define ESDCTL_MDDR_EMR		0x02000000
+
+#define ESDCTL_DDR2_CONFIG	0x0079542A
+#define ESDCTL_DDR2_EMR2	0x04000000
+#define ESDCTL_DDR2_EMR3	0x06000000
+#define ESDCTL_DDR2_EN_DLL	0x02000400
+#define ESDCTL_DDR2_RESET_DLL	0x00000333
+#define ESDCTL_DDR2_MR		0x00000233
+#define ESDCTL_DDR2_OCD_DEFAULT 0x02000780
+
+#define ESDCTL_DELAY_LINE5	0x00F49F00
+#endif				/* __BOARD_MX35_3STACK_H */

board/freescale/mx35_3stack/config.mk

@@ -0,0 +1,3 @@
+LDSCRIPT := $(SRCTREE)/board/$(VENDOR)/$(BOARD)/u-boot.lds
+
+TEXT_BASE = 0x87800000

board/freescale/mx35_3stack/flash_header.S

@@ -0,0 +1,130 @@
+/*
+ * Copyright (C) 2009-2011 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <asm/arch/mx35.h>
+#include "board-mx35_3stack.h"
+
+#ifdef	CONFIG_FLASH_HEADER
+#ifndef CONFIG_FLASH_HEADER_OFFSET
+# error "Must define the offset of flash header"
+#endif
+
+/* Flash header setup */
+#define DCDGEN(i,type, addr, data) \
+dcd_##i:                         ;\
+    .long type                   ;\
+    .long addr                   ;\
+    .long data
+
+#define GEN_FHEADERADDR(x) (x)
+
+.section ".text.flasheader", "x"
+	b _start
+	.org CONFIG_FLASH_HEADER_OFFSET
+app_code_jump_v:    .long GEN_FHEADERADDR(_start)
+app_code_barker:    .long CONFIG_FLASH_HEADER_BARKER
+app_code_csf:       .long 0
+hwcfg_ptr_ptr:      .long GEN_FHEADERADDR(hwcfg_ptr)
+super_root_key:     .long 0
+hwcfg_ptr:          .long GEN_FHEADERADDR(dcd_data)
+app_dest_ptr:       .long TEXT_BASE
+dcd_data:           .long 0xB17219E9
+#ifdef MEMORY_MDDR_ENABLE
+                    .long (dcd_data_end - dcd_data - 8)
+
+//WEIM config-CS5 init
+DCDGEN(1, 4, 0xB8002054, 0x444a4541)
+DCDGEN(1_1, 4, 0xB8002050, 0x0000dcf6)
+DCDGEN(1_2, 4, 0xB8002058, 0x44443302)
+//MDDR init
+//enable mDDR
+DCDGEN(2, 4, 0xB8001010, 0x00000004)
+//reset delay time
+DCDGEN(3, 4, 0xB8001010, 0x0000000C)
+DCDGEN(4, 4, 0xB800100C, 0x007ffc3f)
+DCDGEN(5, 4, 0xB800100C, 0x007ffc3f)
+DCDGEN(6, 4, 0xB8001004, 0x007ffc3f)
+DCDGEN(7, 4, 0xB8001000, 0x92220000)
+DCDGEN(8, 1, 0x80000400, 0xda)
+DCDGEN(9, 4, 0xB8001000, 0xA2220000)
+DCDGEN(10, 4, 0x80000000, 0x87654321)
+DCDGEN(11, 4, 0x80000000, 0x87654321)
+DCDGEN(12, 4, 0xB8001000, 0xB2220000)
+DCDGEN(13, 1, 0x80000033, 0xda)
+DCDGEN(14, 1, 0x82000000, 0xda)
+DCDGEN(15, 4, 0xB8001000, 0x82226080)
+DCDGEN(16, 4, 0xB8001010, 0x00000004)
+DCDGEN(17, 4, 0xB8001008, 0x00002000)
+
+#else
+                    .long (dcd_data_end - dcd_data - 8)
+
+//WEIM config-CS5 init
+DCDGEN(1, 4, 0xB8002050, 0x0000d843)
+DCDGEN(1_1, 4, 0xB8002054, 0x22252521)
+DCDGEN(1_2, 4, 0xB8002058, 0x22220a00)
+
+//DDR2 init
+DCDGEN(2, 4, 0xB8001010, 0x00000304)
+	DCDGEN(3, 4, 0xB8001004, 0x0079542A)
+	DCDGEN(4, 4, 0xB8001000, 0x92220000)
+	DCDGEN(5, 1, 0x80000400, 0x00)
+	DCDGEN(6, 4, 0xB8001000, 0xB2220000)
+	DCDGEN(7, 1, 0x84000000, 0x00)
+	DCDGEN(8, 1, 0x86000000, 0x00)
+	DCDGEN(9, 1, 0x82000400, 0x00)
+	DCDGEN(10, 1, 0x80000333, 0x00)
+	DCDGEN(11, 4, 0xB8001000, 0x92220000)
+	DCDGEN(12, 1, 0x80000400, 0x00)
+	DCDGEN(13, 4, 0xB8001000, 0xA2220000)
+	DCDGEN(14, 1, 0x80000000, 0x00)
+	DCDGEN(15, 1, 0x80000000, 0x00)
+	DCDGEN(16, 4, 0xB8001000, 0xB2220000)
+	DCDGEN(17, 1, 0x80000233, 0x00)
+	DCDGEN(18, 1, 0x82000780, 0x00)
+	DCDGEN(19, 1, 0x82000400, 0x00)
+	DCDGEN(20, 4, 0xB8001000, 0x82226080)
+#ifdef CONFIG_MX35_256M_RAM
+	DCDGEN(22, 4, 0xB800100C, 0x0079542A)
+	DCDGEN(23, 4, 0xB8001008, 0x92220000)
+	DCDGEN(24, 1, 0x90000400, 0x00)
+	DCDGEN(25, 4, 0xB8001008, 0xB2220000)
+	DCDGEN(26, 1, 0x84000000, 0x00)
+	DCDGEN(27, 1, 0x86000000, 0x00)
+	DCDGEN(28, 1, 0x82000400, 0x00)
+	DCDGEN(29, 1, 0x90000333, 0x00)
+	DCDGEN(30, 4, 0xB8001008, 0x92220000)
+	DCDGEN(31, 1, 0x82000400, 0x00)
+	DCDGEN(32, 4, 0xB8001008, 0xA2220000)
+	DCDGEN(33, 1, 0x90000000, 0x00)
+	DCDGEN(34, 1, 0x90000000, 0x00)
+	DCDGEN(35, 4, 0xB8001008, 0xB2220000)
+	DCDGEN(36, 1, 0x90000233, 0x00)
+	DCDGEN(37, 1, 0x82000780, 0x00)
+	DCDGEN(38, 1, 0x82000400, 0x00)
+	DCDGEN(39, 4, 0xB8001008, 0x82226080)
+#endif
+
+#endif
+dcd_data_end:
+
+//CARD_FLASH_CFG_PARMS_T---length
+card_cfg:           .long 0x100000
+#endif

board/freescale/mx35_3stack/lowlevel_init.S

@@ -0,0 +1,756 @@
+/*
+ * Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
+ *
+ * (C) Copyright 2008-2011 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <asm/arch/mx35.h>
+#include "board-mx35_3stack.h"
+
+/*
+ * return soc version
+ * 	0x10:  TO1
+ *	0x20:  TO2
+ *	0x30:  TO3
+ */
+.macro check_soc_version ret, tmp
+	ldr \tmp, =IIM_BASE_ADDR
+	ldr \ret, [\tmp, #IIM_SREV]
+	cmp \ret, #0x00
+	moveq \tmp, #ROMPATCH_REV
+	ldreq \ret, [\tmp]
+	moveq \ret, \ret, lsl #4
+	addne \ret, \ret, #0x10
+.endm
+
+/*
+ * L2CC Cache setup/invalidation/disable
+ */
+.macro init_l2cc
+    /* Disable L2 cache first */
+    mov r0, #L2CC_BASE_ADDR
+    ldr r1, [r0, #L2_CACHE_CTL_REG]
+    bic r1, r1, #0x1
+    str r1, [r0, #L2_CACHE_CTL_REG]
+
+    /*
+     * Configure L2 Cache:
+     * - 128k size(16k way)
+     * - 8-way associativity
+     * - 0 ws TAG/VALID/DIRTY
+     * - 4 ws DATA R/W
+     */
+    ldr r1, [r0, #L2_CACHE_AUX_CTL_REG]
+    and r1, r1, #0xFE000000
+    ldr r2, =L2CC_AUX_CTL_CONFIG
+    orr r1, r1, r2
+    str r1, [r0, #L2_CACHE_AUX_CTL_REG]
+
+    /* Workaournd for TO1 DDR issue:WT*/
+    check_soc_version r1, r2
+    cmp r1, #CHIP_REV_2_0
+    ldrlo r1, [r0, #L2_CACHE_DBG_CTL_REG]
+    orrlo r1, r1, #2
+    strlo r1, [r0, #L2_CACHE_DBG_CTL_REG]
+
+   /* Invalidate L2 */
+    mov r1, #0x000000FF
+    str r1, [r0, #L2_CACHE_INV_WAY_REG]
+1:
+    /* Poll Invalidate By Way register */
+    ldr r2, [r0, #L2_CACHE_INV_WAY_REG]
+    cmp r2, #0
+    bne 1b
+.endm /* init_l2cc */
+
+/* AIPS setup - Only setup MPROTx registers.
+ * The PACR default values are good.*/
+.macro init_aips
+	/*
+	 * Clear the on and off peripheral modules Supervisor Protect bit
+	 * for SDMA to access them. Did not change the AIPS control registers
+	 * (offset 0x20) access type
+	 */
+	ldr r0, =AIPS1_BASE_ADDR
+	ldr r1, =AIPS_PACR_CONFIG
+	str r1, [r0, #0x24]
+	str r1, [r0, #0x28]
+	str r1, [r0, #0x2C]
+	str r1, [r0, #0x40]
+	str r1, [r0, #0x44]
+	str r1, [r0, #0x48]
+	str r1, [r0, #0x4C]
+	str r1, [r0, #0x50]
+	ldr r0, =AIPS2_BASE_ADDR
+	str r1, [r0, #0x24]
+	str r1, [r0, #0x28]
+	str r1, [r0, #0x2C]
+	str r1, [r0, #0x40]
+	str r1, [r0, #0x44]
+	str r1, [r0, #0x48]
+	str r1, [r0, #0x4C]
+	str r1, [r0, #0x50]
+
+	ldr r0, =AIPS1_BASE_ADDR
+	ldr r1, =AIPS_PACR0_CONFIG
+	str r1, [r0, #0x20]
+	ldr r0, =AIPS2_BASE_ADDR
+	str r1, [r0, #0x20]
+
+	/*
+	 * Set all MPROTx to be non-bufferable, trusted for R/W,
+	 * not forced to user-mode.
+	 */
+	ldr r0, =AIPS1_BASE_ADDR
+	ldr r1, =AIPS_MPR_CONFIG
+	str r1, [r0, #0x00]
+	str r1, [r0, #0x04]
+	ldr r0, =AIPS2_BASE_ADDR
+	str r1, [r0, #0x00]
+	str r1, [r0, #0x04]
+
+.endm /* init_aips */
+
+/* MAX (Multi-Layer AHB Crossbar Switch) setup */
+.macro init_max
+	ldr r0, =MAX_BASE_ADDR
+	/* MPR - priority is M4 > M2 > M3 > M5 > M0 > M1 */
+	ldr r1, =MAX_MPR_CONFIG
+	str r1, [r0, #0x000]        /* for S0 */
+	str r1, [r0, #0x100]        /* for S1 */
+	str r1, [r0, #0x200]        /* for S2 */
+	str r1, [r0, #0x300]        /* for S3 */
+	str r1, [r0, #0x400]        /* for S4 */
+	/* SGPCR - always park on last master */
+	ldr r1, =MAX_SGPCR_CONFIG
+	str r1, [r0, #0x010]        /* for S0 */
+	str r1, [r0, #0x110]        /* for S1 */
+	str r1, [r0, #0x210]        /* for S2 */
+	str r1, [r0, #0x310]        /* for S3 */
+	str r1, [r0, #0x410]        /* for S4 */
+	/* MGPCR - restore default values */
+	ldr r1, =MAX_MGPCR_CONFIG
+	str r1, [r0, #0x800]        /* for M0 */
+	str r1, [r0, #0x900]        /* for M1 */
+	str r1, [r0, #0xA00]        /* for M2 */
+	str r1, [r0, #0xB00]        /* for M3 */
+	str r1, [r0, #0xC00]        /* for M4 */
+	str r1, [r0, #0xD00]        /* for M5 */
+.endm /* init_max */
+
+/* M3IF setup */
+.macro init_m3if
+	/* Configure M3IF registers */
+	ldr r1, =M3IF_BASE_ADDR
+	/*
+	* M3IF Control Register (M3IFCTL)
+	* MRRP[0] = L2CC0 not on priority list (0 << 0)	= 0x00000000
+	* MRRP[1] = L2CC1 not on priority list (0 << 0)	= 0x00000000
+	* MRRP[2] = MBX not on priority list (0 << 0)	= 0x00000000
+	* MRRP[3] = MAX1 not on priority list (0 << 0)	= 0x00000000
+	* MRRP[4] = SDMA not on priority list (0 << 0)	= 0x00000000
+	* MRRP[5] = MPEG4 not on priority list (0 << 0)	= 0x00000000
+	* MRRP[6] = IPU1 on priority list (1 << 6)	= 0x00000040
+	* MRRP[7] = IPU2 not on priority list (0 << 0)	= 0x00000000
+	*						------------
+	*						  0x00000040
+	*/
+	ldr r0, =M3IF_CONFIG
+	str r0, [r1]  /* M3IF control reg */
+.endm /* init_m3if */
+
+/* To support 133MHz DDR */
+.macro  init_drive_strength
+/*
+	mov r0, #0x2
+	ldr r1, =IOMUXC_BASE_ADDR
+	add r1, r1, #0x368
+        add r2, r1, #0x4C8 - 0x368
+1:      str r0, [r1], #4
+	cmp r1, r2
+        ble 1b
+*/
+.endm /* init_drive_strength */
+
+/* CPLD on CS5 setup */
+.macro init_debug_board
+	ldr r0, =DBG_BASE_ADDR
+	ldr r1, =DBG_CSCR_U_CONFIG
+	str r1, [r0, #0x00]
+	ldr r1, =DBG_CSCR_L_CONFIG
+	str r1, [r0, #0x04]
+	ldr r1, =DBG_CSCR_A_CONFIG
+	str r1, [r0, #0x08]
+.endm /* init_debug_board */
+
+/* clock setup */
+.macro init_clock
+	ldr r0, =CCM_BASE_ADDR
+
+        /* default CLKO to 1/32 of the ARM core*/
+        ldr r1, [r0, #CLKCTL_COSR]
+        bic r1, r1, #0x00000FF00
+        bic r1, r1, #0x0000000FF
+        mov r2, #0x00006C00
+        add r2, r2, #0x67
+        orr r1, r1, r2
+        str r1, [r0, #CLKCTL_COSR]
+
+        ldr r2, =CCM_CCMR_CONFIG
+        str r2, [r0, #CLKCTL_CCMR]
+
+    	check_soc_version r1, r2
+	cmp r1, #CHIP_REV_2_0
+	ldrhs r3, =CCM_MPLL_532_HZ
+	bhs 1f
+	ldr r2, [r0, #CLKCTL_PDR0]
+        tst r2, #CLKMODE_CONSUMER
+        ldrne r3, =CCM_MPLL_532_HZ  /* consumer path*/
+        ldreq r3, =CCM_MPLL_399_HZ  /* auto path*/
+1:
+	str r3, [r0, #CLKCTL_MPCTL]
+
+        ldr r1, =CCM_PPLL_300_HZ
+        str r1, [r0, #CLKCTL_PPCTL]
+
+        ldr r1, =CCM_PDR0_CONFIG
+        bic r1, r1, #0x800000
+        str r1, [r0, #CLKCTL_PDR0]
+
+        ldr r1, [r0, #CLKCTL_CGR0]
+        orr r1, r1, #0x0C300000
+        str r1, [r0, #CLKCTL_CGR0]
+
+        ldr r1, [r0, #CLKCTL_CGR1]
+        orr r1, r1, #0x00000C00
+        orr r1, r1, #0x00000003
+        str r1, [r0, #CLKCTL_CGR1]
+.endm /* init_clock */
+
+.macro setup_sdram
+        ldr r0, =ESDCTL_BASE_ADDR
+        mov r3, #0x2000
+        str r3, [r0, #0x0]
+        str r3, [r0, #0x8]
+
+	/*ip(r12) has used to save lr register in upper calling*/
+        mov fp, lr
+
+	mov r5, #0x00
+        mov r1, #CSD0_BASE_ADDR
+        bl setup_sdram_ddr2_bank
+        cmp r3, #0x0
+        orreq r5, r5, #1
+        blne setup_sdram_mddr_bank
+
+        mov lr, fp
+
+	check_soc_version r3, r4
+	cmp r1, #CHIP_REV_2_0
+	bhs 1f
+	cmp r5, #0
+        movne r3, #L2CC_BASE_ADDR
+        ldrne r4, [r3, #L2_CACHE_AUX_CTL_REG]
+        orrne r4, r4, #0x1000
+        strne r4, [r3, #L2_CACHE_AUX_CTL_REG]
+1:
+        ldr r3, =ESDCTL_DELAY_LINE5
+        str r3, [r0, #0x30]
+.endm /* setup_sdram */
+
+.section ".text.init", "x"
+
+.globl lowlevel_init
+lowlevel_init:
+	/* Platform CHIP level init*/
+#ifdef TURN_OFF_IMPRECISE_ABORT
+	mrs r0, cpsr
+	bic r0, r0, #0x100
+	msr cpsr, r0
+#endif
+
+	mrc 15, 0, r1, c1, c0, 0
+
+#ifndef BRANCH_PREDICTION_ENABLE
+	mrc 15, 0, r0, c1, c0, 1
+	bic r0, r0, #7
+	mcr 15, 0, r0, c1, c0, 1
+#else
+	mrc 15, 0, r0, c1, c0, 1
+	orr r0, r0, #7
+	mcr 15, 0, r0, c1, c0, 1
+	orr r1, r1, #(1<<11)
+#endif
+
+#ifdef UNALIGNED_ACCESS_ENABLE
+	orr r1, r1, #(1<<22)
+#endif
+
+#ifdef LOW_INT_LATENCY_ENABLE
+	orr r1, r1, #(1<<21)
+#endif
+	mcr 15, 0, r1, c1, c0, 0
+
+	mov r0, #0
+#ifdef BRANCH_PREDICTION_ENABLE
+	mcr 15, 0, r0, c15, c2, 4
+#endif
+	mcr 15, 0, r0, c7, c7, 0        /* invalidate I cache and D cache */
+	mcr 15, 0, r0, c8, c7, 0        /* invalidate TLBs */
+	mcr 15, 0, r0, c7, c10, 4       /* Drain the write buffer */
+
+	/* initializes very early AIPS, what for?
+	 * Then it also initializes Multi-Layer AHB Crossbar Switch,
+	 * M3IF */
+	/* Also setup the Peripheral Port Remap register inside the core */
+	ldr r0, =0x40000015        /* start from AIPS 2GB region */
+	mcr p15, 0, r0, c15, c2, 4
+
+	init_l2cc
+
+	init_aips
+
+	init_max
+
+	init_m3if
+
+	init_drive_strength
+
+	init_clock
+	init_debug_board
+
+	cmp pc, #PHYS_SDRAM_1
+	blo init_sdram_start
+	cmp pc, #(PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE)
+	blo skip_sdram_setup
+
+init_sdram_start:
+	/*init_sdram*/
+	setup_sdram
+skip_sdram_setup:
+	mov r0, #NFC_BASE_ADDR
+	add r1, r0, #NFC_BUF_SIZE
+	cmp pc, r0
+	movlo pc, lr
+	cmp pc, r1
+	movhi pc, lr
+	/* return from mxc_nand_load */
+	/* r12 saved upper lr*/
+	b mxc_nand_load
+
+/*
+ * r0: ESDCTL control base, r1: sdram slot base
+ * r2: DDR type(0:DDR2, 1:MDDR) r3, r4:working base
+ */
+setup_sdram_ddr2_bank:
+	/*
+	 * DDR2 initialization
+	 */
+	ldr	r0, =ESDCTL_BASE_ADDR
+
+	/* Configure for DDR2 */
+	ldr     r3, =0x30E      /* bit 9 is DDR2_EN */
+	str     r3, [r0, #ESDCTL_ESDMISC_OFFSET]
+	ldr	r3, =0x304
+	str     r3, [r0, #ESDCTL_ESDMISC_OFFSET]
+
+	/*----------------------------------------
+	 * Configure DDR2 memory on CSD0
+	 *----------------------------------------*/
+	ldr     r1, =CSD0_BASE_ADDR
+
+	/* Configure timing parameters */
+	ldr     r3, =ESDCTL_DDR2_CONFIG // Moderate
+	str     r3, [r0, #ESDCTL_ESDCFG0_OFFSET]
+
+	/*
+	 * Set precharge command
+	 *
+	 *   DSIZ - 32-bit memory width (2 << 16)            = 0x00020000
+	 *   COL - 10 column addresses (2 << 20)             = 0x00200000
+	 *   ROW - 13 Row addresses (2 << 24)                = 0x02000000
+	 *   SP - User mode access (0 << 27)                 = 0x00000000
+	 *   SMODE - Precharge command (1 << 28)             = 0x10000000
+	 *   SDE - Enable controller (1 << 31)               = 0x80000000
+	 *                                                   ------------
+	 *                                                     0x92220000
+	 */
+	ldr     r3, =ESDCTL_0x92220000
+	str     r3, [r0, #ESDCTL_ESDCTL0_OFFSET]
+
+	/* Access SDRAM with A10 high to precharge all banks */
+	ldr     r3, =0x0
+	strb    r3, [r1, #ESDCTL_PRECHARGE]
+
+	/*
+	 * Set load mode command
+	 *
+	 *   DSIZ - 32-bit memory width (2 << 16)            = 0x00020000
+	 *   COL - 10 column addresses (2 << 20)             = 0x00200000
+	 *   ROW - 13 Row addresses (2 << 24)                = 0x02000000
+	 *   SP - User mode access (0 << 27)                 = 0x00000000
+	 *   SMODE - Load mode command (3 << 28)             = 0x30000000
+	 *   SDE - Enable controller (1 << 31)               = 0x80000000
+	 *                                                   ------------
+	 *                                                     0xB2220000
+	 */
+	ldr     r3, =ESDCTL_0xB2220000
+	str     r3, [r0, #ESDCTL_ESDCTL0_OFFSET]
+
+	/* DDR2 EMR2 */
+	ldr     r3, =0x0
+	ldr     r4, =ESDCTL_DDR2_EMR2
+	strb    r3, [r1, r4]
+
+	/* DDR2 EMR3 */
+	ldr     r3, =0x0
+	ldr     r4, =ESDCTL_DDR2_EMR3
+	strb    r3, [r1, r4]
+
+	/* DDR2 EMR1: enable DLL, disable /DQS */
+	ldr     r3, =0x0
+	ldr     r4, =ESDCTL_DDR2_EN_DLL
+	strb    r3, [r1, r4]
+
+	/* DDR2 MR: reset DLL, BL=8, CL=3 */
+	ldr     r3, =0x0
+	ldr	r4, =ESDCTL_DDR2_RESET_DLL
+	strb    r3, [r1, r4]
+
+	/*
+	 * Set precharge command
+	 *
+	 *   DSIZ - 32-bit memory width (2 << 16)            = 0x00020000
+	 *   COL - 10 column addresses (2 << 20)             = 0x00200000
+	 *   ROW - 13 Row addresses (2 << 24)                = 0x02000000
+	 *   SP - User mode access (0 << 27)                 = 0x00000000
+	 *   SMODE - Precharge command (1 << 28)             = 0x10000000
+	 *   SDE - Enable controller (1 << 31)               = 0x80000000
+	 *                                                   ------------
+	 *                                                     0x92220000
+	 */
+	ldr     r3, =ESDCTL_0x92220000
+	str     r3, [r0, #ESDCTL_ESDCTL0_OFFSET]
+
+	/* Access SDRAM with A10 high to precharge all banks */
+	ldr     r3, =0x0
+	ldr	r4, =ESDCTL_DDR2_EN_DLL
+	strb    r3, [r1, r4]
+
+	/*
+	 * Set autorefresh command
+	 *
+	 *   DSIZ - 32-bit memory width (2 << 16)            = 0x00020000
+	 *   COL - 10 column addresses (2 << 20)             = 0x00200000
+	 *   ROW - 13 Row addresses (2 << 24)                = 0x02000000
+	 *   SP - User mode access (0 << 27)                 = 0x00000000
+	 *   SMODE - Autorefresh command (2 << 28)           = 0x20000000
+	 *   SDE - Enable controller (1 << 31)               = 0x80000000
+	 *                                                   ------------
+	 *                                                     0xA2220000
+	 */
+	ldr     r3, =ESDCTL_0xA2220000
+	str     r3, [r1, #ESDCTL_ESDCTL0_OFFSET]
+
+	/* Use writes to refresh all banks of SDRAM */
+	ldr     r3, =0x0
+	strb    r3, [r1]
+	strb    r3, [r1]
+
+	/*
+	 * Set load mode command
+	 *
+	 *   DSIZ - 32-bit memory width (2 << 16)            = 0x00020000
+	 *   COL - 10 column addresses (2 << 20)             = 0x00200000
+	 *   ROW - 13 Row addresses (2 << 24)                = 0x02000000
+	 *   SP - User mode access (0 << 27)                 = 0x00000000
+	 *   SMODE - Load mode command (3 << 28)             = 0x30000000
+	 *   SDE - Enable controller (1 << 31)               = 0x80000000
+	 *                                                   ------------
+	 *                                                     0xB2220000
+	 */
+	ldr     r3, =ESDCTL_0xB2220000
+	str     r3, [r0, #ESDCTL_ESDCTL0_OFFSET]
+
+	/* DDR2 MR: end DLL reset, BL=8, CL=3 */
+	ldr     r3, =0x0
+	strb    r3, [r1, #ESDCTL_DDR2_MR]
+
+	/* Hold for more than 200 cycles */
+	ldr     r3, =0x100
+hold_1:
+	subs    r3, r3, #1
+	bne     hold_1
+
+	/* DDR2 EMR1: OCD calibration default */
+	ldr     r3, =0x0
+	ldr     r4, =ESDCTL_DDR2_OCD_DEFAULT
+	strb    r3, [r1, r4]
+
+	/* DDR2 EMR1: OCD calibration exit, enable DLL, disable /DQS */
+	ldr     r3, =0x0
+	ldr     r4, =ESDCTL_DDR2_EN_DLL
+	strb    r3, [r1, r4]
+
+	/*
+	 * Set normal mode command
+	 *
+	 *   PRCT - Precharge timer disabled (0 << 5)        = 0x00000000
+	 *   BL - Burst of 8 for SDR/DDR (1 << 7)            = 0x00000080
+	 *   FP - No full page mode (0 << 8)                 = 0x00000000
+	 *   PWDT - Power down timeout disabled (3 << 10)    = 0x00000000
+	 *   SREFR - 4 rows refreshed each clock (3 << 13)   = 0x00006000
+	 *   DSIZ - 32-bit memory width (2 << 16)            = 0x00020000
+	 *   COL - 10 column addresses (2 << 20)             = 0x00200000
+	 *   ROW - 13 Row addresses (2 << 24)                = 0x02000000
+	 *   SP - User mode access (0 << 27)                 = 0x00000000
+	 *   SMODE - Normal mode command (0 << 28)           = 0x00000000
+	 *   SDE - Enable controller (1 << 31)               = 0x80000000
+	 *                                                   ------------
+	 *                                                     0x82226080
+	 */
+	ldr     r3, =ESDCTL_0x82226080
+	str     r3, [r0, #ESDCTL_ESDCTL0_OFFSET]
+
+#ifdef CONFIG_MX35_256M_RAM
+	/*----------------------------------------
+	 * Configure DDR2 memory on CSD1
+	 *----------------------------------------*/
+	ldr     r1, =CSD1_BASE_ADDR
+	/* Configure timing parameters */
+	ldr     r3, =ESDCTL_DDR2_CONFIG /* Moderate */
+	str     r3, [r0, #ESDCTL_ESDCFG1_OFFSET]
+
+	/*
+	 * Set precharge command
+	 *
+	 *   DSIZ - 32-bit memory width (2 << 16)            = 0x00020000
+	 *   COL - 10 column addresses (2 << 20)             = 0x00200000
+	 *   ROW - 13 Row addresses (2 << 24)                = 0x02000000
+	 *   SP - User mode access (0 << 27)                 = 0x00000000
+	 *   SMODE - Precharge command (1 << 28)             = 0x10000000
+	 *   SDE - Enable controller (1 << 31)               = 0x80000000
+	 *                                                   ------------
+	 *                                                     0x92220000
+	 */
+	ldr     r3, =ESDCTL_0x92220000
+	str     r3, [r0, #ESDCTL_ESDCTL1_OFFSET]
+
+	/* Access SDRAM with A10 high to precharge all banks */
+	ldr     r3, =0x0
+	ldr	r4, =ESDCTL_DDR2_EN_DLL
+	strb    r3, [r1, r4]
+
+	/*
+	 * Set load mode command
+	 *
+	 *   DSIZ - 32-bit memory width (2 << 16)            = 0x00020000
+	 *   COL - 10 column addresses (2 << 20)             = 0x00200000
+	 *   ROW - 13 Row addresses (2 << 24)                = 0x02000000
+	 *   SP - User mode access (0 << 27)                 = 0x00000000
+	 *   SMODE - Load mode command (3 << 28)             = 0x30000000
+	 *   SDE - Enable controller (1 << 31)               = 0x80000000
+	 *                                                   ------------
+	 *                                                     0xB2220000
+	 */
+	ldr     r3, =ESDCTL_0xB2220000
+	str     r3, [r0, #ESDCTL_ESDCTL1_OFFSET]
+
+	/* DDR2 EMR2 */
+	ldr     r3, =0x0
+	ldr     r4, =ESDCTL_DDR2_EMR2
+	strb    r3, [r1, r4]
+
+	/* DDR2 EMR3 */
+	ldr     r3, =0x0
+	ldr     r4, =ESDCTL_DDR2_EMR3
+	strb    r3, [r1, r4]
+
+	/* DDR2 EMR1: enable DLL, disable /DQS */
+	ldr     r3, =0x0
+	ldr     r4, =ESDCTL_DDR2_EN_DLL
+	strb    r3, [r1, r4]
+
+	/* DDR2 MR: reset DLL, BL=8, CL=3 */
+	ldr     r3, =0x0
+	strb    r3, [r1, #ESDCTL_DDR2_RESET_DLL]
+
+	/*
+	 * Set precharge command
+	 *
+	 *   DSIZ - 32-bit memory width (2 << 16)            = 0x00020000
+	 *   COL - 10 column addresses (2 << 20)             = 0x00200000
+	 *   ROW - 13 Row addresses (2 << 24)                = 0x02000000
+	 *   SP - User mode access (0 << 27)                 = 0x00000000
+	 *   SMODE - Precharge command (1 << 28)             = 0x10000000
+	 *   SDE - Enable controller (1 << 31)               = 0x80000000
+	 *                                                   ------------
+	 *                                                     0x92220000
+	 */
+	ldr     r3, =ESDCTL_0x92220000
+	str     r3, [r0, #ESDCTL_ESDCTL1_OFFSET]
+
+	/* Access SDRAM with A10 high to precharge all banks */
+	ldr     r3, =0x0
+	strb    r3, [r1, #ESDCTL_PRECHARGE]
+
+	/*
+	 * Set autorefresh command
+	 *
+	 *   DSIZ - 32-bit memory width (2 << 16)            = 0x00020000
+	 *   COL - 10 column addresses (2 << 20)             = 0x00200000
+	 *   ROW - 13 Row addresses (2 << 24)                = 0x02000000
+	 *   SP - User mode access (0 << 27)                 = 0x00000000
+	 *   SMODE - Autorefresh command (2 << 28)           = 0x20000000
+	 *   SDE - Enable controller (1 << 31)               = 0x80000000
+	 *                                                   ------------
+	 *                                                     0xA2220000
+	 */
+	ldr     r3, =ESDCTL_0xA2220000
+	str     r3, [r0, #ESDCTL_ESDCTL1_OFFSET]
+
+	/* Use writes to refresh all banks of SDRAM */
+	ldr     r3, =0x0
+	strb    r3, [r1]
+	strb    r3, [r1]
+
+	/*
+	 * Set load mode command
+	 *
+	 *   DSIZ - 32-bit memory width (2 << 16)            = 0x00020000
+	 *   COL - 10 column addresses (2 << 20)             = 0x00200000
+	 *   ROW - 13 Row addresses (2 << 24)                = 0x02000000
+	 *   SP - User mode access (0 << 27)                 = 0x00000000
+	 *   SMODE - Load mode command (3 << 28)             = 0x30000000
+	 *   SDE - Enable controller (1 << 31)               = 0x80000000
+	 *                                                   ------------
+	 *                                                     0xB2220000
+	 *
+	 */
+	ldr     r3, =ESDCTL_0xB2220000
+	str     r3, [r0, #ESDCTL_ESDCTL1_OFFSET]
+
+	/* DDR2 MR: end DLL reset, BL=8, CL=3 */
+	ldr     r3, =0x0
+	strb    r3, [r1, #ESDCTL_DDR2_MR]
+
+	/* Hold for more than 200 cycles */
+	ldr     r3, =0x100
+hold1:
+	subs    r3, r3, #1
+	bne     hold1
+
+	/* DDR2 EMR1: OCD calibration default */
+	ldr     r3, =0x0
+	ldr     r4, =ESDCTL_DDR2_OCD_DEFAULT
+	strb    r3, [r1, r4]
+
+	/* DDR2 EMR1: OCD calibration exit, enable DLL, disable /DQS */
+	ldr     r3, =0x0
+	ldr     r4, =ESDCTL_DDR2_EN_DLL
+	strb    r3, [r1, r4]
+
+	/*
+	 * Set normal mode command
+	 *
+	 *   PRCT - Precharge timer disabled (0 << 5)        = 0x00000000
+	 *   BL - Burst of 8 for SDR/DDR (1 << 7)            = 0x00000080
+	 *   FP - No full page mode (0 << 8)                 = 0x00000000
+	 *   PWDT - Power down timeout disabled (3 << 10)    = 0x00000000
+	 *   SREFR - 4 rows refreshed each clock (3 << 13)   = 0x00006000
+	 *   DSIZ - 32-bit memory width (2 << 16)            = 0x00020000
+	 *   COL - 10 column addresses (2 << 20)             = 0x00200000
+	 *   ROW - 13 Row addresses (2 << 24)                = 0x02000000
+	 *   SP - User mode access (0 << 27)                 = 0x00000000
+	 *   SMODE - Normal mode command (0 << 28)           = 0x00000000
+	 *   SDE - Enable controller (1 << 31)               = 0x80000000
+	 *                                                   ------------
+	 *                                                     0x82226080
+	 */
+	ldr     r3, =ESDCTL_0x82226080
+	str     r3, [r0, #ESDCTL_ESDCTL1_OFFSET]
+#endif
+
+	str r3, [r1, #0x100]
+	ldr r4, [r1, #0x100]
+	cmp r3, r4
+	movne r3, #1
+	moveq r3, #0
+
+	mov pc, lr
+
+/*
+ * r0: ESDCTL control base, r1: sdram slot base
+ * r2: DDR type(0:DDR2, 1:MDDR) r3, r4:working base
+ */
+setup_sdram_mddr_bank:
+        mov r3, #0xE /*0xA + 0x4*/
+        str r3, [r0, #0x10]
+        bic r3, r3, #0x00A
+        str r3, [r0, #0x10]
+
+        mov r3, #0x20000
+1:
+	subs r3, r3, #1
+        bne 1b
+
+2:
+        ldr r3, =ESDCTL_MDDR_CONFIG
+        cmp r1, #CSD1_BASE_ADDR
+        strlo r3, [r0, #0x4]
+        strhs r3, [r0, #0xC]
+
+        ldr r3, =ESDCTL_0x92220000
+        strlo r3, [r0, #0x0]
+        strhs r3, [r0, #0x8]
+        mov r3, #0xDA
+        ldr r4, =ESDCTL_PRECHARGE
+        strb r3, [r1, r4]
+
+        ldr r3, =ESDCTL_0xA2220000
+        strlo r3, [r0, #0x0]
+        strhs r3, [r0, #0x8]
+        mov r3, #0xDA
+        strb r3, [r1]
+        strb r3, [r1]
+
+        ldr r3, =ESDCTL_0xB2220000
+        strlo r3, [r0, #0x0]
+        strhs r3, [r0, #0x8]
+        ldr r4, =ESDCTL_MDDR_MR
+       	mov r3, #0xDA
+        strb r3, [r1, r4]
+        ldr r4, =ESDCTL_MDDR_EMR
+        strb r3, [r1, r4]
+
+        ldr r3, =ESDCTL_0x82226080
+        strlo r3, [r0, #0x0]
+        strhs r3, [r0, #0x8]
+
+        mov r4, #0x200
+1:      subs r4, r4, #1
+        bne 1b
+
+       	str r3, [r1, #0x100]
+        ldr r4, [r1, #0x100]
+        cmp r3, r4
+        movne r3, #1
+        moveq r3, #0
+
+        mov pc, lr

board/freescale/mx35_3stack/mx35_3stack.c

@@ -0,0 +1,467 @@
+/*
+ * Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
+ *
+ * Copyright (C) 2008-2011 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/errno.h>
+#include <asm/arch/mx35.h>
+#include <asm/arch/mx35_pins.h>
+#include <asm/arch/iomux.h>
+#include <i2c.h>
+#include <linux/types.h>
+
+#ifdef CONFIG_CMD_MMC
+#include <mmc.h>
+#include <fsl_esdhc.h>
+#endif
+
+#ifdef CONFIG_ARCH_MMU
+#include <asm/mmu.h>
+#include <asm/arch/mmu.h>
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static u32 system_rev;
+
+u32 get_board_rev(void)
+{
+	return system_rev;
+}
+
+static inline void setup_soc_rev(void)
+{
+	int reg;
+	reg = __REG(IIM_BASE_ADDR + IIM_SREV);
+	if (!reg) {
+		reg = __REG(ROMPATCH_REV);
+		reg <<= 4;
+	} else
+		reg += CHIP_REV_1_0;
+	system_rev = 0x35000 + (reg & 0xFF);
+}
+
+static inline void set_board_rev(int rev)
+{
+	system_rev =  (system_rev & ~(0xF << 8)) | (rev & 0xF) << 8;
+}
+
+int is_soc_rev(int rev)
+{
+	return (system_rev & 0xFF) - rev;
+}
+
+#ifdef CONFIG_ARCH_MMU
+void board_mmu_init(void)
+{
+	unsigned long ttb_base = PHYS_SDRAM_1 + 0x4000;
+	unsigned long i;
+
+	/*
+	 * Set the TTB register
+	 */
+	asm volatile ("mcr  p15,0,%0,c2,c0,0" : : "r"(ttb_base) /*:*/);
+
+	/*
+	 * Set the Domain Access Control Register
+	 */
+	i = ARM_ACCESS_DACR_DEFAULT;
+	asm volatile ("mcr  p15,0,%0,c3,c0,0" : : "r"(i) /*:*/);
+
+	/*
+	 * First clear all TT entries - ie Set them to Faulting
+	 */
+	memset((void *)ttb_base, 0, ARM_FIRST_LEVEL_PAGE_TABLE_SIZE);
+	/* Actual   Virtual  Size   Attributes   	Function */
+	/* Base     Base     MB     cached? buffered?  access permissions */
+	/* xxx00000 xxx00000 */
+	X_ARM_MMU_SECTION(0x000, 0xF00, 0x1,
+			  ARM_UNCACHEABLE, ARM_UNBUFFERABLE,
+			  ARM_ACCESS_PERM_RW_RW); /* ROM */
+	X_ARM_MMU_SECTION(0x100, 0x100, 0x1,
+			  ARM_UNCACHEABLE, ARM_UNBUFFERABLE,
+			  ARM_ACCESS_PERM_RW_RW); /* iRAM */
+	X_ARM_MMU_SECTION(0x300, 0x300, 0x1,
+			  ARM_UNCACHEABLE, ARM_UNBUFFERABLE,
+			  ARM_ACCESS_PERM_RW_RW); /* L2CC */
+	/* Internal Regsisters upto SDRAM*/
+	X_ARM_MMU_SECTION(0x400, 0x400, 0x400,
+			  ARM_UNCACHEABLE, ARM_UNBUFFERABLE,
+			  ARM_ACCESS_PERM_RW_RW);
+	X_ARM_MMU_SECTION(0x800, 0x000, 0x80,
+			  ARM_CACHEABLE, ARM_BUFFERABLE,
+			  ARM_ACCESS_PERM_RW_RW); /* SDRAM 0:128M*/
+	X_ARM_MMU_SECTION(0x800, 0x800, 0x80,
+			  ARM_CACHEABLE, ARM_BUFFERABLE,
+			  ARM_ACCESS_PERM_RW_RW); /* SDRAM 0:128M*/
+	X_ARM_MMU_SECTION(0x800, 0x880, 0x80,
+			  ARM_UNCACHEABLE, ARM_UNBUFFERABLE,
+			  ARM_ACCESS_PERM_RW_RW); /* SDRAM 0:128M*/
+	X_ARM_MMU_SECTION(0x900, 0x900, 0x80,
+			  ARM_CACHEABLE, ARM_BUFFERABLE,
+			  ARM_ACCESS_PERM_RW_RW); /* SDRAM 1:128M*/
+	X_ARM_MMU_SECTION(0x900, 0x980, 0x80,
+			  ARM_UNCACHEABLE, ARM_UNBUFFERABLE,
+			  ARM_ACCESS_PERM_RW_RW); /* SDRAM 1:128M*/
+	X_ARM_MMU_SECTION(0xA00, 0xA00, 0x40,
+			  ARM_CACHEABLE, ARM_BUFFERABLE,
+			  ARM_ACCESS_PERM_RW_RW); /* Flash */
+	X_ARM_MMU_SECTION(0xB00, 0xB00, 0x20,
+			  ARM_CACHEABLE, ARM_BUFFERABLE,
+			  ARM_ACCESS_PERM_RW_RW); /* PSRAM */
+	/* ESDCTL, WEIM, M3IF, EMI, NFC, External I/O */
+	X_ARM_MMU_SECTION(0xB20, 0xB20, 0x1E0,
+			  ARM_UNCACHEABLE, ARM_UNBUFFERABLE,
+			  ARM_ACCESS_PERM_RW_RW);
+
+	/* Enable MMU */
+	MMU_ON();
+}
+#endif
+
+int dram_init(void)
+{
+	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+#ifdef CONFIG_MX35_256M_RAM
+	gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
+	gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
+#endif
+
+	return 0;
+}
+
+int board_init(void)
+{
+	int pad;
+
+#ifdef CONFIG_MFG
+/* MFG firmware need reset usb to avoid host crash firstly */
+#define USBCMD 0x53FF4140
+	int val = readl(USBCMD);
+	val &= ~0x1; /*RS bit*/
+	writel(val, USBCMD);
+#endif
+
+	setup_soc_rev();
+
+	/* enable clocks */
+	__REG(CCM_BASE_ADDR + CLKCTL_CGR0) |= 0x003F0000;
+	__REG(CCM_BASE_ADDR + CLKCTL_CGR1) |= 0x00030FFF;
+
+	/* setup pins for I2C1 */
+	mxc_request_iomux(MX35_PIN_I2C1_CLK, MUX_CONFIG_SION);
+	mxc_request_iomux(MX35_PIN_I2C1_DAT, MUX_CONFIG_SION);
+
+	pad = (PAD_CTL_HYS_SCHMITZ | PAD_CTL_PKE_ENABLE \
+			| PAD_CTL_PUE_PUD | PAD_CTL_ODE_OpenDrain);
+
+	mxc_iomux_set_pad(MX35_PIN_I2C1_CLK, pad);
+	mxc_iomux_set_pad(MX35_PIN_I2C1_DAT, pad);
+
+	/* setup pins for FEC */
+	mxc_request_iomux(MX35_PIN_FEC_TX_CLK, MUX_CONFIG_FUNC);
+	mxc_request_iomux(MX35_PIN_FEC_RX_CLK, MUX_CONFIG_FUNC);
+	mxc_request_iomux(MX35_PIN_FEC_RX_DV, MUX_CONFIG_FUNC);
+	mxc_request_iomux(MX35_PIN_FEC_COL, MUX_CONFIG_FUNC);
+	mxc_request_iomux(MX35_PIN_FEC_RDATA0, MUX_CONFIG_FUNC);
+	mxc_request_iomux(MX35_PIN_FEC_TDATA0, MUX_CONFIG_FUNC);
+	mxc_request_iomux(MX35_PIN_FEC_TX_EN, MUX_CONFIG_FUNC);
+	mxc_request_iomux(MX35_PIN_FEC_MDC, MUX_CONFIG_FUNC);
+	mxc_request_iomux(MX35_PIN_FEC_MDIO, MUX_CONFIG_FUNC);
+	mxc_request_iomux(MX35_PIN_FEC_TX_ERR, MUX_CONFIG_FUNC);
+	mxc_request_iomux(MX35_PIN_FEC_RX_ERR, MUX_CONFIG_FUNC);
+	mxc_request_iomux(MX35_PIN_FEC_CRS, MUX_CONFIG_FUNC);
+	mxc_request_iomux(MX35_PIN_FEC_RDATA1, MUX_CONFIG_FUNC);
+	mxc_request_iomux(MX35_PIN_FEC_TDATA1, MUX_CONFIG_FUNC);
+	mxc_request_iomux(MX35_PIN_FEC_RDATA2, MUX_CONFIG_FUNC);
+	mxc_request_iomux(MX35_PIN_FEC_TDATA2, MUX_CONFIG_FUNC);
+	mxc_request_iomux(MX35_PIN_FEC_RDATA3, MUX_CONFIG_FUNC);
+	mxc_request_iomux(MX35_PIN_FEC_TDATA3, MUX_CONFIG_FUNC);
+
+	pad = (PAD_CTL_DRV_3_3V | PAD_CTL_PUE_PUD | PAD_CTL_ODE_CMOS | \
+			PAD_CTL_DRV_NORMAL | PAD_CTL_SRE_SLOW);
+
+	mxc_iomux_set_pad(MX35_PIN_FEC_TX_CLK, pad | PAD_CTL_HYS_SCHMITZ | \
+			PAD_CTL_PKE_ENABLE | PAD_CTL_100K_PD);
+	mxc_iomux_set_pad(MX35_PIN_FEC_RX_CLK, pad | PAD_CTL_HYS_SCHMITZ | \
+			PAD_CTL_PKE_ENABLE | PAD_CTL_100K_PD);
+	mxc_iomux_set_pad(MX35_PIN_FEC_RX_DV, pad | PAD_CTL_HYS_SCHMITZ | \
+			 PAD_CTL_PKE_ENABLE | PAD_CTL_100K_PD);
+	mxc_iomux_set_pad(MX35_PIN_FEC_COL, pad | PAD_CTL_HYS_SCHMITZ | \
+			  PAD_CTL_PKE_ENABLE | PAD_CTL_100K_PD);
+	mxc_iomux_set_pad(MX35_PIN_FEC_RDATA0, pad | PAD_CTL_HYS_SCHMITZ | \
+			  PAD_CTL_PKE_ENABLE | PAD_CTL_100K_PD);
+	mxc_iomux_set_pad(MX35_PIN_FEC_TDATA0, pad | PAD_CTL_HYS_CMOS | \
+			  PAD_CTL_PKE_NONE | PAD_CTL_100K_PD);
+	mxc_iomux_set_pad(MX35_PIN_FEC_TX_EN, pad | PAD_CTL_HYS_CMOS | \
+			  PAD_CTL_PKE_NONE | PAD_CTL_100K_PD);
+	mxc_iomux_set_pad(MX35_PIN_FEC_MDC, pad | PAD_CTL_HYS_CMOS | \
+			  PAD_CTL_PKE_NONE | PAD_CTL_100K_PD);
+	mxc_iomux_set_pad(MX35_PIN_FEC_MDIO, pad | PAD_CTL_HYS_SCHMITZ | \
+			  PAD_CTL_PKE_ENABLE | PAD_CTL_22K_PU);
+	mxc_iomux_set_pad(MX35_PIN_FEC_TX_ERR, pad | PAD_CTL_HYS_CMOS | \
+			  PAD_CTL_PKE_NONE | PAD_CTL_100K_PD);
+	mxc_iomux_set_pad(MX35_PIN_FEC_RX_ERR, pad | PAD_CTL_HYS_SCHMITZ | \
+			  PAD_CTL_PKE_ENABLE | PAD_CTL_100K_PD);
+	mxc_iomux_set_pad(MX35_PIN_FEC_CRS, pad | PAD_CTL_HYS_SCHMITZ | \
+			  PAD_CTL_PKE_ENABLE | PAD_CTL_100K_PD);
+	mxc_iomux_set_pad(MX35_PIN_FEC_RDATA1, pad | PAD_CTL_HYS_SCHMITZ | \
+			  PAD_CTL_PKE_ENABLE | PAD_CTL_100K_PD);
+	mxc_iomux_set_pad(MX35_PIN_FEC_TDATA1, pad | PAD_CTL_HYS_CMOS | \
+			  PAD_CTL_PKE_NONE | PAD_CTL_100K_PD);
+	mxc_iomux_set_pad(MX35_PIN_FEC_RDATA2, pad | PAD_CTL_HYS_SCHMITZ | \
+			  PAD_CTL_PKE_ENABLE | PAD_CTL_100K_PD);
+	mxc_iomux_set_pad(MX35_PIN_FEC_TDATA2, pad | PAD_CTL_HYS_CMOS | \
+			  PAD_CTL_PKE_NONE | PAD_CTL_100K_PD);
+	mxc_iomux_set_pad(MX35_PIN_FEC_RDATA3, pad | PAD_CTL_HYS_SCHMITZ | \
+			  PAD_CTL_PKE_ENABLE | PAD_CTL_100K_PD);
+	mxc_iomux_set_pad(MX35_PIN_FEC_TDATA3, pad | PAD_CTL_HYS_CMOS | \
+			  PAD_CTL_PKE_NONE | PAD_CTL_100K_PD);
+
+	gd->bd->bi_arch_number = MACH_TYPE_MX35_3DS;	/* board id for linux */
+	gd->bd->bi_boot_params = 0x80000100;	/* address of boot parameters */
+
+	return 0;
+}
+
+#ifdef BOARD_LATE_INIT
+static inline int board_detect(void)
+{
+	u8 buf[4];
+	int id;
+
+	if (i2c_read(0x08, 0x7, 1, buf, 3) < 0) {
+		printf("board_late_init: read PMIC@0x08:0x7 fail\n");
+		return 0;
+	}
+	id = (buf[0] << 16) + (buf[1] << 8) + buf[2];
+	printf("PMIC@0x08:0x7 is %x\n", id);
+	id = (id >> 6) & 0x7;
+	if (id == 0x7) {
+		set_board_rev(1);
+		return 1;
+	}
+	set_board_rev(0);
+	return 0;
+}
+
+int board_late_init(void)
+{
+	u8 reg[3];
+	int i;
+
+	if (board_detect()) {
+		mxc_request_iomux(MX35_PIN_WATCHDOG_RST, MUX_CONFIG_SION |
+					MUX_CONFIG_ALT1);
+		printf("i.MX35 CPU board version 2.0\n");
+		if (i2c_read(0x08, 0x1E, 1, reg, 3)) {
+			printf("board_late_init: read PMIC@0x08:0x1E fail\n");
+			return 0;
+		}
+		reg[2] |= 0x3;
+		if (i2c_write(0x08, 0x1E, 1, reg, 3)) {
+			printf("board_late_init: write PMIC@0x08:0x1E fail\n");
+			return 0;
+		}
+		if (i2c_read(0x08, 0x20, 1, reg, 3)) {
+			printf("board_late_init: read PMIC@0x08:0x20 fail\n");
+			return 0;
+		}
+		reg[2] |= 0x1;
+		if (i2c_write(0x08, 0x20, 1, reg, 3)) {
+			printf("board_late_init: write PMIC@0x08:0x20 fail\n");
+			return 0;
+		}
+		mxc_request_iomux(MX35_PIN_COMPARE, MUX_CONFIG_GPIO);
+		mxc_iomux_set_input(MUX_IN_GPIO1_IN_5, INPUT_CTL_PATH0);
+		__REG(GPIO1_BASE_ADDR + 0x04) |= 1 << 5;
+		__REG(GPIO1_BASE_ADDR) |= 1 << 5;
+	} else
+		printf("i.MX35 CPU board version 1.0\n");
+
+	if (i2c_read(0x69, 0x20, 1, reg, 1) < 0) {
+		printf("board_late_init: read PMIC@0x69:0x20 fail\n");
+		return 0;
+	}
+
+	reg[0] |= 0x4;
+	if (i2c_write(0x69, 0x20, 1, reg, 1) < 0) {
+		printf("board_late_init: write back PMIC@0x69:0x20 fail\n");
+		return 0;
+	}
+
+	for (i = 0; i < 1000; i++)
+		udelay(200);
+
+	if (i2c_read(0x69, 0x1A, 1, reg, 1) < 0) {
+		printf("board_late_init: read PMIC@0x69:0x1A fail\n");
+		return 0;
+	}
+
+	reg[0] &= 0x7F;
+	if (i2c_write(0x69, 0x1A, 1, reg, 1) < 0) {
+		printf("board_late_init: write back PMIC@0x69:0x1A fail\n");
+		return 0;
+	}
+	for (i = 0; i < 1000; i++)
+		udelay(200);
+
+	reg[0] |= 0x80;
+	if (i2c_write(0x69, 0x1A, 1, reg, 1) < 0) {
+		printf("board_late_init: 2st write back PMIC@0x69:0x1A fail\n");
+		return 0;
+	}
+
+	return 0;
+}
+#endif
+
+int checkboard(void)
+{
+	printf("Board: MX35 3STACK ");
+
+	if (system_rev & CHIP_REV_2_0)
+		printf("2.0 [");
+	else
+		printf("1.0 [");
+
+	switch (__REG(CCM_BASE_ADDR + CLKCTL_RCSR) & 0x0F) {
+	case 0x0000:
+		printf("POR");
+		break;
+	case 0x0002:
+		printf("JTAG");
+		break;
+	case 0x0004:
+		printf("RST");
+		break;
+	case 0x0008:
+		printf("WDT");
+		break;
+	default:
+		printf("unknown");
+	}
+	printf("]\n");
+	return 0;
+}
+
+#if defined(CONFIG_SMC911X)
+extern int smc911x_initialize(u8 dev_num, int base_addr);
+#endif
+
+int board_eth_init(bd_t *bis)
+{
+	int rc = -ENODEV;
+#if defined(CONFIG_SMC911X)
+	rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);
+#endif
+
+	cpu_eth_init(bis);
+
+	return rc;
+}
+
+#ifdef CONFIG_CMD_MMC
+
+struct fsl_esdhc_cfg esdhc_cfg[2] = {
+	{MMC_SDHC1_BASE_ADDR, 1, 1},
+	{MMC_SDHC2_BASE_ADDR, 1, 1},
+};
+
+int esdhc_gpio_init(bd_t *bis)
+{
+	u32 pad_val = 0, index = 0;
+	s32 status = 0;
+
+	/* IOMUX PROGRAMMING */
+	for (index = 0; index < CONFIG_SYS_FSL_ESDHC_NUM;
+		++index) {
+		switch (index) {
+		case 0:
+			pad_val = PAD_CTL_PUE_PUD | PAD_CTL_PKE_ENABLE |
+				PAD_CTL_HYS_SCHMITZ | PAD_CTL_DRV_HIGH |
+				PAD_CTL_100K_PD | PAD_CTL_SRE_FAST;
+			mxc_request_iomux(MX35_PIN_SD1_CMD,
+				MUX_CONFIG_FUNC | MUX_CONFIG_SION);
+			mxc_iomux_set_pad(MX35_PIN_SD1_CMD, pad_val);
+
+			pad_val = PAD_CTL_PUE_PUD | PAD_CTL_PKE_ENABLE |
+					PAD_CTL_HYS_SCHMITZ | PAD_CTL_DRV_HIGH |
+					PAD_CTL_100K_PU | PAD_CTL_SRE_FAST;
+			mxc_request_iomux(MX35_PIN_SD1_CLK,
+					MUX_CONFIG_FUNC | MUX_CONFIG_SION);
+			mxc_iomux_set_pad(MX35_PIN_SD1_CLK, pad_val);
+			mxc_request_iomux(MX35_PIN_SD1_DATA0,
+					MUX_CONFIG_FUNC);
+			mxc_iomux_set_pad(MX35_PIN_SD1_DATA0, pad_val);
+			mxc_request_iomux(MX35_PIN_SD1_DATA3,
+					MUX_CONFIG_FUNC);
+			mxc_iomux_set_pad(MX35_PIN_SD1_DATA3, pad_val);
+
+			break;
+		case 1:
+			mxc_request_iomux(MX35_PIN_SD2_CLK,
+					MUX_CONFIG_FUNC | MUX_CONFIG_SION);
+			mxc_request_iomux(MX35_PIN_SD2_CMD,
+					MUX_CONFIG_FUNC | MUX_CONFIG_SION);
+			mxc_request_iomux(MX35_PIN_SD2_DATA0,
+					MUX_CONFIG_FUNC);
+			mxc_request_iomux(MX35_PIN_SD2_DATA3,
+					MUX_CONFIG_FUNC);
+
+			pad_val = PAD_CTL_PUE_PUD | PAD_CTL_PKE_ENABLE |
+					PAD_CTL_HYS_SCHMITZ | PAD_CTL_DRV_MAX |
+					PAD_CTL_100K_PD | PAD_CTL_SRE_FAST;
+			mxc_iomux_set_pad(MX35_PIN_SD2_CMD, pad_val);
+
+			pad_val = PAD_CTL_PUE_PUD | PAD_CTL_PKE_ENABLE |
+					PAD_CTL_HYS_SCHMITZ | PAD_CTL_DRV_HIGH |
+					PAD_CTL_100K_PU | PAD_CTL_SRE_FAST;
+			mxc_iomux_set_pad(MX35_PIN_SD2_CLK, pad_val);
+			mxc_iomux_set_pad(MX35_PIN_SD2_DATA0, pad_val);
+			mxc_iomux_set_pad(MX35_PIN_SD2_DATA3, pad_val);
+
+			break;
+		default:
+			printf("Warning: you configured more ESDHC controller"
+				"(%d) as supported by the board(2)\n",
+				CONFIG_SYS_FSL_ESDHC_NUM);
+			return status;
+			break;
+		}
+		status |= fsl_esdhc_initialize(bis, &esdhc_cfg[index]);
+	}
+
+	return status;
+}
+
+int board_mmc_init(bd_t *bis)
+{
+	if (!esdhc_gpio_init(bis))
+		return 0;
+	else
+		return -1;
+}
+#endif

board/freescale/mx35_3stack/u-boot.lds

@@ -0,0 +1,77 @@
+/*
+ * January 2004 - Changed to support H4 device
+ * Copyright (c) 2004 Texas Instruments
+ *
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
+ *
+ * (C) Copyright 2008-2009 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+	. = 0x00000000;
+
+	. = ALIGN(4);
+	.text	   :
+	{
+	  /* WARNING - the following is hand-optimized to fit within	*/
+	  /* the sector layout of our flash chips!	XXX FIXME XXX	*/
+	  board/freescale/mx35_3stack/flash_header.o	(.text.flasheader)
+	  *(.text.head)		/*arm startup code*/
+	  *(.text.init)		/*platform lowlevel initial code*/
+	  *(.text.load)		/*load bootloader*/
+	  *(.text.setup)	/*platform post lowlevel initial code*/
+	  *(.text.vect)	/*platform post lowlevel initial code*/
+	  board/freescale/mx35_3stack/libmx35_3stack.a	(.text)
+	  lib_arm/libarm.a		(.text)
+	  net/libnet.a			(.text)
+	  drivers/mtd/libmtd.a		(.text)
+	  drivers/mmc/libmmc.a		(.text)
+
+	  . = DEFINED(env_offset) ? env_offset : .;
+	  common/env_embedded.o(.text)
+
+	  *(.text)
+	}
+
+	. = ALIGN(4);
+	.rodata : { *(.rodata) }
+
+	. = ALIGN(4);
+	.data : { *(.data) }
+
+	. = ALIGN(4);
+	.got : { *(.got) }
+
+	. = .;
+	__u_boot_cmd_start = .;
+	.u_boot_cmd : { *(.u_boot_cmd) }
+	__u_boot_cmd_end = .;
+
+	. = ALIGN(4);
+	__bss_start = .;
+	.bss : { *(.bss) }
+	_end = .;
+}

board/freescale/mx50_rdp/Makefile

@@ -0,0 +1,49 @@
+#
+# Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
+#
+# (C) Copyright 2010 Freescale Semiconductor, Inc.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).a
+
+COBJS	:= mx50_rdp.o
+SOBJS	:= lowlevel_init.o flash_header.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################

board/freescale/mx50_rdp/config.mk

@@ -0,0 +1,7 @@
+LDSCRIPT := $(SRCTREE)/board/$(VENDOR)/$(BOARD)/u-boot.lds
+
+sinclude $(OBJTREE)/board/$(VENDOR)/$(BOARD)/config.tmp
+
+ifndef TEXT_BASE
+	TEXT_BASE = 0x77800000
+endif

board/freescale/mx50_rdp/lowlevel_init.S

@@ -0,0 +1,207 @@
+/*
+ * Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
+ *
+ * Copyright (C) 2010 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <asm/arch/mx50.h>
+
+/*
+ * L2CC Cache setup/invalidation/disable
+ */
+.macro init_l2cc
+	/* explicitly disable L2 cache */
+        mrc 15, 0, r0, c1, c0, 1
+        bic r0, r0, #0x2
+        mcr 15, 0, r0, c1, c0, 1
+
+        /* reconfigure L2 cache aux control reg */
+        mov r0, #0xC0                   /* tag RAM */
+        add r0, r0, #0x4                /* data RAM */
+        orr r0, r0, #(1 << 24)          /* disable write allocate delay */
+        orr r0, r0, #(1 << 23)          /* disable write allocate combine */
+        orr r0, r0, #(1 << 22)          /* disable write allocate */
+
+	mcr 15, 1, r0, c9, c0, 2
+.endm /* init_l2cc */
+
+/* AIPS setup - Only setup MPROTx registers.
+ * The PACR default values are good.*/
+.macro init_aips
+	/*
+	 * Set all MPROTx to be non-bufferable, trusted for R/W,
+	 * not forced to user-mode.
+	 */
+	ldr r0, =AIPS1_BASE_ADDR
+	ldr r1, =0x77777777
+	str r1, [r0, #0x0]
+	str r1, [r0, #0x4]
+	ldr r0, =AIPS2_BASE_ADDR
+	str r1, [r0, #0x0]
+	str r1, [r0, #0x4]
+.endm /* init_aips */
+
+.macro setup_pll pll, freq
+	ldr r0, =\pll
+	ldr r1, =0x00001232
+	str r1, [r0, #PLL_DP_CTL]
+	mov r1, #0x2
+	str r1, [r0, #PLL_DP_CONFIG]
+
+	ldr r1, W_DP_OP_\freq
+	str r1, [r0, #PLL_DP_OP]
+	str r1, [r0, #PLL_DP_HFS_OP]
+
+	ldr r1,	W_DP_MFD_\freq
+	str r1, [r0, #PLL_DP_MFD]
+	str r1, [r0, #PLL_DP_HFS_MFD]
+
+	ldr r1,  W_DP_MFN_\freq
+	str r1, [r0, #PLL_DP_MFN]
+	str r1, [r0, #PLL_DP_HFS_MFN]
+
+	ldr r1, =0x00001232
+	str r1, [r0, #PLL_DP_CTL]
+1:	ldr r1, [r0, #PLL_DP_CTL]
+	ands r1, r1, #0x1
+	beq 1b
+.endm
+
+.macro init_clock
+
+	setup_pll PLL3_BASE_ADDR, 400
+
+	/* Switch peripheral to PLL3 */
+	/* Set periph_clk_sel[1:0]=0b10 to PLL3 */
+
+	ldr r0, CCM_BASE_ADDR_W
+	ldr r1, [r0, #CLKCTL_CBCDR]
+	orr r1, r1, #(3 << 25)
+	eor r1, r1, #(3 << 25)
+	orr r1, r1, #(2 << 25)
+	str r1, [r0, #CLKCTL_CBCDR]
+
+	/* make sure change is effective */
+1:      ldr r1, [r0, #CLKCTL_CDHIPR]
+	cmp r1, #0x0
+	bne 1b
+
+        setup_pll PLL2_BASE_ADDR, CONFIG_SYS_PLL2_FREQ
+
+	/* Switch peripheral to PLL2 */
+	/* Set periph_clk_sel[1:0]=0b01 to PLL2 */
+
+        ldr r0, CCM_BASE_ADDR_W
+        ldr r1, [r0, #CLKCTL_CBCDR]
+        orr r1, r1, #(3 << 25)
+        eor r1, r1, #(3 << 25)
+        orr r1, r1, #(1 << 25)
+
+	orr r1, r1, #(CONFIG_SYS_AHB_PODF << 10)
+	orr r1, r1, #(CONFIG_SYS_AXIA_PODF << 16)
+	orr r1, r1, #(CONFIG_SYS_AXIB_PODF << 19)
+	str r1, [r0, #CLKCTL_CBCDR]
+
+	/* make sure change is effective */
+1:      ldr r1, [r0, #CLKCTL_CDHIPR]
+	cmp r1, #0x0
+	bne 1b
+
+        setup_pll PLL3_BASE_ADDR, 216
+
+	/* Set the platform clock dividers */
+	ldr r0, PLATFORM_BASE_ADDR_W
+	ldr r1, PLATFORM_CLOCK_DIV_W
+	str r1, [r0, #PLATFORM_ICGC]
+
+	/* ARM2 run at full speed */
+	ldr r0, CCM_BASE_ADDR_W
+	mov r1, #0
+	str r1, [r0, #CLKCTL_CACRR]
+
+        /* make sure change is effective */
+1:      ldr r1, [r0, #CLKCTL_CDHIPR]
+        cmp r1, #0x0
+        bne 1b
+
+	/* Restore the default values in the Gate registers */
+	ldr r1, =0xFFFFFFFF
+	str r1, [r0, #CLKCTL_CCGR0]
+	str r1, [r0, #CLKCTL_CCGR1]
+	str r1, [r0, #CLKCTL_CCGR2]
+	str r1, [r0, #CLKCTL_CCGR3]
+	str r1, [r0, #CLKCTL_CCGR4]
+	str r1, [r0, #CLKCTL_CCGR5]
+	str r1, [r0, #CLKCTL_CCGR6]
+	str r1, [r0, #CLKCTL_CCGR7]
+
+        /* for cko - for ARM div by 8 */
+        mov r1, #0x000A0000
+        add r1, r1, #0x00000F0
+        str r1, [r0, #CLKCTL_CCOSR]
+.endm
+
+.section ".text.init", "x"
+
+.globl lowlevel_init
+lowlevel_init:
+
+#ifdef ENABLE_IMPRECISE_ABORT
+        mrs r1, spsr            /* save old spsr */
+        mrs r0, cpsr            /* read out the cpsr */
+	bic r0, r0, #0x100      /* clear the A bit */
+	msr spsr, r0            /* update spsr */
+	add lr, pc, #0x8        /* update lr */
+        movs pc, lr             /* update cpsr */
+        nop
+        nop
+        nop
+	nop
+	msr spsr, r1            /* restore old spsr */
+#endif
+
+	/* ARM errata ID #468414 */
+	mrc 15, 0, r1, c1, c0, 1
+	orr r1, r1, #(1 << 5)    /* enable L1NEON bit */
+	mcr 15, 0, r1, c1, c0, 1
+
+	init_l2cc
+
+	init_aips
+
+	init_clock /* not finished */
+
+	mov pc, lr
+
+/* Board level setting value */
+CCM_BASE_ADDR_W:        .word CCM_BASE_ADDR
+W_DP_OP_800:           	.word DP_OP_800
+W_DP_MFD_800:           .word DP_MFD_800
+W_DP_MFN_800:           .word DP_MFN_800
+W_DP_OP_600:            .word DP_OP_600
+W_DP_MFD_600:           .word DP_MFD_600
+W_DP_MFN_600:           .word DP_MFN_600
+W_DP_OP_400:            .word DP_OP_400
+W_DP_MFD_400:           .word DP_MFD_400
+W_DP_MFN_400:           .word DP_MFN_400
+W_DP_OP_216:            .word DP_OP_216
+W_DP_MFD_216:           .word DP_MFD_216
+W_DP_MFN_216:           .word DP_MFN_216
+PLATFORM_BASE_ADDR_W:   .word ARM_BASE_ADDR
+PLATFORM_CLOCK_DIV_W:   .word 0x00000124

board/freescale/mx50_rdp/u-boot.lds

@@ -0,0 +1,73 @@
+/*
+ * January 2004 - Changed to support H4 device
+ * Copyright (c) 2004 Texas Instruments
+ *
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
+ *
+ * (C) Copyright 2010 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+	. = 0x00000000;
+
+	. = ALIGN(4);
+	.text	   :
+	{
+	  /* WARNING - the following is hand-optimized to fit within	*/
+	  /* the sector layout of our flash chips!	XXX FIXME XXX	*/
+	  board/freescale/mx50_rdp/flash_header.o	(.text.flasheader)
+	  cpu/arm_cortexa8/start.o
+	  board/freescale/mx50_rdp/libmx50_rdp.a	(.text)
+	  lib_arm/libarm.a		(.text)
+	  net/libnet.a			(.text)
+	  drivers/mtd/libmtd.a		(.text)
+	  drivers/mmc/libmmc.a		(.text)
+
+	  . = DEFINED(env_offset) ? env_offset : .;
+	  common/env_embedded.o(.text)
+
+	  *(.text)
+	}
+
+	. = ALIGN(4);
+	.rodata : { *(.rodata) }
+
+	. = ALIGN(4);
+	.data : { *(.data) }
+
+	. = ALIGN(4);
+	.got : { *(.got) }
+
+	. = .;
+	__u_boot_cmd_start = .;
+	.u_boot_cmd : { *(.u_boot_cmd) }
+	__u_boot_cmd_end = .;
+
+	. = ALIGN(4);
+	__bss_start = .;
+	.bss : { *(.bss) }
+	_end = .;
+}

board/freescale/mx51_3stack/Makefile

@@ -0,0 +1,49 @@
+#
+# Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
+#
+# (C) Copyright 2009 Freescale Semiconductor, Inc.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).a
+
+COBJS	:= mx51_3stack.o
+SOBJS	:= lowlevel_init.o flash_header.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################

board/freescale/mx51_3stack/board-mx51_3stack.h

@@ -0,0 +1,64 @@
+/*
+ * Copyright 2009 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#ifndef __BOARD_FREESCALE_BOARD_MX51_3STACK_H__
+#define __BOARD_FREESCALE_BOARD_MX51_3STACK_H__
+
+/*!
+ * @defgroup BRDCFG_MX51 Board Configuration Options
+ * @ingroup MSL_MX51
+ */
+
+/*!
+ * @file mx51_3stack/board-mx51_3stack.h
+ *
+ * @brief This file contains all the board level configuration options.
+ *
+ * It currently hold the options defined for MX51 3Stack Platform.
+ *
+ * @ingroup BRDCFG_MX51
+ */
+
+/* CPLD offsets */
+#define PBC_LED_CTRL		(0x20000)
+#define PBC_SB_STAT		(0x20008)
+#define PBC_ID_AAAA		(0x20040)
+#define PBC_ID_5555		(0x20048)
+#define PBC_VERSION		(0x20050)
+#define PBC_ID_CAFE		(0x20058)
+#define PBC_INT_STAT		(0x20010)
+#define PBC_INT_MASK		(0x20038)
+#define PBC_INT_REST		(0x20020)
+#define PBC_SW_RESET		(0x20060)
+
+/* LED switchs */
+#define LED_SWITCH_REG		0x00
+/* buttons */
+#define SWITCH_BUTTONS_REG	0x08
+/* status, interrupt */
+#define INTR_STATUS_REG	0x10
+#define INTR_MASK_REG		0x38
+#define INTR_RESET_REG		0x20
+/* magic word for debug CPLD */
+#define MAGIC_NUMBER1_REG	0x40
+#define MAGIC_NUMBER2_REG	0x48
+/* CPLD code version */
+#define CPLD_CODE_VER_REG	0x50
+/* magic word for debug CPLD */
+#define MAGIC_NUMBER3_REG	0x58
+/* module reset register*/
+#define MODULE_RESET_REG	0x60
+/* CPU ID and Personality ID */
+#define MCU_BOARD_ID_REG	0x68
+
+#endif				/* __BOARD_FREESCALE_BOARD_MX51_3STACK_H__ */

board/freescale/mx51_3stack/config.mk

@@ -0,0 +1,3 @@
+LDSCRIPT := $(SRCTREE)/board/$(VENDOR)/$(BOARD)/u-boot.lds
+
+TEXT_BASE = 0x97800000

board/freescale/mx51_3stack/flash_header.S

@@ -0,0 +1,113 @@
+/*
+ * Copyright 2009 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <asm/arch/mx51.h>
+#include "board-mx51_3stack.h"
+
+#ifdef	CONFIG_FLASH_HEADER
+#ifndef CONFIG_FLASH_HEADER_OFFSET
+# error "Must define the offset of flash header"
+#endif
+#define MXC_DCD_ITEM(i, type, addr, val)	\
+dcd_node_##i:					\
+	.word type			;	\
+	.word addr			;	\
+	.word val			;	\
+
+.section ".text.flasheader", "x"
+	b	_start
+	.org	CONFIG_FLASH_HEADER_OFFSET
+app_code_jump_v:	.word	_start
+app_code_code_barker:	.word	CONFIG_FLASH_HEADER_BARKER
+app_code_csf:		.word	0
+dcd_ptr_ptr:		.word	dcd_ptr
+super_root_key:		.word	0
+dcd_ptr:		.word	dcd_array_start
+app_dest_ptr:		.word	TEXT_BASE
+dcd_array_start:
+magic:			.word	0xB17219E9
+dcd_array_size:		.word	dcd_data_end - dcd_array_start - 8
+/* DCD */
+/* DDR2 IOMUX configuration */
+MXC_DCD_ITEM(1, 4, IOMUXC_BASE_ADDR + 0x8a0, 0x200)
+MXC_DCD_ITEM(2, 4, IOMUXC_BASE_ADDR + 0x50c, 0x20c5)
+MXC_DCD_ITEM(3, 4, IOMUXC_BASE_ADDR + 0x510, 0x20c5)
+MXC_DCD_ITEM(4, 4, IOMUXC_BASE_ADDR + 0x83c, 0x2)
+MXC_DCD_ITEM(5, 4, IOMUXC_BASE_ADDR + 0x848, 0x2)
+MXC_DCD_ITEM(6, 4, IOMUXC_BASE_ADDR + 0x4b8, 0xe7)
+MXC_DCD_ITEM(7, 4, IOMUXC_BASE_ADDR + 0x4bc, 0x45)
+MXC_DCD_ITEM(8, 4, IOMUXC_BASE_ADDR + 0x4c0, 0x45)
+MXC_DCD_ITEM(9, 4, IOMUXC_BASE_ADDR + 0x4c4, 0x45)
+MXC_DCD_ITEM(10, 4, IOMUXC_BASE_ADDR + 0x4c8, 0x45)
+MXC_DCD_ITEM(11, 4, IOMUXC_BASE_ADDR + 0x820, 0x0)
+MXC_DCD_ITEM(12, 4, IOMUXC_BASE_ADDR + 0x4a4, 0x3)
+MXC_DCD_ITEM(13, 4, IOMUXC_BASE_ADDR + 0x4a8, 0x3)
+MXC_DCD_ITEM(14, 4, IOMUXC_BASE_ADDR + 0x4ac, 0xe3)
+MXC_DCD_ITEM(15, 4, IOMUXC_BASE_ADDR + 0x4b0, 0xe3)
+MXC_DCD_ITEM(16, 4, IOMUXC_BASE_ADDR + 0x4b4, 0xe3)
+MXC_DCD_ITEM(17, 4, IOMUXC_BASE_ADDR + 0x4cc, 0xe3)
+MXC_DCD_ITEM(18, 4, IOMUXC_BASE_ADDR + 0x4d0, 0xe2)
+/* Set drive strength to MAX */
+MXC_DCD_ITEM(19, 4, IOMUXC_BASE_ADDR + 0x82c, 0x6)
+MXC_DCD_ITEM(20, 4, IOMUXC_BASE_ADDR + 0x8a4, 0x6)
+MXC_DCD_ITEM(21, 4, IOMUXC_BASE_ADDR + 0x8ac, 0x6)
+MXC_DCD_ITEM(22, 4, IOMUXC_BASE_ADDR + 0x8b8, 0x6)
+/* 13 ROW, 10 COL, 32Bit, SREF=4 Micron Model */
+/* CAS=3,  BL=4 */
+MXC_DCD_ITEM(23, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDCTL0, 0x82a20000)
+MXC_DCD_ITEM(24, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDCTL1, 0x82a20000)
+MXC_DCD_ITEM(25, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDMISC, 0x000ad0d0)
+MXC_DCD_ITEM(26, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDCFG0, 0x333574aa)
+MXC_DCD_ITEM(27, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDCFG1, 0x333574aa)
+/* Init DRAM on CS0 */
+MXC_DCD_ITEM(28, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x04008008)
+MXC_DCD_ITEM(29, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x0000801a)
+MXC_DCD_ITEM(30, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x0000801b)
+MXC_DCD_ITEM(31, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x00448019)
+MXC_DCD_ITEM(32, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x07328018)
+MXC_DCD_ITEM(33, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x04008008)
+MXC_DCD_ITEM(34, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x00008010)
+MXC_DCD_ITEM(35, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x00008010)
+MXC_DCD_ITEM(36, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x06328018)
+MXC_DCD_ITEM(37, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x03808019)
+MXC_DCD_ITEM(38, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x00408019)
+MXC_DCD_ITEM(39, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x00008000)
+/* Init DRAM on CS1 */
+MXC_DCD_ITEM(40, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x0400800c)
+MXC_DCD_ITEM(41, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x0000801e)
+MXC_DCD_ITEM(42, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x0000801f)
+MXC_DCD_ITEM(43, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x0000801d)
+MXC_DCD_ITEM(44, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x0732801c)
+MXC_DCD_ITEM(45, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x0400800c)
+MXC_DCD_ITEM(46, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x00008014)
+MXC_DCD_ITEM(47, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x00008014)
+MXC_DCD_ITEM(48, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x0632801c)
+MXC_DCD_ITEM(49, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x0380801d)
+MXC_DCD_ITEM(50, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x0040801d)
+MXC_DCD_ITEM(51, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x00008004)
+MXC_DCD_ITEM(52, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDCTL0, 0xb2a20000)
+MXC_DCD_ITEM(53, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDCTL1, 0xb2a20000)
+MXC_DCD_ITEM(54, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDMISC, 0x000ad6d0)
+MXC_DCD_ITEM(55, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDCDLYGD, 0x90000000)
+MXC_DCD_ITEM(56, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x00000000)
+dcd_data_end:
+//image_len:		.word	0x80000
+image_len:		.word	__u_boot_cmd_end - TEXT_BASE
+#endif

board/freescale/mx51_3stack/lowlevel_init.S

@@ -0,0 +1,365 @@
+/*
+ * Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
+ *
+ * (C) Copyright 2009-2010 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <asm/arch/mx51.h>
+#include "board-mx51_3stack.h"
+
+/*
+ * return soc version
+ * 	0x10:  TO1
+ *	0x20:  TO2
+ *	0x30:  TO3
+ */
+.macro check_soc_version ret, tmp
+.endm
+
+/*
+ * L2CC Cache setup/invalidation/disable
+ */
+.macro init_l2cc
+	/* explicitly disable L2 cache */
+        mrc 15, 0, r0, c1, c0, 1
+        bic r0, r0, #0x2
+        mcr 15, 0, r0, c1, c0, 1
+
+        /* reconfigure L2 cache aux control reg */
+        mov r0, #0xC0                   /* tag RAM */
+        add r0, r0, #0x4                /* data RAM */
+        orr r0, r0, #(1 << 24)          /* disable write allocate delay */
+        orr r0, r0, #(1 << 23)          /* disable write allocate combine */
+        orr r0, r0, #(1 << 22)          /* disable write allocate */
+
+	ldr r1, =0x00000000
+	ldr r3, [r1, #ROM_SI_REV]
+	cmp r3, #0x10    /* r3 contains the silicon rev */
+	/* disable write combine for TO 2 and lower */
+	orrls r0, r0, #(1 << 25)
+
+	mcr 15, 1, r0, c9, c0, 2
+.endm /* init_l2cc */
+
+/* AIPS setup - Only setup MPROTx registers.
+ * The PACR default values are good.*/
+.macro init_aips
+	/*
+	 * Set all MPROTx to be non-bufferable, trusted for R/W,
+	 * not forced to user-mode.
+	 */
+	ldr r0, =AIPS1_BASE_ADDR
+	ldr r1, =0x77777777
+	str r1, [r0, #0x0]
+	str r1, [r0, #0x4]
+	ldr r0, =AIPS2_BASE_ADDR
+	str r1, [r0, #0x0]
+	str r1, [r0, #0x4]
+	/*
+	 * Clear the on and off peripheral modules Supervisor Protect bit
+	 * for SDMA to access them. Did not change the AIPS control registers
+	 * (offset 0x20) access type
+	 */
+.endm /* init_aips */
+
+/* MAX (Multi-Layer AHB Crossbar Switch) setup */
+.macro init_max
+.endm /* init_max */
+
+/* M4IF setup */
+.macro init_m4if
+	/* VPU and IPU given higher priority (0x4)
+	 * IPU accesses with ID=0x1 given highest priority (=0xA)
+	 */
+	ldr r0, =M4IF_BASE_ADDR
+
+	ldr r1, =0x00000203
+	str r1, [r0, #0x40]
+
+	ldr r1, =0x0
+	str r1, [r0, #0x44]
+
+	ldr r1, =0x00120125
+	str r1, [r0, #0x9C]
+
+	ldr r1, =0x001901A3
+	str r1, [r0, #0x48]
+.endm /* init_m4if */
+
+/* To support 133MHz DDR */
+.macro  init_drive_strength
+.endm /* init_drive_strength */
+
+/* CPLD on CS5 setup */
+.macro init_debug_board
+.endm /* init_debug_board */
+
+.macro setup_pll pll, freq
+	ldr r2, =\pll
+	ldr r1, =0x00001232
+	str r1, [r2, #PLL_DP_CTL] /* Set DPLL ON (set UPEN bit): BRMO=1 */
+	mov r1, #0x2
+	str r1, [r2, #PLL_DP_CONFIG] /* Enable auto-restart AREN bit */
+
+	str r3, [r2, #PLL_DP_OP]
+	str r3, [r2, #PLL_DP_HFS_OP]
+
+	str r4, [r2, #PLL_DP_MFD]
+	str r4, [r2, #PLL_DP_HFS_MFD]
+
+	str r5, [r2, #PLL_DP_MFN]
+	str r5, [r2, #PLL_DP_HFS_MFN]
+
+	ldr r1, =0x00001232
+	str r1, [r2, #PLL_DP_CTL]
+1:	ldr r1, [r2, #PLL_DP_CTL]
+	ands r1, r1, #0x1
+	beq 1b
+.endm
+
+.macro init_clock
+	ldr r0, =CCM_BASE_ADDR
+
+	/* Gate of clocks to the peripherals first */
+	ldr r1, =0x3FFFFFFF
+	str r1, [r0, #CLKCTL_CCGR0]
+	ldr r1, =0x0
+	str r1, [r0, #CLKCTL_CCGR1]
+	str r1, [r0, #CLKCTL_CCGR2]
+	str r1, [r0, #CLKCTL_CCGR3]
+
+	ldr r1, =0x00030000
+	str r1, [r0, #CLKCTL_CCGR4]
+	ldr r1, =0x00FFF030
+	str r1, [r0, #CLKCTL_CCGR5]
+	ldr r1, =0x00000300
+	str r1, [r0, #CLKCTL_CCGR6]
+
+        /* Disable IPU and HSC dividers */
+        mov r1, #0x60000
+        str r1, [r0, #CLKCTL_CCDR]
+
+	/* Make sure to switch the DDR away from PLL 1 */
+	ldr r1, =0x19239145
+	str r1, [r0, #CLKCTL_CBCDR]
+	/* make sure divider effective */
+1:	ldr r1, [r0, #CLKCTL_CDHIPR]
+	cmp r1, #0x0
+	bne 1b
+
+	/* Switch ARM to step clock */
+	mov r1, #0x4
+	str r1, [r0, #CLKCTL_CCSR]
+
+	mov r3, #DP_OP_800
+	mov r4, #DP_MFD_800
+	mov r5, #DP_MFN_800
+	setup_pll PLL1_BASE_ADDR
+	mov r3, #DP_OP_665
+	mov r4, #DP_MFD_665
+	mov r5, #DP_MFN_665
+	setup_pll PLL3_BASE_ADDR
+
+	/* Switch peripheral to PLL 3 */
+	ldr r0, =CCM_BASE_ADDR
+        ldr r1, =0x000010C0
+	str r1, [r0, #CLKCTL_CBCMR]
+	ldr r1, =0x13239145
+	str r1, [r0, #CLKCTL_CBCDR]
+
+	mov r3, #DP_OP_665
+	mov r4, #DP_MFD_665
+	mov r5, #DP_MFN_665
+	setup_pll PLL2_BASE_ADDR
+
+	/* Switch peripheral to PLL2 */
+	ldr r0, =CCM_BASE_ADDR
+	ldr r1, =0x19239145
+	str r1, [r0, #CLKCTL_CBCDR]
+	ldr r1, =0x000020C0
+	str r1, [r0, #CLKCTL_CBCMR]
+
+	mov r3, #DP_OP_216
+	mov r4, #DP_MFD_216
+	mov r5, #DP_MFN_216
+	setup_pll PLL3_BASE_ADDR
+
+	/* Set the platform clock dividers */
+	ldr r0, =ARM_BASE_ADDR
+	ldr r1, =0x00000725
+	str r1, [r0, #0x14]
+
+	ldr r0, =CCM_BASE_ADDR
+	/* Run TO 3.0 at Full speed, for other TO's wait
+	till we increase VDDGP */
+	ldr r1, =0x0
+	ldr r3, [r1, #ROM_SI_REV]
+	cmp r3, #0x10
+	movls r1, #0x1
+	movhi r1, #0
+	str r1, [r0, #CLKCTL_CACRR]
+
+	/* Switch ARM back to PLL 1 */
+	mov r1, #0
+	str r1, [r0, #CLKCTL_CCSR]
+
+	/* setup the rest */
+	/* Use lp_apm (24MHz) source for perclk */
+	ldr r1, =0x000020C2
+	str r1, [r0, #CLKCTL_CBCMR]
+	/* ddr clock from PLL 1, all perclk dividers are 1 since using 24MHz */
+#ifdef CONFIG_IMX51_MDDR
+	ldr r1, =0x61E35100
+#else
+	ldr r1, =0x59E35100
+#endif
+	str r1, [r0, #CLKCTL_CBCDR]
+
+	/* Restore the default values in the Gate registers */
+	ldr r1, =0xFFFFFFFF
+	str r1, [r0, #CLKCTL_CCGR0]
+	str r1, [r0, #CLKCTL_CCGR1]
+	str r1, [r0, #CLKCTL_CCGR2]
+	str r1, [r0, #CLKCTL_CCGR3]
+	str r1, [r0, #CLKCTL_CCGR4]
+	str r1, [r0, #CLKCTL_CCGR5]
+	str r1, [r0, #CLKCTL_CCGR6]
+
+	/* Use PLL 2 for UART's, get 66.5MHz from it */
+	ldr r1, =0xA5A2A020
+	str r1, [r0, #CLKCTL_CSCMR1]
+	ldr r1, =0x00C30321
+	str r1, [r0, #CLKCTL_CSCDR1]
+
+	/* make sure divider effective */
+1:	ldr r1, [r0, #CLKCTL_CDHIPR]
+	cmp r1, #0x0
+	bne 1b
+
+	mov r1, #0x0
+	str r1, [r0, #CLKCTL_CCDR]
+
+	/* for cko - for ARM div by 8 */
+	mov r1, #0x000A0000
+	add r1, r1, #0x00000F0
+	str r1, [r0, #CLKCTL_CCOSR]
+.endm
+
+.macro setup_wdog
+	ldr r0, =WDOG1_BASE_ADDR
+	mov r1, #0x30
+	strh r1, [r0]
+.endm
+
+.macro setup_sdram
+	ldr r0, =ESDCTL_BASE_ADDR
+	/* Set CSD0 */
+	mov r1, #0x80000000
+	str r1, [r0, #ESDCTL_ESDCTL0]
+	/* Precharge command */
+        ldr r1, DDR_PERCHARGE_CMD
+        str r1, [r0, #ESDCTL_ESDSCR]
+        /* 2 refresh commands */
+        ldr r1, DDR_REFRESH_CMD
+        str r1, [r0, #ESDCTL_ESDSCR]
+        str r1, [r0, #ESDCTL_ESDSCR]
+        /* LMR with CAS=3 and BL=3 */
+        ldr r1, DDR_LMR1_W
+	str r1, [r0, #ESDCTL_ESDSCR]
+        /* 13 ROW, 10 COL, 32Bit, SREF=4 Micron Model */
+        ldr r1, DDR_LMR_CMD
+        str r1, [r0, #ESDCTL_ESDCTL0]
+        /* Timing parameters */
+        ldr r1, DDR_TIMING_W
+        str r1, [r0, #ESDCTL_ESDCFG0]
+        /* MDDR enable, RLAT=2 */
+        ldr r1, DDR_MISC_W
+        str r1, [r0, #ESDCTL_ESDMISC]
+        /* Normal mode */
+        mov r1, #0x00000000
+        str r1, [r0, #ESDCTL_ESDSCR]
+1:
+.endm /* setup_sdram */
+
+.section ".text.init", "x"
+
+.globl lowlevel_init
+lowlevel_init:
+        ldr r1, =0x00000000
+        ldr r3, [r1, #ROM_SI_REV]
+        ldr r0, =GPC_BASE_ADDR
+        cmp r3, #0x10    // r3 contains the silicon rev
+        ldrls r1, =0x1FC00000
+        ldrhi r1, =0x1A800000
+        str r1, [r0, #4]
+
+#ifdef ENABLE_IMPRECISE_ABORT
+        mrs r1, spsr            /* save old spsr */
+        mrs r0, cpsr            /* read out the cpsr */
+	bic r0, r0, #0x100      /* clear the A bit */
+	msr spsr, r0            /* update spsr */
+	add lr, pc, #0x8        /* update lr */
+        movs pc, lr             /* update cpsr */
+        nop
+        nop
+        nop
+	nop
+	msr spsr, r1            /* restore old spsr */
+#endif
+
+	/* ARM errata ID #468414 */
+	mrc 15, 0, r1, c1, c0, 1
+	orr r1, r1, #(1 << 5)    /* enable L1NEON bit */
+	mcr 15, 0, r1, c1, c0, 1
+
+	init_l2cc
+
+	init_aips
+
+
+	init_max
+
+	init_m4if
+
+	init_drive_strength
+
+	cmp pc, #PHYS_SDRAM_1
+	blo do_sdram_setup
+	cmp pc, #(PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE)
+	blo init_clock_start
+
+do_sdram_setup:
+	setup_sdram
+
+init_clock_start:
+	init_clock
+	init_debug_board
+	/*init_sdram*/
+
+	/* return from mxc_nand_load */
+	/* r12 saved upper lr*/
+	b mxc_nand_load
+
+/* Board level setting value */
+DDR_PERCHARGE_CMD:	.word 0x04008008
+DDR_REFRESH_CMD:	.word 0x00008010
+DDR_LMR1_W:		.word 0x00338018
+DDR_LMR_CMD:		.word 0xB2220000
+DDR_TIMING_W:		.word 0xB02567A9
+DDR_MISC_W:		.word 0x000A0104

board/freescale/mx51_3stack/mx51_3stack.c

@@ -0,0 +1,988 @@
+/*
+ * Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
+ *
+ * (C) Copyright 2009-2010 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/errno.h>
+#include <asm/arch/mx51.h>
+#include <asm/arch/mx51_pins.h>
+#include <asm/arch/iomux.h>
+#include <i2c.h>
+#include "board-mx51_3stack.h"
+#include <netdev.h>
+
+#ifdef CONFIG_CMD_MMC
+#include <mmc.h>
+#include <fsl_esdhc.h>
+#endif
+
+#ifdef CONFIG_ARCH_MMU
+#include <asm/mmu.h>
+#include <asm/arch/mmu.h>
+#endif
+
+#ifdef CONFIG_ANDROID_RECOVERY
+#include "../common/recovery.h"
+#include <mxc_keyb.h>
+#include <part.h>
+#include <ext2fs.h>
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/partitions.h>
+#include <ubi_uboot.h>
+#include <jffs2/load_kernel.h>
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static u32 system_rev;
+static enum boot_device boot_dev;
+u32	mx51_io_base_addr;
+
+static inline void setup_boot_device(void)
+{
+	uint *fis_addr = (uint *)IRAM_BASE_ADDR;
+
+	switch (*fis_addr) {
+	case NAND_FLASH_BOOT:
+		boot_dev = NAND_BOOT;
+		break;
+	case SPI_NOR_FLASH_BOOT:
+		boot_dev = SPI_NOR_BOOT;
+		break;
+	case MMC_FLASH_BOOT:
+		boot_dev = MMC_BOOT;
+		break;
+	default:
+		{
+			uint soc_sbmr = readl(SRC_BASE_ADDR + 0x4);
+			uint bt_mem_ctl = soc_sbmr & 0x00000003;
+			uint bt_mem_type = (soc_sbmr & 0x00000180) >> 7;
+
+			switch (bt_mem_ctl) {
+			case 0x3:
+				if (bt_mem_type == 0)
+					boot_dev = MMC_BOOT;
+				else if (bt_mem_type == 3)
+					boot_dev = SPI_NOR_BOOT;
+				else
+					boot_dev = UNKNOWN_BOOT;
+				break;
+			case 0x1:
+				boot_dev = NAND_BOOT;
+				break;
+			default:
+				boot_dev = UNKNOWN_BOOT;
+			}
+		}
+		break;
+	}
+}
+
+enum boot_device get_boot_device(void)
+{
+	return boot_dev;
+}
+
+u32 get_board_rev(void)
+{
+	return system_rev;
+}
+
+static inline void setup_soc_rev(void)
+{
+	int reg;
+#ifdef CONFIG_ARCH_MMU
+	reg = __REG(0x20000000 + ROM_SI_REV); /* Virtual address */
+#else
+	reg = __REG(ROM_SI_REV); /* Virtual address */
+#endif
+
+	switch (reg) {
+	case 0x02:
+		system_rev = 0x51000 | CHIP_REV_1_1;
+		break;
+	case 0x10:
+		system_rev = 0x51000 | CHIP_REV_2_0;
+		break;
+	default:
+		system_rev = 0x51000 | CHIP_REV_1_0;
+	}
+}
+
+static inline void set_board_rev(int rev)
+{
+	system_rev |= (rev & 0xF) << 8;
+}
+
+inline int is_soc_rev(int rev)
+{
+	return (system_rev & 0xFF) - rev;
+}
+
+#ifdef CONFIG_ARCH_MMU
+void board_mmu_init(void)
+{
+	unsigned long ttb_base = PHYS_SDRAM_1 + 0x4000;
+	unsigned long i;
+
+	/*
+	* Set the TTB register
+	*/
+	asm volatile ("mcr p15, 0, %0, c2, c0, 0" : : "r"(ttb_base) /*:*/);
+
+	/*
+	* Set the Domain Access Control Register
+	*/
+	i = ARM_ACCESS_DACR_DEFAULT;
+	asm volatile ("mcr p15, 0, %0, c3, c0, 0" : : "r"(i) /*:*/);
+
+	/*
+	* First clear all TT entries - ie Set them to Faulting
+	*/
+	memset((void *)ttb_base, 0, ARM_FIRST_LEVEL_PAGE_TABLE_SIZE);
+	/* Actual   Virtual  Size   Attributes          Function */
+	/* Base     Base     MB     cached? buffered?  access permissions */
+	/* xxx00000 xxx00000 */
+	X_ARM_MMU_SECTION(0x000, 0x200, 0x1,
+			ARM_UNCACHEABLE, ARM_UNBUFFERABLE,
+			ARM_ACCESS_PERM_RW_RW); /* ROM */
+	X_ARM_MMU_SECTION(0x1FF, 0x1FF, 0x001,
+			ARM_UNCACHEABLE, ARM_UNBUFFERABLE,
+			ARM_ACCESS_PERM_RW_RW); /* IRAM */
+	X_ARM_MMU_SECTION(0x300, 0x300, 0x100,
+			ARM_UNCACHEABLE, ARM_UNBUFFERABLE,
+			ARM_ACCESS_PERM_RW_RW); /* GPU */
+	X_ARM_MMU_SECTION(0x400, 0x400, 0x200,
+			ARM_UNCACHEABLE, ARM_UNBUFFERABLE,
+			ARM_ACCESS_PERM_RW_RW); /* IPUv3D */
+	X_ARM_MMU_SECTION(0x600, 0x600, 0x300,
+			ARM_UNCACHEABLE, ARM_UNBUFFERABLE,
+			ARM_ACCESS_PERM_RW_RW); /* periperals */
+	X_ARM_MMU_SECTION(0x900, 0x000, 0x080,
+			ARM_CACHEABLE, ARM_BUFFERABLE,
+			ARM_ACCESS_PERM_RW_RW); /* SDRAM */
+	X_ARM_MMU_SECTION(0x900, 0x900, 0x080,
+			ARM_CACHEABLE, ARM_BUFFERABLE,
+			ARM_ACCESS_PERM_RW_RW); /* SDRAM */
+	X_ARM_MMU_SECTION(0x900, 0x980, 0x080,
+			ARM_UNCACHEABLE, ARM_UNBUFFERABLE,
+			ARM_ACCESS_PERM_RW_RW); /* SDRAM 0:128M*/
+	X_ARM_MMU_SECTION(0xA00, 0xA00, 0x100,
+			ARM_CACHEABLE, ARM_BUFFERABLE,
+			ARM_ACCESS_PERM_RW_RW); /* SDRAM */
+	X_ARM_MMU_SECTION(0xB80, 0xB80, 0x10,
+			ARM_UNCACHEABLE, ARM_UNBUFFERABLE,
+			ARM_ACCESS_PERM_RW_RW); /* CS1 EIM control*/
+	X_ARM_MMU_SECTION(0xCC0, 0xCC0, 0x040,
+			ARM_UNCACHEABLE, ARM_UNBUFFERABLE,
+			ARM_ACCESS_PERM_RW_RW); /* CS4/5/NAND Flash buffer */
+
+	/* Workaround for arm errata #709718 */
+	/* Setup PRRR so device is always mapped to non-shared */
+	asm volatile ("mrc p15, 0, %0, c10, c2, 0" : "=r"(i) : /*:*/);
+	i &= (~(3 << 0x10));
+	asm volatile ("mcr p15, 0, %0, c10, c2, 0" : : "r"(i) /*:*/);
+
+	/* Enable MMU */
+	MMU_ON();
+}
+#endif
+
+int dram_init(void)
+{
+	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+	return 0;
+}
+
+static void setup_uart(void)
+{
+	unsigned int pad = PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE |
+			 PAD_CTL_PUE_PULL | PAD_CTL_DRV_HIGH;
+	mxc_request_iomux(MX51_PIN_UART1_RXD, IOMUX_CONFIG_ALT0);
+	mxc_iomux_set_pad(MX51_PIN_UART1_RXD, pad | PAD_CTL_SRE_FAST);
+	mxc_request_iomux(MX51_PIN_UART1_TXD, IOMUX_CONFIG_ALT0);
+	mxc_iomux_set_pad(MX51_PIN_UART1_TXD, pad | PAD_CTL_SRE_FAST);
+	mxc_request_iomux(MX51_PIN_UART1_RTS, IOMUX_CONFIG_ALT0);
+	mxc_iomux_set_pad(MX51_PIN_UART1_RTS, pad);
+	mxc_request_iomux(MX51_PIN_UART1_CTS, IOMUX_CONFIG_ALT0);
+	mxc_iomux_set_pad(MX51_PIN_UART1_CTS, pad);
+}
+
+void setup_nfc(void)
+{
+	/* Enable NFC IOMUX */
+	mxc_request_iomux(MX51_PIN_NANDF_CS0, IOMUX_CONFIG_ALT0);
+	mxc_request_iomux(MX51_PIN_NANDF_CS1, IOMUX_CONFIG_ALT0);
+	mxc_request_iomux(MX51_PIN_NANDF_CS2, IOMUX_CONFIG_ALT0);
+	mxc_request_iomux(MX51_PIN_NANDF_CS3, IOMUX_CONFIG_ALT0);
+	mxc_request_iomux(MX51_PIN_NANDF_CS4, IOMUX_CONFIG_ALT0);
+	mxc_request_iomux(MX51_PIN_NANDF_CS5, IOMUX_CONFIG_ALT0);
+	mxc_request_iomux(MX51_PIN_NANDF_CS6, IOMUX_CONFIG_ALT0);
+	mxc_request_iomux(MX51_PIN_NANDF_CS7, IOMUX_CONFIG_ALT0);
+}
+
+static void setup_expio(void)
+{
+	u32 reg;
+	/* CS5 setup */
+	mxc_request_iomux(MX51_PIN_EIM_CS5, IOMUX_CONFIG_ALT0);
+	writel(0x00410089, WEIM_BASE_ADDR + 0x78 + CSGCR1);
+	writel(0x00000002, WEIM_BASE_ADDR + 0x78 + CSGCR2);
+	/* RWSC=50, RADVA=2, RADVN=6, OEA=0, OEN=0, RCSA=0, RCSN=0 */
+	writel(0x32260000, WEIM_BASE_ADDR + 0x78 + CSRCR1);
+	/* APR = 0 */
+	writel(0x00000000, WEIM_BASE_ADDR + 0x78 + CSRCR2);
+	/* WAL=0, WBED=1, WWSC=50, WADVA=2, WADVN=6, WEA=0, WEN=0,
+	 * WCSA=0, WCSN=0
+	 */
+	writel(0x72080F00, WEIM_BASE_ADDR + 0x78 + CSWCR1);
+	if ((readw(CS5_BASE_ADDR + PBC_ID_AAAA) == 0xAAAA) &&
+	    (readw(CS5_BASE_ADDR + PBC_ID_5555) == 0x5555)) {
+		if (is_soc_rev(CHIP_REV_2_0) < 0) {
+			reg = readl(CCM_BASE_ADDR + CLKCTL_CBCDR);
+			reg = (reg & (~0x70000)) | 0x30000;
+			writel(reg, CCM_BASE_ADDR + CLKCTL_CBCDR);
+			/* make sure divider effective */
+			while (readl(CCM_BASE_ADDR + CLKCTL_CDHIPR) != 0)
+				;
+			writel(0x0, CCM_BASE_ADDR + CLKCTL_CCDR);
+		}
+		mx51_io_base_addr = CS5_BASE_ADDR;
+	} else {
+		/* CS1 */
+		writel(0x00410089, WEIM_BASE_ADDR + 0x18 + CSGCR1);
+		writel(0x00000002, WEIM_BASE_ADDR + 0x18 + CSGCR2);
+		/*  RWSC=50, RADVA=2, RADVN=6, OEA=0, OEN=0, RCSA=0, RCSN=0 */
+		writel(0x32260000, WEIM_BASE_ADDR + 0x18 + CSRCR1);
+		/* APR=0 */
+		writel(0x00000000, WEIM_BASE_ADDR + 0x18 + CSRCR2);
+		/* WAL=0, WBED=1, WWSC=50, WADVA=2, WADVN=6, WEA=0,
+		 * WEN=0, WCSA=0, WCSN=0
+		 */
+		writel(0x72080F00, WEIM_BASE_ADDR + 0x18 + CSWCR1);
+		mx51_io_base_addr = CS1_BASE_ADDR;
+	}
+
+	/* Reset interrupt status reg */
+	writew(0x1F, mx51_io_base_addr + PBC_INT_REST);
+	writew(0x00, mx51_io_base_addr + PBC_INT_REST);
+	writew(0xFFFF, mx51_io_base_addr + PBC_INT_MASK);
+
+	/* Reset the XUART and Ethernet controllers */
+	reg = readw(mx51_io_base_addr + PBC_SW_RESET);
+	reg |= 0x9;
+	writew(reg, mx51_io_base_addr + PBC_SW_RESET);
+	reg &= ~0x9;
+	writew(reg, mx51_io_base_addr + PBC_SW_RESET);
+}
+
+#if defined(CONFIG_MXC_ATA)
+int setup_ata(void)
+{
+	u32 pad;
+
+	pad = (PAD_CTL_DRV_HIGH | PAD_CTL_DRV_VOT_HIGH);
+
+	/* Need to disable nand iomux first */
+	mxc_request_iomux(MX51_PIN_NANDF_ALE, IOMUX_CONFIG_ALT1);
+	mxc_iomux_set_pad(MX51_PIN_NANDF_ALE, pad);
+
+	mxc_request_iomux(MX51_PIN_NANDF_CS2, IOMUX_CONFIG_ALT1);
+	mxc_iomux_set_pad(MX51_PIN_NANDF_CS2, pad);
+
+	mxc_request_iomux(MX51_PIN_NANDF_CS3, IOMUX_CONFIG_ALT1);
+	mxc_iomux_set_pad(MX51_PIN_NANDF_CS3, pad);
+
+	mxc_request_iomux(MX51_PIN_NANDF_CS4, IOMUX_CONFIG_ALT1);
+	mxc_iomux_set_pad(MX51_PIN_NANDF_CS4, pad);
+
+	mxc_request_iomux(MX51_PIN_NANDF_CS5, IOMUX_CONFIG_ALT1);
+	mxc_iomux_set_pad(MX51_PIN_NANDF_CS5, pad);
+
+	mxc_request_iomux(MX51_PIN_NANDF_CS6, IOMUX_CONFIG_ALT1);
+	mxc_iomux_set_pad(MX51_PIN_NANDF_CS6, pad);
+
+	mxc_request_iomux(MX51_PIN_NANDF_RE_B, IOMUX_CONFIG_ALT1);
+	mxc_iomux_set_pad(MX51_PIN_NANDF_RE_B, pad);
+
+	mxc_request_iomux(MX51_PIN_NANDF_WE_B, IOMUX_CONFIG_ALT1);
+	mxc_iomux_set_pad(MX51_PIN_NANDF_WE_B, pad);
+
+	mxc_request_iomux(MX51_PIN_NANDF_CLE, IOMUX_CONFIG_ALT1);
+	mxc_iomux_set_pad(MX51_PIN_NANDF_CLE, pad);
+
+	mxc_request_iomux(MX51_PIN_NANDF_RB0, IOMUX_CONFIG_ALT1);
+	mxc_iomux_set_pad(MX51_PIN_NANDF_RB0, pad);
+
+	mxc_request_iomux(MX51_PIN_NANDF_WP_B, IOMUX_CONFIG_ALT1);
+	mxc_iomux_set_pad(MX51_PIN_NANDF_WP_B, pad);
+
+	/* TO 2.0 */
+	mxc_request_iomux(MX51_PIN_GPIO_NAND, IOMUX_CONFIG_ALT1);
+	mxc_iomux_set_pad(MX51_PIN_GPIO_NAND, pad);
+
+	/* TO 1.0 */
+	mxc_request_iomux(MX51_PIN_NANDF_RB5, IOMUX_CONFIG_ALT1);
+	mxc_iomux_set_pad(MX51_PIN_NANDF_RB5, pad);
+
+	mxc_request_iomux(MX51_PIN_NANDF_RB1, IOMUX_CONFIG_ALT1);
+	mxc_iomux_set_pad(MX51_PIN_NANDF_RB1, pad);
+
+	mxc_request_iomux(MX51_PIN_NANDF_D0, IOMUX_CONFIG_ALT1);
+	mxc_iomux_set_pad(MX51_PIN_NANDF_D0, pad);
+
+	mxc_request_iomux(MX51_PIN_NANDF_D1, IOMUX_CONFIG_ALT1);
+	mxc_iomux_set_pad(MX51_PIN_NANDF_D1, pad);
+
+	mxc_request_iomux(MX51_PIN_NANDF_D2, IOMUX_CONFIG_ALT1);
+	mxc_iomux_set_pad(MX51_PIN_NANDF_D2, pad);
+
+	mxc_request_iomux(MX51_PIN_NANDF_D3, IOMUX_CONFIG_ALT1);
+	mxc_iomux_set_pad(MX51_PIN_NANDF_D3, pad);
+
+	mxc_request_iomux(MX51_PIN_NANDF_D4, IOMUX_CONFIG_ALT1);
+	mxc_iomux_set_pad(MX51_PIN_NANDF_D4, pad);
+
+	mxc_request_iomux(MX51_PIN_NANDF_D5, IOMUX_CONFIG_ALT1);
+	mxc_iomux_set_pad(MX51_PIN_NANDF_D5, pad);
+
+	mxc_request_iomux(MX51_PIN_NANDF_D6, IOMUX_CONFIG_ALT1);
+	mxc_iomux_set_pad(MX51_PIN_NANDF_D6, pad);
+
+	mxc_request_iomux(MX51_PIN_NANDF_D7, IOMUX_CONFIG_ALT1);
+	mxc_iomux_set_pad(MX51_PIN_NANDF_D7, pad);
+
+	mxc_request_iomux(MX51_PIN_NANDF_D8, IOMUX_CONFIG_ALT1);
+	mxc_iomux_set_pad(MX51_PIN_NANDF_D8, pad);
+
+	mxc_request_iomux(MX51_PIN_NANDF_D9, IOMUX_CONFIG_ALT1);
+	mxc_iomux_set_pad(MX51_PIN_NANDF_D9, pad);
+
+	mxc_request_iomux(MX51_PIN_NANDF_D10, IOMUX_CONFIG_ALT1);
+	mxc_iomux_set_pad(MX51_PIN_NANDF_D10, pad);
+
+	mxc_request_iomux(MX51_PIN_NANDF_D11, IOMUX_CONFIG_ALT1);
+	mxc_iomux_set_pad(MX51_PIN_NANDF_D11, pad);
+
+	mxc_request_iomux(MX51_PIN_NANDF_D12, IOMUX_CONFIG_ALT1);
+	mxc_iomux_set_pad(MX51_PIN_NANDF_D12, pad);
+
+	mxc_request_iomux(MX51_PIN_NANDF_D13, IOMUX_CONFIG_ALT1);
+	mxc_iomux_set_pad(MX51_PIN_NANDF_D13, pad);
+
+	mxc_request_iomux(MX51_PIN_NANDF_D14, IOMUX_CONFIG_ALT1);
+	mxc_iomux_set_pad(MX51_PIN_NANDF_D14, pad);
+
+	mxc_request_iomux(MX51_PIN_NANDF_D15, IOMUX_CONFIG_ALT1);
+	mxc_iomux_set_pad(MX51_PIN_NANDF_D15, pad);
+
+	return 0;
+}
+#endif
+
+#ifdef CONFIG_I2C_MXC
+static setup_i2c(unsigned int module_base)
+{
+	unsigned int reg;
+
+	switch (module_base) {
+	case I2C1_BASE_ADDR:
+		reg = IOMUXC_BASE_ADDR + 0x210; /* i2c SDA */
+		writel(0x11, reg);
+		reg = IOMUXC_BASE_ADDR + 0x600;
+		writel(0x1ad, reg);
+		reg = IOMUXC_BASE_ADDR + 0x9B4;
+		writel(0x1, reg);
+
+		reg = IOMUXC_BASE_ADDR + 0x224; /* i2c SCL */
+		writel(0x11, reg);
+		reg = IOMUXC_BASE_ADDR + 0x614;
+		writel(0x1ad, reg);
+		reg = IOMUXC_BASE_ADDR + 0x9B0;
+		writel(0x1, reg);
+		break;
+	case I2C2_BASE_ADDR:
+		/* Workaround for Atlas Lite */
+		writel(0x0, IOMUXC_BASE_ADDR + 0x3CC); /* i2c SCL */
+		writel(0x0, IOMUXC_BASE_ADDR + 0x3D0); /* i2c SDA */
+		reg = readl(GPIO1_BASE_ADDR + 0x0);
+		reg |= 0xC;  /* write a 1 on the SCL and SDA lines */
+		writel(reg, GPIO1_BASE_ADDR + 0x0);
+		reg = readl(GPIO1_BASE_ADDR + 0x4);
+		reg |= 0xC;  /* configure GPIO lines as output */
+		writel(reg, GPIO1_BASE_ADDR + 0x4);
+		reg = readl(GPIO1_BASE_ADDR + 0x0);
+		reg &= ~0x4 ; /* set SCL low for a few milliseconds */
+		writel(reg, GPIO1_BASE_ADDR + 0x0);
+		udelay(20000);
+		reg |= 0x4;
+		writel(reg, GPIO1_BASE_ADDR + 0x0);
+		udelay(10);
+		reg = readl(GPIO1_BASE_ADDR + 0x4);
+		reg &= ~0xC;  /* configure GPIO lines back as input */
+		writel(reg, GPIO1_BASE_ADDR + 0x4);
+
+		writel(0x12, IOMUXC_BASE_ADDR + 0x3CC);  /* i2c SCL */
+		writel(0x3, IOMUXC_BASE_ADDR + 0x9B8);
+		writel(0x1ed, IOMUXC_BASE_ADDR + 0x7D4);
+
+		writel(0x12, IOMUXC_BASE_ADDR + 0x3D0); /* i2c SDA */
+		writel(0x3, IOMUXC_BASE_ADDR + 0x9BC);
+		writel(0x1ed, IOMUXC_BASE_ADDR + 0x7D8);
+		break;
+	default:
+		printf("Invalid I2C base: 0x%x\n", module_base);
+		break;
+	}
+}
+
+#define REV_ATLAS_LITE_1_0	   0x8
+#define REV_ATLAS_LITE_1_1	   0x9
+#define REV_ATLAS_LITE_2_0	   0x10
+#define REV_ATLAS_LITE_2_1	   0x11
+
+void setup_core_voltages(void)
+{
+	unsigned char buf[4] = { 0 };
+
+	i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
+
+	if (is_soc_rev(CHIP_REV_2_0) <= 0) {
+		/* Set core voltage to 1.1V */
+		if (i2c_read(0x8, 24, 1, buf, 3)) {
+			puts("setup_core_voltages: read PMIC@0x08:0x18 fail\n");
+			return;
+		}
+		buf[2] = (buf[2] & (~0x1F)) | 0x14;
+		if (i2c_write(0x8, 24, 1, buf, 3)) {
+			puts("setup_core_voltages: write PMIC@0x08:0x18 fail\n");
+			return;
+		}
+
+		/* Setup VCC (SW2) to 1.25 */
+		if (i2c_read(0x8, 25, 1, buf, 3)) {
+			puts("setup_core_voltages: read PMIC@0x08:0x19 fail\n");
+			return;
+		}
+		buf[2] = (buf[2] & (~0x1F)) | 0x1A;
+		if (i2c_write(0x8, 25, 1, buf, 3)) {
+			puts("setup_core_voltages: write PMIC@0x08:0x19 fail\n");
+			return;
+		}
+
+		/* Setup 1V2_DIG1 (SW3) to 1.25 */
+		if (i2c_read(0x8, 26, 1, buf, 3)) {
+			puts("setup_core_voltages: read PMIC@0x08:0x1A fail\n");
+			return;
+		}
+		buf[2] = (buf[2] & (~0x1F)) | 0x1A;
+		if (i2c_write(0x8, 26, 1, buf, 3)) {
+			puts("setup_core_voltages: write PMIC@0x08:0x1A fail\n");
+			return;
+		}
+
+		udelay(50);
+
+		/* Raise the core frequency to 800MHz */
+		writel(0x0, CCM_BASE_ADDR + CLKCTL_CACRR);
+	} else {
+		/* TO 3.0 */
+		/* Setup VCC (SW2) to 1.225 */
+		if (i2c_read(0x8, 25, 1, buf, 3)) {
+			puts("setup_core_voltages: read PMIC@0x08:0x19 fail\n");
+			return;
+		}
+		buf[2] = (buf[2] & (~0x1F)) | 0x19;
+		if (i2c_write(0x8, 25, 1, buf, 3)) {
+			puts("setup_core_voltages: write PMIC@0x08:0x19 fail\n");
+			return;
+		}
+
+		/* Setup 1V2_DIG1 (SW3) to 1.2 */
+		if (i2c_read(0x8, 26, 1, buf, 3)) {
+			puts("setup_core_voltages: read PMIC@0x08:0x1A fail\n");
+			return;
+		}
+		buf[2] = (buf[2] & (~0x1F)) | 0x18;
+		if (i2c_write(0x8, 26, 1, buf, 3)) {
+			puts("setup_core_voltages: write PMIC@0x08:0x1A fail\n");
+			return;
+		}
+	}
+
+	if (i2c_read(0x8, 7, 1, buf, 3)) {
+		puts("setup_core_voltages: read PMIC@0x08:0x07 fail\n");
+		return;
+	}
+
+	if (((buf[2] & 0x1F) < REV_ATLAS_LITE_2_0) || (((buf[1] >> 1) & 0x3) == 0)) {
+		/* Set switchers in PWM mode for Atlas 2.0 and lower */
+		/* Setup the switcher mode for SW1 & SW2*/
+		if (i2c_read(0x8, 28, 1, buf, 3)) {
+			puts("setup_core_voltages: read PMIC@0x08:0x1C fail\n");
+			return;
+		}
+		buf[2] = (buf[2] & (~0xF)) | 0x5;
+		buf[1] = (buf[1] & (~0x3C)) | 0x14;
+		if (i2c_write(0x8, 28, 1, buf, 3)) {
+			puts("setup_core_voltages: write PMIC@0x08:0x1C fail\n");
+			return;
+		}
+
+		/* Setup the switcher mode for SW3 & SW4*/
+		if (i2c_read(0x8, 29, 1, buf, 3)) {
+			puts("setup_core_voltages: read PMIC@0x08:0x1D fail\n");
+			return;
+		}
+		buf[2] = (buf[2] & (~0xF)) | 0x5;
+		buf[1] = (buf[1] & (~0xF)) | 0x5;
+		if (i2c_write(0x8, 29, 1, buf, 3)) {
+			puts("setup_core_voltages: write PMIC@0x08:0x1D fail\n");
+			return;
+		}
+	} else {
+		/* Set switchers in Auto in NORMAL mode & STANDBY mode for Atlas 2.0a */
+		/* Setup the switcher mode for SW1 & SW2*/
+		if (i2c_read(0x8, 28, 1, buf, 3)) {
+			puts("setup_core_voltages: read PMIC@0x08:0x1C fail\n");
+			return;
+		}
+		buf[2] = (buf[2] & (~0xF)) | 0x8;
+		buf[1] = (buf[1] & (~0x3C)) | 0x20;
+		if (i2c_write(0x8, 28, 1, buf, 3)) {
+			puts("setup_core_voltages: write PMIC@0x08:0x1C fail\n");
+			return;
+		}
+
+		/* Setup the switcher mode for SW3 & SW4*/
+		if (i2c_read(0x8, 29, 1, buf, 3)) {
+			puts("setup_core_voltages: read PMIC@0x08:0x1D fail\n");
+			return;
+		}
+		buf[2] = (buf[2] & (~0xF)) | 0x8;
+		buf[1] = (buf[1] & (~0xF)) | 0x8;
+		if (i2c_write(0x8, 29, 1, buf, 3)) {
+			puts("setup_core_voltages: write PMIC@0x08:0x1D fail\n");
+			return;
+		}
+	}
+}
+
+#endif
+
+int board_init(void)
+{
+	setup_boot_device();
+	setup_soc_rev();
+
+	gd->bd->bi_arch_number = MACH_TYPE_MX51_3DS;	/* board id for linux */
+	/* address of boot parameters */
+	gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
+
+	setup_uart();
+	setup_nfc();
+	setup_expio();
+#ifdef CONFIG_I2C_MXC
+	setup_i2c(I2C2_BASE_ADDR);
+	setup_core_voltages();
+#endif
+	return 0;
+}
+
+#ifdef CONFIG_ANDROID_RECOVERY
+struct reco_envs supported_reco_envs[BOOT_DEV_NUM] = {
+	{
+	 .cmd = CONFIG_ANDROID_RECOVERY_BOOTCMD_NAND,
+	 .args = CONFIG_ANDROID_RECOVERY_BOOTARGS_NAND,
+	 },
+	{
+	 .cmd = NULL,
+	 .args = NULL,
+	 },
+	{
+	 .cmd = CONFIG_ANDROID_RECOVERY_BOOTCMD_MMC,
+	 .args = CONFIG_ANDROID_RECOVERY_BOOTARGS_MMC,
+	 },
+};
+
+static int check_mmc_recovery_cmd_file(int dev_num, int part_num, char *path)
+{
+	block_dev_desc_t *dev_desc = NULL;
+	struct mmc *mmc = find_mmc_device(dev_num);
+	disk_partition_t info;
+	ulong part_length = 0;
+	int filelen = 0;
+
+	memset(&info, 0, sizeof(disk_partition_t));
+
+	dev_desc = get_dev("mmc", dev_num);
+
+	if (NULL == dev_desc) {
+		printf("** Block device MMC %d not supported\n",
+				dev_num);
+		return 0;
+	}
+
+	mmc_init(mmc);
+
+	if (get_partition_info(dev_desc,
+			part_num,
+			&info)) {
+		printf("** Bad partition %d **\n",
+			part_num);
+		return 0;
+	}
+
+	part_length = ext2fs_set_blk_dev(dev_desc,
+						part_num);
+	if (part_length == 0) {
+		printf("** Bad partition - mmc 0:%d **\n",
+			part_num);
+		ext2fs_close();
+		return 0;
+	}
+
+	if (!ext2fs_mount(part_length)) {
+		printf("** Bad ext2 partition or disk - mmc 0:%d **\n",
+			part_num);
+		ext2fs_close();
+		return 0;
+	}
+
+	filelen = ext2fs_open(path);
+
+	ext2fs_close();
+
+	return (filelen > 0) ? 1 : 0;
+}
+
+extern int ubifs_init(void);
+extern int ubifs_mount(char *vol_name);
+extern int ubifs_load(char *filename, u32 addr, u32 size);
+
+static int check_nand_recovery_cmd_file(char *mtd_part_name,
+				char *ubi_part_name,
+				char *path)
+{
+	struct mtd_device *dev_desc = NULL;
+	struct part_info *part = NULL;
+	struct mtd_partition mtd_part;
+	struct mtd_info *mtd_info = NULL;
+	char mtd_dev[16] = { 0 };
+	char mtd_buffer[80] = { 0 };
+	u8 pnum = 0,
+	   read_test = 0;
+	int err = 0,
+		filelen = 0;
+
+	memset(&mtd_part, 0, sizeof(struct mtd_partition));
+
+	/* ========== ubi and mtd operations ========== */
+	if (mtdparts_init() != 0) {
+		printf("Error initializing mtdparts!\n");
+		return 0;
+	}
+
+	if (find_dev_and_part(mtd_part_name, &dev_desc, &pnum, &part)) {
+		printf("Partition %s not found!\n", mtd_part_name);
+		return 0;
+	}
+	sprintf(mtd_dev, "%s%d",
+			MTD_DEV_TYPE(dev_desc->id->type),
+			dev_desc->id->num);
+	mtd_info = get_mtd_device_nm(mtd_dev);
+	if (IS_ERR(mtd_info)) {
+		printf("Partition %s not found on device %s!\n",
+			"nand", mtd_dev);
+		return 0;
+	}
+
+	sprintf(mtd_buffer, "mtd=%d", pnum);
+	memset(&mtd_part, 0, sizeof(mtd_part));
+	mtd_part.name = mtd_buffer;
+	mtd_part.size = part->size;
+	mtd_part.offset = part->offset;
+	add_mtd_partitions(mtd_info, &mtd_part, 1);
+
+	err = ubi_mtd_param_parse(mtd_buffer, NULL);
+	if (err) {
+		del_mtd_partitions(mtd_info);
+		return 0;
+	}
+
+	err = ubi_init();
+	if (err) {
+		del_mtd_partitions(mtd_info);
+		return 0;
+	}
+
+	/* ========== ubifs operations ========== */
+	/* Init ubifs */
+	ubifs_init();
+
+	if (ubifs_mount(ubi_part_name)) {
+		printf("Mount ubifs volume %s fail!\n",
+				ubi_part_name);
+		return 0;
+	}
+
+	/* Try to read one byte for a read test. */
+	if (ubifs_load(path, (u32)&read_test, 1)) {
+		/* File not found */
+		filelen = 0;
+	} else
+		filelen = 1;
+
+	return filelen;
+}
+
+int check_recovery_cmd_file(void)
+{
+	int if_exist = 0;
+	char *env = NULL;
+
+	switch (get_boot_device()) {
+	case MMC_BOOT:
+		if_exist = check_mmc_recovery_cmd_file(0,
+				CONFIG_ANDROID_CACHE_PARTITION_MMC,
+				CONFIG_ANDROID_RECOVERY_CMD_FILE);
+		break;
+	case NAND_BOOT:
+		env = getenv("mtdparts");
+		if (!env)
+			setenv("mtdparts", MTDPARTS_DEFAULT);
+
+		env = getenv("mtdids");
+		if (!env)
+			setenv("mtdids", MTDIDS_DEFAULT);
+
+		env = getenv("partition");
+		if (!env)
+			setenv("partition", MTD_ACTIVE_PART);
+
+		/*
+		if_exist = check_nand_recovery_cmd_file(CONFIG_ANDROID_UBIFS_PARTITION_NM,
+						CONFIG_ANDROID_CACHE_PARTITION_NAND,
+						CONFIG_ANDROID_RECOVERY_CMD_FILE);
+		*/
+		break;
+	case SPI_NOR_BOOT:
+		return 0;
+		break;
+	case UNKNOWN_BOOT:
+	default:
+		return 0;
+		break;
+	}
+
+	return if_exist;
+}
+#endif
+
+#ifdef BOARD_LATE_INIT
+int board_late_init(void)
+{
+	return 0;
+}
+#endif
+
+int checkboard(void)
+{
+	printf("Board: MX51 3STACK ");
+
+	if (system_rev & CHIP_REV_2_0) {
+		printf("2.0 [");
+	} else if (system_rev & CHIP_REV_1_1) {
+		printf("1.1 [");
+	} else {
+		printf("1.0 [");
+	}
+
+	switch (__REG(SRC_BASE_ADDR + 0x8)) {
+	case 0x0001:
+		printf("POR");
+		break;
+	case 0x0009:
+		printf("RST");
+		break;
+	case 0x0010:
+	case 0x0011:
+		printf("WDOG");
+		break;
+	default:
+		printf("unknown");
+	}
+	printf("]\n");
+
+	printf("Boot Device: ");
+	switch (get_boot_device()) {
+	case NAND_BOOT:
+		printf("NAND\n");
+		break;
+	case SPI_NOR_BOOT:
+		printf("SPI NOR\n");
+		break;
+	case MMC_BOOT:
+		printf("MMC\n");
+		break;
+	case UNKNOWN_BOOT:
+	default:
+		printf("UNKNOWN\n");
+		break;
+	}
+
+	return 0;
+}
+
+#if defined(CONFIG_SMC911X)
+extern int smc911x_initialize(u8 dev_num, int base_addr);
+#endif
+
+#ifdef CONFIG_NET_MULTI
+int board_eth_init(bd_t *bis)
+{
+	int rc = -ENODEV;
+#if defined(CONFIG_SMC911X)
+	rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);
+#endif
+
+	cpu_eth_init(bis);
+
+	return rc;
+}
+#endif
+
+#ifdef CONFIG_CMD_MMC
+
+struct fsl_esdhc_cfg esdhc_cfg[2] = {
+	{MMC_SDHC1_BASE_ADDR, 1, 1},
+};
+
+#ifdef CONFIG_DYNAMIC_MMC_DEVNO
+int get_mmc_env_devno()
+{
+	uint soc_sbmr = readl(SRC_BASE_ADDR + 0x4);
+	return (soc_sbmr & 0x00180000) ? 1 : 0;
+}
+#endif
+
+int esdhc_gpio_init(bd_t *bis)
+{
+	u32 index = 0;
+	s32 status = 0;
+
+	for (index = 0; index < CONFIG_SYS_FSL_ESDHC_NUM;
+		++index) {
+		switch (index) {
+		case 0:
+			mxc_request_iomux(MX51_PIN_SD1_CMD,
+				  IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
+			mxc_request_iomux(MX51_PIN_SD1_CLK,
+				  IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
+
+			mxc_request_iomux(MX51_PIN_SD1_DATA0,
+					IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
+			mxc_request_iomux(MX51_PIN_SD1_DATA1,
+					IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
+			mxc_request_iomux(MX51_PIN_SD1_DATA2,
+					IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
+			mxc_request_iomux(MX51_PIN_SD1_DATA3,
+					IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
+			mxc_iomux_set_pad(MX51_PIN_SD1_CMD,
+					PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH |
+					PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU |
+					PAD_CTL_PUE_PULL |
+					PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
+			mxc_iomux_set_pad(MX51_PIN_SD1_CLK,
+					PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH |
+					PAD_CTL_HYS_NONE | PAD_CTL_47K_PU |
+					PAD_CTL_PUE_PULL |
+					PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
+			mxc_iomux_set_pad(MX51_PIN_SD1_DATA0,
+					PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH |
+					PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU |
+					PAD_CTL_PUE_PULL |
+					PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
+			mxc_iomux_set_pad(MX51_PIN_SD1_DATA1,
+					PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH |
+					PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU |
+					PAD_CTL_PUE_PULL |
+					PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
+			mxc_iomux_set_pad(MX51_PIN_SD1_DATA2,
+					PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH |
+					PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU |
+					PAD_CTL_PUE_PULL |
+					PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
+			mxc_iomux_set_pad(MX51_PIN_SD1_DATA3,
+					PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH |
+					PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PD |
+					PAD_CTL_PUE_PULL |
+					PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
+			break;
+		case 1:
+			status = 1;
+			break;
+		case 2:
+			status = 1;
+			break;
+		case 3:
+			status = 1;
+			break;
+		default:
+			status = 1;
+			break;
+		}
+		status |= fsl_esdhc_initialize(bis, &esdhc_cfg[index]);
+	}
+
+	return status;
+}
+
+int board_mmc_init(bd_t *bis)
+{
+	if (!esdhc_gpio_init(bis))
+		return fsl_esdhc_mmc_init(gd->bd);
+	else
+		return -1;
+}
+#endif
+
+#if defined(CONFIG_MXC_KPD)
+int setup_mxc_kpd(void)
+{
+	mxc_request_iomux(MX51_PIN_KEY_COL0, IOMUX_CONFIG_ALT0);
+	mxc_request_iomux(MX51_PIN_KEY_COL1, IOMUX_CONFIG_ALT0);
+	mxc_request_iomux(MX51_PIN_KEY_COL2, IOMUX_CONFIG_ALT0);
+	mxc_request_iomux(MX51_PIN_KEY_COL3, IOMUX_CONFIG_ALT0);
+	mxc_request_iomux(MX51_PIN_KEY_COL4, IOMUX_CONFIG_ALT0);
+	mxc_request_iomux(MX51_PIN_KEY_COL5, IOMUX_CONFIG_ALT0);
+	mxc_request_iomux(MX51_PIN_KEY_ROW0, IOMUX_CONFIG_ALT0);
+	mxc_request_iomux(MX51_PIN_KEY_ROW1, IOMUX_CONFIG_ALT0);
+	mxc_request_iomux(MX51_PIN_KEY_ROW2, IOMUX_CONFIG_ALT0);
+	mxc_request_iomux(MX51_PIN_KEY_ROW3, IOMUX_CONFIG_ALT0);
+
+	return 0;
+}
+#endif

board/freescale/mx51_3stack/u-boot.lds

@@ -0,0 +1,73 @@
+/*
+ * January 2004 - Changed to support H4 device
+ * Copyright (c) 2004 Texas Instruments
+ *
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
+ *
+ * (C) Copyright 2009 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+	. = 0x00000000;
+
+	. = ALIGN(4);
+	.text	   :
+	{
+	  /* WARNING - the following is hand-optimized to fit within	*/
+	  /* the sector layout of our flash chips!	XXX FIXME XXX	*/
+	  board/freescale/mx51_3stack/flash_header.o	(.text.flasheader)
+	  cpu/arm_cortexa8/start.o
+	  board/freescale/mx51_3stack/libmx51_3stack.a	(.text)
+	  lib_arm/libarm.a		(.text)
+	  net/libnet.a			(.text)
+	  drivers/mtd/libmtd.a		(.text)
+	  drivers/mmc/libmmc.a		(.text)
+
+	  . = DEFINED(env_offset) ? env_offset : .;
+	  common/env_embedded.o(.text)
+
+	  *(.text)
+	}
+
+	. = ALIGN(4);
+	.rodata : { *(.rodata) }
+
+	. = ALIGN(4);
+	.data : { *(.data) }
+
+	. = ALIGN(4);
+	.got : { *(.got) }
+
+	. = .;
+	__u_boot_cmd_start = .;
+	.u_boot_cmd : { *(.u_boot_cmd) }
+	__u_boot_cmd_end = .;
+
+	. = ALIGN(4);
+	__bss_start = .;
+	.bss : { *(.bss) }
+	_end = .;
+}

board/freescale/mx51_bbg/Makefile

@@ -0,0 +1,49 @@
+#
+# Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
+#
+# (C) Copyright 2009 Freescale Semiconductor, Inc.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).a
+
+COBJS	:= mx51_bbg.o
+SOBJS	:= lowlevel_init.o flash_header.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################

board/freescale/mx51_bbg/board-imx51.h

@@ -0,0 +1,64 @@
+/*
+ * Copyright 2009 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#ifndef __BOARD_FREESCALE_BOARD_IMX51_H__
+#define __BOARD_FREESCALE_BOARD_IMX51_H__
+
+/*!
+ * @defgroup BRDCFG_MX51 Board Configuration Options
+ * @ingroup MSL_MX51
+ */
+
+/*!
+ * @file mx51_3stack/board-imx51.h
+ *
+ * @brief This file contains all the board level configuration options.
+ *
+ * It currently hold the options defined for MX51 3Stack Platform.
+ *
+ * @ingroup BRDCFG_IMX51
+ */
+
+/* CPLD offsets */
+#define PBC_LED_CTRL		(0x20000)
+#define PBC_SB_STAT		(0x20008)
+#define PBC_ID_AAAA		(0x20040)
+#define PBC_ID_5555		(0x20048)
+#define PBC_VERSION		(0x20050)
+#define PBC_ID_CAFE		(0x20058)
+#define PBC_INT_STAT		(0x20010)
+#define PBC_INT_MASK		(0x20038)
+#define PBC_INT_REST		(0x20020)
+#define PBC_SW_RESET		(0x20060)
+
+/* LED switchs */
+#define LED_SWITCH_REG		0x00
+/* buttons */
+#define SWITCH_BUTTONS_REG	0x08
+/* status, interrupt */
+#define INTR_STATUS_REG	0x10
+#define INTR_MASK_REG		0x38
+#define INTR_RESET_REG		0x20
+/* magic word for debug CPLD */
+#define MAGIC_NUMBER1_REG	0x40
+#define MAGIC_NUMBER2_REG	0x48
+/* CPLD code version */
+#define CPLD_CODE_VER_REG	0x50
+/* magic word for debug CPLD */
+#define MAGIC_NUMBER3_REG	0x58
+/* module reset register*/
+#define MODULE_RESET_REG	0x60
+/* CPU ID and Personality ID */
+#define MCU_BOARD_ID_REG	0x68
+
+#endif				/* __BOARD_FREESCALE_BOARD_IMX51_H__ */

board/freescale/mx51_bbg/config.mk

@@ -0,0 +1,7 @@
+LDSCRIPT := $(SRCTREE)/board/$(VENDOR)/$(BOARD)/u-boot.lds
+
+sinclude $(OBJTREE)/board/$(VENDOR)/$(BOARD)/config.tmp
+
+ifndef TEXT_BASE
+	TEXT_BASE = 0x97800000
+endif

board/freescale/mx51_bbg/flash_header.S

@@ -0,0 +1,112 @@
+/*
+ * (C) Copyright 2009-2010 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <asm/arch/mx51.h>
+#include "board-imx51.h"
+
+#ifdef	CONFIG_FLASH_HEADER
+#ifndef CONFIG_FLASH_HEADER_OFFSET
+# error "Must define the offset of flash header"
+#endif
+#define MXC_DCD_ITEM(i, type, addr, val)	\
+dcd_node_##i:					\
+	.word type			;	\
+	.word addr			;	\
+	.word val			;	\
+
+.section ".text.flasheader", "x"
+	b	_start
+	.org	CONFIG_FLASH_HEADER_OFFSET
+app_code_jump_v:	.word	_start
+app_code_code_barker:	.word	CONFIG_FLASH_HEADER_BARKER
+app_code_csf:		.word	0
+dcd_ptr_ptr:		.word	dcd_ptr
+super_root_key:		.word	0
+dcd_ptr:		.word	dcd_array_start
+app_dest_ptr:		.word	TEXT_BASE
+dcd_array_start:
+magic:			.word	0xB17219E9
+dcd_array_size:		.word	dcd_data_end - dcd_array_start - 8
+/* DCD */
+/* DDR2 IOMUX configuration */
+MXC_DCD_ITEM(1, 4, IOMUXC_BASE_ADDR + 0x8a0, 0x200)
+MXC_DCD_ITEM(2, 4, IOMUXC_BASE_ADDR + 0x50c, 0x20c5)
+MXC_DCD_ITEM(3, 4, IOMUXC_BASE_ADDR + 0x510, 0x20c5)
+MXC_DCD_ITEM(4, 4, IOMUXC_BASE_ADDR + 0x83c, 0x2)
+MXC_DCD_ITEM(5, 4, IOMUXC_BASE_ADDR + 0x848, 0x2)
+MXC_DCD_ITEM(6, 4, IOMUXC_BASE_ADDR + 0x4b8, 0xe7)
+MXC_DCD_ITEM(7, 4, IOMUXC_BASE_ADDR + 0x4bc, 0x45)
+MXC_DCD_ITEM(8, 4, IOMUXC_BASE_ADDR + 0x4c0, 0x45)
+MXC_DCD_ITEM(9, 4, IOMUXC_BASE_ADDR + 0x4c4, 0x45)
+MXC_DCD_ITEM(10, 4, IOMUXC_BASE_ADDR + 0x4c8, 0x45)
+MXC_DCD_ITEM(11, 4, IOMUXC_BASE_ADDR + 0x820, 0x0)
+MXC_DCD_ITEM(12, 4, IOMUXC_BASE_ADDR + 0x4a4, 0x3)
+MXC_DCD_ITEM(13, 4, IOMUXC_BASE_ADDR + 0x4a8, 0x3)
+MXC_DCD_ITEM(14, 4, IOMUXC_BASE_ADDR + 0x4ac, 0xe3)
+MXC_DCD_ITEM(15, 4, IOMUXC_BASE_ADDR + 0x4b0, 0xe3)
+MXC_DCD_ITEM(16, 4, IOMUXC_BASE_ADDR + 0x4b4, 0xe3)
+MXC_DCD_ITEM(17, 4, IOMUXC_BASE_ADDR + 0x4cc, 0xe3)
+MXC_DCD_ITEM(18, 4, IOMUXC_BASE_ADDR + 0x4d0, 0xe2)
+/* Set drive strength to MAX */
+MXC_DCD_ITEM(19, 4, IOMUXC_BASE_ADDR + 0x82c, 0x4)
+MXC_DCD_ITEM(20, 4, IOMUXC_BASE_ADDR + 0x8a4, 0x4)
+MXC_DCD_ITEM(21, 4, IOMUXC_BASE_ADDR + 0x8ac, 0x4)
+MXC_DCD_ITEM(22, 4, IOMUXC_BASE_ADDR + 0x8b8, 0x4)
+/* 13 ROW, 10 COL, 32Bit, SREF=4 Micron Model */
+/* CAS=3,  BL=4 */
+MXC_DCD_ITEM(23, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDCTL0, 0x82a20000)
+MXC_DCD_ITEM(24, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDCTL1, 0x82a20000)
+MXC_DCD_ITEM(25, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDMISC, 0x000ad0d0)
+MXC_DCD_ITEM(26, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDCFG0, 0x333584ab)
+MXC_DCD_ITEM(27, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDCFG1, 0x333584ab)
+/* Init DRAM on CS0 */
+MXC_DCD_ITEM(28, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x04008008)
+MXC_DCD_ITEM(29, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x0000801a)
+MXC_DCD_ITEM(30, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x0000801b)
+MXC_DCD_ITEM(31, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x00448019)
+MXC_DCD_ITEM(32, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x07328018)
+MXC_DCD_ITEM(33, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x04008008)
+MXC_DCD_ITEM(34, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x00008010)
+MXC_DCD_ITEM(35, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x00008010)
+MXC_DCD_ITEM(36, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x06328018)
+MXC_DCD_ITEM(37, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x03808019)
+MXC_DCD_ITEM(38, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x00408019)
+MXC_DCD_ITEM(39, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x00008000)
+/* Init DRAM on CS1 */
+MXC_DCD_ITEM(40, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x0400800c)
+MXC_DCD_ITEM(41, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x0000801e)
+MXC_DCD_ITEM(42, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x0000801f)
+MXC_DCD_ITEM(43, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x0000801d)
+MXC_DCD_ITEM(44, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x0732801c)
+MXC_DCD_ITEM(45, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x0400800c)
+MXC_DCD_ITEM(46, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x00008014)
+MXC_DCD_ITEM(47, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x00008014)
+MXC_DCD_ITEM(48, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x0632801c)
+MXC_DCD_ITEM(49, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x0380801d)
+MXC_DCD_ITEM(50, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x0040801d)
+MXC_DCD_ITEM(51, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x00008004)
+MXC_DCD_ITEM(52, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDCTL0, 0xb2a20000)
+MXC_DCD_ITEM(53, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDCTL1, 0xb2a20000)
+MXC_DCD_ITEM(54, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDMISC, 0x000ad6d0)
+MXC_DCD_ITEM(55, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDCDLYGD, 0x90000000)
+MXC_DCD_ITEM(56, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x00000000)
+dcd_data_end:
+image_len:		.word	_end - TEXT_BASE
+#endif

board/freescale/mx51_bbg/lowlevel_init.S

@@ -0,0 +1,372 @@
+/*
+ * Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
+ *
+ * (C) Copyright 2009-2011 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <asm/arch/mx51.h>
+#include "board-imx51.h"
+
+/*
+ * return soc version
+ * 	0x10:  TO1
+ *	0x20:  TO2
+ *	0x30:  TO3
+ */
+.macro check_soc_version ret, tmp
+.endm
+
+/*
+ * L2CC Cache setup/invalidation/disable
+ */
+.macro init_l2cc
+	/* explicitly disable L2 cache */
+        mrc 15, 0, r0, c1, c0, 1
+        bic r0, r0, #0x2
+        mcr 15, 0, r0, c1, c0, 1
+
+        /* reconfigure L2 cache aux control reg */
+        mov r0, #0xC0                   /* tag RAM */
+        add r0, r0, #0x4                /* data RAM */
+        orr r0, r0, #(1 << 24)          /* disable write allocate delay */
+        orr r0, r0, #(1 << 23)          /* disable write allocate combine */
+        orr r0, r0, #(1 << 22)          /* disable write allocate */
+
+	ldr r1, =0x00000000
+	ldr r3, [r1, #ROM_SI_REV]
+	cmp r3, #0x10    /* r3 contains the silicon rev */
+	orrls r0, r0, #(1 << 25)    /* disable write combine for TO 2 and lower revs */
+
+	mcr 15, 1, r0, c9, c0, 2
+.endm /* init_l2cc */
+
+/* AIPS setup - Only setup MPROTx registers.
+ * The PACR default values are good.*/
+.macro init_aips
+	/*
+	 * Set all MPROTx to be non-bufferable, trusted for R/W,
+	 * not forced to user-mode.
+	 */
+	ldr r0, =AIPS1_BASE_ADDR
+	ldr r1, =0x77777777
+	str r1, [r0, #0x0]
+	str r1, [r0, #0x4]
+	ldr r0, =AIPS2_BASE_ADDR
+	str r1, [r0, #0x0]
+	str r1, [r0, #0x4]
+	/*
+	 * Clear the on and off peripheral modules Supervisor Protect bit
+	 * for SDMA to access them. Did not change the AIPS control registers
+	 * (offset 0x20) access type
+	 */
+.endm /* init_aips */
+
+/* MAX (Multi-Layer AHB Crossbar Switch) setup */
+.macro init_max
+.endm /* init_max */
+
+/* M4IF setup */
+.macro init_m4if
+	/* VPU and IPU given higher priority (0x4)
+	 * IPU accesses with ID=0x1 given highest priority (=0xA)
+	 */
+	ldr r0, =M4IF_BASE_ADDR
+
+	ldr r1, =0x00000203
+	str r1, [r0, #0x40]
+
+	ldr r1, =0x0
+	str r1, [r0, #0x44]
+
+	ldr r1, =0x00120125
+	str r1, [r0, #0x9C]
+
+	ldr r1, =0x001901A3
+	str r1, [r0, #0x48]
+
+/*
+	ldr r1, =0x00000a01
+	str r1, [r0, #0x48]
+	ldr r1, =0x00000404
+	str r1, [r0, #0x40]
+*/
+.endm /* init_m4if */
+
+/* To support 133MHz DDR */
+.macro  init_drive_strength
+.endm /* init_drive_strength */
+
+/* CPLD on CS5 setup */
+.macro init_debug_board
+.endm /* init_debug_board */
+
+.macro setup_pll pll, freq
+	ldr r2, =\pll
+
+	ldr r1, =PLL1_BASE_ADDR
+	cmp r1, r2
+	bne    5f
+
+	ldr r1, [r2, #PLL_DP_CONFIG]
+	bic r1, r1, #0x2
+	str r1, [r2, #PLL_DP_CONFIG] /* disable auto-restart AREN bit */
+
+5:	str r3, [r2, #PLL_DP_OP]
+	str r3, [r2, #PLL_DP_HFS_OP]
+
+	str r4, [r2, #PLL_DP_MFD]
+	str r4, [r2, #PLL_DP_HFS_MFD]
+
+	str r5, [r2, #PLL_DP_MFN]
+	str r5, [r2, #PLL_DP_HFS_MFN]
+
+
+	ldr r1, =PLL1_BASE_ADDR
+	cmp r1, r2
+	bne    6f
+	ldr r1, =0x00001236 /* Set PLM =1, manual restart and enable PLL*/
+	b       7f
+
+6:	ldr r1, =0x00001232
+
+7:	str r1, [r2, #PLL_DP_CTL]
+
+1:	ldr r1, [r2, #PLL_DP_CTL]
+	ands r1, r1, #0x1
+	beq 1b
+
+	/* Workaround for PLL1 issue */
+	ldr r1, =PLL1_BASE_ADDR
+	cmp r1, r2
+	bne 4f
+
+	/* set PLL1 to 800Mhz */
+	ldr r1, =60
+	str r1, [r2, #PLL_DP_MFN]
+
+	ldr r1, [r2, #PLL_DP_CONFIG]
+	orr r1, r1, #1 /* set LDREQ */
+	str r1, [r2, #PLL_DP_CONFIG]
+
+      /* Wait till LDREQ bit is cleared. */
+2:	ldr r1, [r2, #PLL_DP_CONFIG]
+	tst r1, #1
+	bne 2b
+
+	mov r0, #100 /* delay more than 4.6 us */
+3:      subs r0, r0, #1
+	bge 3b
+4:
+.endm
+
+.macro init_clock
+	ldr r0, =CCM_BASE_ADDR
+
+	/* Gate of clocks to the peripherals first */
+	ldr r1, =0x3FFFFFFF
+	str r1, [r0, #CLKCTL_CCGR0]
+	ldr r1, =0x0
+	str r1, [r0, #CLKCTL_CCGR1]
+	str r1, [r0, #CLKCTL_CCGR2]
+	str r1, [r0, #CLKCTL_CCGR3]
+
+	ldr r1, =0x00030000
+	str r1, [r0, #CLKCTL_CCGR4]
+	ldr r1, =0x00FFF030
+	str r1, [r0, #CLKCTL_CCGR5]
+	ldr r1, =0x00000300
+	str r1, [r0, #CLKCTL_CCGR6]
+
+        /* Disable IPU and HSC dividers */
+        mov r1, #0x60000
+        str r1, [r0, #CLKCTL_CCDR]
+
+	/* PLL1 workaround */
+	/* (1). switch off all clock from PLL1, CPU/DDR */
+	/* Make sure to switch the DDR away from PLL 1 */
+	ldr r1, =0x19239145
+	str r1, [r0, #CLKCTL_CBCDR]
+	/* make sure divider effective */
+1:	ldr r1, [r0, #CLKCTL_CDHIPR]
+	cmp r1, #0x0
+	bne 1b
+
+	/* Make sure step clock is 24MHz OSC. */
+	ldr   r1, [r0, #CLKCTL_CCSR]
+	bic  r1, r1, #(3 << 7)
+	str  r1, [r0, #CLKCTL_CCSR]
+
+	/* Switch ARM to step clock */
+	ldr   r1, [r0, #CLKCTL_CCSR]
+	orr  r1, r1, #4
+	str r1, [r0, #CLKCTL_CCSR]
+
+	/* PLL1 workaround:|MFN/(MFD+1)| <1 */
+	mov r3, #0x80 /* MFI = 8*/
+	mov r4, #179 /* MFD = 179 */
+	mov r5, #180 /* MFN = 180 */
+	setup_pll PLL1_BASE_ADDR
+
+	mov r3, #DP_OP_665
+	mov r4, #DP_MFD_665
+	mov r5, #DP_MFN_665
+	setup_pll PLL3_BASE_ADDR
+
+	/* Switch peripheral to PLL 3 */
+	ldr r0, =CCM_BASE_ADDR
+        ldr r1, =0x000010C0
+	str r1, [r0, #CLKCTL_CBCMR]
+	ldr r1, =0x13239145
+	str r1, [r0, #CLKCTL_CBCDR]
+	mov r3, #DP_OP_665
+	mov r4, #DP_MFD_665
+	mov r5, #DP_MFN_665
+	setup_pll PLL2_BASE_ADDR
+
+	/* Switch peripheral to PLL2 */
+	ldr r0, =CCM_BASE_ADDR
+	ldr r1, =0x19239145
+	str r1, [r0, #CLKCTL_CBCDR]
+	ldr r1, =0x000020C0
+	str r1, [r0, #CLKCTL_CBCMR]
+
+	mov r3, #DP_OP_216
+	mov r4, #DP_MFD_216
+	mov r5, #DP_MFN_216
+	setup_pll PLL3_BASE_ADDR
+
+
+	/* Set the platform clock dividers */
+	ldr r0, =ARM_BASE_ADDR
+	ldr r1, =0x00000725
+	str r1, [r0, #0x14]
+
+	ldr r0, =CCM_BASE_ADDR
+	/* Run TO 3.0 at Full speed, for other TO's wait till we increase VDDGP */
+	ldr r1, =0x0
+	ldr r3, [r1, #ROM_SI_REV]
+	cmp r3, #0x10
+	movls r1, #0x1
+	movhi r1, #0
+	str r1, [r0, #CLKCTL_CACRR]
+
+	/* Switch ARM back to PLL 1 */
+	mov r1, #0
+	str r1, [r0, #CLKCTL_CCSR]
+
+	/* setup the rest */
+	/* Use lp_apm (24MHz) source for perclk */
+	ldr r1, =0x000020C2
+	str r1, [r0, #CLKCTL_CBCMR]
+	/* ddr clock from PLL 1, all perclk dividers are 1 since using 24MHz */
+	ldr r1, =0x59E35100
+	str r1, [r0, #CLKCTL_CBCDR]
+
+	/* Restore the default values in the Gate registers */
+	ldr r1, =0xFFFFFFFF
+	str r1, [r0, #CLKCTL_CCGR0]
+	str r1, [r0, #CLKCTL_CCGR1]
+	str r1, [r0, #CLKCTL_CCGR2]
+	str r1, [r0, #CLKCTL_CCGR3]
+	str r1, [r0, #CLKCTL_CCGR4]
+	str r1, [r0, #CLKCTL_CCGR5]
+	str r1, [r0, #CLKCTL_CCGR6]
+
+	/* Use PLL 2 for UART's, get 66.5MHz from it */
+	ldr r1, =0xA5A2A020
+	str r1, [r0, #CLKCTL_CSCMR1]
+	ldr r1, =0x00C30321
+	str r1, [r0, #CLKCTL_CSCDR1]
+
+	/* make sure divider effective */
+1:	ldr r1, [r0, #CLKCTL_CDHIPR]
+	cmp r1, #0x0
+	bne 1b
+
+	mov r1, #0x0
+	str r1, [r0, #CLKCTL_CCDR]
+
+	/* for cko - for ARM div by 8 */
+	mov r1, #0x000A0000
+	add r1, r1, #0x00000F0
+	str r1, [r0, #CLKCTL_CCOSR]
+.endm
+
+.macro setup_wdog
+	ldr r0, =WDOG1_BASE_ADDR
+	mov r1, #0x30
+	strh r1, [r0]
+.endm
+
+.section ".text.init", "x"
+
+.globl lowlevel_init
+lowlevel_init:
+	ldr r0, =GPIO1_BASE_ADDR
+	ldr r1, [r0, #0x0]
+	orr r1, r1, #(1 << 23)
+	str r1, [r0, #0x0]
+	ldr r1, [r0, #0x4]
+	orr r1, r1, #(1 << 23)
+	str r1, [r0, #0x4]
+
+#ifdef ENABLE_IMPRECISE_ABORT
+        mrs r1, spsr            /* save old spsr */
+        mrs r0, cpsr            /* read out the cpsr */
+	bic r0, r0, #0x100      /* clear the A bit */
+	msr spsr, r0            /* update spsr */
+	add lr, pc, #0x8        /* update lr */
+        movs pc, lr             /* update cpsr */
+        nop
+        nop
+        nop
+	nop
+	msr spsr, r1            /* restore old spsr */
+#endif
+
+	/* ARM errata ID #468414 */
+	mrc 15, 0, r1, c1, c0, 1
+	orr r1, r1, #(1 << 5)    /* enable L1NEON bit */
+	mcr 15, 0, r1, c1, c0, 1
+
+	init_l2cc
+
+	init_aips
+
+	init_max
+
+	init_m4if
+
+	init_drive_strength
+
+	init_clock
+
+	init_debug_board
+
+	/* return from mxc_nand_load */
+	/* r12 saved upper lr*/
+	b mxc_nand_load
+
+/* Board level setting value */
+DDR_PERCHARGE_CMD:	.word 0x04008008
+DDR_REFRESH_CMD:	.word 0x00008010
+DDR_LMR1_W:		.word 0x00338018
+DDR_LMR_CMD:		.word 0xB2220000
+DDR_TIMING_W:		.word 0xB02567A9
+DDR_MISC_W:		.word 0x000A0104

board/freescale/mx51_bbg/u-boot.lds

@@ -0,0 +1,73 @@
+/*
+ * January 2004 - Changed to support H4 device
+ * Copyright (c) 2004 Texas Instruments
+ *
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
+ *
+ * (C) Copyright 2009 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+	. = 0x00000000;
+
+	. = ALIGN(4);
+	.text	   :
+	{
+	  /* WARNING - the following is hand-optimized to fit within	*/
+	  /* the sector layout of our flash chips!	XXX FIXME XXX	*/
+	  board/freescale/mx51_bbg/flash_header.o	(.text.flasheader)
+	  cpu/arm_cortexa8/start.o
+	  board/freescale/mx51_bbg/libmx51_bbg.a	(.text)
+	  lib_arm/libarm.a		(.text)
+	  net/libnet.a			(.text)
+	  drivers/mtd/libmtd.a		(.text)
+	  drivers/mmc/libmmc.a		(.text)
+
+	  . = DEFINED(env_offset) ? env_offset : .;
+	  common/env_embedded.o(.text)
+
+	  *(.text)
+	}
+
+	. = ALIGN(4);
+	.rodata : { *(.rodata) }
+
+	. = ALIGN(4);
+	.data : { *(.data) }
+
+	. = ALIGN(4);
+	.got : { *(.got) }
+
+	. = .;
+	__u_boot_cmd_start = .;
+	.u_boot_cmd : { *(.u_boot_cmd) }
+	__u_boot_cmd_end = .;
+
+	. = ALIGN(4);
+	__bss_start = .;
+	.bss : { *(.bss) }
+	_end = .;
+}

board/freescale/mx53_ard/Makefile

@@ -0,0 +1,49 @@
+#
+# Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
+#
+# (C) Copyright 2010 Freescale Semiconductor, Inc.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).a
+
+COBJS	:= mx53_ard.o
+SOBJS	:= lowlevel_init.o flash_header.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################

board/freescale/mx53_ard/config.mk

@@ -0,0 +1,3 @@
+LDSCRIPT := $(SRCTREE)/board/$(VENDOR)/$(BOARD)/u-boot.lds
+
+TEXT_BASE = 0x77800000

board/freescale/mx53_ard/flash_header.S

@@ -0,0 +1,304 @@
+/*
+ * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <asm/arch/mx53.h>
+
+#define REG_LD_AND_STR_INIT(base)	\
+	ldr r0, =base;
+
+#define REG_LD_AND_STR_OP(i, offset, val)	\
+	ldr r1, =val;	\
+	ldr r2, =offset;	\
+	str r1, [r0, r2];
+
+#define REG_LD_AND_STR_END(base)
+
+
+#ifdef	CONFIG_FLASH_HEADER
+#ifndef CONFIG_FLASH_HEADER_OFFSET
+# error "Must define the offset of flash header"
+#endif
+
+.section ".text.flasheader", "x"
+	b	_start
+	.org	CONFIG_FLASH_HEADER_OFFSET
+
+ivt_header:		.long 0x402000D1/* Tag=0xD1, Len=0x0020, Ver=0x40 */
+app_code_jump_v:	.long (0xF8006000 + (plugin_start - TEXT_BASE))
+reserv1:		.long 0x0
+dcd_ptr:		.long 0x0
+boot_data_ptr:		.long (0xF8006000 + (boot_data - TEXT_BASE))
+self_ptr:		.long (0xF8006000 + (ivt_header - TEXT_BASE))
+app_code_csf:		.long 0x0
+reserv2:		.long 0x0
+boot_data:		.long 0xF8006000
+image_len:		.long (3 * 1024)
+plugin:			.long 0x1
+
+/* Second IVT to give entry point into the bootloader copied to DDR */
+ivt2_header:		.long 0x402000D1/*Tag=0xD1, Len=0x0020, Ver=0x40 */
+app2_code_jump_v:	.long _start   /* Entry point for the bootloader */
+reserv3:		.long 0x0
+dcd2_ptr:		.long 0x0
+boot_data2_ptr:		.long boot_data2
+self_ptr2:		.long ivt2_header
+app_code_csf2:		.long 0x0
+reserv4:		.long 0x0
+boot_data2:		.long TEXT_BASE
+image_len2:		.long  _end_of_copy - TEXT_BASE + CONFIG_FLASH_HEADER_OFFSET
+plugin2:		.long 0x0
+
+/* Here starts the plugin code */
+plugin_start:
+	/* Save the return address and the function arguments */
+	push {r0-r6, lr}
+	/* We should distinguish USB recovery mode(SDP mode) and internal boot mode.
+	If ROM runs in SDP mode, then it needn't load boot code from storage media.
+	If ROM runs in SDP mode, then r0 must be 0x00
+	If ROM runs in internal boot mode, then r0 should be larger than IRAM base address. */
+	mov r7, r0
+
+#if defined(CONFIG_MX53_ARD_DDR3)
+	/* IOMUX */
+	REG_LD_AND_STR_INIT(IOMUXC_BASE_ADDR)
+	REG_LD_AND_STR_OP(1, 0x554, 0x00300000)
+	REG_LD_AND_STR_OP(2, 0x558, 0x00300040)
+	REG_LD_AND_STR_OP(3, 0x560, 0x00300000)
+	REG_LD_AND_STR_OP(4, 0x564, 0x00300040)
+	REG_LD_AND_STR_OP(5, 0x568, 0x00300040)
+	REG_LD_AND_STR_OP(6, 0x570, 0x00300000)
+	REG_LD_AND_STR_OP(7, 0x574, 0x00300000)
+	REG_LD_AND_STR_OP(8, 0x578, 0x00300000)
+	REG_LD_AND_STR_OP(9, 0x57c, 0x00300040)
+	REG_LD_AND_STR_OP(10, 0x580, 0x00300040)
+	REG_LD_AND_STR_OP(11, 0x584, 0x00300000)
+	REG_LD_AND_STR_OP(12, 0x588, 0x00300000)
+	REG_LD_AND_STR_OP(13, 0x590, 0x00300040)
+	REG_LD_AND_STR_OP(14, 0x594, 0x00300000)
+	REG_LD_AND_STR_OP(15, 0x6f0, 0x00300000)
+	REG_LD_AND_STR_OP(16, 0x6f4, 0x00000000)
+	REG_LD_AND_STR_OP(17, 0x6fc, 0x00000000)
+	REG_LD_AND_STR_OP(18, 0x714, 0x00000000)
+	REG_LD_AND_STR_OP(19, 0x718, 0x00300000)
+	REG_LD_AND_STR_OP(20, 0x71c, 0x00300000)
+	REG_LD_AND_STR_OP(21, 0x720, 0x00300000)
+	REG_LD_AND_STR_OP(22, 0x724, 0x04000000)
+	REG_LD_AND_STR_OP(23, 0x728, 0x00300000)
+	REG_LD_AND_STR_OP(24, 0x72c, 0x00300000)
+	REG_LD_AND_STR_END(IOMUXC_BASE_ADDR)
+
+	/* ESDCTL */
+	REG_LD_AND_STR_INIT(ESDCTL_BASE_ADDR)
+	REG_LD_AND_STR_OP(25, 0x088, 0x35343535)
+	REG_LD_AND_STR_OP(26, 0x090, 0x4d444c44)
+	REG_LD_AND_STR_OP(27, 0x07c, 0x01370138)
+	REG_LD_AND_STR_OP(28, 0x080, 0x013b013c)
+	REG_LD_AND_STR_OP(29, 0x0f8, 0x00000800)
+	REG_LD_AND_STR_OP(30, 0x018, 0x00001740)
+	REG_LD_AND_STR_OP(31, 0x000, 0xc3190000)
+	REG_LD_AND_STR_OP(32, 0x00c, 0x9f5152e3)
+	REG_LD_AND_STR_OP(33, 0x010, 0xb68e8a63)
+	REG_LD_AND_STR_OP(34, 0x014, 0x01ff00db)
+	REG_LD_AND_STR_OP(35, 0x02c, 0x000026d2)
+	REG_LD_AND_STR_OP(36, 0x030, 0x009f0e21)
+	REG_LD_AND_STR_OP(37, 0x008, 0x12273030)
+	REG_LD_AND_STR_OP(38, 0x004, 0x0002002d)
+	REG_LD_AND_STR_OP(39, 0x01c, 0x00008032)
+	REG_LD_AND_STR_OP(40, 0x01c, 0x00008033)
+	REG_LD_AND_STR_OP(41, 0x01c, 0x00028031)
+	REG_LD_AND_STR_OP(42, 0x01c, 0x052080b0)
+	REG_LD_AND_STR_OP(43, 0x01c, 0x04008040)
+	REG_LD_AND_STR_OP(44, 0x01c, 0x0000803a)
+	REG_LD_AND_STR_OP(45, 0x01c, 0x0000803b)
+	REG_LD_AND_STR_OP(46, 0x01c, 0x00028039)
+	REG_LD_AND_STR_OP(47, 0x01c, 0x05208138)
+	REG_LD_AND_STR_OP(48, 0x01c, 0x04008048)
+	REG_LD_AND_STR_OP(49, 0x020, 0x00005800)
+	REG_LD_AND_STR_OP(50, 0x040, 0x04b80003)
+	REG_LD_AND_STR_OP(51, 0x058, 0x00022227)
+	REG_LD_AND_STR_OP(52, 0x01C, 0x00000000)
+	REG_LD_AND_STR_END(ESDCTL_BASE_ADDR)
+#else
+	/* IOMUX */
+	REG_LD_AND_STR_INIT(IOMUXC_BASE_ADDR)
+	REG_LD_AND_STR_OP(1, 0x554, 0x00200000)
+	REG_LD_AND_STR_OP(2, 0x560, 0x00200000)
+	REG_LD_AND_STR_OP(3, 0x594, 0x00200000)
+	REG_LD_AND_STR_OP(4, 0x584, 0x00200000)
+	REG_LD_AND_STR_OP(5, 0x558, 0x00200040)
+	REG_LD_AND_STR_OP(6, 0x568, 0x00200040)
+	REG_LD_AND_STR_OP(7, 0x590, 0x00200040)
+	REG_LD_AND_STR_OP(8, 0x57c, 0x00200040)
+	REG_LD_AND_STR_OP(9, 0x564, 0x00200040)
+	REG_LD_AND_STR_OP(10, 0x580, 0x00200040)
+	REG_LD_AND_STR_OP(11, 0x570, 0x00200000)
+	REG_LD_AND_STR_OP(12, 0x578, 0x00200000)
+	REG_LD_AND_STR_OP(13, 0x72c, 0x00200000)
+	REG_LD_AND_STR_OP(14, 0x728, 0x00200000)
+	REG_LD_AND_STR_OP(15, 0x71c, 0x00200000)
+	REG_LD_AND_STR_OP(16, 0x718, 0x00200000)
+	REG_LD_AND_STR_OP(17, 0x574, 0x00280000)
+	REG_LD_AND_STR_OP(18, 0x588, 0x00280000)
+	REG_LD_AND_STR_OP(19, 0x6f0, 0x00280000)
+	REG_LD_AND_STR_OP(20, 0x720, 0x00280000)
+	REG_LD_AND_STR_OP(21, 0x6fc, 0x00000000)
+	REG_LD_AND_STR_OP(22, 0x6f4, 0x00000200)
+	REG_LD_AND_STR_OP(23, 0x714, 0x00000000)
+	REG_LD_AND_STR_OP(24, 0x724, 0x06000000)
+	REG_LD_AND_STR_END(IOMUXC_BASE_ADDR)
+
+	/* ESDCTL */
+	REG_LD_AND_STR_INIT(ESDCTL_BASE_ADDR)
+	REG_LD_AND_STR_OP(25, 0x088, 0x34333936)
+	REG_LD_AND_STR_OP(26, 0x090, 0x49434942)
+	REG_LD_AND_STR_OP(27, 0x0f8, 0x00000800)
+	REG_LD_AND_STR_OP(28, 0x07c, 0x01350138)
+	REG_LD_AND_STR_OP(29, 0x080, 0x01380139)
+	REG_LD_AND_STR_OP(30, 0x0f8, 0x00000800)
+	REG_LD_AND_STR_OP(31, 0x018, 0x00001710)
+	REG_LD_AND_STR_OP(32, 0x000, 0xc4110000)
+	REG_LD_AND_STR_OP(33, 0x00c, 0x4d5122d2)
+	REG_LD_AND_STR_OP(34, 0x010, 0x92d18a22)
+	REG_LD_AND_STR_OP(35, 0x014, 0x00c70092)
+	REG_LD_AND_STR_OP(36, 0x02c, 0x000026d2)
+	REG_LD_AND_STR_OP(37, 0x030, 0x009f000e)
+	REG_LD_AND_STR_OP(38, 0x008, 0x12272000)
+	REG_LD_AND_STR_OP(39, 0x004, 0x00030012)
+	REG_LD_AND_STR_OP(40, 0x01c, 0x04008010)
+	REG_LD_AND_STR_OP(41, 0x01c, 0x00008032)
+	REG_LD_AND_STR_OP(42, 0x01c, 0x00008033)
+	REG_LD_AND_STR_OP(43, 0x01c, 0x00008031)
+	REG_LD_AND_STR_OP(44, 0x01c, 0x0b5280b0)
+	REG_LD_AND_STR_OP(45, 0x01c, 0x04008010)
+	REG_LD_AND_STR_OP(46, 0x01c, 0x00008020)
+	REG_LD_AND_STR_OP(47, 0x01c, 0x00008020)
+	REG_LD_AND_STR_OP(48, 0x01c, 0x0a528030)
+	REG_LD_AND_STR_OP(49, 0x01c, 0x03c68031)
+	REG_LD_AND_STR_OP(50, 0x01c, 0x00448031)
+	REG_LD_AND_STR_OP(51, 0x01c, 0x04008018)
+	REG_LD_AND_STR_OP(52, 0x01c, 0x0000803a)
+	REG_LD_AND_STR_OP(53, 0x01c, 0x0000803b)
+	REG_LD_AND_STR_OP(54, 0x01c, 0x00008039)
+	REG_LD_AND_STR_OP(55, 0x01c, 0x0b528138)
+	REG_LD_AND_STR_OP(56, 0x01c, 0x04008018)
+	REG_LD_AND_STR_OP(57, 0x01c, 0x00008028)
+	REG_LD_AND_STR_OP(58, 0x01c, 0x00008028)
+	REG_LD_AND_STR_OP(59, 0x01c, 0x0a528038)
+	REG_LD_AND_STR_OP(60, 0x01c, 0x03c68039)
+	REG_LD_AND_STR_OP(61, 0x01c, 0x00448039)
+	REG_LD_AND_STR_OP(62, 0x020, 0x00005800)
+	REG_LD_AND_STR_OP(63, 0x058, 0x00033335)
+	REG_LD_AND_STR_OP(64, 0x01c, 0x00000000)
+	REG_LD_AND_STR_OP(65, 0x040, 0x04b80003)
+	REG_LD_AND_STR_END(ESDCTL_BASE_ADDR)
+#endif
+
+/*
+ *  The following is to fill in those arguments for this ROM function
+ * pu_irom_hwcnfg_setup(void **start, size_t *bytes, const void *boot_data)
+ *
+ *  This function is used to copy data from the storage media into DDR.
+ *
+ *  start - Initial (possibly partial) image load address on entry. Final image
+ * load address on exit.
+ *  bytes - Initial (possibly partial) image size on entry. Final image size on
+ * exit.
+ *  boot_data - Initial @ref ivt Boot Data load address.
+ */
+	adr r0, DDR_DEST_ADDR
+	adr r1, COPY_SIZE
+	adr r2, BOOT_DATA
+before_calling_rom___pu_irom_hwcnfg_setup:
+
+	/* We should distinguish USB recovery mode(SDP mode) and internal boot mode.
+	If ROM runs in SDP mode, then it needn't load boot code from storage media.
+	If ROM runs in SDP mode, then r0 must be 0x00
+	If ROM runs in internal boot mode, then r0 should be larger than IRAM base address. */
+	cmp r7, #0xF8000000
+	bls return_sdp
+	/* Different ROM address for TO 1.0 & TO 2.0 */
+	ldr r3, =ROM_SI_REV
+	ldr r4, [r3]
+
+	cmp r4, #0x21
+	/* TO2.1 */
+	moveq r6, #0x1800
+	addeq r6, r6, #0x4d
+	beq 2f
+
+	cmp r4, #0x20
+	/* TO2 */
+	moveq r6, #0x1800
+	addeq r6, r6, #0x4d
+	beq 2f
+
+	/* TO1 */
+	mov r6, #0x400000
+	add r6, r6, #0x5000
+	add r6, r6, #0xc7
+
+2:
+	blx r6 /* This address might change in future ROM versions */
+after_calling_rom___pu_irom_hwcnfg_setup:
+
+return_sdp:
+	cmp r7, #0xF8000000
+	bhi quit_plugin
+
+	/* Workaround run plug-ins in SDP mode without USB re-enumeration.
+	how it works:
+	ROM running in usb download mode.
+	Host manufacturing application sends SDP command to download plug-in image.
+	Host manufacturing application sends SDP command to jump to plug-in image and run it.
+	Plug-in starts execution and after its regular tasks plug-in will then call into ROM
+	call into pl_parse_and_handle() */
+	ldr r3, =ROM_SI_REV
+	ldr r5, [r3]
+	cmp r5, #0x20       /* check silicon revision to determine the function entry address */
+
+	ldrlt r4, =0x00000edd   /* function entry in TO1 ROM */
+	ldrge r4, =0x0040487d   /* function entry in TO2 ROM */
+	blx r4
+
+/* To return to ROM from plugin, we need to fill in these argument.
+ * Here is what need to do:
+ * Need to construct the paramters for this function before return to ROM:
+ * plugin_download(void **start, size_t *bytes, UINT32 *ivt_offset)
+ */
+quit_plugin:
+	pop {r0-r6, lr}
+	ldr r7, DDR_DEST_ADDR
+	str r7, [r0]
+	ldr r7, COPY_SIZE
+	str r7, [r1]
+	mov r7, #0x400  /* Point to the second IVT table at offset 0x42C */
+	add r7, r7, #0x2C
+	str r7, [r2]
+	mov r0, #1
+
+	bx lr  /* return back to ROM code */
+
+DDR_DEST_ADDR:    .word   TEXT_BASE
+COPY_SIZE:        .word   _end - TEXT_BASE
+BOOT_DATA:        .word   TEXT_BASE
+                  .word   _end - TEXT_BASE
+                  .word   0
+
+#endif

board/freescale/mx53_ard/lowlevel_init.S

@@ -0,0 +1,371 @@
+/*
+ * Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
+ *
+ * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <asm/arch/mx53.h>
+
+/*
+ * L2CC Cache setup/invalidation/disable
+ */
+.macro init_l2cc
+	/* explicitly disable L2 cache */
+        mrc 15, 0, r0, c1, c0, 1
+        bic r0, r0, #0x2
+        mcr 15, 0, r0, c1, c0, 1
+
+        /* reconfigure L2 cache aux control reg */
+        mov r0, #0xC0                   /* tag RAM */
+        add r0, r0, #0x4                /* data RAM */
+        orr r0, r0, #(1 << 24)          /* disable write allocate delay */
+        orr r0, r0, #(1 << 23)          /* disable write allocate combine */
+        orr r0, r0, #(1 << 22)          /* disable write allocate */
+
+	mcr 15, 1, r0, c9, c0, 2
+.endm /* init_l2cc */
+
+/* AIPS setup - Only setup MPROTx registers.
+ * The PACR default values are good.*/
+.macro init_aips
+	/*
+	 * Set all MPROTx to be non-bufferable, trusted for R/W,
+	 * not forced to user-mode.
+	 */
+	ldr r0, =AIPS1_BASE_ADDR
+	ldr r1, =0x77777777
+	str r1, [r0, #0x0]
+	str r1, [r0, #0x4]
+	ldr r0, =AIPS2_BASE_ADDR
+	str r1, [r0, #0x0]
+	str r1, [r0, #0x4]
+.endm /* init_aips */
+
+.macro setup_pll pll, freq
+	/*
+	 * If freq < 300MHz, we need to set dpdck0_2_en to 0
+	 */
+	ldr r0, =\freq
+	ldr r1, =0x300
+	cmp r0, r1
+	ldrcs r1, =0x00001232
+	ldrcc r1, =0x00000232
+	ldr r0, =\pll
+	str r1, [r0, #PLL_DP_CTL]
+	mov r1, #0x2
+	str r1, [r0, #PLL_DP_CONFIG]
+
+	ldr r1, W_DP_OP_\freq
+	str r1, [r0, #PLL_DP_OP]
+	str r1, [r0, #PLL_DP_HFS_OP]
+
+	ldr r1,	W_DP_MFD_\freq
+	str r1, [r0, #PLL_DP_MFD]
+	str r1, [r0, #PLL_DP_HFS_MFD]
+
+	ldr r1,  W_DP_MFN_\freq
+	str r1, [r0, #PLL_DP_MFN]
+	str r1, [r0, #PLL_DP_HFS_MFN]
+
+	ldr r1, =0x00001232
+	str r1, [r0, #PLL_DP_CTL]
+1:	ldr r1, [r0, #PLL_DP_CTL]
+	ands r1, r1, #0x1
+	beq 1b
+.endm
+
+.macro init_m4if
+	/*increase master2 priority for WIFI*/
+	ldr r0, =M4IF_BASE_ADDR
+	ldr r1, [r0, #0x40]
+	orr r1, r1, #(0x33 << 16)
+	str r1, [r0, #0x40]
+
+	/*increase master4 priority for FEC*/
+	ldr r1, [r0, #0x44]
+	orr r1, r1, #0x33
+	str r1, [r0, #0x44]
+
+	/*set SDHC-port3 high priority to all AHB MAX Slave port*/
+	ldr r0, =AHBMAX_BASE_ADDR
+
+#ifdef CONFIG_WIFI_SDHC_PORT3
+	/*set PARK to SDHC-port3*/
+	ldr r0, =AHBMAX_BASE_ADDR
+	ldr r1, [r0, #0x10]
+	bic r1, r1, #(0x7 << 0)
+	orr r1, r1, #0x3
+	bic r1, r1, #(0x3 << 4)
+	bic r1, r1, #(0x3 << 8)
+	orr r1, r1, #(0x1 << 30)
+	bic r1, r1, #(0x1 << 31)
+
+	ldr r1, [r0, #0x110]
+	bic r1, r1, #(0x7 << 0)
+	orr r1, r1, #0x3
+	bic r1, r1, #(0x3 << 4)
+	bic r1, r1, #(0x3 << 8)
+	orr r1, r1, #(0x1 << 30)
+	bic r1, r1, #(0x1 << 31)
+
+	ldr r1, [r0, #0x210]
+	bic r1, r1, #(0x7 << 0)
+	orr r1, r1, #0x3
+	bic r1, r1, #(0x3 << 4)
+	bic r1, r1, #(0x3 << 8)
+	orr r1, r1, #(0x1 << 30)
+	bic r1, r1, #(0x1 << 31)
+
+	ldr r1, [r0, #0x310]
+	bic r1, r1, #(0x7 << 0)
+	orr r1, r1, #0x3
+	bic r1, r1, #(0x3 << 4)
+	bic r1, r1, #(0x3 << 8)
+	orr r1, r1, #(0x1 << 30)
+	bic r1, r1, #(0x1 << 31)
+
+	/*set SDHC-port3 arbitration*/
+	ldr r0, =AHBMAX_BASE_ADDR
+	ldr r1, [r0, #0xb00]
+	bic r1, r1, #(0x7 << 0)
+	orr r1, r1, #0x1
+#endif
+
+#ifdef CONFIG_WIFI_SDHC_PORT2
+	/*set PARK to SDHC-port3*/
+	ldr r0, =AHBMAX_BASE_ADDR
+	ldr r1, [r0, #0x10]
+	bic r1, r1, #(0x7 << 0)
+	orr r1, r1, #0x2
+	bic r1, r1, #(0x3 << 4)
+	bic r1, r1, #(0x3 << 8)
+	orr r1, r1, #(0x1 << 30)
+	bic r1, r1, #(0x1 << 31)
+
+	ldr r1, [r0, #0x110]
+	bic r1, r1, #(0x7 << 0)
+	orr r1, r1, #0x2
+	bic r1, r1, #(0x3 << 4)
+	bic r1, r1, #(0x3 << 8)
+	orr r1, r1, #(0x1 << 30)
+	bic r1, r1, #(0x1 << 31)
+
+	ldr r1, [r0, #0x210]
+	bic r1, r1, #(0x7 << 0)
+	orr r1, r1, #0x2
+	bic r1, r1, #(0x3 << 4)
+	bic r1, r1, #(0x3 << 8)
+	orr r1, r1, #(0x1 << 30)
+	bic r1, r1, #(0x1 << 31)
+
+	ldr r1, [r0, #0x310]
+	bic r1, r1, #(0x7 << 0)
+	orr r1, r1, #0x2
+	bic r1, r1, #(0x3 << 4)
+	bic r1, r1, #(0x3 << 8)
+	orr r1, r1, #(0x1 << 30)
+	bic r1, r1, #(0x1 << 31)
+
+	/*set SDHC-port2 arbitration*/
+	ldr r0, =AHBMAX_BASE_ADDR
+	ldr r1, [r0, #0xA00]
+	bic r1, r1, #(0x7 << 0)
+#endif
+
+	/*set JMP step to zero*/
+	ldr r0, =M4IF_BASE_ADDR
+	ldr r1, [r0, #0x48]
+	bic r1, r1, #(0x3 << 8)
+	str r1, [r0, #0x48]
+.endm
+
+.macro init_clock
+	ldr r0, =ROM_SI_REV
+	ldr r1, [r0]
+	cmp r1, #0x20
+
+	/* For TO2 only, set LDO to 1.3V */
+	ldr r0, =0x53fa8000
+	ldr r1, =0x00194005
+	streq r1, [r0, #0x04]
+
+	ldr r0, CCM_BASE_ADDR_W
+
+	/* Gate of clocks to the peripherals first */
+	ldr r1, =0x3FFFFFFF
+	str r1, [r0, #CLKCTL_CCGR0]
+	ldr r1, =0x0
+	str r1, [r0, #CLKCTL_CCGR1]
+	str r1, [r0, #CLKCTL_CCGR2]
+	str r1, [r0, #CLKCTL_CCGR3]
+	str r1, [r0, #CLKCTL_CCGR7]
+	ldr r1, =0x00030000
+	str r1, [r0, #CLKCTL_CCGR4]
+	ldr r1, =0x00FFF030
+	str r1, [r0, #CLKCTL_CCGR5]
+	ldr r1, =0x0F00030F
+	str r1, [r0, #CLKCTL_CCGR6]
+
+	/* Switch ARM to step clock */
+	mov r1, #0x4
+	str r1, [r0, #CLKCTL_CCSR]
+
+	setup_pll PLL1_BASE_ADDR, 800
+
+        setup_pll PLL3_BASE_ADDR, 400
+
+        /* Switch peripheral to PLL3 */
+        ldr r0, CCM_BASE_ADDR_W
+        ldr r1, CCM_VAL_0x00015154
+        str r1, [r0, #CLKCTL_CBCMR]
+        ldr r1, CCM_VAL_0x02888945
+        orr r1, r1, #(1 << 16)
+        str r1, [r0, #CLKCTL_CBCDR]
+        /* make sure change is effective */
+1:      ldr r1, [r0, #CLKCTL_CDHIPR]
+        cmp r1, #0x0
+        bne 1b
+
+        setup_pll PLL2_BASE_ADDR, CONFIG_SYS_PLL2_FREQ
+
+	/* Switch peripheral to PLL2 */
+	ldr r0, CCM_BASE_ADDR_W
+	ldr r1, CCM_VAL_0x00808145
+	orr r1, r1, #(CONFIG_SYS_AHB_PODF << 10)
+	orr r1, r1, #(CONFIG_SYS_AXIA_PODF << 16)
+	orr r1, r1, #(CONFIG_SYS_AXIB_PODF << 19)
+	str r1, [r0, #CLKCTL_CBCDR]
+
+	ldr r1, CCM_VAL_0x00016154
+	str r1, [r0, #CLKCTL_CBCMR]
+
+	/*change uart clk parent to pll2*/
+	ldr r1, [r0, #CLKCTL_CSCMR1]
+	and r1, r1, #0xfcffffff
+	orr r1, r1, #0x01000000
+	str r1, [r0, #CLKCTL_CSCMR1]
+
+	/* make sure change is effective */
+1:      ldr r1, [r0, #CLKCTL_CDHIPR]
+	cmp r1, #0x0
+	bne 1b
+
+        setup_pll PLL3_BASE_ADDR, 216
+
+	setup_pll PLL4_BASE_ADDR, 455
+
+	/* Set the platform clock dividers */
+	ldr r0, PLATFORM_BASE_ADDR_W
+	ldr r1, PLATFORM_CLOCK_DIV_W
+	str r1, [r0, #PLATFORM_ICGC]
+
+	ldr r0, CCM_BASE_ADDR_W
+	mov r1, #0
+	str r1, [r0, #CLKCTL_CACRR]
+
+	/* Switch ARM back to PLL 1. */
+	mov r1, #0x0
+	str r1, [r0, #CLKCTL_CCSR]
+
+	/* make uart div=6*/
+	ldr r1, [r0, #CLKCTL_CSCDR1]
+	and r1, r1, #0xffffffc0
+	orr r1, r1, #0x0a
+	str r1, [r0, #CLKCTL_CSCDR1]
+
+	/* Restore the default values in the Gate registers */
+	ldr r1, =0xFFFFFFFF
+	str r1, [r0, #CLKCTL_CCGR0]
+	str r1, [r0, #CLKCTL_CCGR1]
+	str r1, [r0, #CLKCTL_CCGR2]
+	str r1, [r0, #CLKCTL_CCGR3]
+	str r1, [r0, #CLKCTL_CCGR4]
+	str r1, [r0, #CLKCTL_CCGR5]
+	str r1, [r0, #CLKCTL_CCGR6]
+	str r1, [r0, #CLKCTL_CCGR7]
+
+        mov r1, #0x00000
+        str r1, [r0, #CLKCTL_CCDR]
+
+        /* for cko - for ARM div by 8 */
+        mov r1, #0x000A0000
+        add r1, r1, #0x00000F0
+        str r1, [r0, #CLKCTL_CCOSR]
+.endm
+
+.section ".text.init", "x"
+
+.globl lowlevel_init
+lowlevel_init:
+
+#ifdef ENABLE_IMPRECISE_ABORT
+        mrs r1, spsr            /* save old spsr */
+        mrs r0, cpsr            /* read out the cpsr */
+	bic r0, r0, #0x100      /* clear the A bit */
+	msr spsr, r0            /* update spsr */
+	add lr, pc, #0x8        /* update lr */
+        movs pc, lr             /* update cpsr */
+        nop
+        nop
+        nop
+	nop
+	msr spsr, r1            /* restore old spsr */
+#endif
+
+	/* ARM errata ID #468414 */
+	mrc 15, 0, r1, c1, c0, 1
+	orr r1, r1, #(1 << 5)    /* enable L1NEON bit */
+	mcr 15, 0, r1, c1, c0, 1
+
+	init_l2cc
+
+	init_aips
+
+#ifdef CONFIG_ADJUST_WIFI_FEC_PERFORMANCE
+        /*increase WIFI & FEC priority of accessing bus*/
+        init_m4if
+#endif
+
+	init_clock
+
+	mov pc, lr
+
+/* Board level setting value */
+CCM_BASE_ADDR_W:        .word CCM_BASE_ADDR
+CCM_VAL_0x00016154:     .word 0x00016154
+CCM_VAL_0x00808145:     .word 0x00808145
+CCM_VAL_0x00015154:     .word 0x00015154
+CCM_VAL_0x02888945:     .word 0x02888945
+W_DP_OP_800:           	.word DP_OP_800
+W_DP_MFD_800:           .word DP_MFD_800
+W_DP_MFN_800:           .word DP_MFN_800
+W_DP_OP_600:            .word DP_OP_600
+W_DP_MFD_600:           .word DP_MFD_600
+W_DP_MFN_600:           .word DP_MFN_600
+W_DP_OP_400:            .word DP_OP_400
+W_DP_MFD_400:           .word DP_MFD_400
+W_DP_MFN_400:           .word DP_MFN_400
+W_DP_OP_216:            .word DP_OP_216
+W_DP_MFD_216:           .word DP_MFD_216
+W_DP_MFN_216:           .word DP_MFN_216
+W_DP_OP_455:            .word DP_OP_455
+W_DP_MFD_455:           .word DP_MFD_455
+W_DP_MFN_455:           .word DP_MFN_455
+PLATFORM_BASE_ADDR_W:   .word ARM_BASE_ADDR
+PLATFORM_CLOCK_DIV_W:   .word 0x00000124

board/freescale/mx53_ard/u-boot.lds

@@ -0,0 +1,74 @@
+/*
+ * January 2004 - Changed to support H4 device
+ * Copyright (c) 2004 Texas Instruments
+ *
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
+ *
+ * (C) Copyright 2010 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+	. = 0x00000000;
+
+	. = ALIGN(4);
+	.text	   :
+	{
+	  /* WARNING - the following is hand-optimized to fit within	*/
+	  /* the sector layout of our flash chips!	XXX FIXME XXX	*/
+	  board/freescale/mx53_ard/flash_header.o	(.text.flasheader)
+	  cpu/arm_cortexa8/start.o
+	  board/freescale/mx53_ard/libmx53_ard.a	(.text)
+	  lib_arm/libarm.a		(.text)
+	  net/libnet.a			(.text)
+	  drivers/mtd/libmtd.a		(.text)
+	  drivers/mmc/libmmc.a		(.text)
+
+	  . = DEFINED(env_offset) ? env_offset : .;
+	  common/env_embedded.o(.text)
+
+	  *(.text)
+	}
+
+	. = ALIGN(4);
+	.rodata : { *(.rodata) }
+
+	. = ALIGN(4);
+	.data : { *(.data) }
+
+	. = ALIGN(4);
+	.got : { *(.got) }
+
+	. = .;
+	__u_boot_cmd_start = .;
+	.u_boot_cmd : { *(.u_boot_cmd) }
+	__u_boot_cmd_end = .;
+
+	. = ALIGN(4);
+	_end_of_copy = .; /* end_of ROM copy code here */
+	__bss_start = .;
+	.bss : { *(.bss) }
+	_end = .;
+}

board/freescale/mx53_evk/Makefile

@@ -0,0 +1,49 @@
+#
+# Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
+#
+# (C) Copyright 2010 Freescale Semiconductor, Inc.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).a
+
+COBJS	:= mx53_evk.o
+SOBJS	:= lowlevel_init.o flash_header.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################

board/freescale/mx53_evk/config.mk

@@ -0,0 +1,3 @@
+LDSCRIPT := $(SRCTREE)/board/$(VENDOR)/$(BOARD)/u-boot.lds
+
+TEXT_BASE = 0x77800000

board/freescale/mx53_evk/flash_header.S

@@ -0,0 +1,242 @@
+/*
+ * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <asm/arch/mx53.h>
+
+#define REG_LD_AND_STR_INIT(base)	\
+	ldr r0, =base;
+
+#define REG_LD_AND_STR_OP(i, offset, val)	\
+	ldr r1, =val;	\
+	ldr r2, =offset;	\
+	str r1, [r0, r2];
+
+#define REG_LD_AND_STR_END(base)
+
+
+#ifdef	CONFIG_FLASH_HEADER
+#ifndef CONFIG_FLASH_HEADER_OFFSET
+# error "Must define the offset of flash header"
+#endif
+
+.section ".text.flasheader", "x"
+	b	_start
+	.org	CONFIG_FLASH_HEADER_OFFSET
+
+ivt_header:		.long 0x402000D1/* Tag=0xD1, Len=0x0020, Ver=0x40 */
+app_code_jump_v:	.long (0xF8006000 + (plugin_start - TEXT_BASE))
+reserv1:		.long 0x0
+dcd_ptr:		.long 0x0
+boot_data_ptr:		.long (0xF8006000 + (boot_data - TEXT_BASE))
+self_ptr:		.long (0xF8006000 + (ivt_header - TEXT_BASE))
+app_code_csf:		.long 0x0
+reserv2:		.long 0x0
+boot_data:		.long 0xF8006000
+image_len:		.long (3 * 1024)
+plugin:			.long 0x1
+
+/* Second IVT to give entry point into the bootloader copied to DDR */
+ivt2_header:		.long 0x402000D1/*Tag=0xD1, Len=0x0020, Ver=0x40 */
+app2_code_jump_v:	.long _start   /* Entry point for the bootloader */
+reserv3:		.long 0x0
+dcd2_ptr:		.long 0x0
+boot_data2_ptr:		.long boot_data2
+self_ptr2:		.long ivt2_header
+app_code_csf2:		.long 0x0
+reserv4:		.long 0x0
+boot_data2:		.long TEXT_BASE
+image_len2:		.long  _end_of_copy - TEXT_BASE + CONFIG_FLASH_HEADER_OFFSET
+plugin2:		.long 0x0
+
+/* Here starts the plugin code */
+plugin_start:
+	/* Save the return address and the function arguments */
+	push {r0-r6, lr}
+	/* We should distinguish USB recovery mode(SDP mode) and internal boot mode.
+	If ROM runs in SDP mode, then it needn't load boot code from storage media.
+	If ROM runs in SDP mode, then r0 must be 0x00
+	If ROM runs in internal boot mode, then r0 should be larger than IRAM base address. */
+	mov r7, r0
+
+	/* IOMUX */
+	REG_LD_AND_STR_INIT(IOMUXC_BASE_ADDR)
+	REG_LD_AND_STR_OP(1, 0x554, 0x00200000)
+	REG_LD_AND_STR_OP(2, 0x560, 0x00200000)
+	REG_LD_AND_STR_OP(3, 0x594, 0x00200000)
+	REG_LD_AND_STR_OP(4, 0x584, 0x00200000)
+	REG_LD_AND_STR_OP(5, 0x558, 0x00200040)
+	REG_LD_AND_STR_OP(6, 0x568, 0x00200040)
+	REG_LD_AND_STR_OP(7, 0x590, 0x00200040)
+	REG_LD_AND_STR_OP(8, 0x57c, 0x00200040)
+	REG_LD_AND_STR_OP(9, 0x564, 0x00200040)
+	REG_LD_AND_STR_OP(10, 0x580, 0x00200040)
+	REG_LD_AND_STR_OP(11, 0x570, 0x00200000)
+	REG_LD_AND_STR_OP(12, 0x578, 0x00200000)
+	REG_LD_AND_STR_OP(13, 0x72c, 0x00200000)
+	REG_LD_AND_STR_OP(14, 0x728, 0x00200000)
+	REG_LD_AND_STR_OP(15, 0x71c, 0x00200000)
+	REG_LD_AND_STR_OP(16, 0x718, 0x00200000)
+	REG_LD_AND_STR_OP(17, 0x574, 0x00280000)
+	REG_LD_AND_STR_OP(18, 0x588, 0x00280000)
+	REG_LD_AND_STR_OP(19, 0x6f0, 0x00280000)
+	REG_LD_AND_STR_OP(20, 0x720, 0x00280000)
+	REG_LD_AND_STR_OP(21, 0x6fc, 0x00000000)
+	REG_LD_AND_STR_OP(22, 0x6f4, 0x00000200)
+	REG_LD_AND_STR_OP(23, 0x714, 0x00000000)
+	REG_LD_AND_STR_OP(24, 0x724, 0x06000000)
+	REG_LD_AND_STR_END(IOMUXC_BASE_ADDR)
+
+	/* ESDCTL */
+	REG_LD_AND_STR_INIT(ESDCTL_BASE_ADDR)
+	REG_LD_AND_STR_OP(25, 0x088, 0x34333936)
+	REG_LD_AND_STR_OP(26, 0x090, 0x49434942)
+	REG_LD_AND_STR_OP(27, 0x0f8, 0x00000800)
+	REG_LD_AND_STR_OP(28, 0x07c, 0x01350138)
+	REG_LD_AND_STR_OP(29, 0x080, 0x01380139)
+	REG_LD_AND_STR_OP(30, 0x0f8, 0x00000800)
+	REG_LD_AND_STR_OP(31, 0x018, 0x00001710)
+	REG_LD_AND_STR_OP(32, 0x000, 0xc4110000)
+	REG_LD_AND_STR_OP(33, 0x00c, 0x4d5122d2)
+	REG_LD_AND_STR_OP(34, 0x010, 0x92d18a22)
+	REG_LD_AND_STR_OP(35, 0x014, 0x00c70092)
+	REG_LD_AND_STR_OP(36, 0x02c, 0x000026d2)
+	REG_LD_AND_STR_OP(37, 0x030, 0x009f000e)
+	REG_LD_AND_STR_OP(38, 0x008, 0x12272000)
+	REG_LD_AND_STR_OP(39, 0x004, 0x00030012)
+	REG_LD_AND_STR_OP(40, 0x01c, 0x04008010)
+	REG_LD_AND_STR_OP(41, 0x01c, 0x00008032)
+	REG_LD_AND_STR_OP(42, 0x01c, 0x00008033)
+	REG_LD_AND_STR_OP(43, 0x01c, 0x00008031)
+	REG_LD_AND_STR_OP(44, 0x01c, 0x0b5280b0)
+	REG_LD_AND_STR_OP(45, 0x01c, 0x04008010)
+	REG_LD_AND_STR_OP(46, 0x01c, 0x00008020)
+	REG_LD_AND_STR_OP(47, 0x01c, 0x00008020)
+	REG_LD_AND_STR_OP(48, 0x01c, 0x0a528030)
+	REG_LD_AND_STR_OP(49, 0x01c, 0x03c68031)
+	REG_LD_AND_STR_OP(50, 0x01c, 0x00448031)
+	REG_LD_AND_STR_OP(51, 0x01c, 0x04008018)
+	REG_LD_AND_STR_OP(52, 0x01c, 0x0000803a)
+	REG_LD_AND_STR_OP(53, 0x01c, 0x0000803b)
+	REG_LD_AND_STR_OP(54, 0x01c, 0x00008039)
+	REG_LD_AND_STR_OP(55, 0x01c, 0x0b528138)
+	REG_LD_AND_STR_OP(56, 0x01c, 0x04008018)
+	REG_LD_AND_STR_OP(57, 0x01c, 0x00008028)
+	REG_LD_AND_STR_OP(58, 0x01c, 0x00008028)
+	REG_LD_AND_STR_OP(59, 0x01c, 0x0a528038)
+	REG_LD_AND_STR_OP(60, 0x01c, 0x03c68039)
+	REG_LD_AND_STR_OP(61, 0x01c, 0x00448039)
+	REG_LD_AND_STR_OP(62, 0x020, 0x00005800)
+	REG_LD_AND_STR_OP(63, 0x058, 0x00033335)
+	REG_LD_AND_STR_OP(64, 0x01c, 0x00000000)
+	REG_LD_AND_STR_OP(65, 0x040, 0x04b80003)
+	REG_LD_AND_STR_END(ESDCTL_BASE_ADDR)
+
+/*
+ *  The following is to fill in those arguments for this ROM function
+ * pu_irom_hwcnfg_setup(void **start, size_t *bytes, const void *boot_data)
+ *
+ *  This function is used to copy data from the storage media into DDR.
+ *
+ *  start - Initial (possibly partial) image load address on entry. Final image
+ * load address on exit.
+ *  bytes - Initial (possibly partial) image size on entry. Final image size on
+ * exit.
+ *  boot_data - Initial @ref ivt Boot Data load address.
+ */
+	adr r0, DDR_DEST_ADDR
+	adr r1, COPY_SIZE
+	adr r2, BOOT_DATA
+before_calling_rom___pu_irom_hwcnfg_setup:
+
+	/* We should distinguish USB recovery mode(SDP mode) and internal boot mode.
+	If ROM runs in SDP mode, then it needn't load boot code from storage media.
+	If ROM runs in SDP mode, then r0 must be 0x00
+	If ROM runs in internal boot mode, then r0 should be larger than IRAM base address. */
+	cmp r7, #0xF8000000
+	bls return_sdp
+	/* Different ROM address for TO 1.0 & TO 2.0 */
+	ldr r3, =ROM_SI_REV
+	ldr r4, [r3]
+
+	cmp r4, #0x21
+	/* TO2.1 */
+	moveq r6, #0x1800
+	addeq r6, r6, #0x4d
+	beq 2f
+
+	cmp r4, #0x20
+	/* TO2 */
+	moveq r6, #0x1800
+	addeq r6, r6, #0x4d
+	beq 2f
+
+	/* TO1 */
+	mov r6, #0x400000
+	add r6, r6, #0x5000
+	add r6, r6, #0xc7
+
+2:
+	blx r6 /* This address might change in future ROM versions */
+after_calling_rom___pu_irom_hwcnfg_setup:
+
+return_sdp:
+	cmp r7, #0xF8000000
+	bhi quit_plugin
+
+	/* Workaround run plug-ins in SDP mode without USB re-enumeration.
+	how it works:
+	ROM running in usb download mode.
+	Host manufacturing application sends SDP command to download plug-in image.
+	Host manufacturing application sends SDP command to jump to plug-in image and run it.
+	Plug-in starts execution and after its regular tasks plug-in will then call into ROM
+	call into pl_parse_and_handle() */
+	ldr r3, =ROM_SI_REV
+	ldr r5, [r3]
+	cmp r5, #0x20       /* check silicon revision to determine the function entry address */
+
+	ldrlt r4, =0x00000edd   /* function entry in TO1 ROM */
+	ldrge r4, =0x0040487d   /* function entry in TO2 ROM */
+	blx r4
+
+/* To return to ROM from plugin, we need to fill in these argument.
+ * Here is what need to do:
+ * Need to construct the paramters for this function before return to ROM:
+ * plugin_download(void **start, size_t *bytes, UINT32 *ivt_offset)
+ */
+quit_plugin:
+	pop {r0-r6, lr}
+	ldr r7, DDR_DEST_ADDR
+	str r7, [r0]
+	ldr r7, COPY_SIZE
+	str r7, [r1]
+	mov r7, #0x400  /* Point to the second IVT table at offset 0x42C */
+	add r7, r7, #0x2C
+	str r7, [r2]
+	mov r0, #1
+
+	bx lr  /* return back to ROM code */
+
+DDR_DEST_ADDR:    .word   TEXT_BASE
+COPY_SIZE:        .word   _end - TEXT_BASE
+BOOT_DATA:        .word   TEXT_BASE
+                  .word   _end - TEXT_BASE
+                  .word   0
+
+#endif

board/freescale/mx53_evk/lowlevel_init.S

@@ -0,0 +1,371 @@
+/*
+ * Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
+ *
+ * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <asm/arch/mx53.h>
+
+/*
+ * L2CC Cache setup/invalidation/disable
+ */
+.macro init_l2cc
+	/* explicitly disable L2 cache */
+        mrc 15, 0, r0, c1, c0, 1
+        bic r0, r0, #0x2
+        mcr 15, 0, r0, c1, c0, 1
+
+        /* reconfigure L2 cache aux control reg */
+        mov r0, #0xC0                   /* tag RAM */
+        add r0, r0, #0x4                /* data RAM */
+        orr r0, r0, #(1 << 24)          /* disable write allocate delay */
+        orr r0, r0, #(1 << 23)          /* disable write allocate combine */
+        orr r0, r0, #(1 << 22)          /* disable write allocate */
+
+	mcr 15, 1, r0, c9, c0, 2
+.endm /* init_l2cc */
+
+/* AIPS setup - Only setup MPROTx registers.
+ * The PACR default values are good.*/
+.macro init_aips
+	/*
+	 * Set all MPROTx to be non-bufferable, trusted for R/W,
+	 * not forced to user-mode.
+	 */
+	ldr r0, =AIPS1_BASE_ADDR
+	ldr r1, =0x77777777
+	str r1, [r0, #0x0]
+	str r1, [r0, #0x4]
+	ldr r0, =AIPS2_BASE_ADDR
+	str r1, [r0, #0x0]
+	str r1, [r0, #0x4]
+.endm /* init_aips */
+
+.macro setup_pll pll, freq
+	/*
+	 * If freq < 300MHz, we need to set dpdck0_2_en to 0
+	 */
+	ldr r0, =\freq
+	ldr r1, =0x300
+	cmp r0, r1
+	ldrcs r1, =0x00001232
+	ldrcc r1, =0x00000232
+	ldr r0, =\pll
+	str r1, [r0, #PLL_DP_CTL]
+	mov r1, #0x2
+	str r1, [r0, #PLL_DP_CONFIG]
+
+	ldr r1, W_DP_OP_\freq
+	str r1, [r0, #PLL_DP_OP]
+	str r1, [r0, #PLL_DP_HFS_OP]
+
+	ldr r1,	W_DP_MFD_\freq
+	str r1, [r0, #PLL_DP_MFD]
+	str r1, [r0, #PLL_DP_HFS_MFD]
+
+	ldr r1,  W_DP_MFN_\freq
+	str r1, [r0, #PLL_DP_MFN]
+	str r1, [r0, #PLL_DP_HFS_MFN]
+
+	ldr r1, =0x00001232
+	str r1, [r0, #PLL_DP_CTL]
+1:	ldr r1, [r0, #PLL_DP_CTL]
+	ands r1, r1, #0x1
+	beq 1b
+.endm
+
+.macro init_m4if
+	/*increase master2 priority for WIFI*/
+	ldr r0, =M4IF_BASE_ADDR
+	ldr r1, [r0, #0x40]
+	orr r1, r1, #(0x33 << 16)
+	str r1, [r0, #0x40]
+
+	/*increase master4 priority for FEC*/
+	ldr r1, [r0, #0x44]
+	orr r1, r1, #0x33
+	str r1, [r0, #0x44]
+
+	/*set SDHC-port3 high priority to all AHB MAX Slave port*/
+	ldr r0, =AHBMAX_BASE_ADDR
+
+#ifdef CONFIG_WIFI_SDHC_PORT3
+	/*set PARK to SDHC-port3*/
+	ldr r0, =AHBMAX_BASE_ADDR
+	ldr r1, [r0, #0x10]
+	bic r1, r1, #(0x7 << 0)
+	orr r1, r1, #0x3
+	bic r1, r1, #(0x3 << 4)
+	bic r1, r1, #(0x3 << 8)
+	orr r1, r1, #(0x1 << 30)
+	bic r1, r1, #(0x1 << 31)
+
+	ldr r1, [r0, #0x110]
+	bic r1, r1, #(0x7 << 0)
+	orr r1, r1, #0x3
+	bic r1, r1, #(0x3 << 4)
+	bic r1, r1, #(0x3 << 8)
+	orr r1, r1, #(0x1 << 30)
+	bic r1, r1, #(0x1 << 31)
+
+	ldr r1, [r0, #0x210]
+	bic r1, r1, #(0x7 << 0)
+	orr r1, r1, #0x3
+	bic r1, r1, #(0x3 << 4)
+	bic r1, r1, #(0x3 << 8)
+	orr r1, r1, #(0x1 << 30)
+	bic r1, r1, #(0x1 << 31)
+
+	ldr r1, [r0, #0x310]
+	bic r1, r1, #(0x7 << 0)
+	orr r1, r1, #0x3
+	bic r1, r1, #(0x3 << 4)
+	bic r1, r1, #(0x3 << 8)
+	orr r1, r1, #(0x1 << 30)
+	bic r1, r1, #(0x1 << 31)
+
+	/*set SDHC-port3 arbitration*/
+	ldr r0, =AHBMAX_BASE_ADDR
+	ldr r1, [r0, #0xb00]
+	bic r1, r1, #(0x7 << 0)
+	orr r1, r1, #0x1
+#endif
+
+#ifdef CONFIG_WIFI_SDHC_PORT2
+	/*set PARK to SDHC-port3*/
+	ldr r0, =AHBMAX_BASE_ADDR
+	ldr r1, [r0, #0x10]
+	bic r1, r1, #(0x7 << 0)
+	orr r1, r1, #0x2
+	bic r1, r1, #(0x3 << 4)
+	bic r1, r1, #(0x3 << 8)
+	orr r1, r1, #(0x1 << 30)
+	bic r1, r1, #(0x1 << 31)
+
+	ldr r1, [r0, #0x110]
+	bic r1, r1, #(0x7 << 0)
+	orr r1, r1, #0x2
+	bic r1, r1, #(0x3 << 4)
+	bic r1, r1, #(0x3 << 8)
+	orr r1, r1, #(0x1 << 30)
+	bic r1, r1, #(0x1 << 31)
+
+	ldr r1, [r0, #0x210]
+	bic r1, r1, #(0x7 << 0)
+	orr r1, r1, #0x2
+	bic r1, r1, #(0x3 << 4)
+	bic r1, r1, #(0x3 << 8)
+	orr r1, r1, #(0x1 << 30)
+	bic r1, r1, #(0x1 << 31)
+
+	ldr r1, [r0, #0x310]
+	bic r1, r1, #(0x7 << 0)
+	orr r1, r1, #0x2
+	bic r1, r1, #(0x3 << 4)
+	bic r1, r1, #(0x3 << 8)
+	orr r1, r1, #(0x1 << 30)
+	bic r1, r1, #(0x1 << 31)
+
+	/*set SDHC-port2 arbitration*/
+	ldr r0, =AHBMAX_BASE_ADDR
+	ldr r1, [r0, #0xA00]
+	bic r1, r1, #(0x7 << 0)
+#endif
+
+	/*set JMP step to zero*/
+	ldr r0, =M4IF_BASE_ADDR
+	ldr r1, [r0, #0x48]
+	bic r1, r1, #(0x3 << 8)
+	str r1, [r0, #0x48]
+.endm
+
+.macro init_clock
+	ldr r0, =ROM_SI_REV
+	ldr r1, [r0]
+	cmp r1, #0x20
+
+	/* For TO2 only, set LDO to 1.3V */
+	ldr r0, =0x53fa8000
+	ldr r1, =0x00194005
+	streq r1, [r0, #0x04]
+
+	ldr r0, CCM_BASE_ADDR_W
+
+	/* Gate of clocks to the peripherals first */
+	ldr r1, =0x3FFFFFFF
+	str r1, [r0, #CLKCTL_CCGR0]
+	ldr r1, =0x0
+	str r1, [r0, #CLKCTL_CCGR1]
+	str r1, [r0, #CLKCTL_CCGR2]
+	str r1, [r0, #CLKCTL_CCGR3]
+	str r1, [r0, #CLKCTL_CCGR7]
+	ldr r1, =0x00030000
+	str r1, [r0, #CLKCTL_CCGR4]
+	ldr r1, =0x00FFF030
+	str r1, [r0, #CLKCTL_CCGR5]
+	ldr r1, =0x0F00030F
+	str r1, [r0, #CLKCTL_CCGR6]
+
+	/* Switch ARM to step clock */
+	mov r1, #0x4
+	str r1, [r0, #CLKCTL_CCSR]
+
+	setup_pll PLL1_BASE_ADDR, 800
+
+        setup_pll PLL3_BASE_ADDR, 400
+
+        /* Switch peripheral to PLL3 */
+        ldr r0, CCM_BASE_ADDR_W
+        ldr r1, CCM_VAL_0x00015154
+        str r1, [r0, #CLKCTL_CBCMR]
+        ldr r1, CCM_VAL_0x02888945
+        orr r1, r1, #(1 << 16)
+        str r1, [r0, #CLKCTL_CBCDR]
+        /* make sure change is effective */
+1:      ldr r1, [r0, #CLKCTL_CDHIPR]
+        cmp r1, #0x0
+        bne 1b
+
+        setup_pll PLL2_BASE_ADDR, CONFIG_SYS_PLL2_FREQ
+
+	/* Switch peripheral to PLL2 */
+	ldr r0, CCM_BASE_ADDR_W
+	ldr r1, CCM_VAL_0x00808145
+	orr r1, r1, #(CONFIG_SYS_AHB_PODF << 10)
+	orr r1, r1, #(CONFIG_SYS_AXIA_PODF << 16)
+	orr r1, r1, #(CONFIG_SYS_AXIB_PODF << 19)
+	str r1, [r0, #CLKCTL_CBCDR]
+
+	ldr r1, CCM_VAL_0x00016154
+	str r1, [r0, #CLKCTL_CBCMR]
+
+	/*change uart clk parent to pll2*/
+	ldr r1, [r0, #CLKCTL_CSCMR1]
+	and r1, r1, #0xfcffffff
+	orr r1, r1, #0x01000000
+	str r1, [r0, #CLKCTL_CSCMR1]
+
+	/* make sure change is effective */
+1:      ldr r1, [r0, #CLKCTL_CDHIPR]
+	cmp r1, #0x0
+	bne 1b
+
+        setup_pll PLL3_BASE_ADDR, 216
+
+	setup_pll PLL4_BASE_ADDR, 455
+
+	/* Set the platform clock dividers */
+	ldr r0, PLATFORM_BASE_ADDR_W
+	ldr r1, PLATFORM_CLOCK_DIV_W
+	str r1, [r0, #PLATFORM_ICGC]
+
+	ldr r0, CCM_BASE_ADDR_W
+	mov r1, #1
+	str r1, [r0, #CLKCTL_CACRR]
+
+	/* Switch ARM back to PLL 1. */
+	mov r1, #0x0
+	str r1, [r0, #CLKCTL_CCSR]
+
+	/* make uart div=6*/
+	ldr r1, [r0, #CLKCTL_CSCDR1]
+	and r1, r1, #0xffffffc0
+	orr r1, r1, #0x0a
+	str r1, [r0, #CLKCTL_CSCDR1]
+
+	/* Restore the default values in the Gate registers */
+	ldr r1, =0xFFFFFFFF
+	str r1, [r0, #CLKCTL_CCGR0]
+	str r1, [r0, #CLKCTL_CCGR1]
+	str r1, [r0, #CLKCTL_CCGR2]
+	str r1, [r0, #CLKCTL_CCGR3]
+	str r1, [r0, #CLKCTL_CCGR4]
+	str r1, [r0, #CLKCTL_CCGR5]
+	str r1, [r0, #CLKCTL_CCGR6]
+	str r1, [r0, #CLKCTL_CCGR7]
+
+        mov r1, #0x00000
+        str r1, [r0, #CLKCTL_CCDR]
+
+        /* for cko - for ARM div by 8 */
+        mov r1, #0x000A0000
+        add r1, r1, #0x00000F0
+        str r1, [r0, #CLKCTL_CCOSR]
+.endm
+
+.section ".text.init", "x"
+
+.globl lowlevel_init
+lowlevel_init:
+
+#ifdef ENABLE_IMPRECISE_ABORT
+        mrs r1, spsr            /* save old spsr */
+        mrs r0, cpsr            /* read out the cpsr */
+	bic r0, r0, #0x100      /* clear the A bit */
+	msr spsr, r0            /* update spsr */
+	add lr, pc, #0x8        /* update lr */
+        movs pc, lr             /* update cpsr */
+        nop
+        nop
+        nop
+	nop
+	msr spsr, r1            /* restore old spsr */
+#endif
+
+	/* ARM errata ID #468414 */
+	mrc 15, 0, r1, c1, c0, 1
+	orr r1, r1, #(1 << 5)    /* enable L1NEON bit */
+	mcr 15, 0, r1, c1, c0, 1
+
+	init_l2cc
+
+	init_aips
+
+#ifdef CONFIG_ADJUST_WIFI_FEC_PERFORMANCE
+        /*increase WIFI & FEC priority of accessing bus*/
+        init_m4if
+#endif
+
+	init_clock
+
+	mov pc, lr
+
+/* Board level setting value */
+CCM_BASE_ADDR_W:        .word CCM_BASE_ADDR
+CCM_VAL_0x00016154:     .word 0x00016154
+CCM_VAL_0x00808145:     .word 0x00808145
+CCM_VAL_0x00015154:     .word 0x00015154
+CCM_VAL_0x02888945:     .word 0x02888945
+W_DP_OP_800:           	.word DP_OP_800
+W_DP_MFD_800:           .word DP_MFD_800
+W_DP_MFN_800:           .word DP_MFN_800
+W_DP_OP_600:            .word DP_OP_600
+W_DP_MFD_600:           .word DP_MFD_600
+W_DP_MFN_600:           .word DP_MFN_600
+W_DP_OP_400:            .word DP_OP_400
+W_DP_MFD_400:           .word DP_MFD_400
+W_DP_MFN_400:           .word DP_MFN_400
+W_DP_OP_216:            .word DP_OP_216
+W_DP_MFD_216:           .word DP_MFD_216
+W_DP_MFN_216:           .word DP_MFN_216
+W_DP_OP_455:            .word DP_OP_455
+W_DP_MFD_455:           .word DP_MFD_455
+W_DP_MFN_455:           .word DP_MFN_455
+PLATFORM_BASE_ADDR_W:   .word ARM_BASE_ADDR
+PLATFORM_CLOCK_DIV_W:   .word 0x00000124

board/freescale/mx53_evk/u-boot.lds

@@ -0,0 +1,74 @@
+/*
+ * January 2004 - Changed to support H4 device
+ * Copyright (c) 2004 Texas Instruments
+ *
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
+ *
+ * (C) Copyright 2010 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+	. = 0x00000000;
+
+	. = ALIGN(4);
+	.text	   :
+	{
+	  /* WARNING - the following is hand-optimized to fit within	*/
+	  /* the sector layout of our flash chips!	XXX FIXME XXX	*/
+	  board/freescale/mx53_evk/flash_header.o	(.text.flasheader)
+	  cpu/arm_cortexa8/start.o
+	  board/freescale/mx53_evk/libmx53_evk.a	(.text)
+	  lib_arm/libarm.a		(.text)
+	  net/libnet.a			(.text)
+	  drivers/mtd/libmtd.a		(.text)
+	  drivers/mmc/libmmc.a		(.text)
+
+	  . = DEFINED(env_offset) ? env_offset : .;
+	  common/env_embedded.o(.text)
+
+	  *(.text)
+	}
+
+	. = ALIGN(4);
+	.rodata : { *(.rodata) }
+
+	. = ALIGN(4);
+	.data : { *(.data) }
+
+	. = ALIGN(4);
+	.got : { *(.got) }
+
+	. = .;
+	__u_boot_cmd_start = .;
+	.u_boot_cmd : { *(.u_boot_cmd) }
+	__u_boot_cmd_end = .;
+
+	. = ALIGN(4);
+	_end_of_copy = .; /* end_of ROM copy code here */
+	__bss_start = .;
+	.bss : { *(.bss) }
+	_end = .;
+}

board/freescale/mx53_loco/Makefile

@@ -0,0 +1,47 @@
+#
+# (C) Copyright 2010 Freescale Semiconductor, Inc.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).a
+
+COBJS	:= mx53_loco.o
+SOBJS	:= lowlevel_init.o flash_header.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################

board/freescale/mx53_loco/config.mk

@@ -0,0 +1,3 @@
+LDSCRIPT := $(SRCTREE)/board/$(VENDOR)/$(BOARD)/u-boot.lds
+
+TEXT_BASE = 0x77800000

board/freescale/mx53_loco/flash_header.S

@@ -0,0 +1,230 @@
+/*
+ * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <asm/arch/mx53.h>
+
+#define REG_LD_AND_STR_INIT(base)	\
+	ldr r0, =base;
+
+#define REG_LD_AND_STR_OP(i, offset, val)	\
+	ldr r1, =val;	\
+	ldr r2, =offset;	\
+	str r1, [r0, r2];
+
+#define REG_LD_AND_STR_END(base)
+
+
+#ifdef	CONFIG_FLASH_HEADER
+#ifndef CONFIG_FLASH_HEADER_OFFSET
+# error "Must define the offset of flash header"
+#endif
+
+.section ".text.flasheader", "x"
+	b	_start
+	.org	CONFIG_FLASH_HEADER_OFFSET
+
+ivt_header:		.long 0x402000D1/* Tag=0xD1, Len=0x0020, Ver=0x40 */
+app_code_jump_v:	.long (0xF8006000 + (plugin_start - TEXT_BASE))
+reserv1:		.long 0x0
+dcd_ptr:		.long 0x0
+boot_data_ptr:		.long (0xF8006000 + (boot_data - TEXT_BASE))
+self_ptr:		.long (0xF8006000 + (ivt_header - TEXT_BASE))
+app_code_csf:		.long 0x0
+reserv2:		.long 0x0
+boot_data:		.long 0xF8006000
+image_len:		.long (3 * 1024)
+plugin:			.long 0x1
+
+/* Second IVT to give entry point into the bootloader copied to DDR */
+ivt2_header:		.long 0x402000D1/*Tag=0xD1, Len=0x0020, Ver=0x40 */
+app2_code_jump_v:	.long _start   /* Entry point for the bootloader */
+reserv3:		.long 0x0
+dcd2_ptr:		.long 0x0
+boot_data2_ptr:		.long boot_data2
+self_ptr2:		.long ivt2_header
+app_code_csf2:		.long 0x0
+reserv4:		.long 0x0
+boot_data2:		.long TEXT_BASE
+image_len2:		.long  _end_of_copy - TEXT_BASE + CONFIG_FLASH_HEADER_OFFSET
+plugin2:		.long 0x0
+
+/* Here starts the plugin code */
+plugin_start:
+	/* Save the return address and the function arguments */
+	push {r0-r6, lr}
+	/* We should distinguish USB recovery mode(SDP mode) and internal boot mode.
+	If ROM runs in SDP mode, then it needn't load boot code from storage media.
+	If ROM runs in SDP mode, then r0 must be 0x00
+	If ROM runs in internal boot mode, then r0 should be larger than IRAM base address. */
+	mov r7, r0
+
+	/* IOMUX */
+	REG_LD_AND_STR_INIT(IOMUXC_BASE_ADDR)
+	REG_LD_AND_STR_OP(1, 0x554, 0x00300000)
+	REG_LD_AND_STR_OP(2, 0x558, 0x00300040)
+	REG_LD_AND_STR_OP(3, 0x560, 0x00300000)
+	REG_LD_AND_STR_OP(4, 0x564, 0x00300040)
+	REG_LD_AND_STR_OP(5, 0x568, 0x00300040)
+	REG_LD_AND_STR_OP(6, 0x570, 0x00300000)
+	REG_LD_AND_STR_OP(7, 0x574, 0x00300000)
+	REG_LD_AND_STR_OP(8, 0x578, 0x00300000)
+	REG_LD_AND_STR_OP(9, 0x57c, 0x00300040)
+	REG_LD_AND_STR_OP(10, 0x580, 0x00300040)
+	REG_LD_AND_STR_OP(11, 0x584, 0x00300000)
+	REG_LD_AND_STR_OP(12, 0x588, 0x00300000)
+	REG_LD_AND_STR_OP(13, 0x590, 0x00300040)
+	REG_LD_AND_STR_OP(14, 0x594, 0x00300000)
+	REG_LD_AND_STR_OP(15, 0x6f0, 0x00300000)
+	REG_LD_AND_STR_OP(16, 0x6f4, 0x00000000)
+	REG_LD_AND_STR_OP(17, 0x6fc, 0x00000000)
+	REG_LD_AND_STR_OP(18, 0x714, 0x00000000)
+	REG_LD_AND_STR_OP(19, 0x718, 0x00300000)
+	REG_LD_AND_STR_OP(20, 0x71c, 0x00300000)
+	REG_LD_AND_STR_OP(21, 0x720, 0x00300000)
+	REG_LD_AND_STR_OP(22, 0x724, 0x04000000)
+	REG_LD_AND_STR_OP(23, 0x728, 0x00300000)
+	REG_LD_AND_STR_OP(24, 0x72c, 0x00300000)
+	REG_LD_AND_STR_END(IOMUXC_BASE_ADDR)
+
+	/* ESDCTL */
+	REG_LD_AND_STR_INIT(ESDCTL_BASE_ADDR)
+	REG_LD_AND_STR_OP(25, 0x088, 0x35343535)
+	REG_LD_AND_STR_OP(26, 0x090, 0x4d444c44)
+	REG_LD_AND_STR_OP(27, 0x07c, 0x01370138)
+	REG_LD_AND_STR_OP(28, 0x080, 0x013b013c)
+	REG_LD_AND_STR_OP(29, 0x0f8, 0x00000800)
+	REG_LD_AND_STR_OP(30, 0x018, 0x00001740)
+	REG_LD_AND_STR_OP(31, 0x000, 0xc3190000)
+	REG_LD_AND_STR_OP(32, 0x00c, 0x9f5152e3)
+	REG_LD_AND_STR_OP(33, 0x010, 0xb68e8a63)
+	REG_LD_AND_STR_OP(34, 0x014, 0x01ff00db)
+	REG_LD_AND_STR_OP(35, 0x02c, 0x000026d2)
+	REG_LD_AND_STR_OP(36, 0x030, 0x009f0e21)
+	REG_LD_AND_STR_OP(37, 0x008, 0x12273030)
+	REG_LD_AND_STR_OP(38, 0x004, 0x0002002d)
+	REG_LD_AND_STR_OP(39, 0x01c, 0x00008032)
+	REG_LD_AND_STR_OP(40, 0x01c, 0x00008033)
+	REG_LD_AND_STR_OP(41, 0x01c, 0x00028031)
+	REG_LD_AND_STR_OP(42, 0x01c, 0x052080b0)
+	REG_LD_AND_STR_OP(43, 0x01c, 0x04008040)
+	REG_LD_AND_STR_OP(44, 0x01c, 0x0000803a)
+	REG_LD_AND_STR_OP(45, 0x01c, 0x0000803b)
+	REG_LD_AND_STR_OP(46, 0x01c, 0x00028039)
+	REG_LD_AND_STR_OP(47, 0x01c, 0x05208138)
+	REG_LD_AND_STR_OP(48, 0x01c, 0x04008048)
+	REG_LD_AND_STR_OP(49, 0x020, 0x00005800)
+	REG_LD_AND_STR_OP(50, 0x040, 0x04b80003)
+	REG_LD_AND_STR_OP(51, 0x058, 0x00022227)
+	REG_LD_AND_STR_OP(52, 0x01C, 0x00000000)
+	REG_LD_AND_STR_END(ESDCTL_BASE_ADDR)
+
+/*
+ *  The following is to fill in those arguments for this ROM function
+ * pu_irom_hwcnfg_setup(void **start, size_t *bytes, const void *boot_data)
+ *
+ *  This function is used to copy data from the storage media into DDR.
+ *
+ *  start - Initial (possibly partial) image load address on entry. Final image
+ *            load address on exit.
+ *  bytes - Initial (possibly partial) image size on entry. Final image size on
+ *             exit.
+ *  boot_data - Initial @ref ivt Boot Data load address.
+ */
+
+	adr r0, DDR_DEST_ADDR
+	adr r1, COPY_SIZE
+	adr r2, BOOT_DATA
+before_calling_rom___pu_irom_hwcnfg_setup:
+
+	/* We should distinguish USB recovery mode(SDP mode) and internal boot mode.
+	If ROM runs in SDP mode, then it needn't load boot code from storage media.
+	If ROM runs in SDP mode, then r0 must be 0x00
+	If ROM runs in internal boot mode, then r0 should be larger than IRAM base address. */
+	cmp r7, #0xF8000000
+	bls return_sdp
+	/* Different ROM address for TO 1.0 & TO 2.0 */
+	ldr r3, =ROM_SI_REV
+	ldr r4, [r3]
+
+	cmp r4, #0x21
+	/* TO2.1 */
+	moveq r6, #0x1800
+	addeq r6, r6, #0x4d
+	beq 2f
+
+	cmp r4, #0x20
+	/* TO2 */
+	moveq r6, #0x1800
+	addeq r6, r6, #0x4d
+	beq 2f
+
+	/* TO1 */
+	mov r6, #0x400000
+	add r6, r6, #0x5000
+	add r6, r6, #0xc7
+
+2:
+	blx r6 /* This address might change in future ROM versions */
+after_calling_rom___pu_irom_hwcnfg_setup:
+
+return_sdp:
+	cmp r7, #0xF8000000
+	bhi quit_plugin
+
+	/* Workaround run plug-ins in SDP mode without USB re-enumeration.
+	how it works:
+	ROM running in usb download mode.
+	Host manufacturing application sends SDP command to download plug-in image.
+	Host manufacturing application sends SDP command to jump to plug-in image and run it.
+	Plug-in starts execution and after its regular tasks plug-in will then call into ROM
+	call into pl_parse_and_handle() */
+	ldr r3, =ROM_SI_REV
+	ldr r5, [r3]
+	cmp r5, #0x20       /* check silicon revision to determine the function entry address */
+
+	ldrlt r4, =0x00000edd   /* function entry in TO1 ROM */
+	ldrge r4, =0x0040487d   /* function entry in TO2 ROM */
+	blx r4
+
+/* To return to ROM from plugin, we need to fill in these argument.
+ * Here is what need to do:
+ * Need to construct the paramters for this function before return to ROM:
+ * plugin_download(void **start, size_t *bytes, UINT32 *ivt_offset)
+ */
+quit_plugin:
+	pop {r0-r6, lr}
+	ldr r7, DDR_DEST_ADDR
+	str r7, [r0]
+	ldr r7, COPY_SIZE
+	str r7, [r1]
+	mov r7, #0x400  /* Point to the second IVT table at offset 0x42C */
+	add r7, r7, #0x2C
+	str r7, [r2]
+	mov r0, #1
+
+	bx lr  /* return back to ROM code */
+
+DDR_DEST_ADDR:    .word   TEXT_BASE
+COPY_SIZE:        .word   _end - TEXT_BASE
+BOOT_DATA:        .word   TEXT_BASE
+                  .word   _end - TEXT_BASE
+                  .word   0
+
+#endif

board/freescale/mx53_loco/lowlevel_init.S

@@ -0,0 +1,372 @@
+/*
+ * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <asm/arch/mx53.h>
+
+/*
+ * L2CC Cache setup/invalidation/disable
+ */
+.macro init_l2cc
+	/* explicitly disable L2 cache */
+        mrc 15, 0, r0, c1, c0, 1
+        bic r0, r0, #0x2
+        mcr 15, 0, r0, c1, c0, 1
+
+        /* reconfigure L2 cache aux control reg */
+        mov r0, #0xC0                   /* tag RAM */
+        add r0, r0, #0x4                /* data RAM */
+        orr r0, r0, #(1 << 24)          /* disable write allocate delay */
+        orr r0, r0, #(1 << 23)          /* disable write allocate combine */
+        orr r0, r0, #(1 << 22)          /* disable write allocate */
+
+	mcr 15, 1, r0, c9, c0, 2
+.endm /* init_l2cc */
+
+/* AIPS setup - Only setup MPROTx registers.
+ * The PACR default values are good.*/
+.macro init_aips
+	/*
+	 * Set all MPROTx to be non-bufferable, trusted for R/W,
+	 * not forced to user-mode.
+	 */
+	ldr r0, =AIPS1_BASE_ADDR
+	ldr r1, =0x77777777
+	str r1, [r0, #0x0]
+	str r1, [r0, #0x4]
+	ldr r0, =AIPS2_BASE_ADDR
+	str r1, [r0, #0x0]
+	str r1, [r0, #0x4]
+.endm /* init_aips */
+
+.macro setup_pll pll, freq
+	/*
+	 * If freq < 300MHz, we need to set dpdck0_2_en to 0
+	 */
+	ldr r0, =\freq
+	ldr r1, =0x300
+	cmp r0, r1
+	ldrcs r1, =0x00001232
+	ldrcc r1, =0x00000232
+	ldr r0, =\pll
+	str r1, [r0, #PLL_DP_CTL]
+	mov r1, #0x2
+	str r1, [r0, #PLL_DP_CONFIG]
+
+	ldr r1, W_DP_OP_\freq
+	str r1, [r0, #PLL_DP_OP]
+	str r1, [r0, #PLL_DP_HFS_OP]
+
+	ldr r1,	W_DP_MFD_\freq
+	str r1, [r0, #PLL_DP_MFD]
+	str r1, [r0, #PLL_DP_HFS_MFD]
+
+	ldr r1,  W_DP_MFN_\freq
+	str r1, [r0, #PLL_DP_MFN]
+	str r1, [r0, #PLL_DP_HFS_MFN]
+
+	ldr r1, =0x00001232
+	str r1, [r0, #PLL_DP_CTL]
+1:	ldr r1, [r0, #PLL_DP_CTL]
+	ands r1, r1, #0x1
+	beq 1b
+.endm
+
+.macro init_m4if
+	/*increase master2 priority for WIFI*/
+	ldr r0, =M4IF_BASE_ADDR
+	ldr r1, [r0, #0x40]
+	orr r1, r1, #(0x33 << 16)
+	str r1, [r0, #0x40]
+
+	/*increase master4 priority for FEC*/
+	ldr r1, [r0, #0x44]
+	orr r1, r1, #0x33
+	str r1, [r0, #0x44]
+
+	/*set SDHC-port3 high priority to all AHB MAX Slave port*/
+	ldr r0, =AHBMAX_BASE_ADDR
+
+#ifdef CONFIG_WIFI_SDHC_PORT3
+	/*set PARK to SDHC-port3*/
+	ldr r0, =AHBMAX_BASE_ADDR
+	ldr r1, [r0, #0x10]
+	bic r1, r1, #(0x7 << 0)
+	orr r1, r1, #0x3
+	bic r1, r1, #(0x3 << 4)
+	bic r1, r1, #(0x3 << 8)
+	orr r1, r1, #(0x1 << 30)
+	bic r1, r1, #(0x1 << 31)
+
+	ldr r1, [r0, #0x110]
+	bic r1, r1, #(0x7 << 0)
+	orr r1, r1, #0x3
+	bic r1, r1, #(0x3 << 4)
+	bic r1, r1, #(0x3 << 8)
+	orr r1, r1, #(0x1 << 30)
+	bic r1, r1, #(0x1 << 31)
+
+	ldr r1, [r0, #0x210]
+	bic r1, r1, #(0x7 << 0)
+	orr r1, r1, #0x3
+	bic r1, r1, #(0x3 << 4)
+	bic r1, r1, #(0x3 << 8)
+	orr r1, r1, #(0x1 << 30)
+	bic r1, r1, #(0x1 << 31)
+
+	ldr r1, [r0, #0x310]
+	bic r1, r1, #(0x7 << 0)
+	orr r1, r1, #0x3
+	bic r1, r1, #(0x3 << 4)
+	bic r1, r1, #(0x3 << 8)
+	orr r1, r1, #(0x1 << 30)
+	bic r1, r1, #(0x1 << 31)
+
+	/*set SDHC-port3 arbitration*/
+	ldr r0, =AHBMAX_BASE_ADDR
+	ldr r1, [r0, #0xb00]
+	bic r1, r1, #(0x7 << 0)
+	orr r1, r1, #0x1
+#endif
+
+#ifdef CONFIG_WIFI_SDHC_PORT2
+	/*set PARK to SDHC-port3*/
+	ldr r0, =AHBMAX_BASE_ADDR
+	ldr r1, [r0, #0x10]
+	bic r1, r1, #(0x7 << 0)
+	orr r1, r1, #0x2
+	bic r1, r1, #(0x3 << 4)
+	bic r1, r1, #(0x3 << 8)
+	orr r1, r1, #(0x1 << 30)
+	bic r1, r1, #(0x1 << 31)
+
+	ldr r1, [r0, #0x110]
+	bic r1, r1, #(0x7 << 0)
+	orr r1, r1, #0x2
+	bic r1, r1, #(0x3 << 4)
+	bic r1, r1, #(0x3 << 8)
+	orr r1, r1, #(0x1 << 30)
+	bic r1, r1, #(0x1 << 31)
+
+	ldr r1, [r0, #0x210]
+	bic r1, r1, #(0x7 << 0)
+	orr r1, r1, #0x2
+	bic r1, r1, #(0x3 << 4)
+	bic r1, r1, #(0x3 << 8)
+	orr r1, r1, #(0x1 << 30)
+	bic r1, r1, #(0x1 << 31)
+
+	ldr r1, [r0, #0x310]
+	bic r1, r1, #(0x7 << 0)
+	orr r1, r1, #0x2
+	bic r1, r1, #(0x3 << 4)
+	bic r1, r1, #(0x3 << 8)
+	orr r1, r1, #(0x1 << 30)
+	bic r1, r1, #(0x1 << 31)
+
+	/*set SDHC-port2 arbitration*/
+	ldr r0, =AHBMAX_BASE_ADDR
+	ldr r1, [r0, #0xA00]
+	bic r1, r1, #(0x7 << 0)
+#endif
+
+	/*set JMP step to zero*/
+	ldr r0, =M4IF_BASE_ADDR
+	ldr r1, [r0, #0x48]
+	bic r1, r1, #(0x3 << 8)
+	str r1, [r0, #0x48]
+.endm
+
+.macro init_clock
+	ldr r0, =ROM_SI_REV
+	ldr r1, [r0]
+	cmp r1, #0x20
+
+	/* For TO2 only, set LDO to 1.3V */
+	ldr r0, =0x53fa8000
+	ldr r1, =0x00194005
+	streq r1, [r0, #0x04]
+
+	ldr r0, CCM_BASE_ADDR_W
+
+	/* Gate of clocks to the peripherals first */
+	ldr r1, =0x3FFFFFFF
+	str r1, [r0, #CLKCTL_CCGR0]
+	ldr r1, =0x0
+	str r1, [r0, #CLKCTL_CCGR1]
+	str r1, [r0, #CLKCTL_CCGR2]
+	str r1, [r0, #CLKCTL_CCGR3]
+	str r1, [r0, #CLKCTL_CCGR7]
+	ldr r1, =0x00030000
+	str r1, [r0, #CLKCTL_CCGR4]
+	ldr r1, =0x00FFF030
+	str r1, [r0, #CLKCTL_CCGR5]
+	ldr r1, =0x0F00030F
+	str r1, [r0, #CLKCTL_CCGR6]
+
+	/* Switch ARM to step clock */
+	mov r1, #0x4
+	str r1, [r0, #CLKCTL_CCSR]
+
+	setup_pll PLL1_BASE_ADDR, 800
+
+        setup_pll PLL3_BASE_ADDR, 400
+
+        /* Switch peripheral to PLL3 */
+        ldr r0, CCM_BASE_ADDR_W
+        ldr r1, CCM_VAL_0x00015154
+        str r1, [r0, #CLKCTL_CBCMR]
+        ldr r1, CCM_VAL_0x02888945
+        orr r1, r1, #(1 << 16)
+        str r1, [r0, #CLKCTL_CBCDR]
+        /* make sure change is effective */
+1:      ldr r1, [r0, #CLKCTL_CDHIPR]
+        cmp r1, #0x0
+        bne 1b
+
+        setup_pll PLL2_BASE_ADDR, CONFIG_SYS_PLL2_FREQ
+
+	/* Switch peripheral to PLL2 */
+	ldr r0, CCM_BASE_ADDR_W
+	ldr r1, CCM_VAL_0x00808145
+	orr r1, r1, #(CONFIG_SYS_AHB_PODF << 10)
+	orr r1, r1, #(CONFIG_SYS_AXIA_PODF << 16)
+	orr r1, r1, #(CONFIG_SYS_AXIB_PODF << 19)
+	str r1, [r0, #CLKCTL_CBCDR]
+
+	ldr r1, CCM_VAL_0x00016154
+	str r1, [r0, #CLKCTL_CBCMR]
+
+	/*change uart clk parent to pll2*/
+	ldr r1, [r0, #CLKCTL_CSCMR1]
+	and r1, r1, #0xfcffffff
+	orr r1, r1, #0x01000000
+	str r1, [r0, #CLKCTL_CSCMR1]
+
+	/* make sure change is effective */
+1:      ldr r1, [r0, #CLKCTL_CDHIPR]
+	cmp r1, #0x0
+	bne 1b
+
+        setup_pll PLL3_BASE_ADDR, 216
+
+	setup_pll PLL4_BASE_ADDR, 455
+
+	/* Set the platform clock dividers */
+	ldr r0, PLATFORM_BASE_ADDR_W
+	ldr r1, PLATFORM_CLOCK_DIV_W
+	str r1, [r0, #PLATFORM_ICGC]
+
+	ldr r0, CCM_BASE_ADDR_W
+	mov r1, #0
+	str r1, [r0, #CLKCTL_CACRR]
+
+	/* Switch ARM back to PLL 1. */
+	mov r1, #0x0
+	str r1, [r0, #CLKCTL_CCSR]
+
+	/* make uart div=6*/
+	ldr r1, [r0, #CLKCTL_CSCDR1]
+	and r1, r1, #0xffffffc0
+	orr r1, r1, #0x0a
+	str r1, [r0, #CLKCTL_CSCDR1]
+
+	/* Restore the default values in the Gate registers */
+	ldr r1, =0xFFFFFFFF
+	str r1, [r0, #CLKCTL_CCGR0]
+	str r1, [r0, #CLKCTL_CCGR1]
+	str r1, [r0, #CLKCTL_CCGR2]
+	str r1, [r0, #CLKCTL_CCGR3]
+	str r1, [r0, #CLKCTL_CCGR4]
+	str r1, [r0, #CLKCTL_CCGR5]
+	str r1, [r0, #CLKCTL_CCGR6]
+	str r1, [r0, #CLKCTL_CCGR7]
+
+        mov r1, #0x00000
+        str r1, [r0, #CLKCTL_CCDR]
+
+        /* for cko - for ARM div by 8 */
+        mov r1, #0x000A0000
+        add r1, r1, #0x00000F0
+        str r1, [r0, #CLKCTL_CCOSR]
+.endm
+
+.section ".text.init", "x"
+
+.globl lowlevel_init
+lowlevel_init:
+
+#ifdef ENABLE_IMPRECISE_ABORT
+        mrs r1, spsr            /* save old spsr */
+        mrs r0, cpsr            /* read out the cpsr */
+	bic r0, r0, #0x100      /* clear the A bit */
+	msr spsr, r0            /* update spsr */
+	add lr, pc, #0x8        /* update lr */
+        movs pc, lr             /* update cpsr */
+        nop
+        nop
+        nop
+	nop
+	msr spsr, r1            /* restore old spsr */
+#endif
+
+	/* ARM errata ID #468414 */
+	mrc 15, 0, r1, c1, c0, 1
+	orr r1, r1, #(1 << 5)    /* enable L1NEON bit */
+	mcr 15, 0, r1, c1, c0, 1
+
+	init_l2cc
+
+	init_aips
+
+#ifdef CONFIG_ADJUST_WIFI_FEC_PERFORMANCE
+        /*increase WIFI & FEC priority of accessing bus*/
+        init_m4if
+#endif
+
+	init_clock
+
+	mov pc, lr
+
+/* Board level setting value */
+CCM_BASE_ADDR_W:        .word CCM_BASE_ADDR
+CCM_VAL_0x00016154:     .word 0x00016154
+CCM_VAL_0x00808145:     .word 0x00808145
+CCM_VAL_0x00015154:     .word 0x00015154
+CCM_VAL_0x02888945:     .word 0x02888945
+W_DP_OP_1000:           .word DP_OP_1000
+W_DP_MFD_1000:          .word DP_MFD_1000
+W_DP_MFN_1000:          .word DP_MFN_1000
+W_DP_OP_800:           	.word DP_OP_800
+W_DP_MFD_800:           .word DP_MFD_800
+W_DP_MFN_800:           .word DP_MFN_800
+W_DP_OP_600:            .word DP_OP_600
+W_DP_MFD_600:           .word DP_MFD_600
+W_DP_MFN_600:           .word DP_MFN_600
+W_DP_OP_400:            .word DP_OP_400
+W_DP_MFD_400:           .word DP_MFD_400
+W_DP_MFN_400:           .word DP_MFN_400
+W_DP_OP_216:            .word DP_OP_216
+W_DP_MFD_216:           .word DP_MFD_216
+W_DP_MFN_216:           .word DP_MFN_216
+W_DP_OP_455:            .word DP_OP_455
+W_DP_MFD_455:           .word DP_MFD_455
+W_DP_MFN_455:           .word DP_MFN_455
+PLATFORM_BASE_ADDR_W:   .word ARM_BASE_ADDR
+PLATFORM_CLOCK_DIV_W:   .word 0x00000124

board/freescale/mx53_loco/u-boot.lds

@@ -0,0 +1,68 @@
+/*
+ * (C) Copyright 2010 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+	. = 0x00000000;
+
+	. = ALIGN(4);
+	.text	   :
+	{
+	  /* WARNING - the following is hand-optimized to fit within	*/
+	  /* the sector layout of our flash chips!	XXX FIXME XXX	*/
+	  board/freescale/mx53_loco/flash_header.o	(.text.flasheader)
+	  cpu/arm_cortexa8/start.o
+	  board/freescale/mx53_loco/libmx53_loco.a	(.text)
+	  lib_arm/libarm.a		(.text)
+	  net/libnet.a			(.text)
+	  drivers/mtd/libmtd.a		(.text)
+	  drivers/mmc/libmmc.a		(.text)
+
+	  . = DEFINED(env_offset) ? env_offset : .;
+	  common/env_embedded.o(.text)
+
+	  *(.text)
+	}
+
+	. = ALIGN(4);
+	.rodata : { *(.rodata) }
+
+	. = ALIGN(4);
+	.data : { *(.data) }
+
+	. = ALIGN(4);
+	.got : { *(.got) }
+
+	. = .;
+	__u_boot_cmd_start = .;
+	.u_boot_cmd : { *(.u_boot_cmd) }
+	__u_boot_cmd_end = .;
+
+	. = ALIGN(4);
+	_end_of_copy = .; /* end_of ROM copy code here */
+	__bss_start = .;
+	.bss : { *(.bss) }
+	_end = .;
+}

board/freescale/mx53_pcba/Makefile

@@ -0,0 +1,47 @@
+#
+# (C) Copyright 2011 Freescale Semiconductor, Inc.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).a
+
+COBJS	:= mx53_pcba.o
+SOBJS	:= lowlevel_init.o flash_header.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################

board/freescale/mx53_pcba/config.mk

@@ -0,0 +1,3 @@
+LDSCRIPT := $(SRCTREE)/board/$(VENDOR)/$(BOARD)/u-boot.lds
+
+TEXT_BASE = 0x77800000

board/freescale/mx53_pcba/flash_header.S

@@ -0,0 +1,674 @@
+/*
+ * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <asm/arch/mx53.h>
+
+#ifdef	CONFIG_FLASH_HEADER
+#ifndef CONFIG_FLASH_HEADER_OFFSET
+# error "Must define the offset of flash header"
+#endif
+
+
+.section ".text.flasheader", "x"
+	b	_start
+	.org	CONFIG_FLASH_HEADER_OFFSET
+
+ivt_header:             .long 0x402000D1    /* Tag=0xD1, Len=0x0020, Ver=0x40 */
+app_code_jump_v:        .long (0xF8006000 + (plugin_start - TEXT_BASE))
+reserv1:                .long 0x0
+dcd_ptr:                .long 0x0
+boot_data_ptr:          .long (0xF8006000 + (boot_data - TEXT_BASE))
+self_ptr:               .long (0xF8006000 + (ivt_header - TEXT_BASE))
+app_code_csf:           .long 0x0
+reserv2:                .long 0x0
+boot_data:              .long 0xF8006000
+image_len:              .long 4*1024
+plugin:                 .long 0x1
+
+/* Second IVT to give entry point into the bootloader copied to DDR */
+ivt2_header:            .long 0x402000D1    /*Tag=0xD1, Len=0x0020, Ver=0x40 */
+app2_code_jump_v:       .long _start   /* Entry point for the bootloader */
+reserv3:                .long 0x0
+dcd2_ptr:               .long 0x0
+boot_data2_ptr:         .long boot_data2
+self_ptr2:              .long ivt2_header
+app_code_csf2:          .long 0x0
+reserv4:                .long 0x0
+boot_data2:             .long TEXT_BASE
+image_len2:             .long  _end - TEXT_BASE
+plugin2:                .long 0x0
+
+
+/* Here starts the plugin code */
+plugin_start:
+    /* Save the return address and the function arguments */
+    push    {r0-r6, lr}
+    /* We should distinguish USB recovery mode(SDP mode) and internal boot mode.
+    If ROM runs in SDP mode, then it needn't load boot code from storage media.
+    If ROM runs in SDP mode, then r0 must be 0x00
+    If ROM runs in internal boot mode, then r0 should be larger than IRAM base address. */
+    mov     r7,	r0
+
+/* DDR3 script for SMD and ARM2 CPU3 board */
+    /* IOMUX Setup */
+    ldr r0, =0x53fa8500
+    mov r1, #0x00300000
+    add r2, r1, #0x40
+
+    str r1, [r0, #0x54]
+    str r2, [r0, #0x58]
+    str r1, [r0, #0x60]
+    str r2, [r0, #0x64]
+    str r2, [r0, #0x68]
+    str r1, [r0, #0x70]
+    str r1, [r0, #0x74]
+    str r1, [r0, #0x78]
+    str r2, [r0, #0x7c]
+    str r2, [r0, #0x80]
+    str r1, [r0, #0x84]
+    str r1, [r0, #0x88]
+    str r2, [r0, #0x90]
+    str r1, [r0, #0x94]
+
+    ldr r0, =0x53fa8600
+    str r1, [r0, #0xf0]
+    mov r2, #0x00000000
+    str r2, [r0, #0xf4]
+    str r2, [r0, #0xfc]
+
+    ldr r0, =0x53fa8700
+    str r2, [r0, #0x14]
+    str r1, [r0, #0x18]
+    str r1, [r0, #0x1c]
+    str r1, [r0, #0x20]
+    mov r2, #0x04000000
+    str r2, [r0, #0x24]
+    str r1, [r0, #0x28]
+    str r1, [r0, #0x2c]
+
+    /* Initialize DDR3 memory for calibration */
+    ldr r0, =ESDCTL_BASE_ADDR
+
+    ldr r1, =0x01340135
+    str r1, [r0, #0x07c]
+    ldr r1, =0x01390139
+    str r1, [r0, #0x080]
+    ldr r1, =0x35343534
+    str r1, [r0, #0x088]
+    ldr r1, =0x4f485146
+    str r1, [r0, #0x090]
+
+    ldr r1, =0x00000800
+    str r1, [r0, #0xf8]
+
+    ldr r1, =0x00011740
+    str r1, [r0, #0x018]
+
+    ldr r1, =0xc3190000
+    str r1, [r0, #0x00]
+
+    ldr r1, =0x9f515333
+    str r1, [r0, #0x0C]
+
+    ldr r1, =0xb68e8a63
+    str r1, [r0, #0x10]
+
+    ldr r1, =0x01ff00db
+    str r1, [r0, #0x14]
+
+    ldr r1, =0x000026d2
+    str r1, [r0, #0x2C]
+
+    ldr r1, =0x009f0e21
+    str r1, [r0, #0x30]
+
+    ldr r1, =0x12373030
+    str r1, [r0, #0x08]
+
+    ldr r1, =0x4402002d
+    str r1, [r0, #0x04]
+
+    ldr r1, =0x00008032
+    str r1, [r0, #0x1C]
+
+    ldr r1, =0x00008033
+    str r1, [r0, #0x1C]
+
+    ldr r1, =0x00028031
+    str r1, [r0, #0x1C]
+
+    ldr r1, =0x092080b0
+    str r1, [r0, #0x1C]
+
+    ldr r1, =0x04008040
+    str r1, [r0, #0x1C]
+
+    ldr r1, =0x0000803a
+    str r1, [r0, #0x1C]
+
+    ldr r1, =0x0000803b
+    str r1, [r0, #0x1C]
+
+    ldr r1, =0x00028039
+    str r1, [r0, #0x1C]
+
+    ldr r1, =0x09208138
+    str r1, [r0, #0x1C]
+
+    ldr r1, =0x04008048
+    str r1, [r0, #0x1C]
+
+    ldr r1, =0x00001800
+    str r1, [r0, #0x20]
+
+//    ldr r1, =0x04b80003
+    ldr r1, =0x04b90003
+    str r1, [r0, #0x40]
+
+    ldr r1, =0x00022227
+    str r1, [r0, #0x58]
+
+    ldr r1, =0x00000000
+    str r1, [r0, #0x1C]
+
+    ldr r6, =0x0
+
+retry:
+	add r6, r6, #0x1
+
+    //delay
+    ldr r1, =0x0
+100:
+    nop
+    add r1, r1, #0x1
+    cmp r1, #0x200
+    bne 100b
+
+    /* DQS calibration */
+    ldr r3, =0x55aaaa55
+    ldr r4, =0x55555555
+    ldr r5, =0xAAAAAAAA
+    str r3, [r0, #0x0cc]
+
+    ldr r1, =0x0
+    ldr r2, =0x0
+110:
+    ldr r0, =CSD0_BASE_ADDR
+    add r0, r0, #0x10000000
+    add r0, r0, r2
+    str r4, [r0, #0x000]
+    str r5, [r0, #0x004]
+    str r5, [r0, #0x008]
+    str r4, [r0, #0x00c]
+
+    add r2, r2, #0x10
+    add r1, r1, #0x1
+    cmp r1, #0x4
+    bne 110b
+
+    ldr r0, =ESDCTL_BASE_ADDR
+    ldr r1, [r0, #0x07c]
+    orr r1, r1, #(1 << 30)
+    str r1, [r0, #0x07c]
+
+    ldr r1, [r0, #0x07c]
+    orr r1, r1, #(1 << 28)
+    str r1, [r0, #0x07c]
+
+    // check for DQS calibration complete
+120:
+    ldr r1, [r0, #0x07c]
+    mov r2, #0x00000000
+    orr r2, r2, #(1 << 28)
+    and r2, r1, r2
+    cmp r2, #0x0
+    bne 120b
+
+    // check for calibration error
+    mov r2, #0x00000000
+    orr r2, r2, #(1 << 12)
+    and r2, r1, r2
+    cmp r2, #0x0
+    beq 130f
+    ldr r0, =WDOG1_BASE_ADDR
+    ldr r1, =0x0033
+    strh r1, [r0, #0x00]
+    ldr r1, =0x0037
+    strh r1, [r0, #0x00]
+    ldr r1, =0x5555
+    strh r1, [r0, #0x02]
+    ldr r1, =0xaaaa
+    strh r1, [r0, #0x02]
+//	bne retry
+130:
+
+    /* Reset */
+    ldr r1, [r0, #0x07c]
+    orr r1, r1, #(1 << 31)
+    str r1, [r0, #0x07c]
+
+140:
+    ldr r1, [r0, #0x07c]
+    mov r2, #0x00000000
+    orr r2, r2, #(1 << 31)
+    and r1, r1, r2
+    cmp r1, #0x0
+    bne 140b
+
+    ldr r2, =CSD0_BASE_ADDR
+    add r2, r2, #0x1100000
+    ldr r3, =0xf0f0f0f0
+    ldr r4, =0xc3c3c3c3
+    str r3, [r2, #0x000]
+    str r4, [r2, #0x004]
+    ldr r3, [r2, #0x000]
+    ldr r4, [r2, #0x004]
+
+    /* RD calibration */
+    ldr r4, =0x55555555
+    ldr r5, =0xAAAAAAAA
+    ldr r1, =0x0
+    ldr r2, =0x0
+
+150:
+    ldr r0, =CSD0_BASE_ADDR
+    add r0, r0, #0x10000000
+    add r0, r0, r2
+    str r4, [r0, #0x000]
+    str r5, [r0, #0x004]
+    str r5, [r0, #0x008]
+    str r4, [r0, #0x00c]
+
+    add r2, r2, #0x10
+    add r1, r1, #0x1
+    cmp r1, #0x4
+    bne 150b
+
+    ldr r0, =ESDCTL_BASE_ADDR
+    ldr r1, =0x04000050
+    str r1, [r0, #0x01c]
+    ldr r1, =0x00000030
+    str r1, [r0, #0x0a0]
+
+    // check for RD calibration complete
+160:
+    ldr r1, [r0, #0x0a0]
+    and r2, r1, #0x10
+    cmp r2, #0x0
+    bne 160b
+
+    // check for calibration error
+    and r2, r1, #0xf
+    cmp r2, #0x0
+    beq 170f
+    ldr r0, =WDOG1_BASE_ADDR
+    ldr r1, =0x0033
+    strh r1, [r0, #0x00]
+    ldr r1, =0x0037
+    strh r1, [r0, #0x00]
+    ldr r1, =0x5555
+    strh r1, [r0, #0x02]
+    ldr r1, =0xaaaa
+    strh r1, [r0, #0x02]
+//	bne retry
+170:
+
+    /* Reset */
+    ldr r1, [r0, #0x07c]
+    orr r1, r1, #(1 << 31)
+    str r1, [r0, #0x07c]
+
+180:
+    ldr r1, [r0, #0x07c]
+    mov r2, #0x00000000
+    orr r2, r2, #(1 << 31)
+    and r1, r1, r2
+    cmp r1, #0x0
+    bne 180b
+
+    ldr r2, =CSD0_BASE_ADDR
+    add r2, r2, #0x1000000
+    ldr r3, =0x01234567
+    ldr r4, =0x89abcdef
+    str r3, [r2, #0x000]
+    str r4, [r2, #0x004]
+    ldr r3, [r2, #0x000]
+    ldr r4, [r2, #0x004]
+
+    //delay
+    ldr r1, =0x0
+181:
+    nop
+    add r1, r1, #0x1
+    cmp r1, #0x200
+    bne 181b
+
+    /* WR calibration */
+    ldr r4, =0x55555555
+    ldr r5, =0xAAAAAAAA
+    ldr r1, =0x0
+    ldr r2, =0x0
+
+190:
+    ldr r0, =CSD0_BASE_ADDR
+    add r0, r0, #0x10000000
+    add r0, r0, r2
+    str r4, [r0, #0x000]
+    str r5, [r0, #0x004]
+    str r5, [r0, #0x008]
+    str r4, [r0, #0x00c]
+
+    add r2, r2, #0x10
+    add r1, r1, #0x1
+    cmp r1, #0x4
+    bne 190b
+
+    ldr r0, =ESDCTL_BASE_ADDR
+    ldr r1, =0x04000050
+    str r1, [r0, #0x01c]
+    ldr r1, =0x00000030
+    str r1, [r0, #0x0a4]
+
+    // check for WR calibration complete
+200:
+    ldr r1, [r0, #0x0a4]
+    and r2, r1, #0x10
+    cmp r2, #0x0
+    bne 200b
+
+    // check for calibration error
+    and r2, r1, #0xf
+    cmp r2, #0x0
+    beq 210f
+    ldr r0, =WDOG1_BASE_ADDR
+    ldr r1, =0x0033
+    strh r1, [r0, #0x00]
+    ldr r1, =0x0037
+    strh r1, [r0, #0x00]
+    ldr r1, =0x5555
+    strh r1, [r0, #0x02]
+    ldr r1, =0xaaaa
+    strh r1, [r0, #0x02]
+//	bne retry
+210:
+
+    /* Reset */
+    ldr r1, [r0, #0x07c]
+    orr r1, r1, #(1 << 31)
+    str r1, [r0, #0x07c]
+
+220:
+    ldr r1, [r0, #0x07c]
+    mov r2, #0x00000000
+    orr r2, r2, #(1 << 31)
+    and r1, r1, r2
+    cmp r1, #0x0
+    bne 220b
+
+    ldr r2, =CSD0_BASE_ADDR
+    add r2, r2, #0x1000000
+    ldr r3, =0x01234567
+    ldr r4, =0x89abcdef
+    str r3, [r2, #0x000]
+    str r4, [r2, #0x004]
+    ldr r3, [r2, #0x000]
+    ldr r4, [r2, #0x004]
+
+    /* Reset */
+    ldr r1, [r0, #0x07c]
+    orr r1, r1, #(1 << 31)
+    str r1, [r0, #0x07c]
+
+230:
+    ldr r1, [r0, #0x07c]
+    mov r2, #0x00000000
+    orr r2, r2, #(1 << 31)
+    and r1, r1, r2
+    cmp r1, #0x0
+    bne 230b
+
+//	cmp r6, #0xff  // for test only
+//	bls retry  // for test only
+
+    ldr r5, [r0, #0x07c]
+    bic r5, r5, #(1 << 30)  // clear bit 30
+    ldr r6, [r0, #0x080]
+    ldr r3, [r0, #0x088]
+    ldr r4, [r0, #0x090]
+
+	// Disable the ESDCTL
+    ldr r0, =ESDCTL_BASE_ADDR
+    ldr r1, =0x00000000
+    str r1, [r0, #0x00]
+
+    //delay
+    ldr r1, =0x0
+260:
+    nop
+    nop
+    nop
+    nop
+    add r1, r1, #0x1
+    cmp r1, #0x100
+    bne 260b
+#if 0
+    /* Reset the DDR controller */
+    ldr r1, [r0, #0x01c]
+    orr r1, r1, #(1 << 15)
+    str r1, [r0, #0x01c]
+
+240:
+    ldr r1, [r0, #0x01c]
+    mov r2, #0x00000000
+    orr r2, r2, #(1 << 14)
+    and r1, r1, r2
+    cmp r1, #0x0
+    beq 240b
+
+    ldr r1, [r0, #0x018]
+    orr r1, r1, #(1 << 1)
+    str r1, [r0, #0x018]
+
+250:
+    ldr r1, [r0, #0x018]
+    mov r2, #0x00000000
+    orr r2, r2, #(1 << 1)
+    and r1, r1, r2
+    cmp r1, #0x0
+    bne 250b
+
+    ldr r1, =0x00000000
+    str r1, [r0, #0x01c]
+#endif
+    nop
+    nop
+    nop
+    nop
+
+    /* Re-initialize DDR3 memory with calibrated data */
+    ldr r0, =ESDCTL_BASE_ADDR
+
+    str r5, [r0, #0x07c]
+    str r6, [r0, #0x080]
+    str r3, [r0, #0x088]
+    str r4, [r0, #0x090]
+
+    ldr r1, =0x00011740
+    str r1, [r0, #0x018]
+
+    ldr r1, =0xc3190000
+    str r1, [r0, #0x00]
+
+    ldr r1, =0x9f515333
+    str r1, [r0, #0x0C]
+
+    ldr r1, =0xb68e8a63
+    str r1, [r0, #0x10]
+
+    ldr r1, =0x01ff00db
+    str r1, [r0, #0x14]
+
+    ldr r1, =0x000026d2
+    str r1, [r0, #0x2C]
+
+    ldr r1, =0x009f0e21
+    str r1, [r0, #0x30]
+
+    ldr r1, =0x12373030
+    str r1, [r0, #0x08]
+
+    ldr r1, =0x4402002d
+    str r1, [r0, #0x04]
+
+    ldr r1, =0x00008032
+    str r1, [r0, #0x1C]
+
+    ldr r1, =0x00008033
+    str r1, [r0, #0x1C]
+
+    ldr r1, =0x00028031
+    str r1, [r0, #0x1C]
+
+    ldr r1, =0x092080b0
+    str r1, [r0, #0x1C]
+
+    ldr r1, =0x04008040
+    str r1, [r0, #0x1C]
+
+    ldr r1, =0x0000803a
+    str r1, [r0, #0x1C]
+
+    ldr r1, =0x0000803b
+    str r1, [r0, #0x1C]
+
+    ldr r1, =0x00028039
+    str r1, [r0, #0x1C]
+
+    ldr r1, =0x09208138
+    str r1, [r0, #0x1C]
+
+    ldr r1, =0x04008048
+    str r1, [r0, #0x1C]
+
+    ldr r1, =0x00001800
+    str r1, [r0, #0x20]
+
+    ldr r1, =0x04b80003
+    str r1, [r0, #0x40]
+
+    ldr r1, =0x00022227
+    str r1, [r0, #0x58]
+
+    ldr r1, =0x00000000
+    str r1, [r0, #0x1C]
+
+/*
+  *  The following is to fill in those arguments for this ROM function
+  * pu_irom_hwcnfg_setup(void **start, size_t *bytes, const void *boot_data)
+  *
+  *  This function is used to copy data from the storage media into DDR.
+  *
+  *  start - Initial (possibly partial) image load address on entry. Final image
+  *            load address on exit.
+  *  bytes - Initial (possibly partial) image size on entry. Final image size on
+  *             exit.
+  *  boot_data - Initial @ref ivt Boot Data load address.
+  */
+    adr r0, DDR_DEST_ADDR
+    adr r1, COPY_SIZE
+    adr r2, BOOT_DATA
+before_calling_rom___pu_irom_hwcnfg_setup:
+
+    /* We should distinguish USB recovery mode(SDP mode) and internal boot mode.
+    If ROM runs in SDP mode, then it needn't load boot code from storage media.
+    If ROM runs in SDP mode, then r0 must be 0x00
+    If ROM runs in internal boot mode, then r0 should be larger than IRAM base address. */
+    cmp r7, #0xF8000000
+    bls return_sdp
+
+    /* Different ROM address for TO 1.0 & TO 2.x */
+    ldr r3, =ROM_SI_REV
+    ldr r4, [r3]
+
+    cmp r4, #0x21
+    /* TO2.1 */
+    moveq r6, #0x1800
+    addeq r6, r6, #0x4d
+    beq 2f
+
+    cmp r4, #0x20
+    /* TO2 */
+    moveq r6, #0x1800
+    addeq r6, r6, #0x4d
+    beq 2f
+
+    /* TO1 */
+    mov r6, #0x400000
+    add r6, r6, #0x5000
+    add r6, r6, #0xc7
+
+
+2:  blx r6 /* This address might change in future ROM versions */
+after_calling_rom___pu_irom_hwcnfg_setup:
+
+return_sdp:
+    cmp r7, #0xF8000000
+    bhi quit_plugin
+
+    /* Workaround run plug-ins in SDP mode without USB re-enumeration.
+    how it works:
+    ROM running in usb download mode.
+    Host manufacturing application sends SDP command to download plug-in image.
+    Host manufacturing application sends SDP command to jump to plug-in image and run it.
+    Plug-in starts execution and after its regular tasks plug-in will then call into ROM
+    call into pl_parse_and_handle() */
+    ldr r3, =ROM_SI_REV
+    ldr r5, [r3]
+    cmp     r5, #0x20       /* check silicon revision to determine the function entry address */
+
+    ldrlt r4, =0x00000edd   /* function entry in TO1 ROM */
+    ldrge r4, =0x0040487d   /* function entry in TO2 ROM */
+    blx     r4
+
+/* To return to ROM from plugin, we need to fill in these argument.
+  * Here is what need to do:
+  * Need to construct the paramters for this function before return to ROM:
+  * plugin_download(void **start, size_t *bytes, UINT32 *ivt_offset)
+  */
+quit_plugin:
+    pop {r0-r6, lr}
+    ldr r7, DDR_DEST_ADDR
+    str r7, [r0]
+    ldr r7, COPY_SIZE
+    str r7, [r1]
+    mov r7, #0x400  /* Point to the second IVT table at offset 0x42C */
+    add r7, r7, #0x2C
+    str r7, [r2]
+    mov r0, #1
+
+    bx lr          /* return back to ROM code */
+
+DDR_DEST_ADDR:    .word   TEXT_BASE
+COPY_SIZE:        .word   _end - TEXT_BASE
+BOOT_DATA:        .word   TEXT_BASE
+                  .word   _end - TEXT_BASE
+                  .word   0
+
+#endif

board/freescale/mx53_pcba/lowlevel_init.S

@@ -0,0 +1,372 @@
+/*
+ * Copyright (C) 2011 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <asm/arch/mx53.h>
+
+/*
+ * L2CC Cache setup/invalidation/disable
+ */
+.macro init_l2cc
+	/* explicitly disable L2 cache */
+        mrc 15, 0, r0, c1, c0, 1
+        bic r0, r0, #0x2
+        mcr 15, 0, r0, c1, c0, 1
+
+        /* reconfigure L2 cache aux control reg */
+        mov r0, #0xC0                   /* tag RAM */
+        add r0, r0, #0x4                /* data RAM */
+        orr r0, r0, #(1 << 24)          /* disable write allocate delay */
+        orr r0, r0, #(1 << 23)          /* disable write allocate combine */
+        orr r0, r0, #(1 << 22)          /* disable write allocate */
+
+	mcr 15, 1, r0, c9, c0, 2
+.endm /* init_l2cc */
+
+/* AIPS setup - Only setup MPROTx registers.
+ * The PACR default values are good.*/
+.macro init_aips
+	/*
+	 * Set all MPROTx to be non-bufferable, trusted for R/W,
+	 * not forced to user-mode.
+	 */
+	ldr r0, =AIPS1_BASE_ADDR
+	ldr r1, =0x77777777
+	str r1, [r0, #0x0]
+	str r1, [r0, #0x4]
+	ldr r0, =AIPS2_BASE_ADDR
+	str r1, [r0, #0x0]
+	str r1, [r0, #0x4]
+.endm /* init_aips */
+
+.macro setup_pll pll, freq
+	/*
+	 * If freq < 300MHz, we need to set dpdck0_2_en to 0
+	 */
+	ldr r0, =\freq
+	ldr r1, =0x300
+	cmp r0, r1
+	ldrcs r1, =0x00001232
+	ldrcc r1, =0x00000232
+	ldr r0, =\pll
+	str r1, [r0, #PLL_DP_CTL]
+	mov r1, #0x2
+	str r1, [r0, #PLL_DP_CONFIG]
+
+	ldr r1, W_DP_OP_\freq
+	str r1, [r0, #PLL_DP_OP]
+	str r1, [r0, #PLL_DP_HFS_OP]
+
+	ldr r1,	W_DP_MFD_\freq
+	str r1, [r0, #PLL_DP_MFD]
+	str r1, [r0, #PLL_DP_HFS_MFD]
+
+	ldr r1,  W_DP_MFN_\freq
+	str r1, [r0, #PLL_DP_MFN]
+	str r1, [r0, #PLL_DP_HFS_MFN]
+
+	ldr r1, =0x00001232
+	str r1, [r0, #PLL_DP_CTL]
+1:	ldr r1, [r0, #PLL_DP_CTL]
+	ands r1, r1, #0x1
+	beq 1b
+.endm
+
+.macro init_m4if
+	/*increase master2 priority for WIFI*/
+	ldr r0, =M4IF_BASE_ADDR
+	ldr r1, [r0, #0x40]
+	orr r1, r1, #(0x33 << 16)
+	str r1, [r0, #0x40]
+
+	/*increase master4 priority for FEC*/
+	ldr r1, [r0, #0x44]
+	orr r1, r1, #0x33
+	str r1, [r0, #0x44]
+
+	/*set SDHC-port3 high priority to all AHB MAX Slave port*/
+	ldr r0, =AHBMAX_BASE_ADDR
+
+#ifdef CONFIG_WIFI_SDHC_PORT3
+	/*set PARK to SDHC-port3*/
+	ldr r0, =AHBMAX_BASE_ADDR
+	ldr r1, [r0, #0x10]
+	bic r1, r1, #(0x7 << 0)
+	orr r1, r1, #0x3
+	bic r1, r1, #(0x3 << 4)
+	bic r1, r1, #(0x3 << 8)
+	orr r1, r1, #(0x1 << 30)
+	bic r1, r1, #(0x1 << 31)
+
+	ldr r1, [r0, #0x110]
+	bic r1, r1, #(0x7 << 0)
+	orr r1, r1, #0x3
+	bic r1, r1, #(0x3 << 4)
+	bic r1, r1, #(0x3 << 8)
+	orr r1, r1, #(0x1 << 30)
+	bic r1, r1, #(0x1 << 31)
+
+	ldr r1, [r0, #0x210]
+	bic r1, r1, #(0x7 << 0)
+	orr r1, r1, #0x3
+	bic r1, r1, #(0x3 << 4)
+	bic r1, r1, #(0x3 << 8)
+	orr r1, r1, #(0x1 << 30)
+	bic r1, r1, #(0x1 << 31)
+
+	ldr r1, [r0, #0x310]
+	bic r1, r1, #(0x7 << 0)
+	orr r1, r1, #0x3
+	bic r1, r1, #(0x3 << 4)
+	bic r1, r1, #(0x3 << 8)
+	orr r1, r1, #(0x1 << 30)
+	bic r1, r1, #(0x1 << 31)
+
+	/*set SDHC-port3 arbitration*/
+	ldr r0, =AHBMAX_BASE_ADDR
+	ldr r1, [r0, #0xb00]
+	bic r1, r1, #(0x7 << 0)
+	orr r1, r1, #0x1
+#endif
+
+#ifdef CONFIG_WIFI_SDHC_PORT2
+	/*set PARK to SDHC-port3*/
+	ldr r0, =AHBMAX_BASE_ADDR
+	ldr r1, [r0, #0x10]
+	bic r1, r1, #(0x7 << 0)
+	orr r1, r1, #0x2
+	bic r1, r1, #(0x3 << 4)
+	bic r1, r1, #(0x3 << 8)
+	orr r1, r1, #(0x1 << 30)
+	bic r1, r1, #(0x1 << 31)
+
+	ldr r1, [r0, #0x110]
+	bic r1, r1, #(0x7 << 0)
+	orr r1, r1, #0x2
+	bic r1, r1, #(0x3 << 4)
+	bic r1, r1, #(0x3 << 8)
+	orr r1, r1, #(0x1 << 30)
+	bic r1, r1, #(0x1 << 31)
+
+	ldr r1, [r0, #0x210]
+	bic r1, r1, #(0x7 << 0)
+	orr r1, r1, #0x2
+	bic r1, r1, #(0x3 << 4)
+	bic r1, r1, #(0x3 << 8)
+	orr r1, r1, #(0x1 << 30)
+	bic r1, r1, #(0x1 << 31)
+
+	ldr r1, [r0, #0x310]
+	bic r1, r1, #(0x7 << 0)
+	orr r1, r1, #0x2
+	bic r1, r1, #(0x3 << 4)
+	bic r1, r1, #(0x3 << 8)
+	orr r1, r1, #(0x1 << 30)
+	bic r1, r1, #(0x1 << 31)
+
+	/*set SDHC-port2 arbitration*/
+	ldr r0, =AHBMAX_BASE_ADDR
+	ldr r1, [r0, #0xA00]
+	bic r1, r1, #(0x7 << 0)
+#endif
+
+	/*set JMP step to zero*/
+	ldr r0, =M4IF_BASE_ADDR
+	ldr r1, [r0, #0x48]
+	bic r1, r1, #(0x3 << 8)
+	str r1, [r0, #0x48]
+.endm
+
+.macro init_clock
+	ldr r0, =ROM_SI_REV
+	ldr r1, [r0]
+	cmp r1, #0x20
+
+	/* For TO2 only, set LDO to 1.3V */
+	ldr r0, =0x53fa8000
+	ldr r1, =0x00194005
+	streq r1, [r0, #0x04]
+
+	ldr r0, CCM_BASE_ADDR_W
+
+	/* Gate of clocks to the peripherals first */
+	ldr r1, =0x3FFFFFFF
+	str r1, [r0, #CLKCTL_CCGR0]
+	ldr r1, =0x0
+	str r1, [r0, #CLKCTL_CCGR1]
+	str r1, [r0, #CLKCTL_CCGR2]
+	str r1, [r0, #CLKCTL_CCGR3]
+	str r1, [r0, #CLKCTL_CCGR7]
+	ldr r1, =0x00030000
+	str r1, [r0, #CLKCTL_CCGR4]
+	ldr r1, =0x00FFF030
+	str r1, [r0, #CLKCTL_CCGR5]
+	ldr r1, =0x0F00030F
+	str r1, [r0, #CLKCTL_CCGR6]
+
+	/* Switch ARM to step clock */
+	mov r1, #0x4
+	str r1, [r0, #CLKCTL_CCSR]
+
+	setup_pll PLL1_BASE_ADDR, 800
+
+        setup_pll PLL3_BASE_ADDR, 400
+
+        /* Switch peripheral to PLL3 */
+        ldr r0, CCM_BASE_ADDR_W
+        ldr r1, CCM_VAL_0x00015154
+        str r1, [r0, #CLKCTL_CBCMR]
+        ldr r1, CCM_VAL_0x02888945
+        orr r1, r1, #(1 << 16)
+        str r1, [r0, #CLKCTL_CBCDR]
+        /* make sure change is effective */
+1:      ldr r1, [r0, #CLKCTL_CDHIPR]
+        cmp r1, #0x0
+        bne 1b
+
+        setup_pll PLL2_BASE_ADDR, CONFIG_SYS_PLL2_FREQ
+
+	/* Switch peripheral to PLL2 */
+	ldr r0, CCM_BASE_ADDR_W
+	ldr r1, CCM_VAL_0x00808145
+	orr r1, r1, #(CONFIG_SYS_AHB_PODF << 10)
+	orr r1, r1, #(CONFIG_SYS_AXIA_PODF << 16)
+	orr r1, r1, #(CONFIG_SYS_AXIB_PODF << 19)
+	str r1, [r0, #CLKCTL_CBCDR]
+
+	ldr r1, CCM_VAL_0x00016154
+	str r1, [r0, #CLKCTL_CBCMR]
+
+	/*change uart clk parent to pll2*/
+	ldr r1, [r0, #CLKCTL_CSCMR1]
+	and r1, r1, #0xfcffffff
+	orr r1, r1, #0x01000000
+	str r1, [r0, #CLKCTL_CSCMR1]
+
+	/* make sure change is effective */
+1:      ldr r1, [r0, #CLKCTL_CDHIPR]
+	cmp r1, #0x0
+	bne 1b
+
+        setup_pll PLL3_BASE_ADDR, 216
+
+	setup_pll PLL4_BASE_ADDR, 455
+
+	/* Set the platform clock dividers */
+	ldr r0, PLATFORM_BASE_ADDR_W
+	ldr r1, PLATFORM_CLOCK_DIV_W
+	str r1, [r0, #PLATFORM_ICGC]
+
+	ldr r0, CCM_BASE_ADDR_W
+	mov r1, #0
+	str r1, [r0, #CLKCTL_CACRR]
+
+	/* Switch ARM back to PLL 1. */
+	mov r1, #0x0
+	str r1, [r0, #CLKCTL_CCSR]
+
+	/* make uart div=6*/
+	ldr r1, [r0, #CLKCTL_CSCDR1]
+	and r1, r1, #0xffffffc0
+	orr r1, r1, #0x0a
+	str r1, [r0, #CLKCTL_CSCDR1]
+
+	/* Restore the default values in the Gate registers */
+	ldr r1, =0xFFFFFFFF
+	str r1, [r0, #CLKCTL_CCGR0]
+	str r1, [r0, #CLKCTL_CCGR1]
+	str r1, [r0, #CLKCTL_CCGR2]
+	str r1, [r0, #CLKCTL_CCGR3]
+	str r1, [r0, #CLKCTL_CCGR4]
+	str r1, [r0, #CLKCTL_CCGR5]
+	str r1, [r0, #CLKCTL_CCGR6]
+	str r1, [r0, #CLKCTL_CCGR7]
+
+	mov r1, #0x00000
+	str r1, [r0, #CLKCTL_CCDR]
+
+	/* for cko - for ARM div by 8 */
+	mov r1, #0x000A0000
+	add r1, r1, #0x00000F0
+	str r1, [r0, #CLKCTL_CCOSR]
+.endm
+
+.section ".text.init", "x"
+
+.globl lowlevel_init
+lowlevel_init:
+
+#ifdef ENABLE_IMPRECISE_ABORT
+	mrs r1, spsr            /* save old spsr */
+	mrs r0, cpsr            /* read out the cpsr */
+	bic r0, r0, #0x100      /* clear the A bit */
+	msr spsr, r0            /* update spsr */
+	add lr, pc, #0x8        /* update lr */
+        movs pc, lr             /* update cpsr */
+        nop
+        nop
+        nop
+	nop
+	msr spsr, r1            /* restore old spsr */
+#endif
+
+	/* ARM errata ID #468414 */
+	mrc 15, 0, r1, c1, c0, 1
+	orr r1, r1, #(1 << 5)    /* enable L1NEON bit */
+	mcr 15, 0, r1, c1, c0, 1
+
+	init_l2cc
+
+	init_aips
+
+#ifdef CONFIG_ADJUST_WIFI_FEC_PERFORMANCE
+        /*increase WIFI & FEC priority of accessing bus*/
+        init_m4if
+#endif
+
+	init_clock
+
+	mov pc, lr
+
+/* Board level setting value */
+CCM_BASE_ADDR_W:        .word CCM_BASE_ADDR
+CCM_VAL_0x00016154:     .word 0x00016154
+CCM_VAL_0x00808145:     .word 0x00808145
+CCM_VAL_0x00015154:     .word 0x00015154
+CCM_VAL_0x02888945:     .word 0x02888945
+W_DP_OP_1000:           .word DP_OP_1000
+W_DP_MFD_1000:          .word DP_MFD_1000
+W_DP_MFN_1000:          .word DP_MFN_1000
+W_DP_OP_800:           	.word DP_OP_800
+W_DP_MFD_800:           .word DP_MFD_800
+W_DP_MFN_800:           .word DP_MFN_800
+W_DP_OP_600:            .word DP_OP_600
+W_DP_MFD_600:           .word DP_MFD_600
+W_DP_MFN_600:           .word DP_MFN_600
+W_DP_OP_400:            .word DP_OP_400
+W_DP_MFD_400:           .word DP_MFD_400
+W_DP_MFN_400:           .word DP_MFN_400
+W_DP_OP_216:            .word DP_OP_216
+W_DP_MFD_216:           .word DP_MFD_216
+W_DP_MFN_216:           .word DP_MFN_216
+W_DP_OP_455:            .word DP_OP_455
+W_DP_MFD_455:           .word DP_MFD_455
+W_DP_MFN_455:           .word DP_MFN_455
+PLATFORM_BASE_ADDR_W:   .word ARM_BASE_ADDR
+PLATFORM_CLOCK_DIV_W:   .word 0x00000124

board/freescale/mx53_pcba/u-boot.lds

@@ -0,0 +1,74 @@
+/*
+ * January 2004 - Changed to support H4 device
+ * Copyright (c) 2004 Texas Instruments
+ *
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
+ *
+ * (C) Copyright 2011 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+	. = 0x00000000;
+
+	. = ALIGN(4);
+	.text	   :
+	{
+	  /* WARNING - the following is hand-optimized to fit within	*/
+	  /* the sector layout of our flash chips!	XXX FIXME XXX	*/
+	  board/freescale/mx53_pcba/flash_header.o	(.text.flasheader)
+	  cpu/arm_cortexa8/start.o
+	  board/freescale/mx53_pcba/libmx53_pcba.a	(.text)
+	  lib_arm/libarm.a		(.text)
+	  net/libnet.a			(.text)
+	  drivers/mtd/libmtd.a		(.text)
+	  drivers/mmc/libmmc.a		(.text)
+
+	  . = DEFINED(env_offset) ? env_offset : .;
+	  common/env_embedded.o(.text)
+
+	  *(.text)
+	}
+
+	. = ALIGN(4);
+	.rodata : { *(.rodata) }
+
+	. = ALIGN(4);
+	.data : { *(.data) }
+
+	. = ALIGN(4);
+	.got : { *(.got) }
+
+	. = .;
+	__u_boot_cmd_start = .;
+	.u_boot_cmd : { *(.u_boot_cmd) }
+	__u_boot_cmd_end = .;
+
+	. = ALIGN(4);
+	_end_of_copy = .; /* end_of ROM copy code here */
+	__bss_start = .;
+	.bss : { *(.bss) }
+	_end = .;
+}

board/freescale/mx53_smd/Makefile

@@ -0,0 +1,47 @@
+#
+# (C) Copyright 2010 Freescale Semiconductor, Inc.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).a
+
+COBJS	:= mx53_smd.o
+SOBJS	:= lowlevel_init.o flash_header.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################

board/freescale/mx53_smd/config.mk

@@ -0,0 +1,3 @@
+LDSCRIPT := $(SRCTREE)/board/$(VENDOR)/$(BOARD)/u-boot.lds
+
+TEXT_BASE = 0x77800000

board/freescale/mx53_smd/flash_header.S

@@ -0,0 +1,227 @@
+/*
+ * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <asm/arch/mx53.h>
+
+#define REG_LD_AND_STR_INIT(base)	\
+	ldr r0, =base;
+
+#define REG_LD_AND_STR_OP(i, offset, val)	\
+	ldr r1, =val;	\
+	ldr r2, =offset;	\
+	str r1, [r0, r2];
+
+#define REG_LD_AND_STR_END(base)
+
+
+#ifdef	CONFIG_FLASH_HEADER
+#ifndef CONFIG_FLASH_HEADER_OFFSET
+# error "Must define the offset of flash header"
+#endif
+
+.section ".text.flasheader", "x"
+	b	_start
+	.org	CONFIG_FLASH_HEADER_OFFSET
+
+ivt_header:		.long 0x402000D1/* Tag=0xD1, Len=0x0020, Ver=0x40 */
+app_code_jump_v:	.long (0xF8006000 + (plugin_start - TEXT_BASE))
+reserv1:		.long 0x0
+dcd_ptr:		.long 0x0
+boot_data_ptr:		.long (0xF8006000 + (boot_data - TEXT_BASE))
+self_ptr:		.long (0xF8006000 + (ivt_header - TEXT_BASE))
+app_code_csf:		.long 0x0
+reserv2:		.long 0x0
+boot_data:		.long 0xF8006000
+image_len:		.long (3 * 1024)
+plugin:			.long 0x1
+
+/* Second IVT to give entry point into the bootloader copied to DDR */
+ivt2_header:		.long 0x402000D1/*Tag=0xD1, Len=0x0020, Ver=0x40 */
+app2_code_jump_v:	.long _start   /* Entry point for the bootloader */
+reserv3:		.long 0x0
+dcd2_ptr:		.long 0x0
+boot_data2_ptr:		.long boot_data2
+self_ptr2:		.long ivt2_header
+app_code_csf2:		.long 0x0
+reserv4:		.long 0x0
+boot_data2:		.long TEXT_BASE
+image_len2:		.long  _end_of_copy - TEXT_BASE + CONFIG_FLASH_HEADER_OFFSET
+plugin2:		.long 0x0
+
+/* Here starts the plugin code */
+plugin_start:
+	/* Save the return address and the function arguments */
+	push {r0-r6, lr}
+	/* We should distinguish USB recovery mode(SDP mode) and internal boot mode.
+	If ROM runs in SDP mode, then it needn't load boot code from storage media.
+	If ROM runs in SDP mode, then r0 must be 0x00
+	If ROM runs in internal boot mode, then r0 should be larger than IRAM base address. */
+	mov r7, r0
+
+	/* IOMUX */
+	REG_LD_AND_STR_INIT(IOMUXC_BASE_ADDR)
+	REG_LD_AND_STR_OP(1, 0x554, 0x00300000)
+	REG_LD_AND_STR_OP(2, 0x558, 0x00300040)
+	REG_LD_AND_STR_OP(3, 0x560, 0x00300000)
+	REG_LD_AND_STR_OP(4, 0x564, 0x00300040)
+	REG_LD_AND_STR_OP(5, 0x568, 0x00300040)
+	REG_LD_AND_STR_OP(6, 0x570, 0x00300000)
+	REG_LD_AND_STR_OP(7, 0x574, 0x00300000)
+	REG_LD_AND_STR_OP(8, 0x578, 0x00300000)
+	REG_LD_AND_STR_OP(9, 0x57c, 0x00300040)
+	REG_LD_AND_STR_OP(10, 0x580, 0x00300040)
+	REG_LD_AND_STR_OP(11, 0x584, 0x00300000)
+	REG_LD_AND_STR_OP(12, 0x588, 0x00300000)
+	REG_LD_AND_STR_OP(13, 0x590, 0x00300040)
+	REG_LD_AND_STR_OP(14, 0x594, 0x00300000)
+	REG_LD_AND_STR_OP(15, 0x6f0, 0x00300000)
+	REG_LD_AND_STR_OP(16, 0x6f4, 0x00000000)
+	REG_LD_AND_STR_OP(17, 0x6fc, 0x00000000)
+	REG_LD_AND_STR_OP(18, 0x714, 0x00000000)
+	REG_LD_AND_STR_OP(19, 0x718, 0x00300000)
+	REG_LD_AND_STR_OP(20, 0x71c, 0x00300000)
+	REG_LD_AND_STR_OP(21, 0x720, 0x00300000)
+	REG_LD_AND_STR_OP(22, 0x724, 0x04000000)
+	REG_LD_AND_STR_OP(23, 0x728, 0x00300000)
+	REG_LD_AND_STR_OP(24, 0x72c, 0x00300000)
+	REG_LD_AND_STR_END(IOMUXC_BASE_ADDR)
+
+	/* ESDCTL */
+	REG_LD_AND_STR_INIT(ESDCTL_BASE_ADDR)
+	REG_LD_AND_STR_OP(25, 0x088, 0x35343535)
+	REG_LD_AND_STR_OP(26, 0x090, 0x4d444c44)
+	REG_LD_AND_STR_OP(27, 0x07c, 0x01370138)
+	REG_LD_AND_STR_OP(28, 0x080, 0x013b013c)
+	REG_LD_AND_STR_OP(29, 0x0f8, 0x00000800)
+	REG_LD_AND_STR_OP(30, 0x018, 0x00001740)
+	REG_LD_AND_STR_OP(31, 0x000, 0xc3190000)
+	REG_LD_AND_STR_OP(32, 0x00c, 0x9f5152e3)
+	REG_LD_AND_STR_OP(33, 0x010, 0xb68e8a63)
+	REG_LD_AND_STR_OP(34, 0x014, 0x01ff00db)
+	REG_LD_AND_STR_OP(35, 0x02c, 0x000026d2)
+	REG_LD_AND_STR_OP(36, 0x030, 0x009f0e21)
+	REG_LD_AND_STR_OP(37, 0x008, 0x12273030)
+	REG_LD_AND_STR_OP(38, 0x004, 0x0002002d)
+	REG_LD_AND_STR_OP(39, 0x01c, 0x00008032)
+	REG_LD_AND_STR_OP(40, 0x01c, 0x00008033)
+	REG_LD_AND_STR_OP(41, 0x01c, 0x00028031)
+	REG_LD_AND_STR_OP(42, 0x01c, 0x052080b0)
+	REG_LD_AND_STR_OP(43, 0x01c, 0x04008040)
+	REG_LD_AND_STR_OP(44, 0x01c, 0x0000803a)
+	REG_LD_AND_STR_OP(45, 0x01c, 0x0000803b)
+	REG_LD_AND_STR_OP(46, 0x01c, 0x00028039)
+	REG_LD_AND_STR_OP(47, 0x01c, 0x05208138)
+	REG_LD_AND_STR_OP(48, 0x01c, 0x04008048)
+	REG_LD_AND_STR_OP(49, 0x020, 0x00005800)
+	REG_LD_AND_STR_OP(50, 0x040, 0x04b80003)
+	REG_LD_AND_STR_OP(51, 0x058, 0x00022227)
+	REG_LD_AND_STR_OP(52, 0x01C, 0x00000000)
+	REG_LD_AND_STR_END(ESDCTL_BASE_ADDR)
+
+/*
+ *  The following is to fill in those arguments for this ROM function
+ * pu_irom_hwcnfg_setup(void **start, size_t *bytes, const void *boot_data)
+ *
+ *  This function is used to copy data from the storage media into DDR.
+ *
+ *  start - Initial (possibly partial) image load address on entry. Final image
+ *            load address on exit.
+ *  bytes - Initial (possibly partial) image size on entry. Final image size on
+ *             exit.
+ *  boot_data - Initial @ref ivt Boot Data load address.
+ */
+	adr r0, DDR_DEST_ADDR
+	adr r1, COPY_SIZE
+	adr r2, BOOT_DATA
+before_calling_rom___pu_irom_hwcnfg_setup:
+	/* We should distinguish USB recovery mode(SDP mode) and internal boot mode.
+	If ROM runs in SDP mode, then it needn't load boot code from storage media.
+	If ROM runs in SDP mode, then r0 must be 0x00
+	If ROM runs in internal boot mode, then r0 should be larger than IRAM base address. */
+	cmp r7, #0xF8000000
+	bls return_sdp
+	/* Different ROM address for TO 1.0 & TO 2.0 */
+	ldr r3, =ROM_SI_REV
+	ldr r4, [r3]
+
+	cmp r4, #0x21
+	/* TO2.1 */
+	moveq r6, #0x1800
+	addeq r6, r6, #0x4d
+	beq 2f
+
+	cmp r4, #0x20
+	/* TO2 */
+	moveq r6, #0x1800
+	addeq r6, r6, #0x4d
+	beq 2f
+
+	/* TO1 */
+	mov r6, #0x400000
+	add r6, r6, #0x5000
+	add r6, r6, #0xc7
+2:
+	blx r6 /* This address might change in future ROM versions */
+after_calling_rom___pu_irom_hwcnfg_setup:
+
+return_sdp:
+	cmp r7, #0xF8000000
+	bhi quit_plugin
+
+	/* Workaround run plug-ins in SDP mode without USB re-enumeration.
+	how it works:
+	ROM running in usb download mode.
+	Host manufacturing application sends SDP command to download plug-in image.
+	Host manufacturing application sends SDP command to jump to plug-in image and run it.
+	Plug-in starts execution and after its regular tasks plug-in will then call into ROM
+	call into pl_parse_and_handle() */
+	ldr r3, =ROM_SI_REV
+	ldr r5, [r3]
+	cmp r5, #0x20       /* check silicon revision to determine the function entry address */
+
+	ldrlt r4, =0x00000edd   /* function entry in TO1 ROM */
+	ldrge r4, =0x0040487d   /* function entry in TO2 ROM */
+	blx r4
+
+/* To return to ROM from plugin, we need to fill in these argument.
+ * Here is what need to do:
+ * Need to construct the paramters for this function before return to ROM:
+ * plugin_download(void **start, size_t *bytes, UINT32 *ivt_offset)
+ */
+quit_plugin:
+	pop {r0-r6, lr}
+	ldr r7, DDR_DEST_ADDR
+	str r7, [r0]
+	ldr r7, COPY_SIZE
+	str r7, [r1]
+	mov r7, #0x400  /* Point to the second IVT table at offset 0x42C */
+	add r7, r7, #0x2C
+	str r7, [r2]
+	mov r0, #1
+
+	bx lr  /* return back to ROM code */
+
+DDR_DEST_ADDR:    .word   TEXT_BASE
+COPY_SIZE:        .word   _end - TEXT_BASE
+BOOT_DATA:        .word   TEXT_BASE
+                  .word   _end - TEXT_BASE
+                  .word   0
+
+#endif

board/freescale/mx53_smd/lowlevel_init.S

@@ -0,0 +1,384 @@
+/*
+ * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <asm/arch/mx53.h>
+
+/*
+ * L2CC Cache setup/invalidation/disable
+ */
+.macro init_l2cc
+	/* explicitly disable L2 cache */
+        mrc 15, 0, r0, c1, c0, 1
+        bic r0, r0, #0x2
+        mcr 15, 0, r0, c1, c0, 1
+
+        /* reconfigure L2 cache aux control reg */
+        mov r0, #0xC0                   /* tag RAM */
+        add r0, r0, #0x4                /* data RAM */
+        orr r0, r0, #(1 << 24)          /* disable write allocate delay */
+        orr r0, r0, #(1 << 23)          /* disable write allocate combine */
+        orr r0, r0, #(1 << 22)          /* disable write allocate */
+
+	mcr 15, 1, r0, c9, c0, 2
+.endm /* init_l2cc */
+
+/* AIPS setup - Only setup MPROTx registers.
+ * The PACR default values are good.*/
+.macro init_aips
+	/*
+	 * Set all MPROTx to be non-bufferable, trusted for R/W,
+	 * not forced to user-mode.
+	 */
+	ldr r0, =AIPS1_BASE_ADDR
+	ldr r1, =0x77777777
+	str r1, [r0, #0x0]
+	str r1, [r0, #0x4]
+	ldr r0, =AIPS2_BASE_ADDR
+	str r1, [r0, #0x0]
+	str r1, [r0, #0x4]
+.endm /* init_aips */
+
+.macro setup_pll pll, freq
+	/*
+	 * If freq < 300MHz, we need to set dpdck0_2_en to 0
+	 */
+	ldr r0, =\freq
+	ldr r1, =0x12c
+	cmp r0, r1
+	ldrcs r1, =0x00001232
+	ldrcc r1, =0x00000232
+	ldr r0, =\pll
+	str r1, [r0, #PLL_DP_CTL]
+	mov r1, #0x2
+	str r1, [r0, #PLL_DP_CONFIG]
+
+	ldr r1, W_DP_OP_\freq
+	str r1, [r0, #PLL_DP_OP]
+	str r1, [r0, #PLL_DP_HFS_OP]
+
+	ldr r1,	W_DP_MFD_\freq
+	str r1, [r0, #PLL_DP_MFD]
+	str r1, [r0, #PLL_DP_HFS_MFD]
+
+	ldr r1,  W_DP_MFN_\freq
+	str r1, [r0, #PLL_DP_MFN]
+	str r1, [r0, #PLL_DP_HFS_MFN]
+
+	ldrcs r1, =0x00001232
+	ldrcc r1, =0x00000232
+	str r1, [r0, #PLL_DP_CTL]
+1:	ldr r1, [r0, #PLL_DP_CTL]
+	ands r1, r1, #0x1
+	beq 1b
+.endm
+
+.macro init_m4if
+	/*increase master2 priority for WIFI*/
+	ldr r0, =M4IF_BASE_ADDR
+	ldr r1, [r0, #0x40]
+	orr r1, r1, #(0x33 << 16)
+	str r1, [r0, #0x40]
+
+	/*increase master4 priority for FEC*/
+	ldr r1, [r0, #0x44]
+	orr r1, r1, #0x33
+	str r1, [r0, #0x44]
+
+	/*set SDHC-port3 high priority to all AHB MAX Slave port*/
+	ldr r0, =AHBMAX_BASE_ADDR
+
+#ifdef CONFIG_WIFI_SDHC_PORT3
+	/*set PARK to SDHC-port3*/
+	ldr r0, =AHBMAX_BASE_ADDR
+	ldr r1, [r0, #0x10]
+	bic r1, r1, #(0x7 << 0)
+	orr r1, r1, #0x3
+	bic r1, r1, #(0x3 << 4)
+	bic r1, r1, #(0x3 << 8)
+	orr r1, r1, #(0x1 << 30)
+	bic r1, r1, #(0x1 << 31)
+
+	ldr r1, [r0, #0x110]
+	bic r1, r1, #(0x7 << 0)
+	orr r1, r1, #0x3
+	bic r1, r1, #(0x3 << 4)
+	bic r1, r1, #(0x3 << 8)
+	orr r1, r1, #(0x1 << 30)
+	bic r1, r1, #(0x1 << 31)
+
+	ldr r1, [r0, #0x210]
+	bic r1, r1, #(0x7 << 0)
+	orr r1, r1, #0x3
+	bic r1, r1, #(0x3 << 4)
+	bic r1, r1, #(0x3 << 8)
+	orr r1, r1, #(0x1 << 30)
+	bic r1, r1, #(0x1 << 31)
+
+	ldr r1, [r0, #0x310]
+	bic r1, r1, #(0x7 << 0)
+	orr r1, r1, #0x3
+	bic r1, r1, #(0x3 << 4)
+	bic r1, r1, #(0x3 << 8)
+	orr r1, r1, #(0x1 << 30)
+	bic r1, r1, #(0x1 << 31)
+
+	/*set SDHC-port3 arbitration*/
+	ldr r0, =AHBMAX_BASE_ADDR
+	ldr r1, [r0, #0xb00]
+	bic r1, r1, #(0x7 << 0)
+	orr r1, r1, #0x1
+#endif
+
+#ifdef CONFIG_WIFI_SDHC_PORT2
+	/*set PARK to SDHC-port3*/
+	ldr r0, =AHBMAX_BASE_ADDR
+	ldr r1, [r0, #0x10]
+	bic r1, r1, #(0x7 << 0)
+	orr r1, r1, #0x2
+	bic r1, r1, #(0x3 << 4)
+	bic r1, r1, #(0x3 << 8)
+	orr r1, r1, #(0x1 << 30)
+	bic r1, r1, #(0x1 << 31)
+
+	ldr r1, [r0, #0x110]
+	bic r1, r1, #(0x7 << 0)
+	orr r1, r1, #0x2
+	bic r1, r1, #(0x3 << 4)
+	bic r1, r1, #(0x3 << 8)
+	orr r1, r1, #(0x1 << 30)
+	bic r1, r1, #(0x1 << 31)
+
+	ldr r1, [r0, #0x210]
+	bic r1, r1, #(0x7 << 0)
+	orr r1, r1, #0x2
+	bic r1, r1, #(0x3 << 4)
+	bic r1, r1, #(0x3 << 8)
+	orr r1, r1, #(0x1 << 30)
+	bic r1, r1, #(0x1 << 31)
+
+	ldr r1, [r0, #0x310]
+	bic r1, r1, #(0x7 << 0)
+	orr r1, r1, #0x2
+	bic r1, r1, #(0x3 << 4)
+	bic r1, r1, #(0x3 << 8)
+	orr r1, r1, #(0x1 << 30)
+	bic r1, r1, #(0x1 << 31)
+
+	/*set SDHC-port2 arbitration*/
+	ldr r0, =AHBMAX_BASE_ADDR
+	ldr r1, [r0, #0xA00]
+	bic r1, r1, #(0x7 << 0)
+#endif
+
+	/*set JMP step to zero*/
+	ldr r0, =M4IF_BASE_ADDR
+	ldr r1, [r0, #0x48]
+	bic r1, r1, #(0x3 << 8)
+	str r1, [r0, #0x48]
+.endm
+
+.macro init_clock
+	ldr r0, =ROM_SI_REV
+	ldr r1, [r0]
+	cmp r1, #0x20
+
+	/* For TO2 only, set LDO to 1.3V */
+	ldr r0, =0x53fa8000
+	ldr r1, =0x00194005
+	streq r1, [r0, #0x04]
+
+	ldr r0, CCM_BASE_ADDR_W
+
+	/* Gate of clocks to the peripherals first */
+	ldr r1, =0x3FFFFFFF
+	str r1, [r0, #CLKCTL_CCGR0]
+	ldr r1, =0x0
+	str r1, [r0, #CLKCTL_CCGR1]
+	str r1, [r0, #CLKCTL_CCGR2]
+	str r1, [r0, #CLKCTL_CCGR3]
+	str r1, [r0, #CLKCTL_CCGR7]
+	ldr r1, =0x00030000
+	str r1, [r0, #CLKCTL_CCGR4]
+	ldr r1, =0x00FFF030
+	str r1, [r0, #CLKCTL_CCGR5]
+	ldr r1, =0x0F00030F
+	str r1, [r0, #CLKCTL_CCGR6]
+
+	/* Switch ARM to step clock */
+	mov r1, #0x4
+	str r1, [r0, #CLKCTL_CCSR]
+
+	setup_pll PLL1_BASE_ADDR, 800
+
+        setup_pll PLL3_BASE_ADDR, 400
+
+        /* Switch peripheral to PLL3 */
+        ldr r0, CCM_BASE_ADDR_W
+        ldr r1, CCM_VAL_0x00015154
+        str r1, [r0, #CLKCTL_CBCMR]
+        ldr r1, CCM_VAL_0x02888945
+        orr r1, r1, #(1 << 16)
+        str r1, [r0, #CLKCTL_CBCDR]
+        /* make sure change is effective */
+1:      ldr r1, [r0, #CLKCTL_CDHIPR]
+        cmp r1, #0x0
+        bne 1b
+
+        setup_pll PLL2_BASE_ADDR, CONFIG_SYS_PLL2_FREQ
+
+	/* Switch peripheral to PLL2 */
+	ldr r0, CCM_BASE_ADDR_W
+	ldr r1, CCM_VAL_0x00808145
+	orr r1, r1, #(CONFIG_SYS_AHB_PODF << 10)
+	orr r1, r1, #(CONFIG_SYS_AXIA_PODF << 16)
+	orr r1, r1, #(CONFIG_SYS_AXIB_PODF << 19)
+	str r1, [r0, #CLKCTL_CBCDR]
+
+	ldr r1, CCM_VAL_0x00016154
+	str r1, [r0, #CLKCTL_CBCMR]
+
+	/*change uart clk parent to pll2*/
+	ldr r1, [r0, #CLKCTL_CSCMR1]
+	and r1, r1, #0xfcffffff
+	orr r1, r1, #0x01000000
+	str r1, [r0, #CLKCTL_CSCMR1]
+
+	/* make sure change is effective */
+1:      ldr r1, [r0, #CLKCTL_CDHIPR]
+	cmp r1, #0x0
+	bne 1b
+
+        setup_pll PLL3_BASE_ADDR, 216
+
+	setup_pll PLL4_BASE_ADDR, 455
+
+	/* Set the platform clock dividers */
+	ldr r0, PLATFORM_BASE_ADDR_W
+	ldr r1, PLATFORM_CLOCK_DIV_W
+	str r1, [r0, #PLATFORM_ICGC]
+
+	ldr r0, CCM_BASE_ADDR_W
+	mov r1, #0
+	str r1, [r0, #CLKCTL_CACRR]
+
+	/* Switch ARM back to PLL 1. */
+	mov r1, #0x0
+	str r1, [r0, #CLKCTL_CCSR]
+
+	/* make uart div=6*/
+	ldr r1, [r0, #CLKCTL_CSCDR1]
+	and r1, r1, #0xffffffc0
+	orr r1, r1, #0x0a
+	str r1, [r0, #CLKCTL_CSCDR1]
+
+	/* Restore the default values in the Gate registers */
+	ldr r1, =0xFFFFFFFF
+	str r1, [r0, #CLKCTL_CCGR0]
+	str r1, [r0, #CLKCTL_CCGR1]
+	str r1, [r0, #CLKCTL_CCGR2]
+	str r1, [r0, #CLKCTL_CCGR3]
+	str r1, [r0, #CLKCTL_CCGR4]
+	str r1, [r0, #CLKCTL_CCGR5]
+	str r1, [r0, #CLKCTL_CCGR6]
+	str r1, [r0, #CLKCTL_CCGR7]
+
+        mov r1, #0x00000
+        str r1, [r0, #CLKCTL_CCDR]
+
+        /* for cko - for ARM div by 8 */
+        mov r1, #0x000A0000
+        add r1, r1, #0x00000F0
+        str r1, [r0, #CLKCTL_CCOSR]
+.endm
+
+.section ".text.init", "x"
+
+.globl lowlevel_init
+lowlevel_init:
+
+#ifdef ENABLE_IMPRECISE_ABORT
+        mrs r1, spsr            /* save old spsr */
+        mrs r0, cpsr            /* read out the cpsr */
+	bic r0, r0, #0x100      /* clear the A bit */
+	msr spsr, r0            /* update spsr */
+	add lr, pc, #0x8        /* update lr */
+        movs pc, lr             /* update cpsr */
+        nop
+        nop
+        nop
+	nop
+	msr spsr, r1            /* restore old spsr */
+#endif
+
+	/* SYS_ON_OFF_CTL (GPIO7) must be set to HIGH as the
+	 * first action in the BOOT sequence.
+	 */
+	ldr r0, =GPIO1_BASE_ADDR
+	ldr r1, [r0, #0x0]
+	orr r1, r1, #(1 << 7)
+	str r1, [r0, #0x0]
+	ldr r1, [r0, #0x4]
+	orr r1, r1, #(1 << 7)
+	str r1, [r0, #0x4]
+
+	/* ARM errata ID #468414 */
+	mrc 15, 0, r1, c1, c0, 1
+	orr r1, r1, #(1 << 5)    /* enable L1NEON bit */
+	mcr 15, 0, r1, c1, c0, 1
+
+	init_l2cc
+
+	init_aips
+
+#ifdef CONFIG_ADJUST_WIFI_FEC_PERFORMANCE
+	/*increase WIFI & FEC priority of accessing bus*/
+	init_m4if
+#endif
+
+	init_clock
+
+	mov pc, lr
+
+/* Board level setting value */
+CCM_BASE_ADDR_W:        .word CCM_BASE_ADDR
+CCM_VAL_0x00016154:     .word 0x00016154
+CCM_VAL_0x00808145:     .word 0x00808145
+CCM_VAL_0x00015154:     .word 0x00015154
+CCM_VAL_0x02888945:     .word 0x02888945
+W_DP_OP_1000:           .word DP_OP_1000
+W_DP_MFD_1000:          .word DP_MFD_1000
+W_DP_MFN_1000:          .word DP_MFN_1000
+W_DP_OP_800:           	.word DP_OP_800
+W_DP_MFD_800:           .word DP_MFD_800
+W_DP_MFN_800:           .word DP_MFN_800
+W_DP_OP_600:            .word DP_OP_600
+W_DP_MFD_600:           .word DP_MFD_600
+W_DP_MFN_600:           .word DP_MFN_600
+W_DP_OP_400:            .word DP_OP_400
+W_DP_MFD_400:           .word DP_MFD_400
+W_DP_MFN_400:           .word DP_MFN_400
+W_DP_OP_216:            .word DP_OP_216
+W_DP_MFD_216:           .word DP_MFD_216
+W_DP_MFN_216:           .word DP_MFN_216
+W_DP_OP_455:            .word DP_OP_455
+W_DP_MFD_455:           .word DP_MFD_455
+W_DP_MFN_455:           .word DP_MFN_455
+PLATFORM_BASE_ADDR_W:   .word ARM_BASE_ADDR
+PLATFORM_CLOCK_DIV_W:   .word 0x00000124

board/freescale/mx53_smd/u-boot.lds

@@ -0,0 +1,74 @@
+/*
+ * January 2004 - Changed to support H4 device
+ * Copyright (c) 2004 Texas Instruments
+ *
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
+ *
+ * (C) Copyright 2010 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+	. = 0x00000000;
+
+	. = ALIGN(4);
+	.text	   :
+	{
+	  /* WARNING - the following is hand-optimized to fit within	*/
+	  /* the sector layout of our flash chips!	XXX FIXME XXX	*/
+	  board/freescale/mx53_smd/flash_header.o	(.text.flasheader)
+	  cpu/arm_cortexa8/start.o
+	  board/freescale/mx53_smd/libmx53_smd.a	(.text)
+	  lib_arm/libarm.a		(.text)
+	  net/libnet.a			(.text)
+	  drivers/mtd/libmtd.a		(.text)
+	  drivers/mmc/libmmc.a		(.text)
+
+	  . = DEFINED(env_offset) ? env_offset : .;
+	  common/env_embedded.o(.text)
+
+	  *(.text)
+	}
+
+	. = ALIGN(4);
+	.rodata : { *(.rodata) }
+
+	. = ALIGN(4);
+	.data : { *(.data) }
+
+	. = ALIGN(4);
+	.got : { *(.got) }
+
+	. = .;
+	__u_boot_cmd_start = .;
+	.u_boot_cmd : { *(.u_boot_cmd) }
+	__u_boot_cmd_end = .;
+
+	. = ALIGN(4);
+	_end_of_copy = .; /* end_of ROM copy code here */
+	__bss_start = .;
+	.bss : { *(.bss) }
+	_end = .;
+}

board/freescale/mx6q_arm2/Makefile

@@ -0,0 +1,47 @@
+#
+# (C) Copyright 2010-2011 Freescale Semiconductor, Inc.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).a
+
+COBJS	:= $(BOARD).o
+SOBJS	:= lowlevel_init.o flash_header.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################

board/freescale/mx6q_arm2/config.mk

@@ -0,0 +1,11 @@
+LDSCRIPT := $(SRCTREE)/board/$(VENDOR)/$(BOARD)/u-boot.lds
+
+sinclude $(OBJTREE)/board/$(VENDOR)/$(BOARD)/config.tmp
+
+ifndef TEXT_BASE
+	TEXT_BASE = 0x27800000
+endif
+
+ifdef CONFIG_MX6Q_ARM2_LPDDR2POP
+	TEXT_BASE = 0x10800000
+endif

board/freescale/mx6q_arm2/lowlevel_init.S

@@ -0,0 +1,167 @@
+/*
+ * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <asm/arch/mx6.h>
+
+/*
+ Disable L2Cache because ROM turn it on when uboot use plug-in.
+ If L2Cache is on default, there are cache coherence problem if kernel have
+ not config L2Cache.
+*/
+.macro init_l2cc
+    ldr     r1, =0xa02000
+    ldr     r0, =0x0
+    str     r0, [r1, #0x100]
+.endm /* init_l2cc */
+
+/* invalidate the D-CACHE */
+.macro inv_dcache
+    mov     r0,#0
+    mcr     p15,2,r0,c0,c0,0  /* cache size selection register, select dcache */
+    mrc     p15,1,r0,c0,c0,0  /* cache size ID register */
+    mov     r0,r0,ASR #13
+    ldr     r3,=0xfff
+    and     r0,r0,r3
+    cmp     r0,#0x7f
+    moveq   r6,#0x1000
+    beq     size_done
+    cmp     r0,#0xff
+    moveq   r6,#0x2000
+    movne   r6,#0x4000
+
+size_done:
+    mov     r2,#0
+    mov     r3,#0x40000000
+    mov     r4,#0x80000000
+    mov     r5,#0xc0000000
+
+d_inv_loop:
+    mcr     p15,0,r2,c7,c6,2  /* invalidate dcache by set / way */
+    mcr     p15,0,r3,c7,c6,2  /* invalidate dcache by set / way */
+    mcr     p15,0,r4,c7,c6,2  /* invalidate dcache by set / way */
+    mcr     p15,0,r5,c7,c6,2  /* invalidate dcache by set / way */
+    add     r2,r2,#0x20
+    add     r3,r3,#0x20
+    add     r4,r4,#0x20
+    add     r5,r5,#0x20
+
+    cmp     r2,r6
+    bne     d_inv_loop
+.endm
+
+/* AIPS setup - Only setup MPROTx registers.
+ * The PACR default values are good.*/
+.macro init_aips
+	/*
+	 * Set all MPROTx to be non-bufferable, trusted for R/W,
+	 * not forced to user-mode.
+	 */
+	ldr r0, =AIPS1_ON_BASE_ADDR
+	ldr r1, =0x77777777
+	str r1, [r0, #0x0]
+	str r1, [r0, #0x4]
+	ldr r1, =0x0
+	str r1, [r0, #0x40]
+	str r1, [r0, #0x44]
+	str r1, [r0, #0x48]
+	str r1, [r0, #0x4C]
+	str r1, [r0, #0x50]
+
+	ldr r0, =AIPS2_ON_BASE_ADDR
+	ldr r1, =0x77777777
+	str r1, [r0, #0x0]
+	str r1, [r0, #0x4]
+	ldr r1, =0x0
+	str r1, [r0, #0x40]
+	str r1, [r0, #0x44]
+	str r1, [r0, #0x48]
+	str r1, [r0, #0x4C]
+	str r1, [r0, #0x50]
+.endm /* init_aips */
+
+.macro setup_pll pll, freq
+.endm
+
+.macro init_clock
+
+/* PLL1, PLL2, and PLL3 are enabled by ROM */
+#ifdef CONFIG_PLL3
+	/* enable PLL3 for UART */
+	ldr r0, ANATOP_BASE_ADDR_W
+
+	/* power up PLL */
+	ldr r1, [r0, #ANATOP_USB1]
+	orr r1, r1, #0x1000
+	str r1, [r0, #ANATOP_USB1]
+
+	/* enable PLL */
+	ldr r1, [r0, #ANATOP_USB1]
+	orr r1, r1, #0x2000
+	str r1, [r0, #ANATOP_USB1]
+
+	/* wait PLL lock */
+100:
+	ldr r1, [r0, #ANATOP_USB1]
+	mov r1, r1, lsr #31
+	cmp r1, #0x1
+	bne 100b
+
+	/* clear bypass bit */
+	ldr r1, [r0, #ANATOP_USB1]
+	and r1, r1, #0xfffeffff
+	str r1, [r0, #ANATOP_USB1]
+#endif
+
+	/* Restore the default values in the Gate registers */
+	ldr r0, CCM_BASE_ADDR_W
+	ldr r1, =0xC0003F
+	str r1, [r0, #CLKCTL_CCGR0]
+	ldr r1, =0x30FC00
+	str r1, [r0, #CLKCTL_CCGR1]
+	ldr r1, =0xFFFC000
+	str r1, [r0, #CLKCTL_CCGR2]
+	ldr r1, =0x3FF00000
+	str r1, [r0, #CLKCTL_CCGR3]
+	ldr r1, =0xFFF300
+	str r1, [r0, #CLKCTL_CCGR4]
+	ldr r1, =0xF0000C3
+	str r1, [r0, #CLKCTL_CCGR5]
+	ldr r1, =0x3FC
+	str r1, [r0, #CLKCTL_CCGR6]
+.endm
+
+.section ".text.init", "x"
+
+.globl lowlevel_init
+lowlevel_init:
+
+	inv_dcache
+
+	init_l2cc
+
+	init_aips
+
+	init_clock
+
+	mov pc, lr
+
+/* Board level setting value */
+ANATOP_BASE_ADDR_W:		.word ANATOP_BASE_ADDR
+CCM_BASE_ADDR_W:		.word CCM_BASE_ADDR

board/freescale/mx6q_arm2/u-boot.lds

@@ -0,0 +1,74 @@
+/*
+ * January 2004 - Changed to support H4 device
+ * Copyright (c) 2004 Texas Instruments
+ *
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
+ *
+ * (C) Copyright 2011 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+	. = 0x00000000;
+
+	. = ALIGN(4);
+	.text	   :
+	{
+	  /* WARNING - the following is hand-optimized to fit within	*/
+	  /* the sector layout of our flash chips!	XXX FIXME XXX	*/
+	  board/freescale/mx6q_arm2/flash_header.o	(.text.flasheader)
+	  cpu/arm_cortexa8/start.o
+	  board/freescale/mx6q_arm2/libmx6q_arm2.a	(.text)
+	  lib_arm/libarm.a		(.text)
+	  net/libnet.a			(.text)
+	  drivers/mtd/libmtd.a		(.text)
+	  drivers/mmc/libmmc.a		(.text)
+
+	  . = DEFINED(env_offset) ? env_offset : .;
+	  common/env_embedded.o(.text)
+
+	  *(.text)
+	}
+
+	. = ALIGN(4);
+	.rodata : { *(.rodata) }
+
+	. = ALIGN(4);
+	.data : { *(.data) }
+
+	. = ALIGN(4);
+	.got : { *(.got) }
+
+	. = .;
+	__u_boot_cmd_start = .;
+	.u_boot_cmd : { *(.u_boot_cmd) }
+	__u_boot_cmd_end = .;
+
+	. = ALIGN(4);
+	_end_of_copy = .; /* end_of ROM copy code here */
+	__bss_start = .;
+	.bss : { *(.bss) }
+	_end = .;
+}

board/freescale/mx6q_sabreauto/Makefile

@@ -0,0 +1,47 @@
+#
+# (C) Copyright 2010-2011 Freescale Semiconductor, Inc.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).a
+
+COBJS	:= $(BOARD).o
+SOBJS	:= lowlevel_init.o flash_header.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################

board/freescale/mx6q_sabreauto/config.mk

@@ -0,0 +1,7 @@
+LDSCRIPT := $(SRCTREE)/board/$(VENDOR)/$(BOARD)/u-boot.lds
+
+sinclude $(OBJTREE)/board/$(VENDOR)/$(BOARD)/config.tmp
+
+ifndef TEXT_BASE
+	TEXT_BASE = 0x27800000
+endif

board/freescale/mx6q_sabreauto/flash_header.S

@@ -0,0 +1,355 @@
+/*
+ * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <asm/arch/mx6.h>
+
+#ifdef	CONFIG_FLASH_HEADER
+#ifndef CONFIG_FLASH_HEADER_OFFSET
+# error "Must define the offset of flash header"
+#endif
+
+#define CPU_2_BE_32(l) \
+       ((((l) & 0x000000FF) << 24) | \
+	(((l) & 0x0000FF00) << 8)  | \
+	(((l) & 0x00FF0000) >> 8)  | \
+	(((l) & 0xFF000000) >> 24))
+
+#define MXC_DCD_ITEM(i, addr, val)   \
+dcd_node_##i:                        \
+        .word CPU_2_BE_32(addr) ;     \
+        .word CPU_2_BE_32(val)  ;     \
+
+.section ".text.flasheader", "x"
+	b	_start
+	.org	CONFIG_FLASH_HEADER_OFFSET
+
+ivt_header:       .word 0x402000D1 /* Tag=0xD1, Len=0x0020, Ver=0x40 */
+app_code_jump_v:  .word _start
+reserv1:          .word 0x0
+dcd_ptr:          .word dcd_hdr
+boot_data_ptr:	  .word boot_data
+self_ptr:         .word ivt_header
+app_code_csf:     .word 0x0
+reserv2:          .word 0x0
+
+boot_data:        .word TEXT_BASE
+image_len:        .word _end_of_copy  - TEXT_BASE + CONFIG_FLASH_HEADER_OFFSET
+plugin:           .word 0x0
+
+#ifdef CONFIG_LPDDR2
+
+dcd_hdr:          .word 0x400804D2 /* Tag=0xD2, Len=128*8 + 4 + 4, Ver=0x40 */
+write_dcd_cmd:    .word 0x040404CC /* Tag=0xCC, Len=128*8 + 4, Param=0x04 */
+
+/* DCD */
+MXC_DCD_ITEM(1, CCM_BASE_ADDR + 0x18, 0x60324)
+
+MXC_DCD_ITEM(2, IOMUXC_BASE_ADDR + 0x5a8, 0x00003038)
+MXC_DCD_ITEM(3, IOMUXC_BASE_ADDR + 0x5b0, 0x00003038)
+MXC_DCD_ITEM(4, IOMUXC_BASE_ADDR + 0x524, 0x00003038)
+MXC_DCD_ITEM(5, IOMUXC_BASE_ADDR + 0x51c, 0x00003038)
+
+MXC_DCD_ITEM(6, IOMUXC_BASE_ADDR + 0x518, 0x00003038)
+MXC_DCD_ITEM(7, IOMUXC_BASE_ADDR + 0x50c, 0x00003038)
+MXC_DCD_ITEM(8, IOMUXC_BASE_ADDR + 0x5b8, 0x00003038)
+MXC_DCD_ITEM(9, IOMUXC_BASE_ADDR + 0x5c0, 0x00003038)
+
+MXC_DCD_ITEM(10, IOMUXC_BASE_ADDR + 0x5ac, 0x00000038)
+MXC_DCD_ITEM(11, IOMUXC_BASE_ADDR + 0x5b4, 0x00000038)
+MXC_DCD_ITEM(12, IOMUXC_BASE_ADDR + 0x528, 0x00000038)
+MXC_DCD_ITEM(13, IOMUXC_BASE_ADDR + 0x520, 0x00000038)
+
+MXC_DCD_ITEM(14, IOMUXC_BASE_ADDR + 0x514, 0x00000038)
+MXC_DCD_ITEM(15, IOMUXC_BASE_ADDR + 0x510, 0x00000038)
+MXC_DCD_ITEM(16, IOMUXC_BASE_ADDR + 0x5bc, 0x00000038)
+MXC_DCD_ITEM(17, IOMUXC_BASE_ADDR + 0x5c4, 0x00000038)
+
+MXC_DCD_ITEM(18, IOMUXC_BASE_ADDR + 0x56c, 0x00000038)
+MXC_DCD_ITEM(19, IOMUXC_BASE_ADDR + 0x578, 0x00000038)
+MXC_DCD_ITEM(20, IOMUXC_BASE_ADDR + 0x588, 0x00000038)
+MXC_DCD_ITEM(21, IOMUXC_BASE_ADDR + 0x594, 0x00000038)
+
+MXC_DCD_ITEM(22, IOMUXC_BASE_ADDR + 0x57c, 0x00000038)
+MXC_DCD_ITEM(23, IOMUXC_BASE_ADDR + 0x590, 0x00000038)
+MXC_DCD_ITEM(24, IOMUXC_BASE_ADDR + 0x598, 0x00000038)
+MXC_DCD_ITEM(25, IOMUXC_BASE_ADDR + 0x58c, 0x00000000)
+
+MXC_DCD_ITEM(26, IOMUXC_BASE_ADDR + 0x59c, 0x00000038)
+MXC_DCD_ITEM(27, IOMUXC_BASE_ADDR + 0x5a0, 0x00000038)
+MXC_DCD_ITEM(28, IOMUXC_BASE_ADDR + 0x784, 0x00000038)
+MXC_DCD_ITEM(29, IOMUXC_BASE_ADDR + 0x788, 0x00000038)
+
+MXC_DCD_ITEM(30, IOMUXC_BASE_ADDR + 0x794, 0x00000038)
+MXC_DCD_ITEM(31, IOMUXC_BASE_ADDR + 0x79c, 0x00000038)
+MXC_DCD_ITEM(32, IOMUXC_BASE_ADDR + 0x7a0, 0x00000038)
+MXC_DCD_ITEM(33, IOMUXC_BASE_ADDR + 0x7a4, 0x00000038)
+
+MXC_DCD_ITEM(34, IOMUXC_BASE_ADDR + 0x7a8, 0x00000038)
+MXC_DCD_ITEM(35, IOMUXC_BASE_ADDR + 0x748, 0x00000038)
+MXC_DCD_ITEM(36, IOMUXC_BASE_ADDR + 0x74c, 0x00000038)
+MXC_DCD_ITEM(37, IOMUXC_BASE_ADDR + 0x750, 0x00020000)
+
+MXC_DCD_ITEM(38, IOMUXC_BASE_ADDR + 0x758, 0x00000000)
+MXC_DCD_ITEM(39, IOMUXC_BASE_ADDR + 0x774, 0x00020000)
+MXC_DCD_ITEM(40, IOMUXC_BASE_ADDR + 0x78c, 0x00000038)
+MXC_DCD_ITEM(41, IOMUXC_BASE_ADDR + 0x798, 0x00080000)
+
+MXC_DCD_ITEM(42, MMDC_P0_BASE_ADDR + 0x01c, 0x00008000)
+MXC_DCD_ITEM(43, MMDC_P1_BASE_ADDR + 0x01c, 0x00008000)
+
+MXC_DCD_ITEM(44, MMDC_P0_BASE_ADDR + 0x85c, 0x1b5f01ff)
+MXC_DCD_ITEM(45, MMDC_P1_BASE_ADDR + 0x85c, 0x1b5f01ff)
+
+MXC_DCD_ITEM(46, MMDC_P0_BASE_ADDR + 0x800, 0xa1390000)
+MXC_DCD_ITEM(47, MMDC_P1_BASE_ADDR + 0x800, 0xa1390000)
+
+MXC_DCD_ITEM(48, MMDC_P0_BASE_ADDR + 0x890, 0x00400000)
+MXC_DCD_ITEM(49, MMDC_P1_BASE_ADDR + 0x890, 0x00400000)
+
+MXC_DCD_ITEM(50, MMDC_P1_BASE_ADDR + 0x8bc, 0x00055555)
+
+MXC_DCD_ITEM(51, MMDC_P0_BASE_ADDR + 0x8b8, 0x00000800)
+MXC_DCD_ITEM(52, MMDC_P1_BASE_ADDR + 0x8b8, 0x00000800)
+
+MXC_DCD_ITEM(53, MMDC_P0_BASE_ADDR + 0x81c, 0x33333333)
+MXC_DCD_ITEM(54, MMDC_P0_BASE_ADDR + 0x820, 0x33333333)
+MXC_DCD_ITEM(55, MMDC_P0_BASE_ADDR + 0x824, 0x33333333)
+MXC_DCD_ITEM(56, MMDC_P0_BASE_ADDR + 0x828, 0x33333333)
+MXC_DCD_ITEM(57, MMDC_P1_BASE_ADDR + 0x81c, 0x33333333)
+MXC_DCD_ITEM(58, MMDC_P1_BASE_ADDR + 0x820, 0x33333333)
+MXC_DCD_ITEM(59, MMDC_P1_BASE_ADDR + 0x824, 0x33333333)
+MXC_DCD_ITEM(60, MMDC_P1_BASE_ADDR + 0x828, 0x33333333)
+
+MXC_DCD_ITEM(61, MMDC_P0_BASE_ADDR + 0x82c, 0xf3333333)
+MXC_DCD_ITEM(62, MMDC_P0_BASE_ADDR + 0x830, 0xf3333333)
+MXC_DCD_ITEM(63, MMDC_P0_BASE_ADDR + 0x834, 0xf3333333)
+MXC_DCD_ITEM(64, MMDC_P0_BASE_ADDR + 0x838, 0xf3333333)
+MXC_DCD_ITEM(65, MMDC_P1_BASE_ADDR + 0x82c, 0xf3333333)
+MXC_DCD_ITEM(66, MMDC_P1_BASE_ADDR + 0x830, 0xf3333333)
+MXC_DCD_ITEM(67, MMDC_P1_BASE_ADDR + 0x834, 0xf3333333)
+MXC_DCD_ITEM(68, MMDC_P1_BASE_ADDR + 0x838, 0xf3333333)
+
+MXC_DCD_ITEM(69, MMDC_P0_BASE_ADDR + 0x848, 0x49383b39)
+MXC_DCD_ITEM(70, MMDC_P0_BASE_ADDR + 0x850, 0x30364738)
+MXC_DCD_ITEM(71, MMDC_P1_BASE_ADDR + 0x848, 0x3e3c3846)
+MXC_DCD_ITEM(72, MMDC_P1_BASE_ADDR + 0x850, 0x4c294b35)
+
+MXC_DCD_ITEM(73, MMDC_P0_BASE_ADDR + 0x83c, 0x20000000)
+MXC_DCD_ITEM(74, MMDC_P0_BASE_ADDR + 0x840, 0x0)
+MXC_DCD_ITEM(75, MMDC_P1_BASE_ADDR + 0x83c, 0x20000000)
+MXC_DCD_ITEM(76, MMDC_P1_BASE_ADDR + 0x840, 0x0)
+
+MXC_DCD_ITEM(77, MMDC_P0_BASE_ADDR + 0x858, 0xf00)
+MXC_DCD_ITEM(78, MMDC_P1_BASE_ADDR + 0x858, 0xf00)
+
+MXC_DCD_ITEM(79, MMDC_P0_BASE_ADDR + 0x8b8, 0x800)
+MXC_DCD_ITEM(80, MMDC_P1_BASE_ADDR + 0x8b8, 0x800)
+
+MXC_DCD_ITEM(81, MMDC_P0_BASE_ADDR + 0xc, 0x555a61a5)
+MXC_DCD_ITEM(82, MMDC_P0_BASE_ADDR + 0x4, 0x20036)
+MXC_DCD_ITEM(83, MMDC_P0_BASE_ADDR + 0x10, 0x160e83)
+MXC_DCD_ITEM(84, MMDC_P0_BASE_ADDR + 0x14, 0xdd)
+MXC_DCD_ITEM(85, MMDC_P0_BASE_ADDR + 0x18, 0x8174c)
+MXC_DCD_ITEM(86, MMDC_P0_BASE_ADDR + 0x2c, 0xf9f26d2)
+MXC_DCD_ITEM(87, MMDC_P0_BASE_ADDR + 0x30, 0x20e)
+MXC_DCD_ITEM(88, MMDC_P0_BASE_ADDR + 0x38, 0x200aac)
+MXC_DCD_ITEM(89, MMDC_P0_BASE_ADDR + 0x8, 0x0)
+
+MXC_DCD_ITEM(90, MMDC_P0_BASE_ADDR + 0x40, 0x5f)
+
+MXC_DCD_ITEM(91, MMDC_P0_BASE_ADDR + 0x0, 0xc3010000)
+
+MXC_DCD_ITEM(92, MMDC_P1_BASE_ADDR + 0xc, 0x555a61a5)
+MXC_DCD_ITEM(93, MMDC_P1_BASE_ADDR + 0x4, 0x20036)
+MXC_DCD_ITEM(94, MMDC_P1_BASE_ADDR + 0x10, 0x160e83)
+MXC_DCD_ITEM(95, MMDC_P1_BASE_ADDR + 0x14, 0xdd)
+MXC_DCD_ITEM(96, MMDC_P1_BASE_ADDR + 0x18, 0x8174c)
+MXC_DCD_ITEM(97, MMDC_P1_BASE_ADDR + 0x2c, 0xf9f26d2)
+MXC_DCD_ITEM(98, MMDC_P1_BASE_ADDR + 0x30, 0x20e)
+MXC_DCD_ITEM(99, MMDC_P1_BASE_ADDR + 0x38, 0x200aac)
+MXC_DCD_ITEM(100, MMDC_P1_BASE_ADDR + 0x8, 0x0)
+
+MXC_DCD_ITEM(101, MMDC_P1_BASE_ADDR + 0x40, 0x3f)
+MXC_DCD_ITEM(102, MMDC_P1_BASE_ADDR + 0x0, 0xc3010000)
+
+MXC_DCD_ITEM(103, MMDC_P0_BASE_ADDR + 0x1c, 0x3f8030)
+MXC_DCD_ITEM(104, MMDC_P0_BASE_ADDR + 0x1c, 0xff0a8030)
+MXC_DCD_ITEM(105, MMDC_P0_BASE_ADDR + 0x1c, 0xc2018030)
+MXC_DCD_ITEM(106, MMDC_P0_BASE_ADDR + 0x1c, 0x6028030)
+MXC_DCD_ITEM(107, MMDC_P0_BASE_ADDR + 0x1c, 0x2038030)
+
+MXC_DCD_ITEM(108, MMDC_P1_BASE_ADDR + 0x1c, 0x3f8030)
+MXC_DCD_ITEM(109, MMDC_P1_BASE_ADDR + 0x1c, 0xff0a8030)
+MXC_DCD_ITEM(110, MMDC_P1_BASE_ADDR + 0x1c, 0xc2018030)
+MXC_DCD_ITEM(111, MMDC_P1_BASE_ADDR + 0x1c, 0x6028030)
+MXC_DCD_ITEM(112, MMDC_P1_BASE_ADDR + 0x1c, 0x2038030)
+
+MXC_DCD_ITEM(113, MMDC_P0_BASE_ADDR + 0x800, 0xa1390003)
+MXC_DCD_ITEM(114, MMDC_P1_BASE_ADDR + 0x800, 0xa1390003)
+
+MXC_DCD_ITEM(115, MMDC_P0_BASE_ADDR + 0x20, 0x7800)
+MXC_DCD_ITEM(116, MMDC_P1_BASE_ADDR + 0x20, 0x7800)
+
+MXC_DCD_ITEM(117, MMDC_P0_BASE_ADDR + 0x818, 0x0)
+MXC_DCD_ITEM(118, MMDC_P1_BASE_ADDR + 0x818, 0x0)
+
+MXC_DCD_ITEM(119, MMDC_P0_BASE_ADDR + 0x800, 0xa1390003)
+MXC_DCD_ITEM(120, MMDC_P1_BASE_ADDR + 0x800, 0xa1390003)
+
+MXC_DCD_ITEM(121, MMDC_P0_BASE_ADDR + 0x8b8, 0x800)
+MXC_DCD_ITEM(122, MMDC_P1_BASE_ADDR + 0x8b8, 0x800)
+
+MXC_DCD_ITEM(123, MMDC_P0_BASE_ADDR + 0x1c, 0x0)
+MXC_DCD_ITEM(124, MMDC_P1_BASE_ADDR + 0x1c, 0x0)
+
+MXC_DCD_ITEM(125, MMDC_P0_BASE_ADDR + 0x404, 0x00011006)
+
+/* enable AXI cache for VDOA/VPU/IPU */
+MXC_DCD_ITEM(126, IOMUXC_BASE_ADDR + 0x010, 0xf00000ff)
+/* set IPU Qos=0x7 */
+MXC_DCD_ITEM(127, IOMUXC_BASE_ADDR + 0x018, 0x00070007)
+MXC_DCD_ITEM(128, IOMUXC_BASE_ADDR + 0x01c, 0x00070007)
+
+#else
+
+dcd_hdr:          .word 0x40C802D2 /* Tag=0xD2, Len=88*8 + 4 + 4, Ver=0x40 */
+write_dcd_cmd:    .word 0x04C402CC /* Tag=0xCC, Len=88*8 + 4, Param=0x04 */
+
+/* DCD */
+/* DDR3 initialization based on the MX6Q Auto Reference Design (ARD) */
+
+MXC_DCD_ITEM(1, IOMUXC_BASE_ADDR + 0x5a8, 0x00000028)
+MXC_DCD_ITEM(2, IOMUXC_BASE_ADDR + 0x5b0, 0x00000028)
+MXC_DCD_ITEM(3, IOMUXC_BASE_ADDR + 0x524, 0x00000028)
+MXC_DCD_ITEM(4, IOMUXC_BASE_ADDR + 0x51c, 0x00000028)
+
+MXC_DCD_ITEM(5, IOMUXC_BASE_ADDR + 0x518, 0x00000028)
+MXC_DCD_ITEM(6, IOMUXC_BASE_ADDR + 0x50c, 0x00000028)
+MXC_DCD_ITEM(7, IOMUXC_BASE_ADDR + 0x5b8, 0x00000028)
+MXC_DCD_ITEM(8, IOMUXC_BASE_ADDR + 0x5c0, 0x00000028)
+
+MXC_DCD_ITEM(9, IOMUXC_BASE_ADDR + 0x5ac, 0x00000028)
+MXC_DCD_ITEM(10, IOMUXC_BASE_ADDR + 0x5b4, 0x00000028)
+MXC_DCD_ITEM(11, IOMUXC_BASE_ADDR + 0x528, 0x00000028)
+MXC_DCD_ITEM(12, IOMUXC_BASE_ADDR + 0x520, 0x00000028)
+
+MXC_DCD_ITEM(13, IOMUXC_BASE_ADDR + 0x514, 0x00000028)
+MXC_DCD_ITEM(14, IOMUXC_BASE_ADDR + 0x510, 0x00000028)
+MXC_DCD_ITEM(15, IOMUXC_BASE_ADDR + 0x5bc, 0x00000028)
+MXC_DCD_ITEM(16, IOMUXC_BASE_ADDR + 0x5c4, 0x00000028)
+
+MXC_DCD_ITEM(17, IOMUXC_BASE_ADDR + 0x56c, 0x00000030)
+MXC_DCD_ITEM(18, IOMUXC_BASE_ADDR + 0x578, 0x00000030)
+MXC_DCD_ITEM(19, IOMUXC_BASE_ADDR + 0x588, 0x00000030)
+MXC_DCD_ITEM(20, IOMUXC_BASE_ADDR + 0x594, 0x00000030)
+
+MXC_DCD_ITEM(21, IOMUXC_BASE_ADDR + 0x57c, 0x00000030)
+MXC_DCD_ITEM(22, IOMUXC_BASE_ADDR + 0x590, 0x00000030)
+MXC_DCD_ITEM(23, IOMUXC_BASE_ADDR + 0x598, 0x00000030)
+MXC_DCD_ITEM(24, IOMUXC_BASE_ADDR + 0x58c, 0x00000000)
+
+MXC_DCD_ITEM(25, IOMUXC_BASE_ADDR + 0x59c, 0x00003030)
+MXC_DCD_ITEM(26, IOMUXC_BASE_ADDR + 0x5a0, 0x00003030)
+MXC_DCD_ITEM(27, IOMUXC_BASE_ADDR + 0x784, 0x00000028)
+MXC_DCD_ITEM(28, IOMUXC_BASE_ADDR + 0x788, 0x00000028)
+
+MXC_DCD_ITEM(29, IOMUXC_BASE_ADDR + 0x794, 0x00000028)
+MXC_DCD_ITEM(30, IOMUXC_BASE_ADDR + 0x79c, 0x00000028)
+MXC_DCD_ITEM(31, IOMUXC_BASE_ADDR + 0x7a0, 0x00000028)
+MXC_DCD_ITEM(32, IOMUXC_BASE_ADDR + 0x7a4, 0x00000028)
+
+MXC_DCD_ITEM(33, IOMUXC_BASE_ADDR + 0x7a8, 0x00000028)
+MXC_DCD_ITEM(34, IOMUXC_BASE_ADDR + 0x748, 0x00000028)
+MXC_DCD_ITEM(35, IOMUXC_BASE_ADDR + 0x74c, 0x00000030)
+MXC_DCD_ITEM(36, IOMUXC_BASE_ADDR + 0x750, 0x00020000)
+
+MXC_DCD_ITEM(37, IOMUXC_BASE_ADDR + 0x758, 0x00000000)
+MXC_DCD_ITEM(38, IOMUXC_BASE_ADDR + 0x774, 0x00020000)
+MXC_DCD_ITEM(39, IOMUXC_BASE_ADDR + 0x78c, 0x00000030)
+MXC_DCD_ITEM(40, IOMUXC_BASE_ADDR + 0x798, 0x000C0000)
+
+MXC_DCD_ITEM(41, MMDC_P0_BASE_ADDR + 0x81c, 0x33333333)
+MXC_DCD_ITEM(42, MMDC_P0_BASE_ADDR + 0x820, 0x33333333)
+MXC_DCD_ITEM(43, MMDC_P0_BASE_ADDR + 0x824, 0x33333333)
+MXC_DCD_ITEM(44, MMDC_P0_BASE_ADDR + 0x828, 0x33333333)
+
+MXC_DCD_ITEM(45, MMDC_P1_BASE_ADDR + 0x81c, 0x33333333)
+MXC_DCD_ITEM(46, MMDC_P1_BASE_ADDR + 0x820, 0x33333333)
+MXC_DCD_ITEM(47, MMDC_P1_BASE_ADDR + 0x824, 0x33333333)
+MXC_DCD_ITEM(48, MMDC_P1_BASE_ADDR + 0x828, 0x33333333)
+
+MXC_DCD_ITEM(49, MMDC_P0_BASE_ADDR + 0x018, 0x00001740)
+
+MXC_DCD_ITEM(50, MMDC_P0_BASE_ADDR + 0x01c, 0x00008000)
+MXC_DCD_ITEM(51, MMDC_P0_BASE_ADDR + 0x00c, 0x8A8F7975)
+MXC_DCD_ITEM(52, MMDC_P0_BASE_ADDR + 0x010, 0xFF538E64)
+MXC_DCD_ITEM(53, MMDC_P0_BASE_ADDR + 0x014, 0x01FF00DB)
+MXC_DCD_ITEM(54, MMDC_P0_BASE_ADDR + 0x02c, 0x000026D2)
+
+MXC_DCD_ITEM(55, MMDC_P0_BASE_ADDR + 0x030, 0x008F0E21)
+MXC_DCD_ITEM(56, MMDC_P0_BASE_ADDR + 0x008, 0x09444040)
+MXC_DCD_ITEM(57, MMDC_P0_BASE_ADDR + 0x004, 0x00020036)
+MXC_DCD_ITEM(58, MMDC_P0_BASE_ADDR + 0x040, 0x00000047)
+MXC_DCD_ITEM(59, MMDC_P0_BASE_ADDR + 0x000, 0x841A0000)
+
+MXC_DCD_ITEM(60, MMDC_P0_BASE_ADDR + 0x01c, 0x04088032)
+MXC_DCD_ITEM(61, MMDC_P0_BASE_ADDR + 0x01c, 0x00008033)
+MXC_DCD_ITEM(62, MMDC_P0_BASE_ADDR + 0x01c, 0x00428031)
+MXC_DCD_ITEM(63, MMDC_P0_BASE_ADDR + 0x01c, 0x09408030)
+
+MXC_DCD_ITEM(64, MMDC_P0_BASE_ADDR + 0x01c, 0x04008040)
+MXC_DCD_ITEM(65, MMDC_P0_BASE_ADDR + 0x800, 0xA1380003)
+MXC_DCD_ITEM(66, MMDC_P0_BASE_ADDR + 0x020, 0x00005800)
+MXC_DCD_ITEM(67, MMDC_P0_BASE_ADDR + 0x818, 0x00022227)
+MXC_DCD_ITEM(68, MMDC_P1_BASE_ADDR + 0x818, 0x00022227)
+
+/* Calibration values based on ARD and 528MHz */
+MXC_DCD_ITEM(69, MMDC_P0_BASE_ADDR + 0x83c, 0x434B0358)
+MXC_DCD_ITEM(70, MMDC_P0_BASE_ADDR + 0x840, 0x033D033C)
+MXC_DCD_ITEM(71, MMDC_P1_BASE_ADDR + 0x83c, 0x03520362)
+MXC_DCD_ITEM(72, MMDC_P1_BASE_ADDR + 0x840, 0x03480318)
+MXC_DCD_ITEM(73, MMDC_P0_BASE_ADDR + 0x848, 0x41383A3C)
+MXC_DCD_ITEM(74, MMDC_P1_BASE_ADDR + 0x848, 0x3F3C374A)
+MXC_DCD_ITEM(75, MMDC_P0_BASE_ADDR + 0x850, 0x42434444)
+MXC_DCD_ITEM(76, MMDC_P1_BASE_ADDR + 0x850, 0x4932473A)
+
+MXC_DCD_ITEM(77, MMDC_P0_BASE_ADDR + 0x80c, 0x001F001F)
+MXC_DCD_ITEM(78, MMDC_P0_BASE_ADDR + 0x810, 0x001F001F)
+
+MXC_DCD_ITEM(79, MMDC_P1_BASE_ADDR + 0x80c, 0x001F001F)
+MXC_DCD_ITEM(80, MMDC_P1_BASE_ADDR + 0x810, 0x001F001F)
+
+MXC_DCD_ITEM(81, MMDC_P0_BASE_ADDR + 0x8b8, 0x00000800)
+MXC_DCD_ITEM(82, MMDC_P1_BASE_ADDR + 0x8b8, 0x00000800)
+
+MXC_DCD_ITEM(83, MMDC_P0_BASE_ADDR + 0x404, 0x00011006)
+MXC_DCD_ITEM(84, MMDC_P0_BASE_ADDR + 0x004, 0x00025576)
+
+MXC_DCD_ITEM(85, MMDC_P0_BASE_ADDR + 0x01c, 0x00000000)
+
+
+/* enable AXI cache for VDOA/VPU/IPU */
+MXC_DCD_ITEM(86, IOMUXC_BASE_ADDR + 0x010, 0xf00000ff)
+/* set IPU Qos=0x7 */
+MXC_DCD_ITEM(87, IOMUXC_BASE_ADDR + 0x018, 0x00070007)
+MXC_DCD_ITEM(88, IOMUXC_BASE_ADDR + 0x01c, 0x00070007)
+#endif
+
+#endif

board/freescale/mx6q_sabreauto/lowlevel_init.S

@@ -0,0 +1,167 @@
+/*
+ * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <asm/arch/mx6.h>
+
+/*
+ Disable L2Cache because ROM turn it on when uboot use plug-in.
+ If L2Cache is on default, there are cache coherence problem if kernel have
+ not config L2Cache.
+*/
+.macro init_l2cc
+    ldr     r1, =0xa02000
+    ldr     r0, =0x0
+    str     r0, [r1, #0x100]
+.endm /* init_l2cc */
+
+/* invalidate the D-CACHE */
+.macro inv_dcache
+    mov     r0,#0
+    mcr     p15,2,r0,c0,c0,0  /* cache size selection register, select dcache */
+    mrc     p15,1,r0,c0,c0,0  /* cache size ID register */
+    mov     r0,r0,ASR #13
+    ldr     r3,=0xfff
+    and     r0,r0,r3
+    cmp     r0,#0x7f
+    moveq   r6,#0x1000
+    beq     size_done
+    cmp     r0,#0xff
+    moveq   r6,#0x2000
+    movne   r6,#0x4000
+
+size_done:
+    mov     r2,#0
+    mov     r3,#0x40000000
+    mov     r4,#0x80000000
+    mov     r5,#0xc0000000
+
+d_inv_loop:
+    mcr     p15,0,r2,c7,c6,2  /* invalidate dcache by set / way */
+    mcr     p15,0,r3,c7,c6,2  /* invalidate dcache by set / way */
+    mcr     p15,0,r4,c7,c6,2  /* invalidate dcache by set / way */
+    mcr     p15,0,r5,c7,c6,2  /* invalidate dcache by set / way */
+    add     r2,r2,#0x20
+    add     r3,r3,#0x20
+    add     r4,r4,#0x20
+    add     r5,r5,#0x20
+
+    cmp     r2,r6
+    bne     d_inv_loop
+.endm
+
+/* AIPS setup - Only setup MPROTx registers.
+ * The PACR default values are good.*/
+.macro init_aips
+	/*
+	 * Set all MPROTx to be non-bufferable, trusted for R/W,
+	 * not forced to user-mode.
+	 */
+	ldr r0, =AIPS1_ON_BASE_ADDR
+	ldr r1, =0x77777777
+	str r1, [r0, #0x0]
+	str r1, [r0, #0x4]
+	ldr r1, =0x0
+	str r1, [r0, #0x40]
+	str r1, [r0, #0x44]
+	str r1, [r0, #0x48]
+	str r1, [r0, #0x4C]
+	str r1, [r0, #0x50]
+
+	ldr r0, =AIPS2_ON_BASE_ADDR
+	ldr r1, =0x77777777
+	str r1, [r0, #0x0]
+	str r1, [r0, #0x4]
+	ldr r1, =0x0
+	str r1, [r0, #0x40]
+	str r1, [r0, #0x44]
+	str r1, [r0, #0x48]
+	str r1, [r0, #0x4C]
+	str r1, [r0, #0x50]
+.endm /* init_aips */
+
+.macro setup_pll pll, freq
+.endm
+
+.macro init_clock
+
+/* PLL1, PLL2, and PLL3 are enabled by ROM */
+#ifdef CONFIG_PLL3
+	/* enable PLL3 for UART */
+	ldr r0, ANATOP_BASE_ADDR_W
+
+	/* power up PLL */
+	ldr r1, [r0, #ANATOP_USB1]
+	orr r1, r1, #0x1000
+	str r1, [r0, #ANATOP_USB1]
+
+	/* enable PLL */
+	ldr r1, [r0, #ANATOP_USB1]
+	orr r1, r1, #0x2000
+	str r1, [r0, #ANATOP_USB1]
+
+	/* wait PLL lock */
+100:
+	ldr r1, [r0, #ANATOP_USB1]
+	mov r1, r1, lsr #31
+	cmp r1, #0x1
+	bne 100b
+
+	/* clear bypass bit */
+	ldr r1, [r0, #ANATOP_USB1]
+	and r1, r1, #0xfffeffff
+	str r1, [r0, #ANATOP_USB1]
+#endif
+
+	/* Restore the default values in the Gate registers */
+	ldr r0, CCM_BASE_ADDR_W
+	ldr r1, =0xC0003F
+	str r1, [r0, #CLKCTL_CCGR0]
+	ldr r1, =0x30FC00
+	str r1, [r0, #CLKCTL_CCGR1]
+	ldr r1, =0xFFFC000
+	str r1, [r0, #CLKCTL_CCGR2]
+	ldr r1, =0x3FF00000
+	str r1, [r0, #CLKCTL_CCGR3]
+	ldr r1, =0xFFF300
+	str r1, [r0, #CLKCTL_CCGR4]
+	ldr r1, =0xF0000C3
+	str r1, [r0, #CLKCTL_CCGR5]
+	ldr r1, =0x3FC
+	str r1, [r0, #CLKCTL_CCGR6]
+.endm
+
+.section ".text.init", "x"
+
+.globl lowlevel_init
+lowlevel_init:
+
+	inv_dcache
+
+	init_l2cc
+
+	init_aips
+
+	init_clock
+
+	mov pc, lr
+
+/* Board level setting value */
+ANATOP_BASE_ADDR_W:		.word ANATOP_BASE_ADDR
+CCM_BASE_ADDR_W:		.word CCM_BASE_ADDR

board/freescale/mx6q_sabreauto/mx6q_sabreauto.c

@@ -0,0 +1,876 @@
+/*
+ * Copyright (C) 2010-2012 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/mx6.h>
+#include <asm/arch/mx6_pins.h>
+#include <asm/arch/iomux-v3.h>
+#include <asm/errno.h>
+#include <miiphy.h>
+#if defined(CONFIG_VIDEO_MX5)
+#include <linux/list.h>
+#include <linux/fb.h>
+#include <linux/mxcfb.h>
+#include <ipu.h>
+#include <lcd.h>
+#endif
+
+#ifdef CONFIG_IMX_ECSPI
+#include <imx_spi.h>
+#endif
+
+#if CONFIG_I2C_MXC
+#include <i2c.h>
+#endif
+
+#ifdef CONFIG_CMD_MMC
+#include <mmc.h>
+#include <fsl_esdhc.h>
+#endif
+
+#ifdef CONFIG_ARCH_MMU
+#include <asm/mmu.h>
+#include <asm/arch/mmu.h>
+#endif
+
+#ifdef CONFIG_CMD_CLOCK
+#include <asm/clock.h>
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static u32 system_rev;
+static enum boot_device boot_dev;
+
+#ifdef CONFIG_VIDEO_MX5
+extern unsigned char fsl_bmp_600x400[];
+extern int fsl_bmp_600x400_size;
+extern int g_ipu_hw_rev;
+
+#if defined(CONFIG_BMP_8BPP)
+unsigned short colormap[256];
+#elif defined(CONFIG_BMP_16BPP)
+unsigned short colormap[65536];
+#else
+unsigned short colormap[16777216];
+#endif
+
+static int di = 1;
+
+extern int ipuv3_fb_init(struct fb_videomode *mode, int di,
+			int interface_pix_fmt,
+			ipu_di_clk_parent_t di_clk_parent,
+			int di_clk_val);
+
+static struct fb_videomode lvds_xga = {
+	 "XGA", 60, 1024, 768, 15385, 220, 40, 21, 7, 60, 10,
+	 FB_SYNC_EXT,
+	 FB_VMODE_NONINTERLACED,
+	 0,
+};
+
+vidinfo_t panel_info;
+#endif
+
+static void set_gpio_output_val(unsigned base, unsigned mask, unsigned val)
+{
+	unsigned reg = readl(base + GPIO_DR);
+	if (val & 1)
+		reg |= mask;	/* set high */
+	else
+		reg &= ~mask;	/* clear low */
+	writel(reg, base + GPIO_DR);
+
+	reg = readl(base + GPIO_GDIR);
+	reg |= mask;		/* configure GPIO line as output */
+	writel(reg, base + GPIO_GDIR);
+}
+
+
+static inline void setup_boot_device(void)
+{
+	uint soc_sbmr = readl(SRC_BASE_ADDR + 0x4);
+	uint bt_mem_ctl = (soc_sbmr & 0x000000FF) >> 4 ;
+	uint bt_mem_type = (soc_sbmr & 0x00000008) >> 3;
+
+	switch (bt_mem_ctl) {
+	case 0x0:
+		if (bt_mem_type)
+			boot_dev = ONE_NAND_BOOT;
+		else
+			boot_dev = WEIM_NOR_BOOT;
+		break;
+	case 0x2:
+			boot_dev = SATA_BOOT;
+		break;
+	case 0x3:
+		if (bt_mem_type)
+			boot_dev = I2C_BOOT;
+		else
+			boot_dev = SPI_NOR_BOOT;
+		break;
+	case 0x4:
+	case 0x5:
+		boot_dev = SD_BOOT;
+		break;
+	case 0x6:
+	case 0x7:
+		boot_dev = MMC_BOOT;
+		break;
+	case 0x8 ... 0xf:
+		boot_dev = NAND_BOOT;
+		break;
+	default:
+		boot_dev = UNKNOWN_BOOT;
+		break;
+	}
+}
+
+enum boot_device get_boot_device(void)
+{
+	return boot_dev;
+}
+
+u32 get_board_rev(void)
+{
+
+	system_rev = 0x63000;
+
+	return system_rev;
+}
+
+#ifdef CONFIG_ARCH_MMU
+void board_mmu_init(void)
+{
+	unsigned long ttb_base = PHYS_SDRAM_1 + 0x4000;
+	unsigned long i;
+
+	/*
+	* Set the TTB register
+	*/
+	asm volatile ("mcr  p15,0,%0,c2,c0,0" : : "r"(ttb_base) /*:*/);
+
+	/*
+	* Set the Domain Access Control Register
+	*/
+	i = ARM_ACCESS_DACR_DEFAULT;
+	asm volatile ("mcr  p15,0,%0,c3,c0,0" : : "r"(i) /*:*/);
+
+	/*
+	* First clear all TT entries - ie Set them to Faulting
+	*/
+	memset((void *)ttb_base, 0, ARM_FIRST_LEVEL_PAGE_TABLE_SIZE);
+	/* Actual   Virtual  Size   Attributes          Function */
+	/* Base     Base     MB     cached? buffered?  access permissions */
+	/* xxx00000 xxx00000 */
+	X_ARM_MMU_SECTION(0x000, 0x000, 0x001,
+			ARM_UNCACHEABLE, ARM_UNBUFFERABLE,
+			ARM_ACCESS_PERM_RW_RW); /* ROM, 1M */
+	X_ARM_MMU_SECTION(0x001, 0x001, 0x008,
+			ARM_UNCACHEABLE, ARM_UNBUFFERABLE,
+			ARM_ACCESS_PERM_RW_RW); /* 8M */
+	X_ARM_MMU_SECTION(0x009, 0x009, 0x001,
+			ARM_UNCACHEABLE, ARM_UNBUFFERABLE,
+			ARM_ACCESS_PERM_RW_RW); /* IRAM */
+	X_ARM_MMU_SECTION(0x00A, 0x00A, 0x0F6,
+			ARM_UNCACHEABLE, ARM_UNBUFFERABLE,
+			ARM_ACCESS_PERM_RW_RW); /* 246M */
+	/* 2 GB memory starting at 0x10000000, only map 1.875 GB */
+	X_ARM_MMU_SECTION(0x100, 0x100, 0x780,
+			ARM_CACHEABLE, ARM_BUFFERABLE,
+			ARM_ACCESS_PERM_RW_RW);
+	/* uncached alias of the same 1.875 GB memory */
+	X_ARM_MMU_SECTION(0x100, 0x880, 0x780,
+			ARM_UNCACHEABLE, ARM_UNBUFFERABLE,
+			ARM_ACCESS_PERM_RW_RW);
+
+	/* Enable MMU */
+	MMU_ON();
+}
+#endif
+
+#ifdef CONFIG_DWC_AHSATA
+
+#define ANATOP_PLL_LOCK                 0x80000000
+#define ANATOP_PLL_ENABLE_MASK          0x00002000
+#define ANATOP_PLL_BYPASS_MASK          0x00010000
+#define ANATOP_PLL_LOCK                 0x80000000
+#define ANATOP_PLL_PWDN_MASK            0x00001000
+#define ANATOP_PLL_HOLD_RING_OFF_MASK   0x00000800
+#define ANATOP_SATA_CLK_ENABLE_MASK     0x00100000
+
+int setup_sata(void)
+{
+	u32 reg = 0;
+	s32 timeout = 100000;
+
+	/* Enable sata clock */
+	reg = readl(CCM_BASE_ADDR + 0x7c); /* CCGR5 */
+	reg |= 0x30;
+	writel(reg, CCM_BASE_ADDR + 0x7c);
+
+	/* Enable PLLs */
+	reg = readl(ANATOP_BASE_ADDR + 0xe0); /* ENET PLL */
+	reg &= ~ANATOP_PLL_PWDN_MASK;
+	writel(reg, ANATOP_BASE_ADDR + 0xe0);
+	reg |= ANATOP_PLL_ENABLE_MASK;
+	while (timeout--) {
+		if (readl(ANATOP_BASE_ADDR + 0xe0) & ANATOP_PLL_LOCK)
+			break;
+	}
+	if (timeout <= 0)
+		return -1;
+	reg &= ~ANATOP_PLL_BYPASS_MASK;
+	writel(reg, ANATOP_BASE_ADDR + 0xe0);
+	reg |= ANATOP_SATA_CLK_ENABLE_MASK;
+	writel(reg, ANATOP_BASE_ADDR + 0xe0);
+
+	/* Enable sata phy */
+	reg = readl(IOMUXC_BASE_ADDR + 0x34); /* GPR13 */
+
+	reg &= ~0x07ffffff;
+	/*
+	 * rx_eq_val_0 = 5 [26:24]
+	 * los_lvl = 0x12 [23:19]
+	 * rx_dpll_mode_0 = 0x3 [18:16]
+	 * mpll_ss_en = 0x0 [14]
+	 * tx_atten_0 = 0x4 [13:11]
+	 * tx_boost_0 = 0x0 [10:7]
+	 * tx_lvl = 0x11 [6:2]
+	 * mpll_ck_off_b = 0x1 [1]
+	 * tx_edgerate_0 = 0x0 [0]
+	 * */
+	reg |= 0x59124c6;
+	writel(reg, IOMUXC_BASE_ADDR + 0x34);
+
+	return 0;
+}
+#endif
+
+int dram_init(void)
+{
+	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+	return 0;
+}
+
+static void setup_uart(void)
+{
+	/* UART4 TXD */
+	mxc_iomux_v3_setup_pad(MX6Q_PAD_KEY_COL0__UART4_TXD);
+
+	/* UART4 RXD */
+	mxc_iomux_v3_setup_pad(MX6Q_PAD_KEY_ROW0__UART4_RXD);
+}
+
+#ifdef CONFIG_VIDEO_MX5
+#ifdef CONFIG_I2C_MXC
+static void setup_i2c(unsigned int module_base)
+{
+	unsigned int reg;
+
+	switch (module_base) {
+	case I2C1_BASE_ADDR:
+		/* i2c1 SDA */
+		mxc_iomux_v3_setup_pad(MX6Q_PAD_CSI0_DAT8__I2C1_SDA);
+
+		/* i2c1 SCL */
+		mxc_iomux_v3_setup_pad(MX6Q_PAD_CSI0_DAT9__I2C1_SCL);
+
+		/* Enable i2c clock */
+		reg = readl(CCM_BASE_ADDR + CLKCTL_CCGR2);
+		reg |= 0xC0;
+		writel(reg, CCM_BASE_ADDR + CLKCTL_CCGR2);
+
+		break;
+	case I2C2_BASE_ADDR:
+		/* i2c2 SDA */
+		mxc_iomux_v3_setup_pad(MX6Q_PAD_KEY_ROW3__I2C2_SDA);
+
+		/* i2c2 SCL */
+		mxc_iomux_v3_setup_pad(MX6Q_PAD_KEY_COL3__I2C2_SCL);
+
+		/* Enable i2c clock */
+		reg = readl(CCM_BASE_ADDR + CLKCTL_CCGR2);
+		reg |= 0x300;
+		writel(reg, CCM_BASE_ADDR + CLKCTL_CCGR2);
+
+		break;
+	case I2C3_BASE_ADDR:
+		/* GPIO_3 for I2C3_SCL */
+		mxc_iomux_v3_setup_pad(MX6Q_PAD_GPIO_3__I2C3_SCL);
+
+		/* GPIO_16 for I2C3_SDA */
+		mxc_iomux_v3_setup_pad(MX6Q_PAD_GPIO_16__I2C3_SDA);
+
+		/* Enable i2c clock */
+		reg = readl(CCM_BASE_ADDR + CLKCTL_CCGR2);
+		reg |= 0xC00;
+		writel(reg, CCM_BASE_ADDR + CLKCTL_CCGR2);
+
+		break;
+	default:
+		printf("Invalid I2C base: 0x%x\n", module_base);
+		break;
+	}
+}
+
+void setup_lvds_poweron(void)
+{
+	uchar value;
+	i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
+
+	i2c_read(0x30, 3, 1, &value, 1);
+	value &= ~0x2;
+	i2c_write(0x30, 3, 1, &value, 1);
+
+	i2c_read(0x30, 1, 1, &value, 1);
+	value |= 0x2;
+	i2c_write(0x30, 1, 1, &value, 1);
+}
+#endif
+#endif
+
+#ifdef CONFIG_IMX_ECSPI
+s32 spi_get_cfg(struct imx_spi_dev_t *dev)
+{
+	switch (dev->slave.cs) {
+	case 0:
+		/* SPI-NOR */
+		dev->base = ECSPI1_BASE_ADDR;
+		dev->freq = 25000000;
+		dev->ss_pol = IMX_SPI_ACTIVE_LOW;
+		dev->ss = 0;
+		dev->fifo_sz = 64 * 4;
+		dev->us_delay = 0;
+		break;
+	case 1:
+		/* SPI-NOR */
+		dev->base = ECSPI1_BASE_ADDR;
+		dev->freq = 25000000;
+		dev->ss_pol = IMX_SPI_ACTIVE_LOW;
+		dev->ss = 1;
+		dev->fifo_sz = 64 * 4;
+		dev->us_delay = 0;
+		break;
+	default:
+		printf("Invalid Bus ID!\n");
+	}
+
+	return 0;
+}
+
+void spi_io_init(struct imx_spi_dev_t *dev)
+{
+	u32 reg;
+
+	switch (dev->base) {
+	case ECSPI1_BASE_ADDR:
+		/* Enable clock */
+		reg = readl(CCM_BASE_ADDR + CLKCTL_CCGR1);
+		reg |= 0x3;
+		writel(reg, CCM_BASE_ADDR + CLKCTL_CCGR1);
+
+		/* SCLK */
+		mxc_iomux_v3_setup_pad(MX6Q_PAD_EIM_D16__ECSPI1_SCLK);
+
+		/* MISO */
+		mxc_iomux_v3_setup_pad(MX6Q_PAD_EIM_D17__ECSPI1_MISO);
+
+		/* MOSI */
+		mxc_iomux_v3_setup_pad(MX6Q_PAD_EIM_D18__ECSPI1_MOSI);
+
+		if (dev->ss == 0)
+			mxc_iomux_v3_setup_pad(MX6Q_PAD_EIM_EB2__ECSPI1_SS0);
+		else if (dev->ss == 1)
+			mxc_iomux_v3_setup_pad(MX6Q_PAD_EIM_D19__ECSPI1_SS1);
+		break;
+	case ECSPI2_BASE_ADDR:
+	case ECSPI3_BASE_ADDR:
+		/* ecspi2-3 fall through */
+		break;
+	default:
+		break;
+	}
+}
+#endif
+
+#ifdef CONFIG_NAND_GPMI
+
+iomux_v3_cfg_t nfc_pads[] = {
+	MX6Q_PAD_NANDF_CLE__RAWNAND_CLE,
+	MX6Q_PAD_NANDF_ALE__RAWNAND_ALE,
+	MX6Q_PAD_NANDF_WP_B__RAWNAND_RESETN,
+	MX6Q_PAD_NANDF_RB0__RAWNAND_READY0,
+	MX6Q_PAD_NANDF_CS0__RAWNAND_CE0N,
+	MX6Q_PAD_NANDF_CS1__RAWNAND_CE1N,
+	MX6Q_PAD_NANDF_CS2__RAWNAND_CE2N,
+	MX6Q_PAD_NANDF_CS3__RAWNAND_CE3N,
+	MX6Q_PAD_SD4_CMD__RAWNAND_RDN,
+	MX6Q_PAD_SD4_CLK__RAWNAND_WRN,
+	MX6Q_PAD_NANDF_D0__RAWNAND_D0,
+	MX6Q_PAD_NANDF_D1__RAWNAND_D1,
+	MX6Q_PAD_NANDF_D2__RAWNAND_D2,
+	MX6Q_PAD_NANDF_D3__RAWNAND_D3,
+	MX6Q_PAD_NANDF_D4__RAWNAND_D4,
+	MX6Q_PAD_NANDF_D5__RAWNAND_D5,
+	MX6Q_PAD_NANDF_D6__RAWNAND_D6,
+	MX6Q_PAD_NANDF_D7__RAWNAND_D7,
+	MX6Q_PAD_SD4_DAT0__RAWNAND_DQS,
+};
+
+int setup_gpmi_nand(void)
+{
+	unsigned int reg;
+
+	/* config gpmi nand iomux */
+	mxc_iomux_v3_setup_multiple_pads(nfc_pads,
+			ARRAY_SIZE(nfc_pads));
+
+
+	/* config gpmi and bch clock to 11Mhz*/
+	reg = readl(CCM_BASE_ADDR + CLKCTL_CS2CDR);
+	reg &= 0xF800FFFF;
+	reg |= 0x01E40000;
+	writel(reg, CCM_BASE_ADDR + CLKCTL_CS2CDR);
+
+	/* enable gpmi and bch clock gating */
+	reg = readl(CCM_BASE_ADDR + CLKCTL_CCGR4);
+	reg |= 0xFF003000;
+	writel(reg, CCM_BASE_ADDR + CLKCTL_CCGR4);
+
+	/* enable apbh clock gating */
+	reg = readl(CCM_BASE_ADDR + CLKCTL_CCGR0);
+	reg |= 0x0030;
+	writel(reg, CCM_BASE_ADDR + CLKCTL_CCGR0);
+
+}
+#endif
+
+#ifdef CONFIG_NET_MULTI
+int board_eth_init(bd_t *bis)
+{
+	int rc = -ENODEV;
+
+	return rc;
+}
+#endif
+
+#ifdef CONFIG_CMD_MMC
+
+/* On this board, only SD3 can support 1.8V signalling
+ * that is required for UHS-I mode of operation.
+ * Last element in struct is used to indicate 1.8V support.
+ */
+struct fsl_esdhc_cfg usdhc_cfg[4] = {
+	{USDHC1_BASE_ADDR, 1, 1, 1, 0},
+	{USDHC2_BASE_ADDR, 1, 1, 1, 0},
+	{USDHC3_BASE_ADDR, 1, 1, 1, 1},
+	{USDHC4_BASE_ADDR, 1, 1, 1, 0},
+};
+
+#ifdef CONFIG_DYNAMIC_MMC_DEVNO
+int get_mmc_env_devno(void)
+{
+	uint soc_sbmr = readl(SRC_BASE_ADDR + 0x4);
+
+	if (SD_BOOT == boot_dev || MMC_BOOT == boot_dev) {
+		/* BOOT_CFG2[3] and BOOT_CFG2[4] */
+		return (soc_sbmr & 0x00001800) >> 11;
+	} else
+		return -1;
+
+}
+#endif
+
+iomux_v3_cfg_t mx6q_usdhc1_pads[] = {
+	MX6Q_PAD_SD1_CLK__USDHC1_CLK,
+	MX6Q_PAD_SD1_CMD__USDHC1_CMD,
+	MX6Q_PAD_SD1_DAT0__USDHC1_DAT0,
+	MX6Q_PAD_SD1_DAT1__USDHC1_DAT1,
+	MX6Q_PAD_SD1_DAT2__USDHC1_DAT2,
+	MX6Q_PAD_SD1_DAT3__USDHC1_DAT3,
+};
+
+iomux_v3_cfg_t mx6q_usdhc2_pads[] = {
+	MX6Q_PAD_SD2_CLK__USDHC2_CLK,
+	MX6Q_PAD_SD2_CMD__USDHC2_CMD,
+	MX6Q_PAD_SD2_DAT0__USDHC2_DAT0,
+	MX6Q_PAD_SD2_DAT1__USDHC2_DAT1,
+	MX6Q_PAD_SD2_DAT2__USDHC2_DAT2,
+	MX6Q_PAD_SD2_DAT3__USDHC2_DAT3,
+};
+
+iomux_v3_cfg_t mx6q_usdhc3_pads[] = {
+	MX6Q_PAD_SD3_CLK__USDHC3_CLK,
+	MX6Q_PAD_SD3_CMD__USDHC3_CMD,
+	MX6Q_PAD_SD3_DAT0__USDHC3_DAT0,
+	MX6Q_PAD_SD3_DAT1__USDHC3_DAT1,
+	MX6Q_PAD_SD3_DAT2__USDHC3_DAT2,
+	MX6Q_PAD_SD3_DAT3__USDHC3_DAT3,
+	MX6Q_PAD_SD3_DAT4__USDHC3_DAT4,
+	MX6Q_PAD_SD3_DAT5__USDHC3_DAT5,
+	MX6Q_PAD_SD3_DAT6__USDHC3_DAT6,
+	MX6Q_PAD_SD3_DAT7__USDHC3_DAT7,
+};
+
+iomux_v3_cfg_t mx6q_usdhc4_pads[] = {
+	MX6Q_PAD_SD4_CLK__USDHC4_CLK,
+	MX6Q_PAD_SD4_CMD__USDHC4_CMD,
+	MX6Q_PAD_SD4_DAT0__USDHC4_DAT0,
+	MX6Q_PAD_SD4_DAT1__USDHC4_DAT1,
+	MX6Q_PAD_SD4_DAT2__USDHC4_DAT2,
+	MX6Q_PAD_SD4_DAT3__USDHC4_DAT3,
+	MX6Q_PAD_SD4_DAT4__USDHC4_DAT4,
+	MX6Q_PAD_SD4_DAT5__USDHC4_DAT5,
+	MX6Q_PAD_SD4_DAT6__USDHC4_DAT6,
+	MX6Q_PAD_SD4_DAT7__USDHC4_DAT7,
+};
+
+int usdhc_gpio_init(bd_t *bis)
+{
+	s32 status = 0;
+	u32 index = 0;
+
+	for (index = 0; index < CONFIG_SYS_FSL_USDHC_NUM;
+		++index) {
+		switch (index) {
+		case 0:
+			mxc_iomux_v3_setup_multiple_pads(mx6q_usdhc1_pads,
+				sizeof(mx6q_usdhc1_pads) /
+				sizeof(mx6q_usdhc1_pads[0]));
+			break;
+		case 1:
+			mxc_iomux_v3_setup_multiple_pads(mx6q_usdhc2_pads,
+				sizeof(mx6q_usdhc2_pads) /
+				sizeof(mx6q_usdhc2_pads[0]));
+			break;
+		case 2:
+			mxc_iomux_v3_setup_multiple_pads(mx6q_usdhc3_pads,
+				sizeof(mx6q_usdhc3_pads) /
+				sizeof(mx6q_usdhc3_pads[0]));
+			break;
+		case 3:
+			mxc_iomux_v3_setup_multiple_pads(mx6q_usdhc4_pads,
+				sizeof(mx6q_usdhc4_pads) /
+				sizeof(mx6q_usdhc4_pads[0]));
+			break;
+		default:
+			printf("Warning: you configured more USDHC controllers"
+				"(%d) then supported by the board (%d)\n",
+				index+1, CONFIG_SYS_FSL_USDHC_NUM);
+			return status;
+		}
+		status |= fsl_esdhc_initialize(bis, &usdhc_cfg[index]);
+	}
+
+	return status;
+}
+
+int board_mmc_init(bd_t *bis)
+{
+	if (!usdhc_gpio_init(bis))
+		return 0;
+	else
+		return -1;
+}
+
+/* For DDR mode operation, provide target delay parameter for each SD port.
+ * Use cfg->esdhc_base to distinguish the SD port #. The delay for each port
+ * is dependent on signal layout for that particular port.  If the following
+ * CONFIG is not defined, then the default target delay value will be used.
+ */
+#ifdef CONFIG_GET_DDR_TARGET_DELAY
+u32 get_ddr_delay(struct fsl_esdhc_cfg *cfg)
+{
+	/* No delay required on SABRE Auto board SD ports */
+	return 0;
+}
+#endif
+
+#endif
+
+#ifdef CONFIG_LCD
+void lcd_enable(void)
+{
+	char *s;
+	int ret;
+	unsigned int reg;
+
+	s = getenv("lvds_num");
+	di = simple_strtol(s, NULL, 10);
+
+	/*
+	* hw_rev 2: IPUV3DEX
+	* hw_rev 3: IPUV3M
+	* hw_rev 4: IPUV3H
+	*/
+	g_ipu_hw_rev = IPUV3_HW_REV_IPUV3H;
+
+	/* set GPIO_9 to high so that backlight control could be high */
+	mxc_iomux_v3_setup_pad(MX6Q_PAD_GPIO_9__GPIO_1_9);
+	reg = readl(GPIO1_BASE_ADDR + GPIO_GDIR);
+	reg |= (1 << 9);
+	writel(reg, GPIO1_BASE_ADDR + GPIO_GDIR);
+
+	reg = readl(GPIO1_BASE_ADDR + GPIO_DR);
+	reg |= (1 << 9);
+	writel(reg, GPIO1_BASE_ADDR + GPIO_DR);
+
+	/* Enable IPU clock */
+	if (di == 1) {
+		reg = readl(CCM_BASE_ADDR + CLKCTL_CCGR3);
+		reg |= 0xC033;
+		writel(reg, CCM_BASE_ADDR + CLKCTL_CCGR3);
+	} else {
+		reg = readl(CCM_BASE_ADDR + CLKCTL_CCGR3);
+		reg |= 0x300F;
+		writel(reg, CCM_BASE_ADDR + CLKCTL_CCGR3);
+	}
+
+	ret = ipuv3_fb_init(&lvds_xga, di, IPU_PIX_FMT_RGB666,
+			DI_PCLK_LDB, 65000000);
+	if (ret)
+		puts("LCD cannot be configured\n");
+
+	reg = readl(ANATOP_BASE_ADDR + 0xF0);
+	reg &= ~0x00003F00;
+	reg |= 0x00001300;
+	writel(reg, ANATOP_BASE_ADDR + 0xF4);
+
+	reg = readl(CCM_BASE_ADDR + CLKCTL_CS2CDR);
+	reg &= ~0x00007E00;
+	reg |= 0x00003600;
+	writel(reg, CCM_BASE_ADDR + CLKCTL_CS2CDR);
+
+	reg = readl(CCM_BASE_ADDR + CLKCTL_CSCMR2);
+	reg |= 0x00000C00;
+	writel(reg, CCM_BASE_ADDR + CLKCTL_CSCMR2);
+
+	reg = 0x0002A953;
+	writel(reg, CCM_BASE_ADDR + CLKCTL_CHSCCDR);
+
+	if (di == 1)
+		writel(0x40C, IOMUXC_BASE_ADDR + 0x8);
+	else
+		writel(0x201, IOMUXC_BASE_ADDR + 0x8);
+}
+#endif
+
+#ifdef CONFIG_VIDEO_MX5
+void panel_info_init(void)
+{
+	panel_info.vl_bpix = LCD_BPP;
+	panel_info.vl_col = lvds_xga.xres;
+	panel_info.vl_row = lvds_xga.yres;
+	panel_info.cmap = colormap;
+}
+#endif
+
+#ifdef CONFIG_SPLASH_SCREEN
+void setup_splash_image(void)
+{
+	char *s;
+	ulong addr;
+
+	s = getenv("splashimage");
+
+	if (s != NULL) {
+		addr = simple_strtoul(s, NULL, 16);
+
+#if defined(CONFIG_ARCH_MMU)
+		addr = ioremap_nocache(iomem_to_phys(addr),
+				fsl_bmp_600x400_size);
+#endif
+		memcpy((char *)addr, (char *)fsl_bmp_600x400,
+				fsl_bmp_600x400_size);
+	}
+}
+#endif
+
+int board_init(void)
+{
+	mxc_iomux_v3_init((void *)IOMUXC_BASE_ADDR);
+	setup_boot_device();
+
+	/* board id for linux */
+	gd->bd->bi_arch_number = MACH_TYPE_MX6Q_SABREAUTO;
+
+	/* address of boot parameters */
+	gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
+
+	setup_uart();
+
+#ifdef CONFIG_DWC_AHSATA
+	setup_sata();
+#endif
+
+#ifdef CONFIG_VIDEO_MX5
+
+#ifdef CONFIG_I2C_MXC
+	setup_i2c(CONFIG_SYS_I2C_PORT);
+	/* Enable lvds power */
+	setup_lvds_poweron();
+#endif
+
+	panel_info_init();
+
+	gd->fb_base = CONFIG_FB_BASE;
+#ifdef CONFIG_ARCH_MMU
+	gd->fb_base = ioremap_nocache(iomem_to_phys(gd->fb_base), 0);
+#endif
+#endif
+
+#ifdef CONFIG_NAND_GPMI
+	setup_gpmi_nand();
+#endif
+	return 0;
+}
+
+int board_late_init(void)
+{
+	return 0;
+}
+
+static int phy_read(char *devname, unsigned char addr, unsigned char reg,
+		    unsigned short *pdata)
+{
+	int ret = miiphy_read(devname, addr, reg, pdata);
+	if (ret)
+		printf("Error reading from %s PHY addr=%02x reg=%02x\n",
+		       devname, addr, reg);
+	return ret;
+}
+
+static int phy_write(char *devname, unsigned char addr, unsigned char reg,
+		     unsigned short value)
+{
+	int ret = miiphy_write(devname, addr, reg, value);
+	if (ret)
+		printf("Error writing to %s PHY addr=%02x reg=%02x\n", devname,
+		       addr, reg);
+	return ret;
+}
+
+int mx6_rgmii_rework(char *devname, int phy_addr)
+{
+
+	/* enable master mode, 1000 Base-T capable */
+	phy_write(devname, phy_addr, 0x9, 0x1f00);
+
+	/* min rx data delay */
+	phy_write(devname, phy_addr, 0x0b, 0x8105);
+	phy_write(devname, phy_addr, 0x0c, 0x0000);
+
+	/* max rx/tx clock delay, min rx/tx control delay */
+	phy_write(devname, phy_addr, 0x0b, 0x8104);
+	phy_write(devname, phy_addr, 0x0c, 0xf0f0);
+	phy_write(devname, phy_addr, 0x0b, 0x104);
+
+	return 0;
+}
+
+iomux_v3_cfg_t enet_pads[] = {
+	MX6Q_PAD_KEY_COL1__ENET_MDIO,
+	MX6Q_PAD_KEY_COL2__ENET_MDC,
+	MX6Q_PAD_RGMII_TXC__ENET_RGMII_TXC,
+	MX6Q_PAD_RGMII_TD0__ENET_RGMII_TD0,
+	MX6Q_PAD_RGMII_TD1__ENET_RGMII_TD1,
+	MX6Q_PAD_RGMII_TD2__ENET_RGMII_TD2,
+	MX6Q_PAD_RGMII_TD3__ENET_RGMII_TD3,
+	MX6Q_PAD_RGMII_TX_CTL__ENET_RGMII_TX_CTL,
+	MX6Q_PAD_ENET_REF_CLK__ENET_TX_CLK,
+	MX6Q_PAD_RGMII_RXC__ENET_RGMII_RXC,
+	MX6Q_PAD_RGMII_RD0__ENET_RGMII_RD0,
+	MX6Q_PAD_RGMII_RD1__ENET_RGMII_RD1,
+	MX6Q_PAD_RGMII_RD2__ENET_RGMII_RD2,
+	MX6Q_PAD_RGMII_RD3__ENET_RGMII_RD3,
+	MX6Q_PAD_RGMII_RX_CTL__ENET_RGMII_RX_CTL,
+};
+
+void enet_board_init(void)
+{
+	unsigned int reg;
+
+	mxc_iomux_v3_setup_multiple_pads(enet_pads,
+			ARRAY_SIZE(enet_pads));
+	set_gpio_output_val(GPIO6_BASE_ADDR, (1 << 24), 1);
+
+}
+
+int checkboard(void)
+{
+	printf("Board: MX6Q-SABREAUTO:[ ");
+
+	switch (__REG(SRC_BASE_ADDR + 0x8)) {
+	case 0x0001:
+		printf("POR");
+		break;
+	case 0x0009:
+		printf("RST");
+		break;
+	case 0x0010:
+	case 0x0011:
+		printf("WDOG");
+		break;
+	default:
+		printf("unknown");
+	}
+	printf(" ]\n");
+
+	printf("Boot Device: ");
+	switch (get_boot_device()) {
+	case WEIM_NOR_BOOT:
+		printf("NOR\n");
+		break;
+	case ONE_NAND_BOOT:
+		printf("ONE NAND\n");
+		break;
+	case PATA_BOOT:
+		printf("PATA\n");
+		break;
+	case SATA_BOOT:
+		printf("SATA\n");
+		break;
+	case I2C_BOOT:
+		printf("I2C\n");
+		break;
+	case SPI_NOR_BOOT:
+		printf("SPI NOR\n");
+		break;
+	case SD_BOOT:
+		printf("SD\n");
+		break;
+	case MMC_BOOT:
+		printf("MMC\n");
+		break;
+	case NAND_BOOT:
+		printf("NAND\n");
+		break;
+	case UNKNOWN_BOOT:
+	default:
+		printf("UNKNOWN\n");
+		break;
+	}
+	return 0;
+}

board/freescale/mx6q_sabreauto/u-boot.lds

@@ -0,0 +1,74 @@
+/*
+ * January 2004 - Changed to support H4 device
+ * Copyright (c) 2004 Texas Instruments
+ *
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
+ *
+ * (C) Copyright 2011 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+	. = 0x00000000;
+
+	. = ALIGN(4);
+	.text	   :
+	{
+	  /* WARNING - the following is hand-optimized to fit within	*/
+	  /* the sector layout of our flash chips!	XXX FIXME XXX	*/
+	  board/freescale/mx6q_sabreauto/flash_header.o	(.text.flasheader)
+	  cpu/arm_cortexa8/start.o
+	  board/freescale/mx6q_sabreauto/libmx6q_sabreauto.a	(.text)
+	  lib_arm/libarm.a		(.text)
+	  net/libnet.a			(.text)
+	  drivers/mtd/libmtd.a		(.text)
+	  drivers/mmc/libmmc.a		(.text)
+
+	  . = DEFINED(env_offset) ? env_offset : .;
+	  common/env_embedded.o(.text)
+
+	  *(.text)
+	}
+
+	. = ALIGN(4);
+	.rodata : { *(.rodata) }
+
+	. = ALIGN(4);
+	.data : { *(.data) }
+
+	. = ALIGN(4);
+	.got : { *(.got) }
+
+	. = .;
+	__u_boot_cmd_start = .;
+	.u_boot_cmd : { *(.u_boot_cmd) }
+	__u_boot_cmd_end = .;
+
+	. = ALIGN(4);
+	_end_of_copy = .; /* end_of ROM copy code here */
+	__bss_start = .;
+	.bss : { *(.bss) }
+	_end = .;
+}

board/freescale/mx6q_sabrelite/Makefile

@@ -0,0 +1,47 @@
+#
+# (C) Copyright 2011 Freescale Semiconductor, Inc.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).a
+
+COBJS	:= $(BOARD).o
+SOBJS	:= lowlevel_init.o flash_header.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################

board/freescale/mx6q_sabrelite/config.mk

@@ -0,0 +1,7 @@
+LDSCRIPT := $(SRCTREE)/board/$(VENDOR)/$(BOARD)/u-boot.lds
+
+sinclude $(OBJTREE)/board/$(VENDOR)/$(BOARD)/config.tmp
+
+ifndef TEXT_BASE
+	TEXT_BASE = 0x27800000
+endif

board/freescale/mx6q_sabrelite/flash_header.S

@@ -0,0 +1,179 @@
+/*
+ * Copyright (C) 2011 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <asm/arch/mx6.h>
+
+#ifdef	CONFIG_FLASH_HEADER
+#ifndef CONFIG_FLASH_HEADER_OFFSET
+# error "Must define the offset of flash header"
+#endif
+
+#define CPU_2_BE_32(l) \
+       ((((l) & 0x000000FF) << 24) | \
+	(((l) & 0x0000FF00) << 8)  | \
+	(((l) & 0x00FF0000) >> 8)  | \
+	(((l) & 0xFF000000) >> 24))
+
+#define MXC_DCD_ITEM(i, addr, val)   \
+dcd_node_##i:                        \
+        .word CPU_2_BE_32(addr) ;     \
+        .word CPU_2_BE_32(val)  ;     \
+
+.section ".text.flasheader", "x"
+	b	_start
+	.org	CONFIG_FLASH_HEADER_OFFSET
+
+ivt_header:       .word 0x402000D1 /* Tag=0xD1, Len=0x0020, Ver=0x40 */
+app_code_jump_v:  .word _start
+reserv1:          .word 0x0
+dcd_ptr:          .word dcd_hdr
+boot_data_ptr:	  .word boot_data
+self_ptr:         .word ivt_header
+app_code_csf:     .word 0x0
+reserv2:          .word 0x0
+
+boot_data:        .word TEXT_BASE
+image_len:        .word _end_of_copy  - TEXT_BASE + CONFIG_FLASH_HEADER_OFFSET
+plugin:           .word 0x0
+
+dcd_hdr:          .word 0x40F002D2 /* Tag=0xD2, Len=93*8 + 4 + 4, Ver=0x40 */
+write_dcd_cmd:    .word 0x04EC02CC /* Tag=0xCC, Len=93*8 + 4, Param=0x04 */
+
+/* DCD */
+
+MXC_DCD_ITEM(1, IOMUXC_BASE_ADDR + 0x5a8, 0x00000030)
+MXC_DCD_ITEM(2, IOMUXC_BASE_ADDR + 0x5b0, 0x00000030)
+MXC_DCD_ITEM(3, IOMUXC_BASE_ADDR + 0x524, 0x00000030)
+MXC_DCD_ITEM(4, IOMUXC_BASE_ADDR + 0x51c, 0x00000030)
+
+MXC_DCD_ITEM(5, IOMUXC_BASE_ADDR + 0x518, 0x00000030)
+MXC_DCD_ITEM(6, IOMUXC_BASE_ADDR + 0x50c, 0x00000030)
+MXC_DCD_ITEM(7, IOMUXC_BASE_ADDR + 0x5b8, 0x00000030)
+MXC_DCD_ITEM(8, IOMUXC_BASE_ADDR + 0x5c0, 0x00000030)
+
+MXC_DCD_ITEM(9, IOMUXC_BASE_ADDR + 0x5ac, 0x00020030)
+MXC_DCD_ITEM(10, IOMUXC_BASE_ADDR + 0x5b4, 0x00020030)
+MXC_DCD_ITEM(11, IOMUXC_BASE_ADDR + 0x528, 0x00020030)
+MXC_DCD_ITEM(12, IOMUXC_BASE_ADDR + 0x520, 0x00020030)
+
+MXC_DCD_ITEM(13, IOMUXC_BASE_ADDR + 0x514, 0x00020030)
+MXC_DCD_ITEM(14, IOMUXC_BASE_ADDR + 0x510, 0x00020030)
+MXC_DCD_ITEM(15, IOMUXC_BASE_ADDR + 0x5bc, 0x00020030)
+MXC_DCD_ITEM(16, IOMUXC_BASE_ADDR + 0x5c4, 0x00020030)
+
+MXC_DCD_ITEM(17, IOMUXC_BASE_ADDR + 0x56c, 0x00020030)
+MXC_DCD_ITEM(18, IOMUXC_BASE_ADDR + 0x578, 0x00020030)
+MXC_DCD_ITEM(19, IOMUXC_BASE_ADDR + 0x588, 0x00020030)
+MXC_DCD_ITEM(20, IOMUXC_BASE_ADDR + 0x594, 0x00020030)
+
+MXC_DCD_ITEM(21, IOMUXC_BASE_ADDR + 0x57c, 0x00020030)
+MXC_DCD_ITEM(22, IOMUXC_BASE_ADDR + 0x590, 0x00003000)
+MXC_DCD_ITEM(23, IOMUXC_BASE_ADDR + 0x598, 0x00003000)
+MXC_DCD_ITEM(24, IOMUXC_BASE_ADDR + 0x58c, 0x00000000)
+
+MXC_DCD_ITEM(25, IOMUXC_BASE_ADDR + 0x59c, 0x00003030)
+MXC_DCD_ITEM(26, IOMUXC_BASE_ADDR + 0x5a0, 0x00003030)
+MXC_DCD_ITEM(27, IOMUXC_BASE_ADDR + 0x784, 0x00000030)
+MXC_DCD_ITEM(28, IOMUXC_BASE_ADDR + 0x788, 0x00000030)
+
+MXC_DCD_ITEM(29, IOMUXC_BASE_ADDR + 0x794, 0x00000030)
+MXC_DCD_ITEM(30, IOMUXC_BASE_ADDR + 0x79c, 0x00000030)
+MXC_DCD_ITEM(31, IOMUXC_BASE_ADDR + 0x7a0, 0x00000030)
+MXC_DCD_ITEM(32, IOMUXC_BASE_ADDR + 0x7a4, 0x00000030)
+
+MXC_DCD_ITEM(33, IOMUXC_BASE_ADDR + 0x7a8, 0x00000030)
+MXC_DCD_ITEM(34, IOMUXC_BASE_ADDR + 0x748, 0x00000030)
+MXC_DCD_ITEM(35, IOMUXC_BASE_ADDR + 0x74c, 0x00000030)
+MXC_DCD_ITEM(36, IOMUXC_BASE_ADDR + 0x750, 0x00020000)
+
+MXC_DCD_ITEM(37, IOMUXC_BASE_ADDR + 0x758, 0x00000000)
+MXC_DCD_ITEM(38, IOMUXC_BASE_ADDR + 0x774, 0x00020000)
+MXC_DCD_ITEM(39, IOMUXC_BASE_ADDR + 0x78c, 0x00000030)
+MXC_DCD_ITEM(40, IOMUXC_BASE_ADDR + 0x798, 0x000C0000)
+
+MXC_DCD_ITEM(41, MMDC_P0_BASE_ADDR + 0x81c, 0x33333333)
+MXC_DCD_ITEM(42, MMDC_P0_BASE_ADDR + 0x820, 0x33333333)
+MXC_DCD_ITEM(43, MMDC_P0_BASE_ADDR + 0x824, 0x33333333)
+MXC_DCD_ITEM(44, MMDC_P0_BASE_ADDR + 0x828, 0x33333333)
+
+MXC_DCD_ITEM(45, MMDC_P1_BASE_ADDR + 0x81c, 0x33333333)
+MXC_DCD_ITEM(46, MMDC_P1_BASE_ADDR + 0x820, 0x33333333)
+MXC_DCD_ITEM(47, MMDC_P1_BASE_ADDR + 0x824, 0x33333333)
+MXC_DCD_ITEM(48, MMDC_P1_BASE_ADDR + 0x828, 0x33333333)
+
+MXC_DCD_ITEM(49, MMDC_P0_BASE_ADDR + 0x018, 0x00081740)
+
+MXC_DCD_ITEM(50, MMDC_P0_BASE_ADDR + 0x01c, 0x00008000)
+MXC_DCD_ITEM(51, MMDC_P0_BASE_ADDR + 0x00c, 0x555A7975)
+MXC_DCD_ITEM(52, MMDC_P0_BASE_ADDR + 0x010, 0xFF538E64)
+MXC_DCD_ITEM(53, MMDC_P0_BASE_ADDR + 0x014, 0x01FF00DB)
+MXC_DCD_ITEM(54, MMDC_P0_BASE_ADDR + 0x02c, 0x000026D2)
+
+MXC_DCD_ITEM(55, MMDC_P0_BASE_ADDR + 0x030, 0x005B0E21)
+MXC_DCD_ITEM(56, MMDC_P0_BASE_ADDR + 0x008, 0x09444040)
+MXC_DCD_ITEM(57, MMDC_P0_BASE_ADDR + 0x004, 0x00025576)
+MXC_DCD_ITEM(58, MMDC_P0_BASE_ADDR + 0x040, 0x00000027)
+MXC_DCD_ITEM(59, MMDC_P0_BASE_ADDR + 0x000, 0x831A0000)
+
+MXC_DCD_ITEM(60, MMDC_P0_BASE_ADDR + 0x01c, 0x04088032)
+MXC_DCD_ITEM(61, MMDC_P0_BASE_ADDR + 0x01c, 0x0408803A)
+MXC_DCD_ITEM(62, MMDC_P0_BASE_ADDR + 0x01c, 0x00008033)
+MXC_DCD_ITEM(63, MMDC_P0_BASE_ADDR + 0x01c, 0x0000803B)
+MXC_DCD_ITEM(64, MMDC_P0_BASE_ADDR + 0x01c, 0x00428031)
+MXC_DCD_ITEM(65, MMDC_P0_BASE_ADDR + 0x01c, 0x00428039)
+MXC_DCD_ITEM(66, MMDC_P0_BASE_ADDR + 0x01c, 0x09408030)
+MXC_DCD_ITEM(67, MMDC_P0_BASE_ADDR + 0x01c, 0x09408038)
+
+MXC_DCD_ITEM(68, MMDC_P0_BASE_ADDR + 0x01c, 0x04008040)
+MXC_DCD_ITEM(69, MMDC_P0_BASE_ADDR + 0x01c, 0x04008048)
+MXC_DCD_ITEM(70, MMDC_P0_BASE_ADDR + 0x800, 0xA1380003)
+MXC_DCD_ITEM(71, MMDC_P1_BASE_ADDR + 0x800, 0xA1380003)
+MXC_DCD_ITEM(72, MMDC_P0_BASE_ADDR + 0x020, 0x00005800)
+MXC_DCD_ITEM(73, MMDC_P0_BASE_ADDR + 0x818, 0x00022227)
+MXC_DCD_ITEM(74, MMDC_P1_BASE_ADDR + 0x818, 0x00022227)
+
+MXC_DCD_ITEM(75, MMDC_P0_BASE_ADDR + 0x83c, 0x434B0350)
+MXC_DCD_ITEM(76, MMDC_P0_BASE_ADDR + 0x840, 0x034C0359)
+MXC_DCD_ITEM(77, MMDC_P1_BASE_ADDR + 0x83c, 0x434B0350)
+MXC_DCD_ITEM(78, MMDC_P1_BASE_ADDR + 0x840, 0x03650348)
+MXC_DCD_ITEM(79, MMDC_P0_BASE_ADDR + 0x848, 0x4436383B)
+MXC_DCD_ITEM(80, MMDC_P1_BASE_ADDR + 0x848, 0x39393341)
+MXC_DCD_ITEM(81, MMDC_P0_BASE_ADDR + 0x850, 0x35373933)
+MXC_DCD_ITEM(82, MMDC_P1_BASE_ADDR + 0x850, 0x48254A36)
+
+MXC_DCD_ITEM(83, MMDC_P0_BASE_ADDR + 0x80c, 0x001F001F)
+MXC_DCD_ITEM(84, MMDC_P0_BASE_ADDR + 0x810, 0x001F001F)
+
+MXC_DCD_ITEM(85, MMDC_P1_BASE_ADDR + 0x80c, 0x00440044)
+MXC_DCD_ITEM(86, MMDC_P1_BASE_ADDR + 0x810, 0x00440044)
+
+MXC_DCD_ITEM(87, MMDC_P0_BASE_ADDR + 0x8b8, 0x00000800)
+MXC_DCD_ITEM(88, MMDC_P1_BASE_ADDR + 0x8b8, 0x00000800)
+
+MXC_DCD_ITEM(89, MMDC_P0_BASE_ADDR + 0x01c, 0x00000000)
+MXC_DCD_ITEM(90, MMDC_P0_BASE_ADDR + 0x404, 0x00011006)
+
+/* enable AXI cache for VDOA/VPU/IPU */
+MXC_DCD_ITEM(91, IOMUXC_BASE_ADDR + 0x010, 0xf00000ff)
+/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
+MXC_DCD_ITEM(92, IOMUXC_BASE_ADDR + 0x018, 0x007f007f)
+MXC_DCD_ITEM(93, IOMUXC_BASE_ADDR + 0x01c, 0x007f007f)
+
+#endif

board/freescale/mx6q_sabrelite/lowlevel_init.S

@@ -0,0 +1,163 @@
+/*
+ * Copyright (C) 2011 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <asm/arch/mx6.h>
+
+/*
+ Disable L2Cache because ROM turn it on when uboot use plug-in.
+ If L2Cache is on default, there are cache coherence problem if kernel have
+ not config L2Cache.
+*/
+.macro init_l2cc
+    ldr     r1, =0xa02000
+    ldr     r0, =0x0
+    str     r0, [r1, #0x100]
+.endm /* init_l2cc */
+
+/* invalidate the D-CACHE */
+.macro inv_dcache
+    mov     r0,#0
+    mcr     p15,2,r0,c0,c0,0  /* cache size selection register, select dcache */
+    mrc     p15,1,r0,c0,c0,0  /* cache size ID register */
+    mov     r0,r0,ASR #13
+    ldr     r3,=0xfff
+    and     r0,r0,r3
+    cmp     r0,#0x7f
+    moveq   r6,#0x1000
+    beq     size_done
+    cmp     r0,#0xff
+    moveq   r6,#0x2000
+    movne   r6,#0x4000
+
+size_done:
+    mov     r2,#0
+    mov     r3,#0x40000000
+    mov     r4,#0x80000000
+    mov     r5,#0xc0000000
+
+d_inv_loop:
+    mcr     p15,0,r2,c7,c6,2  /* invalidate dcache by set / way */
+    mcr     p15,0,r3,c7,c6,2  /* invalidate dcache by set / way */
+    mcr     p15,0,r4,c7,c6,2  /* invalidate dcache by set / way */
+    mcr     p15,0,r5,c7,c6,2  /* invalidate dcache by set / way */
+    add     r2,r2,#0x20
+    add     r3,r3,#0x20
+    add     r4,r4,#0x20
+    add     r5,r5,#0x20
+
+    cmp     r2,r6
+    bne     d_inv_loop
+.endm
+
+/* AIPS setup - Only setup MPROTx registers.
+ * The PACR default values are good.*/
+.macro init_aips
+	/*
+	 * Set all MPROTx to be non-bufferable, trusted for R/W,
+	 * not forced to user-mode.
+	 */
+	ldr r0, =AIPS1_ON_BASE_ADDR
+	ldr r1, =0x77777777
+	str r1, [r0, #0x0]
+	str r1, [r0, #0x4]
+	ldr r1, =0x0
+	str r1, [r0, #0x40]
+	str r1, [r0, #0x44]
+	str r1, [r0, #0x48]
+	str r1, [r0, #0x4C]
+	str r1, [r0, #0x50]
+
+	ldr r0, =AIPS2_ON_BASE_ADDR
+	ldr r1, =0x77777777
+	str r1, [r0, #0x0]
+	str r1, [r0, #0x4]
+	ldr r1, =0x0
+	str r1, [r0, #0x40]
+	str r1, [r0, #0x44]
+	str r1, [r0, #0x48]
+	str r1, [r0, #0x4C]
+	str r1, [r0, #0x50]
+.endm /* init_aips */
+
+.macro setup_pll pll, freq
+.endm
+
+.macro init_clock
+
+/* PLL1, PLL2, and PLL3 are enabled by ROM */
+#ifdef CONFIG_PLL3
+	/* enable PLL3 for UART */
+	ldr r0, ANATOP_BASE_ADDR_W
+
+	/* power up PLL */
+	ldr r1, [r0, #ANATOP_USB1]
+	orr r1, r1, #0x1000
+	str r1, [r0, #ANATOP_USB1]
+
+	/* enable PLL */
+	ldr r1, [r0, #ANATOP_USB1]
+	orr r1, r1, #0x2000
+	str r1, [r0, #ANATOP_USB1]
+
+	/* wait PLL lock */
+100:
+	ldr r1, [r0, #ANATOP_USB1]
+	mov r1, r1, lsr #31
+	cmp r1, #0x1
+	bne 100b
+
+	/* clear bypass bit */
+	ldr r1, [r0, #ANATOP_USB1]
+	and r1, r1, #0xfffeffff
+	str r1, [r0, #ANATOP_USB1]
+#endif
+
+	/* Restore the default values in the Gate registers */
+	ldr r1, =0xFFFFFFFF
+	ldr r0, CCM_BASE_ADDR_W
+	str r1, [r0, #CLKCTL_CCGR0]
+	str r1, [r0, #CLKCTL_CCGR1]
+	str r1, [r0, #CLKCTL_CCGR2]
+	str r1, [r0, #CLKCTL_CCGR3]
+	str r1, [r0, #CLKCTL_CCGR4]
+	str r1, [r0, #CLKCTL_CCGR5]
+	str r1, [r0, #CLKCTL_CCGR6]
+	str r1, [r0, #CLKCTL_CCGR7]
+
+.endm
+
+.section ".text.init", "x"
+
+.globl lowlevel_init
+lowlevel_init:
+
+	inv_dcache
+
+	init_l2cc
+
+	init_aips
+
+	init_clock
+
+	mov pc, lr
+
+/* Board level setting value */
+ANATOP_BASE_ADDR_W:		.word ANATOP_BASE_ADDR
+CCM_BASE_ADDR_W:		.word CCM_BASE_ADDR